Merge git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
[wrt350n-kernel.git] / arch / mips / mips-boards / generic / init.c
blob1695dca5506bbe7e008221ca400836ff97446703
1 /*
2 * Copyright (C) 1999, 2000, 2004, 2005 MIPS Technologies, Inc.
3 * All rights reserved.
4 * Authors: Carsten Langgaard <carstenl@mips.com>
5 * Maciej W. Rozycki <macro@mips.com>
7 * This program is free software; you can distribute it and/or modify it
8 * under the terms of the GNU General Public License (Version 2) as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * for more details.
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
20 * PROM library initialisation code.
22 #include <linux/init.h>
23 #include <linux/string.h>
24 #include <linux/kernel.h>
26 #include <asm/bootinfo.h>
27 #include <asm/gt64120.h>
28 #include <asm/io.h>
29 #include <asm/system.h>
30 #include <asm/cacheflush.h>
31 #include <asm/traps.h>
33 #include <asm/mips-boards/prom.h>
34 #include <asm/mips-boards/generic.h>
35 #include <asm/mips-boards/bonito64.h>
36 #include <asm/mips-boards/msc01_pci.h>
38 #include <asm/mips-boards/malta.h>
40 #ifdef CONFIG_KGDB
41 extern int rs_kgdb_hook(int, int);
42 extern int rs_putDebugChar(char);
43 extern char rs_getDebugChar(void);
44 extern int saa9730_kgdb_hook(int);
45 extern int saa9730_putDebugChar(char);
46 extern char saa9730_getDebugChar(void);
47 #endif
49 int prom_argc;
50 int *_prom_argv, *_prom_envp;
53 * YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer.
54 * This macro take care of sign extension, if running in 64-bit mode.
56 #define prom_envp(index) ((char *)(long)_prom_envp[(index)])
58 int init_debug = 0;
60 int mips_revision_corid;
61 int mips_revision_sconid;
63 /* Bonito64 system controller register base. */
64 unsigned long _pcictrl_bonito;
65 unsigned long _pcictrl_bonito_pcicfg;
67 /* GT64120 system controller register base */
68 unsigned long _pcictrl_gt64120;
70 /* MIPS System controller register base */
71 unsigned long _pcictrl_msc;
73 char *prom_getenv(char *envname)
76 * Return a pointer to the given environment variable.
77 * In 64-bit mode: we're using 64-bit pointers, but all pointers
78 * in the PROM structures are only 32-bit, so we need some
79 * workarounds, if we are running in 64-bit mode.
81 int i, index=0;
83 i = strlen(envname);
85 while (prom_envp(index)) {
86 if(strncmp(envname, prom_envp(index), i) == 0) {
87 return(prom_envp(index+1));
89 index += 2;
92 return NULL;
95 static inline unsigned char str2hexnum(unsigned char c)
97 if (c >= '0' && c <= '9')
98 return c - '0';
99 if (c >= 'a' && c <= 'f')
100 return c - 'a' + 10;
101 return 0; /* foo */
104 static inline void str2eaddr(unsigned char *ea, unsigned char *str)
106 int i;
108 for (i = 0; i < 6; i++) {
109 unsigned char num;
111 if((*str == '.') || (*str == ':'))
112 str++;
113 num = str2hexnum(*str++) << 4;
114 num |= (str2hexnum(*str++));
115 ea[i] = num;
119 int get_ethernet_addr(char *ethernet_addr)
121 char *ethaddr_str;
123 ethaddr_str = prom_getenv("ethaddr");
124 if (!ethaddr_str) {
125 printk("ethaddr not set in boot prom\n");
126 return -1;
128 str2eaddr(ethernet_addr, ethaddr_str);
130 if (init_debug > 1) {
131 int i;
132 printk("get_ethernet_addr: ");
133 for (i=0; i<5; i++)
134 printk("%02x:", (unsigned char)*(ethernet_addr+i));
135 printk("%02x\n", *(ethernet_addr+i));
138 return 0;
141 #ifdef CONFIG_SERIAL_8250_CONSOLE
142 static void __init console_config(void)
144 char console_string[40];
145 int baud = 0;
146 char parity = '\0', bits = '\0', flow = '\0';
147 char *s;
149 if ((strstr(prom_getcmdline(), "console=")) == NULL) {
150 s = prom_getenv("modetty0");
151 if (s) {
152 while (*s >= '0' && *s <= '9')
153 baud = baud*10 + *s++ - '0';
154 if (*s == ',') s++;
155 if (*s) parity = *s++;
156 if (*s == ',') s++;
157 if (*s) bits = *s++;
158 if (*s == ',') s++;
159 if (*s == 'h') flow = 'r';
161 if (baud == 0)
162 baud = 38400;
163 if (parity != 'n' && parity != 'o' && parity != 'e')
164 parity = 'n';
165 if (bits != '7' && bits != '8')
166 bits = '8';
167 if (flow == '\0')
168 flow = 'r';
169 sprintf(console_string, " console=ttyS0,%d%c%c%c", baud, parity, bits, flow);
170 strcat(prom_getcmdline(), console_string);
171 pr_info("Config serial console:%s\n", console_string);
174 #endif
176 #ifdef CONFIG_KGDB
177 void __init kgdb_config(void)
179 extern int (*generic_putDebugChar)(char);
180 extern char (*generic_getDebugChar)(void);
181 char *argptr;
182 int line, speed;
184 argptr = prom_getcmdline();
185 if ((argptr = strstr(argptr, "kgdb=ttyS")) != NULL) {
186 argptr += strlen("kgdb=ttyS");
187 if (*argptr != '0' && *argptr != '1')
188 printk("KGDB: Unknown serial line /dev/ttyS%c, "
189 "falling back to /dev/ttyS1\n", *argptr);
190 line = *argptr == '0' ? 0 : 1;
191 printk("KGDB: Using serial line /dev/ttyS%d for session\n", line);
193 speed = 0;
194 if (*++argptr == ',')
196 int c;
197 while ((c = *++argptr) && ('0' <= c && c <= '9'))
198 speed = speed * 10 + c - '0';
200 #ifdef CONFIG_MIPS_ATLAS
201 if (line == 1) {
202 speed = saa9730_kgdb_hook(speed);
203 generic_putDebugChar = saa9730_putDebugChar;
204 generic_getDebugChar = saa9730_getDebugChar;
206 else
207 #endif
209 speed = rs_kgdb_hook(line, speed);
210 generic_putDebugChar = rs_putDebugChar;
211 generic_getDebugChar = rs_getDebugChar;
214 pr_info("KGDB: Using serial line /dev/ttyS%d at %d for "
215 "session, please connect your debugger\n",
216 line ? 1 : 0, speed);
219 char *s;
220 for (s = "Please connect GDB to this port\r\n"; *s; )
221 generic_putDebugChar(*s++);
224 /* Breakpoint is invoked after interrupts are initialised */
227 #endif
229 void __init mips_nmi_setup(void)
231 void *base;
232 extern char except_vec_nmi;
234 base = cpu_has_veic ?
235 (void *)(CAC_BASE + 0xa80) :
236 (void *)(CAC_BASE + 0x380);
237 memcpy(base, &except_vec_nmi, 0x80);
238 flush_icache_range((unsigned long)base, (unsigned long)base + 0x80);
241 void __init mips_ejtag_setup(void)
243 void *base;
244 extern char except_vec_ejtag_debug;
246 base = cpu_has_veic ?
247 (void *)(CAC_BASE + 0xa00) :
248 (void *)(CAC_BASE + 0x300);
249 memcpy(base, &except_vec_ejtag_debug, 0x80);
250 flush_icache_range((unsigned long)base, (unsigned long)base + 0x80);
253 extern struct plat_smp_ops msmtc_smp_ops;
255 void __init prom_init(void)
257 prom_argc = fw_arg0;
258 _prom_argv = (int *) fw_arg1;
259 _prom_envp = (int *) fw_arg2;
261 mips_display_message("LINUX");
263 #ifdef CONFIG_MIPS_SEAD
264 set_io_port_base(KSEG1);
265 #else
267 * early setup of _pcictrl_bonito so that we can determine
268 * the system controller on a CORE_EMUL board
270 _pcictrl_bonito = (unsigned long)ioremap(BONITO_REG_BASE, BONITO_REG_SIZE);
272 mips_revision_corid = MIPS_REVISION_CORID;
274 if (mips_revision_corid == MIPS_REVISION_CORID_CORE_EMUL) {
275 if (BONITO_PCIDID == 0x0001df53 ||
276 BONITO_PCIDID == 0x0003df53)
277 mips_revision_corid = MIPS_REVISION_CORID_CORE_EMUL_BON;
278 else
279 mips_revision_corid = MIPS_REVISION_CORID_CORE_EMUL_MSC;
282 mips_revision_sconid = MIPS_REVISION_SCONID;
283 if (mips_revision_sconid == MIPS_REVISION_SCON_OTHER) {
284 switch (mips_revision_corid) {
285 case MIPS_REVISION_CORID_QED_RM5261:
286 case MIPS_REVISION_CORID_CORE_LV:
287 case MIPS_REVISION_CORID_CORE_FPGA:
288 case MIPS_REVISION_CORID_CORE_FPGAR2:
289 mips_revision_sconid = MIPS_REVISION_SCON_GT64120;
290 break;
291 case MIPS_REVISION_CORID_CORE_EMUL_BON:
292 case MIPS_REVISION_CORID_BONITO64:
293 case MIPS_REVISION_CORID_CORE_20K:
294 mips_revision_sconid = MIPS_REVISION_SCON_BONITO;
295 break;
296 case MIPS_REVISION_CORID_CORE_MSC:
297 case MIPS_REVISION_CORID_CORE_FPGA2:
298 case MIPS_REVISION_CORID_CORE_FPGA3:
299 case MIPS_REVISION_CORID_CORE_FPGA4:
300 case MIPS_REVISION_CORID_CORE_24K:
301 case MIPS_REVISION_CORID_CORE_EMUL_MSC:
302 mips_revision_sconid = MIPS_REVISION_SCON_SOCIT;
303 break;
304 default:
305 mips_display_message("CC Error");
306 while (1); /* We die here... */
310 switch (mips_revision_sconid) {
311 u32 start, map, mask, data;
313 case MIPS_REVISION_SCON_GT64120:
315 * Setup the North bridge to do Master byte-lane swapping
316 * when running in bigendian.
318 _pcictrl_gt64120 = (unsigned long)ioremap(MIPS_GT_BASE, 0x2000);
320 #ifdef CONFIG_CPU_LITTLE_ENDIAN
321 GT_WRITE(GT_PCI0_CMD_OFS, GT_PCI0_CMD_MBYTESWAP_BIT |
322 GT_PCI0_CMD_SBYTESWAP_BIT);
323 #else
324 GT_WRITE(GT_PCI0_CMD_OFS, 0);
325 #endif
326 /* Fix up PCI I/O mapping if necessary (for Atlas). */
327 start = GT_READ(GT_PCI0IOLD_OFS);
328 map = GT_READ(GT_PCI0IOREMAP_OFS);
329 if ((start & map) != 0) {
330 map &= ~start;
331 GT_WRITE(GT_PCI0IOREMAP_OFS, map);
334 set_io_port_base(MALTA_GT_PORT_BASE);
335 break;
337 case MIPS_REVISION_SCON_BONITO:
338 _pcictrl_bonito_pcicfg = (unsigned long)ioremap(BONITO_PCICFG_BASE, BONITO_PCICFG_SIZE);
341 * Disable Bonito IOBC.
343 BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG &
344 ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
345 BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
348 * Setup the North bridge to do Master byte-lane swapping
349 * when running in bigendian.
351 #ifdef CONFIG_CPU_LITTLE_ENDIAN
352 BONITO_BONGENCFG = BONITO_BONGENCFG &
353 ~(BONITO_BONGENCFG_MSTRBYTESWAP |
354 BONITO_BONGENCFG_BYTESWAP);
355 #else
356 BONITO_BONGENCFG = BONITO_BONGENCFG |
357 BONITO_BONGENCFG_MSTRBYTESWAP |
358 BONITO_BONGENCFG_BYTESWAP;
359 #endif
361 set_io_port_base(MALTA_BONITO_PORT_BASE);
362 break;
364 case MIPS_REVISION_SCON_SOCIT:
365 case MIPS_REVISION_SCON_ROCIT:
366 _pcictrl_msc = (unsigned long)ioremap(MIPS_MSC01_PCI_REG_BASE, 0x2000);
367 mips_pci_controller:
368 mb();
369 MSC_READ(MSC01_PCI_CFG, data);
370 MSC_WRITE(MSC01_PCI_CFG, data & ~MSC01_PCI_CFG_EN_BIT);
371 wmb();
373 /* Fix up lane swapping. */
374 #ifdef CONFIG_CPU_LITTLE_ENDIAN
375 MSC_WRITE(MSC01_PCI_SWAP, MSC01_PCI_SWAP_NOSWAP);
376 #else
377 MSC_WRITE(MSC01_PCI_SWAP,
378 MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_IO_SHF |
379 MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_MEM_SHF |
380 MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_BAR0_SHF);
381 #endif
382 /* Fix up target memory mapping. */
383 MSC_READ(MSC01_PCI_BAR0, mask);
384 MSC_WRITE(MSC01_PCI_P2SCMSKL, mask & MSC01_PCI_BAR0_SIZE_MSK);
386 /* Don't handle target retries indefinitely. */
387 if ((data & MSC01_PCI_CFG_MAXRTRY_MSK) ==
388 MSC01_PCI_CFG_MAXRTRY_MSK)
389 data = (data & ~(MSC01_PCI_CFG_MAXRTRY_MSK <<
390 MSC01_PCI_CFG_MAXRTRY_SHF)) |
391 ((MSC01_PCI_CFG_MAXRTRY_MSK - 1) <<
392 MSC01_PCI_CFG_MAXRTRY_SHF);
394 wmb();
395 MSC_WRITE(MSC01_PCI_CFG, data);
396 mb();
398 set_io_port_base(MALTA_MSC_PORT_BASE);
399 break;
401 case MIPS_REVISION_SCON_SOCITSC:
402 case MIPS_REVISION_SCON_SOCITSCP:
403 _pcictrl_msc = (unsigned long)ioremap(MIPS_SOCITSC_PCI_REG_BASE, 0x2000);
404 goto mips_pci_controller;
406 default:
407 /* Unknown system controller */
408 mips_display_message("SC Error");
409 while (1); /* We die here... */
411 #endif
412 board_nmi_handler_setup = mips_nmi_setup;
413 board_ejtag_handler_setup = mips_ejtag_setup;
415 pr_info("\nLINUX started...\n");
416 prom_init_cmdline();
417 prom_meminit();
418 #ifdef CONFIG_SERIAL_8250_CONSOLE
419 console_config();
420 #endif
421 #ifdef CONFIG_MIPS_MT_SMP
422 register_smp_ops(&vsmp_smp_ops);
423 #endif
424 #ifdef CONFIG_MIPS_MT_SMTC
425 register_smp_ops(&msmtc_smp_ops);
426 #endif