2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
7 * Copyright (C) 1997, 1998, 1999, 2000 Ralf Baechle ralf@gnu.org
8 * Carsten Langgaard, carstenl@mips.com
9 * Copyright (C) 2002 MIPS Technologies, Inc. All rights reserved.
11 #include <linux/init.h>
12 #include <linux/sched.h>
16 #include <asm/bootinfo.h>
17 #include <asm/mmu_context.h>
18 #include <asm/pgtable.h>
19 #include <asm/system.h>
21 extern void build_tlb_refill_handler(void);
23 #define TFP_TLB_SIZE 384
24 #define TFP_TLB_SET_SHIFT 7
26 /* CP0 hazard avoidance. */
27 #define BARRIER __asm__ __volatile__(".set noreorder\n\t" \
28 "nop; nop; nop; nop; nop; nop;\n\t" \
31 void local_flush_tlb_all(void)
34 unsigned long old_ctx
;
37 local_irq_save(flags
);
38 /* Save old context and create impossible VPN2 value */
39 old_ctx
= read_c0_entryhi();
42 for (entry
= 0; entry
< TFP_TLB_SIZE
; entry
++) {
43 write_c0_tlbset(entry
>> TFP_TLB_SET_SHIFT
);
44 write_c0_vaddr(entry
<< PAGE_SHIFT
);
45 write_c0_entryhi(CKSEG0
+ (entry
<< (PAGE_SHIFT
+ 1)));
50 write_c0_entryhi(old_ctx
);
51 local_irq_restore(flags
);
54 void local_flush_tlb_mm(struct mm_struct
*mm
)
56 int cpu
= smp_processor_id();
58 if (cpu_context(cpu
, mm
) != 0)
59 drop_mmu_context(mm
, cpu
);
62 void local_flush_tlb_range(struct vm_area_struct
*vma
, unsigned long start
,
65 struct mm_struct
*mm
= vma
->vm_mm
;
66 int cpu
= smp_processor_id();
68 int oldpid
, newpid
, size
;
70 if (!cpu_context(cpu
, mm
))
73 size
= (end
- start
+ (PAGE_SIZE
- 1)) >> PAGE_SHIFT
;
74 size
= (size
+ 1) >> 1;
76 local_irq_save(flags
);
78 if (size
> TFP_TLB_SIZE
/ 2) {
79 drop_mmu_context(mm
, cpu
);
83 oldpid
= read_c0_entryhi();
84 newpid
= cpu_asid(cpu
, mm
);
89 end
+= (PAGE_SIZE
- 1);
94 write_c0_vaddr(start
);
95 write_c0_entryhi(start
);
98 idx
= read_c0_tlbset();
102 write_c0_entryhi(CKSEG0
+ (idx
<< (PAGE_SHIFT
+ 1)));
105 write_c0_entryhi(oldpid
);
108 local_irq_restore(flags
);
111 /* Usable for KV1 addresses only! */
112 void local_flush_tlb_kernel_range(unsigned long start
, unsigned long end
)
117 size
= (end
- start
+ (PAGE_SIZE
- 1)) >> PAGE_SHIFT
;
118 size
= (size
+ 1) >> 1;
120 if (size
> TFP_TLB_SIZE
/ 2) {
121 local_flush_tlb_all();
125 local_irq_save(flags
);
130 end
+= (PAGE_SIZE
- 1);
132 while (start
< end
) {
135 write_c0_vaddr(start
);
136 write_c0_entryhi(start
);
139 idx
= read_c0_tlbset();
143 write_c0_entryhi(CKSEG0
+ (idx
<< (PAGE_SHIFT
+ 1)));
147 local_irq_restore(flags
);
150 void local_flush_tlb_page(struct vm_area_struct
*vma
, unsigned long page
)
152 int cpu
= smp_processor_id();
157 if (!cpu_context(cpu
, vma
->vm_mm
))
160 newpid
= cpu_asid(cpu
, vma
->vm_mm
);
162 local_irq_save(flags
);
163 oldpid
= read_c0_entryhi();
164 write_c0_vaddr(page
);
165 write_c0_entryhi(newpid
);
167 idx
= read_c0_tlbset();
172 write_c0_entryhi(CKSEG0
+ (idx
<< (PAGE_SHIFT
+ 1)));
176 write_c0_entryhi(oldpid
);
177 local_irq_restore(flags
);
181 * We will need multiple versions of update_mmu_cache(), one that just
182 * updates the TLB with the new pte(s), and another which also checks
183 * for the R4k "end of page" hardware bug and does the needy.
185 void __update_tlb(struct vm_area_struct
* vma
, unsigned long address
, pte_t pte
)
194 * Handle debugger faulting in for debugee.
196 if (current
->active_mm
!= vma
->vm_mm
)
199 pid
= read_c0_entryhi() & ASID_MASK
;
201 local_irq_save(flags
);
202 address
&= PAGE_MASK
;
203 write_c0_vaddr(address
);
204 write_c0_entryhi(pid
);
205 pgdp
= pgd_offset(vma
->vm_mm
, address
);
206 pmdp
= pmd_offset(pgdp
, address
);
207 ptep
= pte_offset_map(pmdp
, address
);
210 write_c0_entrylo(pte_val(*ptep
++) >> 6);
213 write_c0_entryhi(pid
);
214 local_irq_restore(flags
);
217 <<<<<<< HEAD
:arch
/mips
/mm
/tlb
-r8k
.c
218 static void __init
probe_tlb(unsigned long config
)
220 static void __cpuinit
probe_tlb(unsigned long config
)
221 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a
:arch
/mips
/mm
/tlb
-r8k
.c
223 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
225 c
->tlbsize
= 3 * 128; /* 3 sets each 128 entries */
228 <<<<<<< HEAD
:arch
/mips
/mm
/tlb
-r8k
.c
229 void __init
tlb_init(void)
231 void __cpuinit
tlb_init(void)
232 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a
:arch
/mips
/mm
/tlb
-r8k
.c
234 unsigned int config
= read_c0_config();
235 unsigned long status
;
239 status
= read_c0_status();
240 status
&= ~(ST0_UPS
| ST0_KPS
);
241 #ifdef CONFIG_PAGE_SIZE_4KB
242 status
|= (TFP_PAGESIZE_4K
<< 32) | (TFP_PAGESIZE_4K
<< 36);
243 #elif defined(CONFIG_PAGE_SIZE_8KB)
244 status
|= (TFP_PAGESIZE_8K
<< 32) | (TFP_PAGESIZE_8K
<< 36);
245 #elif defined(CONFIG_PAGE_SIZE_16KB)
246 status
|= (TFP_PAGESIZE_16K
<< 32) | (TFP_PAGESIZE_16K
<< 36);
247 #elif defined(CONFIG_PAGE_SIZE_64KB)
248 status
|= (TFP_PAGESIZE_64K
<< 32) | (TFP_PAGESIZE_64K
<< 36);
250 write_c0_status(status
);
254 local_flush_tlb_all();
256 build_tlb_refill_handler();