arch/mips/mm/uasm.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * A small micro-assembler. It is intentionally kept simple, does only
   7  * support a subset of instructions, and does not try to hide pipeline
   8  * effects like branch delay slots.
   9  *
  10  * Copyright (C) 2004, 2005, 2006, 2008  Thiemo Seufer
  11  * Copyright (C) 2005, 2007  Maciej W. Rozycki
  12  * Copyright (C) 2006  Ralf Baechle (ralf@linux-mips.org)
  13  */
  14
  15 #include <linux/kernel.h>
  16 #include <linux/types.h>
  17 #include <linux/init.h>
  18
  19 #include <asm/inst.h>
  20 #include <asm/elf.h>
  21 #include <asm/bugs.h>
  22
  23 #include "uasm.h"
  24
  25 enum fields {
  26         RS = 0x001,
  27         RT = 0x002,
  28         RD = 0x004,
  29         RE = 0x008,
  30         SIMM = 0x010,
  31         UIMM = 0x020,
  32         BIMM = 0x040,
  33         JIMM = 0x080,
  34         FUNC = 0x100,
  35         SET = 0x200
  36 };
  37
  38 #define OP_MASK         0x3f
  39 #define OP_SH           26
  40 #define RS_MASK         0x1f
  41 #define RS_SH           21
  42 #define RT_MASK         0x1f
  43 #define RT_SH           16
  44 #define RD_MASK         0x1f
  45 #define RD_SH           11
  46 #define RE_MASK         0x1f
  47 #define RE_SH           6
  48 #define IMM_MASK        0xffff
  49 #define IMM_SH          0
  50 #define JIMM_MASK       0x3ffffff
  51 #define JIMM_SH         0
  52 #define FUNC_MASK       0x3f
  53 #define FUNC_SH         0
  54 #define SET_MASK        0x7
  55 #define SET_SH          0
  56
  57 enum opcode {
  58         insn_invalid,
  59         insn_addu, insn_addiu, insn_and, insn_andi, insn_beq,
  60         insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl,
  61         insn_bne, insn_daddu, insn_daddiu, insn_dmfc0, insn_dmtc0,
  62         insn_dsll, insn_dsll32, insn_dsra, insn_dsrl, insn_dsrl32,
  63         insn_dsubu, insn_eret, insn_j, insn_jal, insn_jr, insn_ld,
  64         insn_ll, insn_lld, insn_lui, insn_lw, insn_mfc0, insn_mtc0,
  65         insn_ori, insn_rfe, insn_sc, insn_scd, insn_sd, insn_sll,
  66         insn_sra, insn_srl, insn_subu, insn_sw, insn_tlbp, insn_tlbwi,
  67         insn_tlbwr, insn_xor, insn_xori
  68 };
  69
  70 struct insn {
  71         enum opcode opcode;
  72         u32 match;
  73         enum fields fields;
  74 };
  75
  76 /* This macro sets the non-variable bits of an instruction. */
  77 #define M(a, b, c, d, e, f)                                     \
  78         ((a) << OP_SH                                           \
  79          | (b) << RS_SH                                         \
  80          | (c) << RT_SH                                         \
  81          | (d) << RD_SH                                         \
  82          | (e) << RE_SH                                         \
  83          | (f) << FUNC_SH)
  84
  85 <<<<<<< HEAD:arch/mips/mm/uasm.c
  86 static struct insn insn_table[] __initdata = {
  87 =======
  88 static struct insn insn_table[] __cpuinitdata = {
  89 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/mips/mm/uasm.c
  90         { insn_addiu, M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
  91         { insn_addu, M(spec_op, 0, 0, 0, 0, addu_op), RS | RT | RD },
  92         { insn_and, M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD },
  93         { insn_andi, M(andi_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
  94         { insn_beq, M(beq_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
  95         { insn_beql, M(beql_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
  96         { insn_bgez, M(bcond_op, 0, bgez_op, 0, 0, 0), RS | BIMM },
  97         { insn_bgezl, M(bcond_op, 0, bgezl_op, 0, 0, 0), RS | BIMM },
  98         { insn_bltz, M(bcond_op, 0, bltz_op, 0, 0, 0), RS | BIMM },
  99         { insn_bltzl, M(bcond_op, 0, bltzl_op, 0, 0, 0), RS | BIMM },
 100         { insn_bne, M(bne_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
 101         { insn_daddiu, M(daddiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
 102         { insn_daddu, M(spec_op, 0, 0, 0, 0, daddu_op), RS | RT | RD },
 103         { insn_dmfc0, M(cop0_op, dmfc_op, 0, 0, 0, 0), RT | RD | SET},
 104         { insn_dmtc0, M(cop0_op, dmtc_op, 0, 0, 0, 0), RT | RD | SET},
 105         { insn_dsll, M(spec_op, 0, 0, 0, 0, dsll_op), RT | RD | RE },
 106         { insn_dsll32, M(spec_op, 0, 0, 0, 0, dsll32_op), RT | RD | RE },
 107         { insn_dsra, M(spec_op, 0, 0, 0, 0, dsra_op), RT | RD | RE },
 108         { insn_dsrl, M(spec_op, 0, 0, 0, 0, dsrl_op), RT | RD | RE },
 109         { insn_dsrl32, M(spec_op, 0, 0, 0, 0, dsrl32_op), RT | RD | RE },
 110         { insn_dsubu, M(spec_op, 0, 0, 0, 0, dsubu_op), RS | RT | RD },
 111         { insn_eret,  M(cop0_op, cop_op, 0, 0, 0, eret_op),  0 },
 112         { insn_j,  M(j_op, 0, 0, 0, 0, 0),  JIMM },
 113         { insn_jal,  M(jal_op, 0, 0, 0, 0, 0),  JIMM },
 114         { insn_jr,  M(spec_op, 0, 0, 0, 0, jr_op),  RS },
 115         { insn_ld,  M(ld_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
 116         { insn_ll,  M(ll_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
 117         { insn_lld,  M(lld_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
 118         { insn_lui,  M(lui_op, 0, 0, 0, 0, 0),  RT | SIMM },
 119         { insn_lw,  M(lw_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
 120         { insn_mfc0,  M(cop0_op, mfc_op, 0, 0, 0, 0),  RT | RD | SET},
 121         { insn_mtc0,  M(cop0_op, mtc_op, 0, 0, 0, 0),  RT | RD | SET},
 122         { insn_ori,  M(ori_op, 0, 0, 0, 0, 0),  RS | RT | UIMM },
 123         { insn_rfe,  M(cop0_op, cop_op, 0, 0, 0, rfe_op),  0 },
 124         { insn_sc,  M(sc_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
 125         { insn_scd,  M(scd_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
 126         { insn_sd,  M(sd_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
 127         { insn_sll,  M(spec_op, 0, 0, 0, 0, sll_op),  RT | RD | RE },
 128         { insn_sra,  M(spec_op, 0, 0, 0, 0, sra_op),  RT | RD | RE },
 129         { insn_srl,  M(spec_op, 0, 0, 0, 0, srl_op),  RT | RD | RE },
 130         { insn_subu,  M(spec_op, 0, 0, 0, 0, subu_op),  RS | RT | RD },
 131         { insn_sw,  M(sw_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
 132         { insn_tlbp,  M(cop0_op, cop_op, 0, 0, 0, tlbp_op),  0 },
 133         { insn_tlbwi,  M(cop0_op, cop_op, 0, 0, 0, tlbwi_op),  0 },
 134         { insn_tlbwr,  M(cop0_op, cop_op, 0, 0, 0, tlbwr_op),  0 },
 135         { insn_xor,  M(spec_op, 0, 0, 0, 0, xor_op),  RS | RT | RD },
 136         { insn_xori,  M(xori_op, 0, 0, 0, 0, 0),  RS | RT | UIMM },
 137         { insn_invalid, 0, 0 }
 138 };
 139
 140 #undef M
 141
 142 <<<<<<< HEAD:arch/mips/mm/uasm.c
 143 static inline __init u32 build_rs(u32 arg)
 144 =======
 145 static inline __cpuinit u32 build_rs(u32 arg)
 146 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/mips/mm/uasm.c
 147 {
 148         if (arg & ~RS_MASK)
 149                 printk(KERN_WARNING "Micro-assembler field overflow\n");
 150
 151         return (arg & RS_MASK) << RS_SH;
 152 }
 153
 154 <<<<<<< HEAD:arch/mips/mm/uasm.c
 155 static inline __init u32 build_rt(u32 arg)
 156 =======
 157 static inline __cpuinit u32 build_rt(u32 arg)
 158 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/mips/mm/uasm.c
 159 {
 160         if (arg & ~RT_MASK)
 161                 printk(KERN_WARNING "Micro-assembler field overflow\n");
 162
 163         return (arg & RT_MASK) << RT_SH;
 164 }
 165
 166 <<<<<<< HEAD:arch/mips/mm/uasm.c
 167 static inline __init u32 build_rd(u32 arg)
 168 =======
 169 static inline __cpuinit u32 build_rd(u32 arg)
 170 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/mips/mm/uasm.c
 171 {
 172         if (arg & ~RD_MASK)
 173                 printk(KERN_WARNING "Micro-assembler field overflow\n");
 174
 175         return (arg & RD_MASK) << RD_SH;
 176 }
 177
 178 <<<<<<< HEAD:arch/mips/mm/uasm.c
 179 static inline __init u32 build_re(u32 arg)
 180 =======
 181 static inline __cpuinit u32 build_re(u32 arg)
 182 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/mips/mm/uasm.c
 183 {
 184         if (arg & ~RE_MASK)
 185                 printk(KERN_WARNING "Micro-assembler field overflow\n");
 186
 187         return (arg & RE_MASK) << RE_SH;
 188 }
 189
 190 <<<<<<< HEAD:arch/mips/mm/uasm.c
 191 static inline __init u32 build_simm(s32 arg)
 192 =======
 193 static inline __cpuinit u32 build_simm(s32 arg)
 194 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/mips/mm/uasm.c
 195 {
 196         if (arg > 0x7fff || arg < -0x8000)
 197                 printk(KERN_WARNING "Micro-assembler field overflow\n");
 198
 199         return arg & 0xffff;
 200 }
 201
 202 <<<<<<< HEAD:arch/mips/mm/uasm.c
 203 static inline __init u32 build_uimm(u32 arg)
 204 =======
 205 static inline __cpuinit u32 build_uimm(u32 arg)
 206 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/mips/mm/uasm.c
 207 {
 208         if (arg & ~IMM_MASK)
 209                 printk(KERN_WARNING "Micro-assembler field overflow\n");
 210
 211         return arg & IMM_MASK;
 212 }
 213
 214 <<<<<<< HEAD:arch/mips/mm/uasm.c
 215 static inline __init u32 build_bimm(s32 arg)
 216 =======
 217 static inline __cpuinit u32 build_bimm(s32 arg)
 218 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/mips/mm/uasm.c
 219 {
 220         if (arg > 0x1ffff || arg < -0x20000)
 221                 printk(KERN_WARNING "Micro-assembler field overflow\n");
 222
 223         if (arg & 0x3)
 224                 printk(KERN_WARNING "Invalid micro-assembler branch target\n");
 225
 226         return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 2) & 0x7fff);
 227 }
 228
 229 <<<<<<< HEAD:arch/mips/mm/uasm.c
 230 static inline __init u32 build_jimm(u32 arg)
 231 =======
 232 static inline __cpuinit u32 build_jimm(u32 arg)
 233 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/mips/mm/uasm.c
 234 {
 235         if (arg & ~((JIMM_MASK) << 2))
 236                 printk(KERN_WARNING "Micro-assembler field overflow\n");
 237
 238         return (arg >> 2) & JIMM_MASK;
 239 }
 240
 241 <<<<<<< HEAD:arch/mips/mm/uasm.c
 242 static inline __init u32 build_func(u32 arg)
 243 =======
 244 static inline __cpuinit u32 build_func(u32 arg)
 245 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/mips/mm/uasm.c
 246 {
 247         if (arg & ~FUNC_MASK)
 248                 printk(KERN_WARNING "Micro-assembler field overflow\n");
 249
 250         return arg & FUNC_MASK;
 251 }
 252
 253 <<<<<<< HEAD:arch/mips/mm/uasm.c
 254 static inline __init u32 build_set(u32 arg)
 255 =======
 256 static inline __cpuinit u32 build_set(u32 arg)
 257 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/mips/mm/uasm.c
 258 {
 259         if (arg & ~SET_MASK)
 260                 printk(KERN_WARNING "Micro-assembler field overflow\n");
 261
 262         return arg & SET_MASK;
 263 }
 264
 265 /*
 266  * The order of opcode arguments is implicitly left to right,
 267  * starting with RS and ending with FUNC or IMM.
 268  */
 269 <<<<<<< HEAD:arch/mips/mm/uasm.c
 270 static void __init build_insn(u32 **buf, enum opcode opc, ...)
 271 =======
 272 static void __cpuinit build_insn(u32 **buf, enum opcode opc, ...)
 273 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/mips/mm/uasm.c
 274 {
 275         struct insn *ip = NULL;
 276         unsigned int i;
 277         va_list ap;
 278         u32 op;
 279
 280         for (i = 0; insn_table[i].opcode != insn_invalid; i++)
 281                 if (insn_table[i].opcode == opc) {
 282                         ip = &insn_table[i];
 283                         break;
 284                 }
 285
 286         if (!ip || (opc == insn_daddiu && r4k_daddiu_bug()))
 287                 panic("Unsupported Micro-assembler instruction %d", opc);
 288
 289         op = ip->match;
 290         va_start(ap, opc);
 291         if (ip->fields & RS)
 292                 op |= build_rs(va_arg(ap, u32));
 293         if (ip->fields & RT)
 294                 op |= build_rt(va_arg(ap, u32));
 295         if (ip->fields & RD)
 296                 op |= build_rd(va_arg(ap, u32));
 297         if (ip->fields & RE)
 298                 op |= build_re(va_arg(ap, u32));
 299         if (ip->fields & SIMM)
 300                 op |= build_simm(va_arg(ap, s32));
 301         if (ip->fields & UIMM)
 302                 op |= build_uimm(va_arg(ap, u32));
 303         if (ip->fields & BIMM)
 304                 op |= build_bimm(va_arg(ap, s32));
 305         if (ip->fields & JIMM)
 306                 op |= build_jimm(va_arg(ap, u32));
 307         if (ip->fields & FUNC)
 308                 op |= build_func(va_arg(ap, u32));
 309         if (ip->fields & SET)
 310                 op |= build_set(va_arg(ap, u32));
 311         va_end(ap);
 312
 313         **buf = op;
 314         (*buf)++;
 315 }
 316
 317 #define I_u1u2u3(op)                                    \
 318 Ip_u1u2u3(op)                                           \
 319 {                                                       \
 320         build_insn(buf, insn##op, a, b, c);             \
 321 }
 322
 323 #define I_u2u1u3(op)                                    \
 324 Ip_u2u1u3(op)                                           \
 325 {                                                       \
 326         build_insn(buf, insn##op, b, a, c);             \
 327 }
 328
 329 #define I_u3u1u2(op)                                    \
 330 Ip_u3u1u2(op)                                           \
 331 {                                                       \
 332         build_insn(buf, insn##op, b, c, a);             \
 333 }
 334
 335 #define I_u1u2s3(op)                                    \
 336 Ip_u1u2s3(op)                                           \
 337 {                                                       \
 338         build_insn(buf, insn##op, a, b, c);             \
 339 }
 340
 341 #define I_u2s3u1(op)                                    \
 342 Ip_u2s3u1(op)                                           \
 343 {                                                       \
 344         build_insn(buf, insn##op, c, a, b);             \
 345 }
 346
 347 #define I_u2u1s3(op)                                    \
 348 Ip_u2u1s3(op)                                           \
 349 {                                                       \
 350         build_insn(buf, insn##op, b, a, c);             \
 351 }
 352
 353 #define I_u1u2(op)                                      \
 354 Ip_u1u2(op)                                             \
 355 {                                                       \
 356         build_insn(buf, insn##op, a, b);                \
 357 }
 358
 359 #define I_u1s2(op)                                      \
 360 Ip_u1s2(op)                                             \
 361 {                                                       \
 362         build_insn(buf, insn##op, a, b);                \
 363 }
 364
 365 #define I_u1(op)                                        \
 366 Ip_u1(op)                                               \
 367 {                                                       \
 368         build_insn(buf, insn##op, a);                   \
 369 }
 370
 371 #define I_0(op)                                         \
 372 Ip_0(op)                                                \
 373 {                                                       \
 374         build_insn(buf, insn##op);                      \
 375 }
 376
 377 I_u2u1s3(_addiu)
 378 I_u3u1u2(_addu)
 379 I_u2u1u3(_andi)
 380 I_u3u1u2(_and)
 381 I_u1u2s3(_beq)
 382 I_u1u2s3(_beql)
 383 I_u1s2(_bgez)
 384 I_u1s2(_bgezl)
 385 I_u1s2(_bltz)
 386 I_u1s2(_bltzl)
 387 I_u1u2s3(_bne)
 388 I_u1u2u3(_dmfc0)
 389 I_u1u2u3(_dmtc0)
 390 I_u2u1s3(_daddiu)
 391 I_u3u1u2(_daddu)
 392 I_u2u1u3(_dsll)
 393 I_u2u1u3(_dsll32)
 394 I_u2u1u3(_dsra)
 395 I_u2u1u3(_dsrl)
 396 I_u2u1u3(_dsrl32)
 397 I_u3u1u2(_dsubu)
 398 I_0(_eret)
 399 I_u1(_j)
 400 I_u1(_jal)
 401 I_u1(_jr)
 402 I_u2s3u1(_ld)
 403 I_u2s3u1(_ll)
 404 I_u2s3u1(_lld)
 405 I_u1s2(_lui)
 406 I_u2s3u1(_lw)
 407 I_u1u2u3(_mfc0)
 408 I_u1u2u3(_mtc0)
 409 I_u2u1u3(_ori)
 410 I_0(_rfe)
 411 I_u2s3u1(_sc)
 412 I_u2s3u1(_scd)
 413 I_u2s3u1(_sd)
 414 I_u2u1u3(_sll)
 415 I_u2u1u3(_sra)
 416 I_u2u1u3(_srl)
 417 I_u3u1u2(_subu)
 418 I_u2s3u1(_sw)
 419 I_0(_tlbp)
 420 I_0(_tlbwi)
 421 I_0(_tlbwr)
 422 I_u3u1u2(_xor)
 423 I_u2u1u3(_xori)
 424
 425 /* Handle labels. */
 426 <<<<<<< HEAD:arch/mips/mm/uasm.c
 427 void __init uasm_build_label(struct uasm_label **lab, u32 *addr, int lid)
 428 =======
 429 void __cpuinit uasm_build_label(struct uasm_label **lab, u32 *addr, int lid)
 430 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/mips/mm/uasm.c
 431 {
 432         (*lab)->addr = addr;
 433         (*lab)->lab = lid;
 434         (*lab)++;
 435 }
 436
 437 <<<<<<< HEAD:arch/mips/mm/uasm.c
 438 int __init uasm_in_compat_space_p(long addr)
 439 =======
 440 int __cpuinit uasm_in_compat_space_p(long addr)
 441 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/mips/mm/uasm.c
 442 {
 443         /* Is this address in 32bit compat space? */
 444 #ifdef CONFIG_64BIT
 445         return (((addr) & 0xffffffff00000000L) == 0xffffffff00000000L);
 446 #else
 447         return 1;
 448 #endif
 449 }
 450
 451 <<<<<<< HEAD:arch/mips/mm/uasm.c
 452 int __init uasm_rel_highest(long val)
 453 =======
 454 int __cpuinit uasm_rel_highest(long val)
 455 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/mips/mm/uasm.c
 456 {
 457 #ifdef CONFIG_64BIT
 458         return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000;
 459 #else
 460         return 0;
 461 #endif
 462 }
 463
 464 <<<<<<< HEAD:arch/mips/mm/uasm.c
 465 int __init uasm_rel_higher(long val)
 466 =======
 467 int __cpuinit uasm_rel_higher(long val)
 468 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/mips/mm/uasm.c
 469 {
 470 #ifdef CONFIG_64BIT
 471         return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000;
 472 #else
 473         return 0;
 474 #endif
 475 }
 476
 477 <<<<<<< HEAD:arch/mips/mm/uasm.c
 478 int __init uasm_rel_hi(long val)
 479 =======
 480 int __cpuinit uasm_rel_hi(long val)
 481 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/mips/mm/uasm.c
 482 {
 483         return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000;
 484 }
 485
 486 <<<<<<< HEAD:arch/mips/mm/uasm.c
 487 int __init uasm_rel_lo(long val)
 488 =======
 489 int __cpuinit uasm_rel_lo(long val)
 490 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/mips/mm/uasm.c
 491 {
 492         return ((val & 0xffff) ^ 0x8000) - 0x8000;
 493 }
 494
 495 <<<<<<< HEAD:arch/mips/mm/uasm.c
 496 void __init UASM_i_LA_mostly(u32 **buf, unsigned int rs, long addr)
 497 =======
 498 void __cpuinit UASM_i_LA_mostly(u32 **buf, unsigned int rs, long addr)
 499 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/mips/mm/uasm.c
 500 {
 501         if (!uasm_in_compat_space_p(addr)) {
 502                 uasm_i_lui(buf, rs, uasm_rel_highest(addr));
 503                 if (uasm_rel_higher(addr))
 504                         uasm_i_daddiu(buf, rs, rs, uasm_rel_higher(addr));
 505                 if (uasm_rel_hi(addr)) {
 506                         uasm_i_dsll(buf, rs, rs, 16);
 507                         uasm_i_daddiu(buf, rs, rs, uasm_rel_hi(addr));
 508                         uasm_i_dsll(buf, rs, rs, 16);
 509                 } else
 510                         uasm_i_dsll32(buf, rs, rs, 0);
 511         } else
 512                 uasm_i_lui(buf, rs, uasm_rel_hi(addr));
 513 }
 514
 515 <<<<<<< HEAD:arch/mips/mm/uasm.c
 516 void __init UASM_i_LA(u32 **buf, unsigned int rs, long addr)
 517 =======
 518 void __cpuinit UASM_i_LA(u32 **buf, unsigned int rs, long addr)
 519 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/mips/mm/uasm.c
 520 {
 521         UASM_i_LA_mostly(buf, rs, addr);
 522         if (uasm_rel_lo(addr)) {
 523                 if (!uasm_in_compat_space_p(addr))
 524                         uasm_i_daddiu(buf, rs, rs, uasm_rel_lo(addr));
 525                 else
 526                         uasm_i_addiu(buf, rs, rs, uasm_rel_lo(addr));
 527         }
 528 }
 529
 530 /* Handle relocations. */
 531 <<<<<<< HEAD:arch/mips/mm/uasm.c
 532 void __init
 533 =======
 534 void __cpuinit
 535 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/mips/mm/uasm.c
 536 uasm_r_mips_pc16(struct uasm_reloc **rel, u32 *addr, int lid)
 537 {
 538         (*rel)->addr = addr;
 539         (*rel)->type = R_MIPS_PC16;
 540         (*rel)->lab = lid;
 541         (*rel)++;
 542 }
 543
 544 <<<<<<< HEAD:arch/mips/mm/uasm.c
 545 static inline void __init
 546 =======
 547 static inline void __cpuinit
 548 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/mips/mm/uasm.c
 549 __resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab)
 550 {
 551         long laddr = (long)lab->addr;
 552         long raddr = (long)rel->addr;
 553
 554         switch (rel->type) {
 555         case R_MIPS_PC16:
 556                 *rel->addr |= build_bimm(laddr - (raddr + 4));
 557                 break;
 558
 559         default:
 560                 panic("Unsupported Micro-assembler relocation %d",
 561                       rel->type);
 562         }
 563 }
 564
 565 <<<<<<< HEAD:arch/mips/mm/uasm.c
 566 void __init
 567 =======
 568 void __cpuinit
 569 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/mips/mm/uasm.c
 570 uasm_resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab)
 571 {
 572         struct uasm_label *l;
 573
 574         for (; rel->lab != UASM_LABEL_INVALID; rel++)
 575                 for (l = lab; l->lab != UASM_LABEL_INVALID; l++)
 576                         if (rel->lab == l->lab)
 577                                 __resolve_relocs(rel, l);
 578 }
 579
 580 <<<<<<< HEAD:arch/mips/mm/uasm.c
 581 void __init
 582 =======
 583 void __cpuinit
 584 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/mips/mm/uasm.c
 585 uasm_move_relocs(struct uasm_reloc *rel, u32 *first, u32 *end, long off)
 586 {
 587         for (; rel->lab != UASM_LABEL_INVALID; rel++)
 588                 if (rel->addr >= first && rel->addr < end)
 589                         rel->addr += off;
 590 }
 591
 592 <<<<<<< HEAD:arch/mips/mm/uasm.c
 593 void __init
 594 =======
 595 void __cpuinit
 596 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/mips/mm/uasm.c
 597 uasm_move_labels(struct uasm_label *lab, u32 *first, u32 *end, long off)
 598 {
 599         for (; lab->lab != UASM_LABEL_INVALID; lab++)
 600                 if (lab->addr >= first && lab->addr < end)
 601                         lab->addr += off;
 602 }
 603
 604 <<<<<<< HEAD:arch/mips/mm/uasm.c
 605 void __init
 606 =======
 607 void __cpuinit
 608 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/mips/mm/uasm.c
 609 uasm_copy_handler(struct uasm_reloc *rel, struct uasm_label *lab, u32 *first,
 610                   u32 *end, u32 *target)
 611 {
 612         long off = (long)(target - first);
 613
 614         memcpy(target, first, (end - first) * sizeof(u32));
 615
 616         uasm_move_relocs(rel, first, end, off);
 617         uasm_move_labels(lab, first, end, off);
 618 }
 619
 620 <<<<<<< HEAD:arch/mips/mm/uasm.c
 621 int __init uasm_insn_has_bdelay(struct uasm_reloc *rel, u32 *addr)
 622 =======
 623 int __cpuinit uasm_insn_has_bdelay(struct uasm_reloc *rel, u32 *addr)
 624 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/mips/mm/uasm.c
 625 {
 626         for (; rel->lab != UASM_LABEL_INVALID; rel++) {
 627                 if (rel->addr == addr
 628                     && (rel->type == R_MIPS_PC16
 629                         || rel->type == R_MIPS_26))
 630                         return 1;
 631         }
 632
 633         return 0;
 634 }
 635
 636 /* Convenience functions for labeled branches. */
 637 <<<<<<< HEAD:arch/mips/mm/uasm.c
 638 void __init
 639 =======
 640 void __cpuinit
 641 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/mips/mm/uasm.c
 642 uasm_il_bltz(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
 643 {
 644         uasm_r_mips_pc16(r, *p, lid);
 645         uasm_i_bltz(p, reg, 0);
 646 }
 647
 648 <<<<<<< HEAD:arch/mips/mm/uasm.c
 649 void __init
 650 =======
 651 void __cpuinit
 652 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/mips/mm/uasm.c
 653 uasm_il_b(u32 **p, struct uasm_reloc **r, int lid)
 654 {
 655         uasm_r_mips_pc16(r, *p, lid);
 656         uasm_i_b(p, 0);
 657 }
 658
 659 <<<<<<< HEAD:arch/mips/mm/uasm.c
 660 void __init
 661 =======
 662 void __cpuinit
 663 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/mips/mm/uasm.c
 664 uasm_il_beqz(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
 665 {
 666         uasm_r_mips_pc16(r, *p, lid);
 667         uasm_i_beqz(p, reg, 0);
 668 }
 669
 670 <<<<<<< HEAD:arch/mips/mm/uasm.c
 671 void __init
 672 =======
 673 void __cpuinit
 674 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/mips/mm/uasm.c
 675 uasm_il_beqzl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
 676 {
 677         uasm_r_mips_pc16(r, *p, lid);
 678         uasm_i_beqzl(p, reg, 0);
 679 }
 680
 681 <<<<<<< HEAD:arch/mips/mm/uasm.c
 682 void __init
 683 =======
 684 void __cpuinit
 685 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/mips/mm/uasm.c
 686 uasm_il_bnez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
 687 {
 688         uasm_r_mips_pc16(r, *p, lid);
 689         uasm_i_bnez(p, reg, 0);
 690 }
 691
 692 <<<<<<< HEAD:arch/mips/mm/uasm.c
 693 void __init
 694 =======
 695 void __cpuinit
 696 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/mips/mm/uasm.c
 697 uasm_il_bgezl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
 698 {
 699         uasm_r_mips_pc16(r, *p, lid);
 700         uasm_i_bgezl(p, reg, 0);
 701 }
 702
 703 <<<<<<< HEAD:arch/mips/mm/uasm.c
 704 void __init
 705 =======
 706 void __cpuinit
 707 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/mips/mm/uasm.c
 708 uasm_il_bgez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
 709 {
 710         uasm_r_mips_pc16(r, *p, lid);
 711         uasm_i_bgez(p, reg, 0);
 712 }