arch/mips/pci/ops-mace.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2000, 2001 Keith M Wesolowski
   7  */
   8 #include <linux/kernel.h>
   9 #include <linux/init.h>
  10 #include <linux/pci.h>
  11 #include <linux/types.h>
  12 #include <asm/pci.h>
  13 #include <asm/ip32/mace.h>
  14
  15 #if 0
  16 # define DPRINTK(args...) printk(args);
  17 #else
  18 # define DPRINTK(args...)
  19 #endif
  20
  21 /*
  22  * O2 has up to 5 PCI devices connected into the MACE bridge.  The device
  23  * map looks like this:
  24  *
  25  * 0  aic7xxx 0
  26  * 1  aic7xxx 1
  27  * 2  expansion slot
  28  * 3  N/C
  29  * 4  N/C
  30  */
  31
  32 static inline int mkaddr(struct pci_bus *bus, unsigned int devfn,
  33         unsigned int reg)
  34 {
  35         return ((bus->number & 0xff) << 16) |
  36                 ((devfn & 0xff) << 8) |
  37                 (reg & 0xfc);
  38 }
  39
  40
  41 static int
  42 mace_pci_read_config(struct pci_bus *bus, unsigned int devfn,
  43                      int reg, int size, u32 *val)
  44 {
  45         u32 control = mace->pci.control;
  46
  47         /* disable master aborts interrupts during config read */
  48         mace->pci.control = control & ~MACEPCI_CONTROL_MAR_INT;
  49         mace->pci.config_addr = mkaddr(bus, devfn, reg);
  50         switch (size) {
  51         case 1:
  52                 *val = mace->pci.config_data.b[(reg & 3) ^ 3];
  53                 break;
  54         case 2:
  55                 *val = mace->pci.config_data.w[((reg >> 1) & 1) ^ 1];
  56                 break;
  57         case 4:
  58                 *val = mace->pci.config_data.l;
  59                 break;
  60         }
  61         /* ack possible master abort */
  62         mace->pci.error &= ~MACEPCI_ERROR_MASTER_ABORT;
  63         mace->pci.control = control;
  64
  65         DPRINTK("read%d: reg=%08x,val=%02x\n", size * 8, reg, *val);
  66
  67         return PCIBIOS_SUCCESSFUL;
  68 }
  69
  70 static int
  71 mace_pci_write_config(struct pci_bus *bus, unsigned int devfn,
  72                       int reg, int size, u32 val)
  73 {
  74         mace->pci.config_addr = mkaddr(bus, devfn, reg);
  75         switch (size) {
  76         case 1:
  77                 mace->pci.config_data.b[(reg & 3) ^ 3] = val;
  78                 break;
  79         case 2:
  80                 mace->pci.config_data.w[((reg >> 1) & 1) ^ 1] = val;
  81                 break;
  82         case 4:
  83                 mace->pci.config_data.l = val;
  84                 break;
  85         }
  86
  87         DPRINTK("write%d: reg=%08x,val=%02x\n", size * 8, reg, val);
  88
  89         return PCIBIOS_SUCCESSFUL;
  90 }
  91
  92 struct pci_ops mace_pci_ops = {
  93         .read = mace_pci_read_config,
  94         .write = mace_pci_write_config,
  95 };