arch/mips/pci/pci-ip27.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2003 Christoph Hellwig (hch@lst.de)
   7  * Copyright (C) 1999, 2000, 04 Ralf Baechle (ralf@linux-mips.org)
   8  * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
   9  */
  10 #include <linux/init.h>
  11 #include <linux/kernel.h>
  12 #include <linux/pci.h>
  13 #include <asm/sn/arch.h>
  14 #include <asm/pci/bridge.h>
  15 #include <asm/paccess.h>
  16 #include <asm/sn/intr.h>
  17 #include <asm/sn/sn0/hub.h>
  18
  19 /*
  20  * Max #PCI busses we can handle; ie, max #PCI bridges.
  21  */
  22 #define MAX_PCI_BUSSES          40
  23
  24 /*
  25  * Max #PCI devices (like scsi controllers) we handle on a bus.
  26  */
  27 #define MAX_DEVICES_PER_PCIBUS  8
  28
  29 /*
  30  * XXX: No kmalloc available when we do our crosstalk scan,
  31  *      we should try to move it later in the boot process.
  32  */
  33 static struct bridge_controller bridges[MAX_PCI_BUSSES];
  34
  35 /*
  36  * Translate from irq to software PCI bus number and PCI slot.
  37  */
  38 struct bridge_controller *irq_to_bridge[MAX_PCI_BUSSES * MAX_DEVICES_PER_PCIBUS];
  39 int irq_to_slot[MAX_PCI_BUSSES * MAX_DEVICES_PER_PCIBUS];
  40
  41 extern struct pci_ops bridge_pci_ops;
  42
  43 <<<<<<< HEAD:arch/mips/pci/pci-ip27.c
  44 int __init bridge_probe(nasid_t nasid, int widget_id, int masterwid)
  45 =======
  46 int __cpuinit bridge_probe(nasid_t nasid, int widget_id, int masterwid)
  47 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/mips/pci/pci-ip27.c
  48 {
  49         unsigned long offset = NODE_OFFSET(nasid);
  50         struct bridge_controller *bc;
  51         static int num_bridges = 0;
  52         bridge_t *bridge;
  53         int slot;
  54
  55         printk("a bridge\n");
  56
  57         /* XXX: kludge alert.. */
  58         if (!num_bridges)
  59                 ioport_resource.end = ~0UL;
  60
  61         bc = &bridges[num_bridges];
  62
  63         bc->pc.pci_ops          = &bridge_pci_ops;
  64         bc->pc.mem_resource     = &bc->mem;
  65         bc->pc.io_resource      = &bc->io;
  66
  67         bc->pc.index            = num_bridges;
  68
  69         bc->mem.name            = "Bridge PCI MEM";
  70         bc->pc.mem_offset       = offset;
  71         bc->mem.start           = 0;
  72         bc->mem.end             = ~0UL;
  73         bc->mem.flags           = IORESOURCE_MEM;
  74
  75         bc->io.name             = "Bridge IO MEM";
  76         bc->pc.io_offset        = offset;
  77         bc->io.start            = 0UL;
  78         bc->io.end              = ~0UL;
  79         bc->io.flags            = IORESOURCE_IO;
  80
  81         bc->irq_cpu = smp_processor_id();
  82         bc->widget_id = widget_id;
  83         bc->nasid = nasid;
  84
  85         bc->baddr = (u64)masterwid << 60 | PCI64_ATTR_BAR;
  86
  87         /*
  88          * point to this bridge
  89          */
  90         bridge = (bridge_t *) RAW_NODE_SWIN_BASE(nasid, widget_id);
  91
  92         /*
  93          * Clear all pending interrupts.
  94          */
  95         bridge->b_int_rst_stat = BRIDGE_IRR_ALL_CLR;
  96
  97         /*
  98          * Until otherwise set up, assume all interrupts are from slot 0
  99          */
 100         bridge->b_int_device = 0x0;
 101
 102         /*
 103          * swap pio's to pci mem and io space (big windows)
 104          */
 105         bridge->b_wid_control |= BRIDGE_CTRL_IO_SWAP |
 106                                  BRIDGE_CTRL_MEM_SWAP;
 107
 108         /*
 109          * Hmm...  IRIX sets additional bits in the address which
 110          * are documented as reserved in the bridge docs.
 111          */
 112         bridge->b_wid_int_upper = 0x8000 | (masterwid << 16);
 113         bridge->b_wid_int_lower = 0x01800090;   /* PI_INT_PEND_MOD off*/
 114         bridge->b_dir_map = (masterwid << 20);  /* DMA */
 115         bridge->b_int_enable = 0;
 116
 117         for (slot = 0; slot < 8; slot ++) {
 118                 bridge->b_device[slot].reg |= BRIDGE_DEV_SWAP_DIR;
 119                 bc->pci_int[slot] = -1;
 120         }
 121         bridge->b_wid_tflush;     /* wait until Bridge PIO complete */
 122
 123         bc->base = bridge;
 124
 125         register_pci_controller(&bc->pc);
 126
 127         num_bridges++;
 128
 129         return 0;
 130 }
 131
 132 /*
 133  * All observed requests have pin == 1. We could have a global here, that
 134  * gets incremented and returned every time - unfortunately, pci_map_irq
 135  * may be called on the same device over and over, and need to return the
 136  * same value. On O2000, pin can be 0 or 1, and PCI slots can be [0..7].
 137  *
 138  * A given PCI device, in general, should be able to intr any of the cpus
 139  * on any one of the hubs connected to its xbow.
 140  */
 141 int __devinit pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 142 {
 143         struct bridge_controller *bc = BRIDGE_CONTROLLER(dev->bus);
 144         int irq = bc->pci_int[slot];
 145
 146         if (irq == -1) {
 147                 irq = bc->pci_int[slot] = request_bridge_irq(bc);
 148                 if (irq < 0)
 149                         panic("Can't allocate interrupt for PCI device %s\n",
 150                               pci_name(dev));
 151         }
 152
 153         irq_to_bridge[irq] = bc;
 154         irq_to_slot[irq] = slot;
 155
 156         return irq;
 157 }
 158
 159 /* Do platform specific device initialization at pci_enable_device() time */
 160 int pcibios_plat_dev_init(struct pci_dev *dev)
 161 {
 162         return 0;
 163 }
 164
 165 /*
 166  * Device might live on a subordinate PCI bus.  XXX Walk up the chain of buses
 167  * to find the slot number in sense of the bridge device register.
 168  * XXX This also means multiple devices might rely on conflicting bridge
 169  * settings.
 170  */
 171
 172 static inline void pci_disable_swapping(struct pci_dev *dev)
 173 {
 174         struct bridge_controller *bc = BRIDGE_CONTROLLER(dev->bus);
 175         bridge_t *bridge = bc->base;
 176         int slot = PCI_SLOT(dev->devfn);
 177
 178         /* Turn off byte swapping */
 179         bridge->b_device[slot].reg &= ~BRIDGE_DEV_SWAP_DIR;
 180         bridge->b_widget.w_tflush;      /* Flush */
 181 }
 182
 183 static inline void pci_enable_swapping(struct pci_dev *dev)
 184 {
 185         struct bridge_controller *bc = BRIDGE_CONTROLLER(dev->bus);
 186         bridge_t *bridge = bc->base;
 187         int slot = PCI_SLOT(dev->devfn);
 188
 189         /* Turn on byte swapping */
 190         bridge->b_device[slot].reg |= BRIDGE_DEV_SWAP_DIR;
 191         bridge->b_widget.w_tflush;      /* Flush */
 192 }
 193
 194 static void __init pci_fixup_ioc3(struct pci_dev *d)
 195 {
 196         pci_disable_swapping(d);
 197 }
 198
 199 int pcibus_to_node(struct pci_bus *bus)
 200 {
 201         struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
 202
 203         return bc->nasid;
 204 }
 205
 206 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
 207         pci_fixup_ioc3);