Merge git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
[wrt350n-kernel.git] / arch / mips / pmc-sierra / yosemite / smp.c
blobe5d1e250f6b1d911060f95d9d09ee01397a72dbc
1 #include <linux/linkage.h>
2 #include <linux/sched.h>
4 #include <asm/pmon.h>
5 #include <asm/titan_dep.h>
6 #include <asm/time.h>
8 #define LAUNCHSTACK_SIZE 256
10 <<<<<<< HEAD:arch/mips/pmc-sierra/yosemite/smp.c
11 static __initdata DEFINE_SPINLOCK(launch_lock);
12 =======
13 static __cpuinitdata DEFINE_SPINLOCK(launch_lock);
14 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/mips/pmc-sierra/yosemite/smp.c
16 <<<<<<< HEAD:arch/mips/pmc-sierra/yosemite/smp.c
17 static unsigned long secondary_sp __initdata;
18 static unsigned long secondary_gp __initdata;
19 =======
20 static unsigned long secondary_sp __cpuinitdata;
21 static unsigned long secondary_gp __cpuinitdata;
22 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/mips/pmc-sierra/yosemite/smp.c
24 static unsigned char launchstack[LAUNCHSTACK_SIZE] __initdata
25 __attribute__((aligned(2 * sizeof(long))));
27 static void __init prom_smp_bootstrap(void)
29 local_irq_disable();
31 while (spin_is_locked(&launch_lock));
33 __asm__ __volatile__(
34 " move $sp, %0 \n"
35 " move $gp, %1 \n"
36 " j smp_bootstrap \n"
38 : "r" (secondary_sp), "r" (secondary_gp));
42 * PMON is a fragile beast. It'll blow up once the mappings it's littering
43 * right into the middle of KSEG3 are blown away so we have to grab the slave
44 * core early and keep it in a waiting loop.
46 void __init prom_grab_secondary(void)
48 spin_lock(&launch_lock);
50 pmon_cpustart(1, &prom_smp_bootstrap,
51 launchstack + LAUNCHSTACK_SIZE, 0);
54 void titan_mailbox_irq(void)
56 int cpu = smp_processor_id();
57 unsigned long status;
59 switch (cpu) {
60 case 0:
61 status = OCD_READ(RM9000x2_OCD_INTP0STATUS3);
62 OCD_WRITE(RM9000x2_OCD_INTP0CLEAR3, status);
64 if (status & 0x2)
65 smp_call_function_interrupt();
66 break;
68 case 1:
69 status = OCD_READ(RM9000x2_OCD_INTP1STATUS3);
70 OCD_WRITE(RM9000x2_OCD_INTP1CLEAR3, status);
72 if (status & 0x2)
73 smp_call_function_interrupt();
74 break;
79 * Send inter-processor interrupt
81 static void yos_send_ipi_single(int cpu, unsigned int action)
84 * Generate an INTMSG so that it can be sent over to the
85 * destination CPU. The INTMSG will put the STATUS bits
86 * based on the action desired. An alternative strategy
87 * is to write to the Interrupt Set register, read the
88 * Interrupt Status register and clear the Interrupt
89 * Clear register. The latter is preffered.
91 switch (action) {
92 case SMP_RESCHEDULE_YOURSELF:
93 if (cpu == 1)
94 OCD_WRITE(RM9000x2_OCD_INTP1SET3, 4);
95 else
96 OCD_WRITE(RM9000x2_OCD_INTP0SET3, 4);
97 break;
99 case SMP_CALL_FUNCTION:
100 if (cpu == 1)
101 OCD_WRITE(RM9000x2_OCD_INTP1SET3, 2);
102 else
103 OCD_WRITE(RM9000x2_OCD_INTP0SET3, 2);
104 break;
108 static void yos_send_ipi_mask(cpumask_t mask, unsigned int action)
110 unsigned int i;
112 for_each_cpu_mask(i, mask)
113 yos_send_ipi_single(i, action);
117 * After we've done initial boot, this function is called to allow the
118 * board code to clean up state, if needed
120 static void __cpuinit yos_init_secondary(void)
122 set_c0_status(ST0_CO | ST0_IE | ST0_IM);
125 static void __cpuinit yos_smp_finish(void)
129 /* Hook for after all CPUs are online */
130 static void yos_cpus_done(void)
135 * Firmware CPU startup hook
136 * Complicated by PMON's weird interface which tries to minimic the UNIX fork.
137 * It launches the next * available CPU and copies some information on the
138 * stack so the first thing we do is throw away that stuff and load useful
139 * values into the registers ...
141 static void __cpuinit yos_boot_secondary(int cpu, struct task_struct *idle)
143 unsigned long gp = (unsigned long) task_thread_info(idle);
144 unsigned long sp = __KSTK_TOS(idle);
146 secondary_sp = sp;
147 secondary_gp = gp;
149 spin_unlock(&launch_lock);
153 * Detect available CPUs, populate phys_cpu_present_map before smp_init
155 * We don't want to start the secondary CPU yet nor do we have a nice probing
156 * feature in PMON so we just assume presence of the secondary core.
158 static void __init yos_smp_setup(void)
160 int i;
162 cpus_clear(phys_cpu_present_map);
164 for (i = 0; i < 2; i++) {
165 cpu_set(i, phys_cpu_present_map);
166 __cpu_number_map[i] = i;
167 __cpu_logical_map[i] = i;
171 static void __init yos_prepare_cpus(unsigned int max_cpus)
174 * Be paranoid. Enable the IPI only if we're really about to go SMP.
176 if (cpus_weight(cpu_possible_map))
177 set_c0_status(STATUSF_IP5);
180 struct plat_smp_ops yos_smp_ops = {
181 .send_ipi_single = yos_send_ipi_single,
182 .send_ipi_mask = yos_send_ipi_mask,
183 .init_secondary = yos_init_secondary,
184 .smp_finish = yos_smp_finish,
185 .cpus_done = yos_cpus_done,
186 .boot_secondary = yos_boot_secondary,
187 .smp_setup = yos_smp_setup,
188 .prepare_cpus = yos_prepare_cpus,