| blob | eabe5866bfcd6ad44dc4b8169c1b2a43eaa4e270 |
1 /*
2 * Device Tree Source for AMCC Kilauea (405EX)
3 *
4 * Copyright 2007 DENX Software Engineering, Stefan Roese <sr@denx.de>
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without
8 * any warranty of any kind, whether express or implied.
9 */
11 / {
12 #address-cells = <1>;
13 #size-cells = <1>;
14 model = "amcc,kilauea";
15 compatible = "amcc,kilauea";
16 dcr-parent = <&/cpus/cpu@0>;
18 aliases {
19 ethernet0 = &EMAC0;
20 ethernet1 = &EMAC1;
21 serial0 = &UART0;
22 serial1 = &UART1;
23 };
25 cpus {
26 #address-cells = <1>;
27 #size-cells = <0>;
29 cpu@0 {
30 device_type = "cpu";
31 model = "PowerPC,405EX";
32 reg = <0>;
33 clock-frequency = <0>; /* Filled in by U-Boot */
34 timebase-frequency = <0>; /* Filled in by U-Boot */
35 i-cache-line-size = <20>;
36 d-cache-line-size = <20>;
37 i-cache-size = <4000>; /* 16 kB */
38 d-cache-size = <4000>; /* 16 kB */
39 dcr-controller;
40 dcr-access-method = "native";
41 };
42 };
44 memory {
45 device_type = "memory";
46 reg = <0 0>; /* Filled in by U-Boot */
47 };
49 UIC0: interrupt-controller {
50 compatible = "ibm,uic-405ex", "ibm,uic";
51 interrupt-controller;
52 cell-index = <0>;
53 dcr-reg = <0c0 009>;
54 #address-cells = <0>;
55 #size-cells = <0>;
56 #interrupt-cells = <2>;
57 };
59 UIC1: interrupt-controller1 {
60 compatible = "ibm,uic-405ex","ibm,uic";
61 interrupt-controller;
62 cell-index = <1>;
63 dcr-reg = <0d0 009>;
64 #address-cells = <0>;
65 #size-cells = <0>;
66 #interrupt-cells = <2>;
67 interrupts = <1e 4 1f 4>; /* cascade */
68 interrupt-parent = <&UIC0>;
69 };
71 UIC2: interrupt-controller2 {
72 compatible = "ibm,uic-405ex","ibm,uic";
73 interrupt-controller;
74 cell-index = <2>;
75 dcr-reg = <0e0 009>;
76 #address-cells = <0>;
77 #size-cells = <0>;
78 #interrupt-cells = <2>;
79 interrupts = <1c 4 1d 4>; /* cascade */
80 interrupt-parent = <&UIC0>;
81 };
83 plb {
84 compatible = "ibm,plb-405ex", "ibm,plb4";
85 #address-cells = <1>;
86 #size-cells = <1>;
87 ranges;
88 clock-frequency = <0>; /* Filled in by U-Boot */
90 SDRAM0: memory-controller {
91 compatible = "ibm,sdram-405ex";
92 dcr-reg = <010 2>;
93 };
95 MAL0: mcmal {
96 compatible = "ibm,mcmal-405ex", "ibm,mcmal2";
97 dcr-reg = <180 62>;
98 num-tx-chans = <2>;
99 num-rx-chans = <2>;
100 interrupt-parent = <&MAL0>;
101 interrupts = <0 1 2 3 4>;
102 #interrupt-cells = <1>;
103 #address-cells = <0>;
104 #size-cells = <0>;
105 interrupt-map = </*TXEOB*/ 0 &UIC0 a 4
106 /*RXEOB*/ 1 &UIC0 b 4
107 /*SERR*/ 2 &UIC1 0 4
108 /*TXDE*/ 3 &UIC1 1 4
109 /*RXDE*/ 4 &UIC1 2 4>;
110 interrupt-map-mask = <ffffffff>;
111 };
113 POB0: opb {
114 compatible = "ibm,opb-405ex", "ibm,opb";
115 #address-cells = <1>;
116 #size-cells = <1>;
117 ranges = <80000000 80000000 10000000
118 ef600000 ef600000 a00000
119 f0000000 f0000000 10000000>;
120 dcr-reg = <0a0 5>;
121 clock-frequency = <0>; /* Filled in by U-Boot */
123 EBC0: ebc {
124 compatible = "ibm,ebc-405ex", "ibm,ebc";
125 dcr-reg = <012 2>;
126 #address-cells = <2>;
127 #size-cells = <1>;
128 clock-frequency = <0>; /* Filled in by U-Boot */
129 /* ranges property is supplied by U-Boot */
130 interrupts = <5 1>;
131 interrupt-parent = <&UIC1>;
133 nor_flash@0,0 {
134 compatible = "amd,s29gl512n", "cfi-flash";
135 bank-width = <2>;
136 reg = <0 000000 4000000>;
137 #address-cells = <1>;
138 #size-cells = <1>;
139 partition@0 {
140 label = "kernel";
141 reg = <0 200000>;
142 };
143 partition@200000 {
144 label = "root";
145 reg = <200000 200000>;
146 };
147 partition@400000 {
148 label = "user";
149 reg = <400000 3b60000>;
150 };
151 partition@3f60000 {
152 label = "env";
153 reg = <3f60000 40000>;
154 };
155 partition@3fa0000 {
156 label = "u-boot";
157 reg = <3fa0000 60000>;
158 };
159 };
160 };
162 UART0: serial@ef600200 {
163 device_type = "serial";
164 compatible = "ns16550";
165 reg = <ef600200 8>;
166 virtual-reg = <ef600200>;
167 clock-frequency = <0>; /* Filled in by U-Boot */
168 current-speed = <0>;
169 interrupt-parent = <&UIC0>;
170 interrupts = <1a 4>;
171 };
173 UART1: serial@ef600300 {
174 device_type = "serial";
175 compatible = "ns16550";
176 reg = <ef600300 8>;
177 virtual-reg = <ef600300>;
178 clock-frequency = <0>; /* Filled in by U-Boot */
179 current-speed = <0>;
180 interrupt-parent = <&UIC0>;
181 interrupts = <1 4>;
182 };
184 IIC0: i2c@ef600400 {
185 <<<<<<< HEAD:arch/powerpc/boot/dts/kilauea.dts
186 device_type = "i2c";
187 =======
188 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/powerpc/boot/dts/kilauea.dts
189 compatible = "ibm,iic-405ex", "ibm,iic";
190 reg = <ef600400 14>;
191 interrupt-parent = <&UIC0>;
192 interrupts = <2 4>;
193 };
195 IIC1: i2c@ef600500 {
196 <<<<<<< HEAD:arch/powerpc/boot/dts/kilauea.dts
197 device_type = "i2c";
198 =======
199 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/powerpc/boot/dts/kilauea.dts
200 compatible = "ibm,iic-405ex", "ibm,iic";
201 reg = <ef600500 14>;
202 interrupt-parent = <&UIC0>;
203 interrupts = <7 4>;
204 };
207 RGMII0: emac-rgmii@ef600b00 {
208 <<<<<<< HEAD:arch/powerpc/boot/dts/kilauea.dts
209 device_type = "rgmii-interface";
210 =======
211 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/powerpc/boot/dts/kilauea.dts
212 compatible = "ibm,rgmii-405ex", "ibm,rgmii";
213 reg = <ef600b00 104>;
214 has-mdio;
215 };
217 EMAC0: ethernet@ef600900 {
218 linux,network-index = <0>;
219 device_type = "network";
220 compatible = "ibm,emac-405ex", "ibm,emac4";
221 interrupt-parent = <&EMAC0>;
222 interrupts = <0 1>;
223 #interrupt-cells = <1>;
224 #address-cells = <0>;
225 #size-cells = <0>;
226 interrupt-map = </*Status*/ 0 &UIC0 18 4
227 /*Wake*/ 1 &UIC1 1d 4>;
228 reg = <ef600900 70>;
229 local-mac-address = [000000000000]; /* Filled in by U-Boot */
230 mal-device = <&MAL0>;
231 mal-tx-channel = <0>;
232 mal-rx-channel = <0>;
233 cell-index = <0>;
234 max-frame-size = <5dc>;
235 rx-fifo-size = <1000>;
236 tx-fifo-size = <800>;
237 phy-mode = "rgmii";
238 phy-map = <00000000>;
239 rgmii-device = <&RGMII0>;
240 rgmii-channel = <0>;
241 has-inverted-stacr-oc;
242 has-new-stacr-staopc;
243 };
245 EMAC1: ethernet@ef600a00 {
246 linux,network-index = <1>;
247 device_type = "network";
248 compatible = "ibm,emac-405ex", "ibm,emac4";
249 interrupt-parent = <&EMAC1>;
250 interrupts = <0 1>;
251 #interrupt-cells = <1>;
252 #address-cells = <0>;
253 #size-cells = <0>;
254 interrupt-map = </*Status*/ 0 &UIC0 19 4
255 /*Wake*/ 1 &UIC1 1f 4>;
256 reg = <ef600a00 70>;
257 local-mac-address = [000000000000]; /* Filled in by U-Boot */
258 mal-device = <&MAL0>;
259 mal-tx-channel = <1>;
260 mal-rx-channel = <1>;
261 cell-index = <1>;
262 max-frame-size = <5dc>;
263 rx-fifo-size = <1000>;
264 tx-fifo-size = <800>;
265 phy-mode = "rgmii";
266 phy-map = <00000000>;
267 rgmii-device = <&RGMII0>;
268 rgmii-channel = <1>;
269 has-inverted-stacr-oc;
270 has-new-stacr-staopc;
271 };
272 };
274 PCIE0: pciex@0a0000000 {
275 device_type = "pci";
276 #interrupt-cells = <1>;
277 #size-cells = <2>;
278 #address-cells = <3>;
279 compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex";
280 primary;
281 port = <0>; /* port number */
282 reg = <a0000000 20000000 /* Config space access */
283 ef000000 00001000>; /* Registers */
284 dcr-reg = <040 020>;
285 sdr-base = <400>;
287 /* Outbound ranges, one memory and one IO,
288 * later cannot be changed
289 */
290 ranges = <02000000 0 80000000 90000000 0 08000000
291 01000000 0 00000000 e0000000 0 00010000>;
293 /* Inbound 2GB range starting at 0 */
294 dma-ranges = <42000000 0 0 0 0 80000000>;
296 /* This drives busses 0x00 to 0x3f */
297 bus-range = <00 3f>;
299 /* Legacy interrupts (note the weird polarity, the bridge seems
300 * to invert PCIe legacy interrupts).
301 * We are de-swizzling here because the numbers are actually for
302 * port of the root complex virtual P2P bridge. But I want
303 * to avoid putting a node for it in the tree, so the numbers
304 * below are basically de-swizzled numbers.
305 * The real slot is on idsel 0, so the swizzling is 1:1
306 */
307 interrupt-map-mask = <0000 0 0 7>;
308 interrupt-map = <
309 0000 0 0 1 &UIC2 0 4 /* swizzled int A */
310 0000 0 0 2 &UIC2 1 4 /* swizzled int B */
311 0000 0 0 3 &UIC2 2 4 /* swizzled int C */
312 0000 0 0 4 &UIC2 3 4 /* swizzled int D */>;
313 };
315 PCIE1: pciex@0c0000000 {
316 device_type = "pci";
317 #interrupt-cells = <1>;
318 #size-cells = <2>;
319 #address-cells = <3>;
320 compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex";
321 primary;
322 port = <1>; /* port number */
323 reg = <c0000000 20000000 /* Config space access */
324 ef001000 00001000>; /* Registers */
325 dcr-reg = <060 020>;
326 sdr-base = <440>;
328 /* Outbound ranges, one memory and one IO,
329 * later cannot be changed
330 */
331 ranges = <02000000 0 80000000 98000000 0 08000000
332 01000000 0 00000000 e0010000 0 00010000>;
334 /* Inbound 2GB range starting at 0 */
335 dma-ranges = <42000000 0 0 0 0 80000000>;
337 /* This drives busses 0x40 to 0x7f */
338 bus-range = <40 7f>;
340 /* Legacy interrupts (note the weird polarity, the bridge seems
341 * to invert PCIe legacy interrupts).
342 * We are de-swizzling here because the numbers are actually for
343 * port of the root complex virtual P2P bridge. But I want
344 * to avoid putting a node for it in the tree, so the numbers
345 * below are basically de-swizzled numbers.
346 * The real slot is on idsel 0, so the swizzling is 1:1
347 */
348 interrupt-map-mask = <0000 0 0 7>;
349 interrupt-map = <
350 0000 0 0 1 &UIC2 b 4 /* swizzled int A */
351 0000 0 0 2 &UIC2 c 4 /* swizzled int B */
352 0000 0 0 3 &UIC2 d 4 /* swizzled int C */
353 0000 0 0 4 &UIC2 e 4 /* swizzled int D */>;
354 };
355 };
356 };