arch/powerpc/boot/dts/mpc8610_hpcd.dts

   1 /*
   2  * MPC8610 HPCD Device Tree Source
   3  *
   4  * Copyright 2007-2008 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under the terms of the GNU General Public License Version 2 as published
   8  * by the Free Software Foundation.
   9  */
  10
  11 /dts-v1/;
  12
  13 / {
  14         model = "MPC8610HPCD";
  15         compatible = "fsl,MPC8610HPCD";
  16         #address-cells = <1>;
  17         #size-cells = <1>;
  18
  19         aliases {
  20                 serial0 = &serial0;
  21                 serial1 = &serial1;
  22                 pci0 = &pci0;
  23                 pci1 = &pci1;
  24         };
  25
  26         cpus {
  27                 #address-cells = <1>;
  28                 #size-cells = <0>;
  29
  30                 PowerPC,8610@0 {
  31                         device_type = "cpu";
  32                         reg = <0>;
  33                         d-cache-line-size = <32>;
  34                         i-cache-line-size = <32>;
  35                         d-cache-size = <32768>;         // L1
  36                         i-cache-size = <32768>;         // L1
  37                         timebase-frequency = <0>;       // From uboot
  38                         bus-frequency = <0>;            // From uboot
  39                         clock-frequency = <0>;          // From uboot
  40                 };
  41         };
  42
  43         memory {
  44                 device_type = "memory";
  45                 reg = <0x00000000 0x20000000>;  // 512M at 0x0
  46         };
  47
  48         soc@e0000000 {
  49                 #address-cells = <1>;
  50                 #size-cells = <1>;
  51                 #interrupt-cells = <2>;
  52                 device_type = "soc";
  53                 compatible = "fsl,mpc8610-immr", "simple-bus";
  54                 ranges = <0x0 0xe0000000 0x00100000>;
  55                 reg = <0xe0000000 0x1000>;
  56                 bus-frequency = <0>;
  57
  58                 i2c@3000 {
  59                         #address-cells = <1>;
  60                         #size-cells = <0>;
  61                         cell-index = <0>;
  62                         compatible = "fsl-i2c";
  63                         reg = <0x3000 0x100>;
  64                         interrupts = <43 2>;
  65                         interrupt-parent = <&mpic>;
  66                         dfsrr;
  67
  68                         cs4270:codec@4f {
  69                                 compatible = "cirrus,cs4270";
  70                                 reg = <0x4f>;
  71                                 /* MCLK source is a stand-alone oscillator */
  72                                 clock-frequency = <12288000>;
  73                         };
  74                 };
  75
  76                 i2c@3100 {
  77                         #address-cells = <1>;
  78                         #size-cells = <0>;
  79                         cell-index = <1>;
  80                         compatible = "fsl-i2c";
  81                         reg = <0x3100 0x100>;
  82                         interrupts = <43 2>;
  83                         interrupt-parent = <&mpic>;
  84                         dfsrr;
  85                 };
  86
  87                 serial0: serial@4500 {
  88                         cell-index = <0>;
  89                         device_type = "serial";
  90                         compatible = "ns16550";
  91                         reg = <0x4500 0x100>;
  92                         clock-frequency = <0>;
  93                         interrupts = <42 2>;
  94                         interrupt-parent = <&mpic>;
  95                 };
  96
  97                 serial1: serial@4600 {
  98                         cell-index = <1>;
  99                         device_type = "serial";
 100                         compatible = "ns16550";
 101                         reg = <0x4600 0x100>;
 102                         clock-frequency = <0>;
 103                         interrupts = <28 2>;
 104                         interrupt-parent = <&mpic>;
 105                 };
 106
 107                 mpic: interrupt-controller@40000 {
 108                         clock-frequency = <0>;
 109                         interrupt-controller;
 110                         #address-cells = <0>;
 111                         #interrupt-cells = <2>;
 112                         reg = <0x40000 0x40000>;
 113                         compatible = "chrp,open-pic";
 114                         device_type = "open-pic";
 115                         big-endian;
 116                 };
 117
 118                 global-utilities@e0000 {
 119                         compatible = "fsl,mpc8610-guts";
 120                         reg = <0xe0000 0x1000>;
 121                         fsl,has-rstcr;
 122                 };
 123
 124                 i2s@16000 {
 125                         compatible = "fsl,mpc8610-ssi";
 126                         cell-index = <0>;
 127                         reg = <0x16000 0x100>;
 128                         interrupt-parent = <&mpic>;
 129                         interrupts = <62 2>;
 130                         fsl,mode = "i2s-slave";
 131                         codec-handle = <&cs4270>;
 132                 };
 133
 134                 ssi@16100 {
 135                         compatible = "fsl,mpc8610-ssi";
 136                         cell-index = <1>;
 137                         reg = <0x16100 0x100>;
 138                         interrupt-parent = <&mpic>;
 139                         interrupts = <63 2>;
 140                 };
 141
 142                 dma@21300 {
 143                         #address-cells = <1>;
 144                         #size-cells = <1>;
 145                         compatible = "fsl,mpc8610-dma", "fsl,eloplus-dma";
 146                         cell-index = <0>;
 147                         reg = <0x21300 0x4>; /* DMA general status register */
 148                         ranges = <0x0 0x21100 0x200>;
 149
 150                         dma-channel@0 {
 151                                 compatible = "fsl,mpc8610-dma-channel",
 152                                         "fsl,eloplus-dma-channel";
 153                                 cell-index = <0>;
 154                                 reg = <0x0 0x80>;
 155                                 interrupt-parent = <&mpic>;
 156                                 interrupts = <20 2>;
 157                         };
 158                         dma-channel@1 {
 159                                 compatible = "fsl,mpc8610-dma-channel",
 160                                         "fsl,eloplus-dma-channel";
 161                                 cell-index = <1>;
 162                                 reg = <0x80 0x80>;
 163                                 interrupt-parent = <&mpic>;
 164                                 interrupts = <21 2>;
 165                         };
 166                         dma-channel@2 {
 167                                 compatible = "fsl,mpc8610-dma-channel",
 168                                         "fsl,eloplus-dma-channel";
 169                                 cell-index = <2>;
 170                                 reg = <0x100 0x80>;
 171                                 interrupt-parent = <&mpic>;
 172                                 interrupts = <22 2>;
 173                         };
 174                         dma-channel@3 {
 175                                 compatible = "fsl,mpc8610-dma-channel",
 176                                         "fsl,eloplus-dma-channel";
 177                                 cell-index = <3>;
 178                                 reg = <0x180 0x80>;
 179                                 interrupt-parent = <&mpic>;
 180                                 interrupts = <23 2>;
 181                         };
 182                 };
 183
 184                 dma@c300 {
 185                         #address-cells = <1>;
 186                         #size-cells = <1>;
 187                         compatible = "fsl,mpc8610-dma", "fsl,mpc8540-dma";
 188                         cell-index = <1>;
 189                         reg = <0xc300 0x4>; /* DMA general status register */
 190                         ranges = <0x0 0xc100 0x200>;
 191
 192                         dma-channel@0 {
 193                                 compatible = "fsl,mpc8610-dma-channel",
 194                                         "fsl,mpc8540-dma-channel";
 195                                 cell-index = <0>;
 196                                 reg = <0x0 0x80>;
 197                                 interrupt-parent = <&mpic>;
 198                                 interrupts = <60 2>;
 199                         };
 200                         dma-channel@1 {
 201                                 compatible = "fsl,mpc8610-dma-channel",
 202                                         "fsl,mpc8540-dma-channel";
 203                                 cell-index = <1>;
 204                                 reg = <0x80 0x80>;
 205                                 interrupt-parent = <&mpic>;
 206                                 interrupts = <61 2>;
 207                         };
 208                         dma-channel@2 {
 209                                 compatible = "fsl,mpc8610-dma-channel",
 210                                         "fsl,mpc8540-dma-channel";
 211                                 cell-index = <2>;
 212                                 reg = <0x100 0x80>;
 213                                 interrupt-parent = <&mpic>;
 214                                 interrupts = <62 2>;
 215                         };
 216                         dma-channel@3 {
 217                                 compatible = "fsl,mpc8610-dma-channel",
 218                                         "fsl,mpc8540-dma-channel";
 219                                 cell-index = <3>;
 220                                 reg = <0x180 0x80>;
 221                                 interrupt-parent = <&mpic>;
 222                                 interrupts = <63 2>;
 223                         };
 224                 };
 225
 226         };
 227
 228         pci0: pci@e0008000 {
 229                 cell-index = <0>;
 230                 compatible = "fsl,mpc8610-pci";
 231                 device_type = "pci";
 232                 #interrupt-cells = <1>;
 233                 #size-cells = <2>;
 234                 #address-cells = <3>;
 235                 reg = <0xe0008000 0x1000>;
 236                 bus-range = <0 0>;
 237                 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x10000000
 238                           0x01000000 0x0 0x00000000 0xe1000000 0x0 0x00100000>;
 239                 clock-frequency = <33333333>;
 240                 interrupt-parent = <&mpic>;
 241                 interrupts = <24 2>;
 242                 interrupt-map-mask = <0xf800 0 0 7>;
 243                 interrupt-map = <
 244                         /* IDSEL 0x11 */
 245                         0x8800 0 0 1 &mpic 4 1
 246                         0x8800 0 0 2 &mpic 5 1
 247                         0x8800 0 0 3 &mpic 6 1
 248                         0x8800 0 0 4 &mpic 7 1
 249
 250                         /* IDSEL 0x12 */
 251                         0x9000 0 0 1 &mpic 5 1
 252                         0x9000 0 0 2 &mpic 6 1
 253                         0x9000 0 0 3 &mpic 7 1
 254                         0x9000 0 0 4 &mpic 4 1
 255                         >;
 256         };
 257
 258         pci1: pcie@e000a000 {
 259                 cell-index = <1>;
 260                 compatible = "fsl,mpc8641-pcie";
 261                 device_type = "pci";
 262                 #interrupt-cells = <1>;
 263                 #size-cells = <2>;
 264                 #address-cells = <3>;
 265                 reg = <0xe000a000 0x1000>;
 266                 bus-range = <1 3>;
 267                 ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
 268                           0x01000000 0x0 0x00000000 0xe3000000 0x0 0x00100000>;
 269                 clock-frequency = <33333333>;
 270                 interrupt-parent = <&mpic>;
 271                 interrupts = <26 2>;
 272                 interrupt-map-mask = <0xf800 0 0 7>;
 273
 274                 interrupt-map = <
 275                         /* IDSEL 0x1b */
 276                         0xd800 0 0 1 &mpic 2 1
 277
 278                         /* IDSEL 0x1c*/
 279                         0xe000 0 0 1 &mpic 1 1
 280                         0xe000 0 0 2 &mpic 1 1
 281                         0xe000 0 0 3 &mpic 1 1
 282                         0xe000 0 0 4 &mpic 1 1
 283
 284                         /* IDSEL 0x1f */
 285                         0xf800 0 0 1 &mpic 3 0
 286                         0xf800 0 0 2 &mpic 0 1
 287                 >;
 288
 289                 pcie@0 {
 290                         reg = <0 0 0 0 0>;
 291                         #size-cells = <2>;
 292                         #address-cells = <3>;
 293                         device_type = "pci";
 294                         ranges = <0x02000000 0x0 0xa0000000
 295                                   0x02000000 0x0 0xa0000000
 296                                   0x0 0x10000000
 297                                   0x01000000 0x0 0x00000000
 298                                   0x01000000 0x0 0x00000000
 299                                   0x0 0x00100000>;
 300                         uli1575@0 {
 301                                 reg = <0 0 0 0 0>;
 302                                 #size-cells = <2>;
 303                                 #address-cells = <3>;
 304                                 ranges = <0x02000000 0x0 0xa0000000
 305                                           0x02000000 0x0 0xa0000000
 306                                           0x0 0x10000000
 307                                           0x01000000 0x0 0x00000000
 308                                           0x01000000 0x0 0x00000000
 309                                           0x0 0x00100000>;
 310                         };
 311                 };
 312         };
 313 };