arch/powerpc/platforms/pasemi/iommu.c

   1 /*
   2  * Copyright (C) 2005-2007, PA Semi, Inc
   3  *
   4  * Maintained by: Olof Johansson <olof@lixom.net>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  18  */
  19
  20 #undef DEBUG
  21
  22 #include <linux/types.h>
  23 #include <linux/spinlock.h>
  24 #include <linux/pci.h>
  25 #include <asm/iommu.h>
  26 #include <asm/machdep.h>
  27 #include <asm/abs_addr.h>
  28 #include <asm/firmware.h>
  29
  30
  31 #define IOBMAP_PAGE_SHIFT       12
  32 #define IOBMAP_PAGE_SIZE        (1 << IOBMAP_PAGE_SHIFT)
  33 #define IOBMAP_PAGE_MASK        (IOBMAP_PAGE_SIZE - 1)
  34
  35 #define IOB_BASE                0xe0000000
  36 #define IOB_SIZE                0x3000
  37 /* Configuration registers */
  38 #define IOBCAP_REG              0x10
  39 #define IOBCOM_REG              0x40
  40 /* Enable IOB address translation */
  41 #define IOBCOM_ATEN             0x00000100
  42
  43 /* Address decode configuration register */
  44 #define IOB_AD_REG              0x53
  45 /* IOBCOM_AD_REG fields */
  46 #define IOB_AD_VGPRT            0x00000e00
  47 #define IOB_AD_VGAEN            0x00000100
  48 /* Direct mapping settings */
  49 #define IOB_AD_MPSEL_MASK       0x00000030
  50 #define IOB_AD_MPSEL_B38        0x00000000
  51 #define IOB_AD_MPSEL_B40        0x00000010
  52 #define IOB_AD_MPSEL_B42        0x00000020
  53 /* Translation window size / enable */
  54 #define IOB_AD_TRNG_MASK        0x00000003
  55 #define IOB_AD_TRNG_256M        0x00000000
  56 #define IOB_AD_TRNG_2G          0x00000001
  57 #define IOB_AD_TRNG_128G        0x00000003
  58
  59 #define IOB_TABLEBASE_REG       0x55
  60
  61 /* Base of the 64 4-byte L1 registers */
  62 #define IOB_XLT_L1_REGBASE      0xac0
  63
  64 /* Register to invalidate TLB entries */
  65 #define IOB_AT_INVAL_TLB_REG    0xb40
  66
  67 /* The top two bits of the level 1 entry contains valid and type flags */
  68 #define IOBMAP_L1E_V            0x40000000
  69 #define IOBMAP_L1E_V_B          0x80000000
  70
  71 /* For big page entries, the bottom two bits contains flags */
  72 #define IOBMAP_L1E_BIG_CACHED   0x00000002
  73 #define IOBMAP_L1E_BIG_PRIORITY 0x00000001
  74
  75 /* For regular level 2 entries, top 2 bits contain valid and cache flags */
  76 #define IOBMAP_L2E_V            0x80000000
  77 #define IOBMAP_L2E_V_CACHED     0xc0000000
  78
  79 static u32 __iomem *iob;
  80 static u32 iob_l1_emptyval;
  81 static u32 iob_l2_emptyval;
  82 static u32 *iob_l2_base;
  83
  84 static struct iommu_table iommu_table_iobmap;
  85 static int iommu_table_iobmap_inited;
  86
  87 static void iobmap_build(struct iommu_table *tbl, long index,
  88                          long npages, unsigned long uaddr,
  89                          enum dma_data_direction direction)
  90 {
  91         u32 *ip;
  92         u32 rpn;
  93         unsigned long bus_addr;
  94
  95         pr_debug("iobmap: build at: %lx, %lx, addr: %lx\n", index, npages, uaddr);
  96
  97         bus_addr = (tbl->it_offset + index) << IOBMAP_PAGE_SHIFT;
  98
  99         ip = ((u32 *)tbl->it_base) + index;
 100
 101         while (npages--) {
 102                 rpn = virt_to_abs(uaddr) >> IOBMAP_PAGE_SHIFT;
 103
 104                 *(ip++) = IOBMAP_L2E_V | rpn;
 105                 /* invalidate tlb, can be optimized more */
 106                 out_le32(iob+IOB_AT_INVAL_TLB_REG, bus_addr >> 14);
 107
 108                 uaddr += IOBMAP_PAGE_SIZE;
 109                 bus_addr += IOBMAP_PAGE_SIZE;
 110         }
 111 }
 112
 113
 114 static void iobmap_free(struct iommu_table *tbl, long index,
 115                         long npages)
 116 {
 117         u32 *ip;
 118         unsigned long bus_addr;
 119
 120         pr_debug("iobmap: free at: %lx, %lx\n", index, npages);
 121
 122         bus_addr = (tbl->it_offset + index) << IOBMAP_PAGE_SHIFT;
 123
 124         ip = ((u32 *)tbl->it_base) + index;
 125
 126         while (npages--) {
 127                 *(ip++) = iob_l2_emptyval;
 128                 /* invalidate tlb, can be optimized more */
 129                 out_le32(iob+IOB_AT_INVAL_TLB_REG, bus_addr >> 14);
 130                 bus_addr += IOBMAP_PAGE_SIZE;
 131         }
 132 }
 133
 134
 135 static void iommu_table_iobmap_setup(void)
 136 {
 137         pr_debug(" -> %s\n", __func__);
 138         iommu_table_iobmap.it_busno = 0;
 139         iommu_table_iobmap.it_offset = 0;
 140         /* it_size is in number of entries */
 141         iommu_table_iobmap.it_size = 0x80000000 >> IOBMAP_PAGE_SHIFT;
 142
 143         /* Initialize the common IOMMU code */
 144         iommu_table_iobmap.it_base = (unsigned long)iob_l2_base;
 145         iommu_table_iobmap.it_index = 0;
 146         /* XXXOJN tune this to avoid IOB cache invals.
 147          * Should probably be 8 (64 bytes)
 148          */
 149         iommu_table_iobmap.it_blocksize = 4;
 150         iommu_init_table(&iommu_table_iobmap, 0);
 151         pr_debug(" <- %s\n", __func__);
 152 }
 153
 154
 155
 156 static void pci_dma_bus_setup_pasemi(struct pci_bus *bus)
 157 {
 158         struct device_node *dn;
 159
 160         pr_debug("pci_dma_bus_setup, bus %p, bus->self %p\n", bus, bus->self);
 161
 162         if (!iommu_table_iobmap_inited) {
 163                 iommu_table_iobmap_inited = 1;
 164                 iommu_table_iobmap_setup();
 165         }
 166
 167         dn = pci_bus_to_OF_node(bus);
 168
 169         if (dn)
 170                 PCI_DN(dn)->iommu_table = &iommu_table_iobmap;
 171
 172 }
 173
 174
 175 static void pci_dma_dev_setup_pasemi(struct pci_dev *dev)
 176 {
 177         pr_debug("pci_dma_dev_setup, dev %p (%s)\n", dev, pci_name(dev));
 178
 179 #if !defined(CONFIG_PPC_PASEMI_IOMMU_DMA_FORCE)
 180         /* For non-LPAR environment, don't translate anything for the DMA
 181          * engine. The exception to this is if the user has enabled
 182          * CONFIG_PPC_PASEMI_IOMMU_DMA_FORCE at build time.
 183          */
 184         if (dev->vendor == 0x1959 && dev->device == 0xa007 &&
 185             !firmware_has_feature(FW_FEATURE_LPAR)) {
 186                 dev->dev.archdata.dma_ops = &dma_direct_ops;
 187                 return;
 188         }
 189 #endif
 190
 191         dev->dev.archdata.dma_data = &iommu_table_iobmap;
 192 }
 193
 194 static void pci_dma_bus_setup_null(struct pci_bus *b) { }
 195 static void pci_dma_dev_setup_null(struct pci_dev *d) { }
 196
 197 int __init iob_init(struct device_node *dn)
 198 {
 199         unsigned long tmp;
 200         u32 regword;
 201         int i;
 202
 203         pr_debug(" -> %s\n", __func__);
 204
 205         /* Allocate a spare page to map all invalid IOTLB pages. */
 206         tmp = lmb_alloc(IOBMAP_PAGE_SIZE, IOBMAP_PAGE_SIZE);
 207         if (!tmp)
 208                 panic("IOBMAP: Cannot allocate spare page!");
 209         /* Empty l1 is marked invalid */
 210         iob_l1_emptyval = 0;
 211         /* Empty l2 is mapped to dummy page */
 212         iob_l2_emptyval = IOBMAP_L2E_V | (tmp >> IOBMAP_PAGE_SHIFT);
 213
 214         iob = ioremap(IOB_BASE, IOB_SIZE);
 215         if (!iob)
 216                 panic("IOBMAP: Cannot map registers!");
 217
 218         /* setup direct mapping of the L1 entries */
 219         for (i = 0; i < 64; i++) {
 220                 /* Each L1 covers 32MB, i.e. 8K entries = 32K of ram */
 221                 regword = IOBMAP_L1E_V | (__pa(iob_l2_base + i*0x2000) >> 12);
 222                 out_le32(iob+IOB_XLT_L1_REGBASE+i, regword);
 223         }
 224
 225         /* set 2GB translation window, based at 0 */
 226         regword = in_le32(iob+IOB_AD_REG);
 227         regword &= ~IOB_AD_TRNG_MASK;
 228         regword |= IOB_AD_TRNG_2G;
 229         out_le32(iob+IOB_AD_REG, regword);
 230
 231         /* Enable translation */
 232         regword = in_le32(iob+IOBCOM_REG);
 233         regword |= IOBCOM_ATEN;
 234         out_le32(iob+IOBCOM_REG, regword);
 235
 236         pr_debug(" <- %s\n", __func__);
 237
 238         return 0;
 239 }
 240
 241
 242 /* These are called very early. */
 243 void __init iommu_init_early_pasemi(void)
 244 {
 245         int iommu_off;
 246
 247 #ifndef CONFIG_PPC_PASEMI_IOMMU
 248         iommu_off = 1;
 249 #else
 250         iommu_off = of_chosen &&
 251                         of_get_property(of_chosen, "linux,iommu-off", NULL);
 252 #endif
 253         if (iommu_off) {
 254                 /* Direct I/O, IOMMU off */
 255                 ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_null;
 256                 ppc_md.pci_dma_bus_setup = pci_dma_bus_setup_null;
 257                 set_pci_dma_ops(&dma_direct_ops);
 258
 259                 return;
 260         }
 261
 262         iob_init(NULL);
 263
 264         ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_pasemi;
 265         ppc_md.pci_dma_bus_setup = pci_dma_bus_setup_pasemi;
 266         ppc_md.tce_build = iobmap_build;
 267         ppc_md.tce_free  = iobmap_free;
 268         set_pci_dma_ops(&dma_iommu_ops);
 269 }
 270
 271 void __init alloc_iobmap_l2(void)
 272 {
 273 #ifndef CONFIG_PPC_PASEMI_IOMMU
 274         return;
 275 #endif
 276         /* For 2G space, 8x64 pages (2^21 bytes) is max total l2 size */
 277         iob_l2_base = (u32 *)abs_to_virt(lmb_alloc_base(1UL<<21, 1UL<<21, 0x80000000));
 278
 279         printk(KERN_INFO "IOBMAP L2 allocated at: %p\n", iob_l2_base);
 280 }