2 * Misc. bootloader code for IBM Spruce reference platform
4 * Authors: Johnnie Peters <jpeters@mvista.com>
5 * Matt Porter <mporter@mvista.com>
7 * Derived from arch/ppc/boot/prep/misc.c
9 * 2000-2001 (c) MontaVista, Software, Inc. This file is licensed under
10 * the terms of the GNU General Public License version 2. This program
11 * is licensed "as is" without any warranty of any kind, whether express
15 #include <linux/types.h>
16 #include <linux/pci.h>
18 #include <asm/bootinfo.h>
20 extern unsigned long decompress_kernel(unsigned long load_addr
, int num_words
,
23 /* Define some important locations of the Spruce. */
24 #define SPRUCE_PCI_CONFIG_ADDR 0xfec00000
25 #define SPRUCE_PCI_CONFIG_DATA 0xfec00004
27 /* PCI configuration space access routines. */
28 unsigned int *pci_config_address
= (unsigned int *)SPRUCE_PCI_CONFIG_ADDR
;
29 unsigned char *pci_config_data
= (unsigned char *)SPRUCE_PCI_CONFIG_DATA
;
31 void cpc700_pcibios_read_config_byte(unsigned char bus
, unsigned char dev_fn
,
32 unsigned char offset
, unsigned char *val
)
34 out_le32(pci_config_address
,
35 (((bus
& 0xff)<<16) | (dev_fn
<<8) | (offset
&0xfc) | 0x80000000));
37 *val
= (in_le32((unsigned *)pci_config_data
) >> (8 * (offset
& 3))) & 0xff;
40 void cpc700_pcibios_write_config_byte(unsigned char bus
, unsigned char dev_fn
,
41 unsigned char offset
, unsigned char val
)
43 out_le32(pci_config_address
,
44 (((bus
& 0xff)<<16) | (dev_fn
<<8) | (offset
&0xfc) | 0x80000000));
46 out_8(pci_config_data
+ (offset
&3), val
);
49 void cpc700_pcibios_read_config_word(unsigned char bus
, unsigned char dev_fn
,
50 unsigned char offset
, unsigned short *val
)
52 out_le32(pci_config_address
,
53 (((bus
& 0xff)<<16) | (dev_fn
<<8) | (offset
&0xfc) | 0x80000000));
55 *val
= in_le16((unsigned short *)(pci_config_data
+ (offset
&3)));
58 void cpc700_pcibios_write_config_word(unsigned char bus
, unsigned char dev_fn
,
59 unsigned char offset
, unsigned short val
)
61 out_le32(pci_config_address
,
62 (((bus
& 0xff)<<16) | (dev_fn
<<8) | (offset
&0xfc) | 0x80000000));
64 out_le16((unsigned short *)(pci_config_data
+ (offset
&3)), val
);
67 void cpc700_pcibios_read_config_dword(unsigned char bus
, unsigned char dev_fn
,
68 unsigned char offset
, unsigned int *val
)
70 out_le32(pci_config_address
,
71 (((bus
& 0xff)<<16) | (dev_fn
<<8) | (offset
&0xfc) | 0x80000000));
73 *val
= in_le32((unsigned *)pci_config_data
);
76 void cpc700_pcibios_write_config_dword(unsigned char bus
, unsigned char dev_fn
,
77 unsigned char offset
, unsigned int val
)
79 out_le32(pci_config_address
,
80 (((bus
& 0xff)<<16) | (dev_fn
<<8) | (offset
&0xfc) | 0x80000000));
82 out_le32((unsigned *)pci_config_data
, val
);
85 #define PCNET32_WIO_RDP 0x10
86 #define PCNET32_WIO_RAP 0x12
87 #define PCNET32_WIO_RESET 0x14
89 #define PCNET32_DWIO_RDP 0x10
90 #define PCNET32_DWIO_RAP 0x14
91 #define PCNET32_DWIO_RESET 0x18
93 /* Processor interface config register access */
94 #define PIFCFGADDR 0xff500000
95 #define PIFCFGDATA 0xff500004
97 #define PLBMIFOPT 0x18 /* PLB Master Interface Options */
100 #define MEM_TYPE 0x28
101 #define MEM_B1SA 0x3c
102 #define MEM_B1EA 0x5c
103 #define MEM_B2SA 0x40
104 #define MEM_B2EA 0x60
110 unsigned long mem_size
= 0;
111 unsigned long mem_mben
;
112 unsigned long mem_type
;
113 unsigned long mem_start
;
114 unsigned long mem_end
;
115 volatile int *mem_addr
= (int *)0xff500008;
116 volatile int *mem_data
= (int *)0xff50000c;
118 /* Get the size of memory from the memory controller. */
119 *mem_addr
= MEM_MBEN
;
121 mem_mben
= *mem_data
;
123 for(loop
= 0; loop
< 1000; loop
++);
125 *mem_addr
= MEM_TYPE
;
127 mem_type
= *mem_data
;
129 for(loop
= 0; loop
< 1000; loop
++);
131 *mem_addr
= MEM_TYPE
;
132 /* Confirm bank 1 has DRAM memory */
133 if ((mem_mben
& 0x40000000) &&
134 ((mem_type
& 0x30000000) == 0x10000000)) {
135 *mem_addr
= MEM_B1SA
;
137 mem_start
= *mem_data
;
139 for(loop
= 0; loop
< 1000; loop
++);
141 *mem_addr
= MEM_B1EA
;
145 for(loop
= 0; loop
< 1000; loop
++);
147 mem_size
= mem_end
- mem_start
+ 0x100000;
150 /* Confirm bank 2 has DRAM memory */
151 if ((mem_mben
& 0x20000000) &&
152 ((mem_type
& 0xc000000) == 0x4000000)) {
153 *mem_addr
= MEM_B2SA
;
155 mem_start
= *mem_data
;
157 for(loop
= 0; loop
< 1000; loop
++);
159 *mem_addr
= MEM_B2EA
;
163 for(loop
= 0; loop
< 1000; loop
++);
165 mem_size
+= mem_end
- mem_start
+ 0x100000;
171 load_kernel(unsigned long load_addr
, int num_words
, unsigned long cksum
,
172 void *ign1
, void *ign2
)
178 unsigned short vendor
;
179 unsigned short device
;
180 unsigned short command
;
181 unsigned char header_type
;
183 volatile int *pif_addr
= (int *)0xff500000;
184 volatile int *pif_data
= (int *)0xff500004;
187 * Gah, these firmware guys need to learn that hardware
188 * byte swapping is evil! Disable all hardware byte
189 * swapping so it doesn't hurt anyone.
191 *pif_addr
= PLBMIFOPT
;
193 *pif_data
= 0x00000000;
196 /* Search out and turn off the PcNet ethernet boot device. */
197 for (pci_devfn
= 1; pci_devfn
< 0xff; pci_devfn
++) {
198 if (PCI_FUNC(pci_devfn
) && !found_multi
)
201 cpc700_pcibios_read_config_byte(0, pci_devfn
,
202 PCI_HEADER_TYPE
, &header_type
);
204 if (!PCI_FUNC(pci_devfn
))
205 found_multi
= header_type
& 0x80;
207 cpc700_pcibios_read_config_word(0, pci_devfn
, PCI_VENDOR_ID
,
210 if (vendor
!= 0xffff) {
211 cpc700_pcibios_read_config_word(0, pci_devfn
,
212 PCI_DEVICE_ID
, &device
);
214 /* If this PCI device is the Lance PCNet board then turn it off */
215 if ((vendor
== PCI_VENDOR_ID_AMD
) &&
216 (device
== PCI_DEVICE_ID_AMD_LANCE
)) {
218 /* Turn on I/O Space on the board. */
219 cpc700_pcibios_read_config_word(0, pci_devfn
,
220 PCI_COMMAND
, &command
);
222 cpc700_pcibios_write_config_word(0, pci_devfn
,
223 PCI_COMMAND
, command
);
225 /* Get the I/O space address */
226 cpc700_pcibios_read_config_dword(0, pci_devfn
,
227 PCI_BASE_ADDRESS_0
, &bar0
);
230 /* Reset the PCNet Board */
231 inl (bar0
+PCNET32_DWIO_RESET
);
232 inw (bar0
+PCNET32_WIO_RESET
);
234 /* First do a work oriented read of csr0. If the value is
235 * 4 then this is the correct mode to access the board.
236 * If not try a double word ortiented read.
238 outw(0, bar0
+ PCNET32_WIO_RAP
);
239 csr0
= inw(bar0
+ PCNET32_WIO_RDP
);
242 /* Check the Chip id register */
243 outw(88, bar0
+ PCNET32_WIO_RAP
);
244 csr_id
= inw(bar0
+ PCNET32_WIO_RDP
);
247 /* This is the valid mode - set the stop bit */
248 outw(0, bar0
+ PCNET32_WIO_RAP
);
249 outw(csr0
, bar0
+ PCNET32_WIO_RDP
);
252 outl(0, bar0
+ PCNET32_DWIO_RAP
);
253 csr0
= inl(bar0
+ PCNET32_DWIO_RDP
);
255 /* Check the Chip id register */
256 outl(88, bar0
+ PCNET32_WIO_RAP
);
257 csr_id
= inl(bar0
+ PCNET32_WIO_RDP
);
260 /* This is the valid mode - set the stop bit*/
261 outl(0, bar0
+ PCNET32_WIO_RAP
);
262 outl(csr0
, bar0
+ PCNET32_WIO_RDP
);
270 return decompress_kernel(load_addr
, num_words
, cksum
);