arch/ppc/platforms/chestnut.c

   1 /*
   2  * Board setup routines for IBM Chestnut
   3  *
   4  * Author: <source@mvista.com>
   5  *
   6  * <2004> (c) MontaVista Software, Inc. This file is licensed under
   7  * the terms of the GNU General Public License version 2. This program
   8  * is licensed "as is" without any warranty of any kind, whether express
   9  * or implied.
  10  */
  11
  12 #include <linux/stddef.h>
  13 #include <linux/kernel.h>
  14 #include <linux/init.h>
  15 #include <linux/errno.h>
  16 #include <linux/reboot.h>
  17 #include <linux/kdev_t.h>
  18 #include <linux/major.h>
  19 #include <linux/blkdev.h>
  20 #include <linux/console.h>
  21 #include <linux/root_dev.h>
  22 #include <linux/initrd.h>
  23 #include <linux/delay.h>
  24 #include <linux/seq_file.h>
  25 #include <linux/ide.h>
  26 #include <linux/serial.h>
  27 #include <linux/serial_core.h>
  28 #include <linux/serial_8250.h>
  29 #include <linux/mtd/physmap.h>
  30 #include <asm/system.h>
  31 #include <asm/pgtable.h>
  32 #include <asm/page.h>
  33 #include <asm/time.h>
  34 #include <asm/dma.h>
  35 #include <asm/io.h>
  36 #include <asm/hw_irq.h>
  37 #include <asm/machdep.h>
  38 #include <asm/kgdb.h>
  39 #include <asm/bootinfo.h>
  40 #include <asm/mv64x60.h>
  41 #include <platforms/chestnut.h>
  42
  43 static void __iomem *sram_base; /* Virtual addr of Internal SRAM */
  44 static void __iomem *cpld_base; /* Virtual addr of CPLD Regs */
  45
  46 static mv64x60_handle_t bh;
  47
  48 extern void gen550_progress(char *, unsigned short);
  49 extern void gen550_init(int, struct uart_port *);
  50 extern void mv64360_pcibios_fixup(mv64x60_handle_t *bh);
  51
  52 #define CHESTNUT_PRESERVE_MASK (BIT(MV64x60_CPU2DEV_0_WIN) | \
  53                                 BIT(MV64x60_CPU2DEV_1_WIN) | \
  54                                 BIT(MV64x60_CPU2DEV_2_WIN) | \
  55                                 BIT(MV64x60_CPU2DEV_3_WIN) | \
  56                                 BIT(MV64x60_CPU2BOOT_WIN))
  57 /**************************************************************************
  58  * FUNCTION: chestnut_calibrate_decr
  59  *
  60  * DESCRIPTION: initialize decrementer interrupt frequency (used as system
  61  *              timer)
  62  *
  63  ****/
  64 static void __init
  65 chestnut_calibrate_decr(void)
  66 {
  67         ulong freq;
  68
  69         freq = CHESTNUT_BUS_SPEED / 4;
  70
  71         printk("time_init: decrementer frequency = %lu.%.6lu MHz\n",
  72                 freq/1000000, freq%1000000);
  73
  74         tb_ticks_per_jiffy = freq / HZ;
  75         tb_to_us = mulhwu_scale_factor(freq, 1000000);
  76 }
  77
  78 static int
  79 chestnut_show_cpuinfo(struct seq_file *m)
  80 {
  81         seq_printf(m, "vendor\t\t: IBM\n");
  82         seq_printf(m, "machine\t\t: 750FX/GX Eval Board (Chestnut/Buckeye)\n");
  83
  84         return 0;
  85 }
  86
  87 /**************************************************************************
  88  * FUNCTION: chestnut_find_end_of_memory
  89  *
  90  * DESCRIPTION: ppc_md memory size callback
  91  *
  92  ****/
  93 unsigned long __init
  94 chestnut_find_end_of_memory(void)
  95 {
  96         static int  mem_size = 0;
  97
  98         if (mem_size == 0) {
  99                 mem_size = mv64x60_get_mem_size(CONFIG_MV64X60_NEW_BASE,
 100                                 MV64x60_TYPE_MV64460);
 101         }
 102         return mem_size;
 103 }
 104
 105 #if defined(CONFIG_SERIAL_8250)
 106 static void __init
 107 chestnut_early_serial_map(void)
 108 {
 109         struct uart_port port;
 110
 111         /* Setup serial port access */
 112         memset(&port, 0, sizeof(port));
 113         port.uartclk = BASE_BAUD * 16;
 114         port.irq = UART0_INT;
 115         port.flags = STD_COM_FLAGS | UPF_IOREMAP;
 116         port.iotype = UPIO_MEM;
 117         port.mapbase = CHESTNUT_UART0_IO_BASE;
 118         port.regshift = 0;
 119
 120         if (early_serial_setup(&port) != 0)
 121                 printk("Early serial init of port 0 failed\n");
 122
 123         /* Assume early_serial_setup() doesn't modify serial_req */
 124         port.line = 1;
 125         port.irq = UART1_INT;
 126         port.mapbase = CHESTNUT_UART1_IO_BASE;
 127
 128         if (early_serial_setup(&port) != 0)
 129                 printk("Early serial init of port 1 failed\n");
 130 }
 131 #endif
 132
 133 /**************************************************************************
 134  * FUNCTION: chestnut_map_irq
 135  *
 136  * DESCRIPTION: 0 return since PCI IRQs not needed
 137  *
 138  ****/
 139 static int __init
 140 chestnut_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
 141 {
 142         static char pci_irq_table[][4] = {
 143                 {CHESTNUT_PCI_SLOT0_IRQ, CHESTNUT_PCI_SLOT0_IRQ,
 144                  CHESTNUT_PCI_SLOT0_IRQ, CHESTNUT_PCI_SLOT0_IRQ},
 145                 {CHESTNUT_PCI_SLOT1_IRQ, CHESTNUT_PCI_SLOT1_IRQ,
 146                  CHESTNUT_PCI_SLOT1_IRQ, CHESTNUT_PCI_SLOT1_IRQ},
 147                 {CHESTNUT_PCI_SLOT2_IRQ, CHESTNUT_PCI_SLOT2_IRQ,
 148                  CHESTNUT_PCI_SLOT2_IRQ, CHESTNUT_PCI_SLOT2_IRQ},
 149                 {CHESTNUT_PCI_SLOT3_IRQ, CHESTNUT_PCI_SLOT3_IRQ,
 150                  CHESTNUT_PCI_SLOT3_IRQ, CHESTNUT_PCI_SLOT3_IRQ},
 151         };
 152         const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
 153
 154         return PCI_IRQ_TABLE_LOOKUP;
 155 }
 156
 157
 158 /**************************************************************************
 159  * FUNCTION: chestnut_setup_bridge
 160  *
 161  * DESCRIPTION: initalize board-specific settings on the MV64360
 162  *
 163  ****/
 164 static void __init
 165 chestnut_setup_bridge(void)
 166 {
 167         struct mv64x60_setup_info       si;
 168         int i;
 169
 170         if ( ppc_md.progress )
 171                 ppc_md.progress("chestnut_setup_bridge: enter", 0);
 172
 173         memset(&si, 0, sizeof(si));
 174
 175         si.phys_reg_base = CONFIG_MV64X60_NEW_BASE;
 176
 177         /* setup only PCI bus 0 (bus 1 not used) */
 178         si.pci_0.enable_bus = 1;
 179         si.pci_0.pci_io.cpu_base = CHESTNUT_PCI0_IO_PROC_ADDR;
 180         si.pci_0.pci_io.pci_base_hi = 0;
 181         si.pci_0.pci_io.pci_base_lo = CHESTNUT_PCI0_IO_PCI_ADDR;
 182         si.pci_0.pci_io.size = CHESTNUT_PCI0_IO_SIZE;
 183         si.pci_0.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE; /* no swapping */
 184         si.pci_0.pci_mem[0].cpu_base = CHESTNUT_PCI0_MEM_PROC_ADDR;
 185         si.pci_0.pci_mem[0].pci_base_hi = CHESTNUT_PCI0_MEM_PCI_HI_ADDR;
 186         si.pci_0.pci_mem[0].pci_base_lo = CHESTNUT_PCI0_MEM_PCI_LO_ADDR;
 187         si.pci_0.pci_mem[0].size = CHESTNUT_PCI0_MEM_SIZE;
 188         si.pci_0.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE; /* no swapping */
 189         si.pci_0.pci_cmd_bits = 0;
 190         si.pci_0.latency_timer = 0x80;
 191
 192         for (i=0; i<MV64x60_CPU2MEM_WINDOWS; i++) {
 193 #if defined(CONFIG_NOT_COHERENT_CACHE)
 194                 si.cpu_prot_options[i] = 0;
 195                 si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE;
 196                 si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE;
 197                 si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE;
 198
 199                 si.pci_1.acc_cntl_options[i] =
 200                     MV64360_PCI_ACC_CNTL_SNOOP_NONE |
 201                     MV64360_PCI_ACC_CNTL_SWAP_NONE |
 202                     MV64360_PCI_ACC_CNTL_MBURST_128_BYTES |
 203                     MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
 204 #else
 205                 si.cpu_prot_options[i] = 0;
 206                 si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE; /* errata */
 207                 si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE; /* errata */
 208                 si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE; /* errata */
 209
 210                 si.pci_1.acc_cntl_options[i] =
 211                     MV64360_PCI_ACC_CNTL_SNOOP_WB |
 212                     MV64360_PCI_ACC_CNTL_SWAP_NONE |
 213                     MV64360_PCI_ACC_CNTL_MBURST_32_BYTES |
 214                     MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES;
 215 #endif
 216         }
 217
 218         /* Lookup host bridge - on CPU 0 - no SMP support */
 219         if (mv64x60_init(&bh, &si)) {
 220                 printk("\n\nPCI Bridge initialization failed!\n");
 221         }
 222
 223         pci_dram_offset = 0;
 224         ppc_md.pci_swizzle = common_swizzle;
 225         ppc_md.pci_map_irq = chestnut_map_irq;
 226         ppc_md.pci_exclude_device = mv64x60_pci_exclude_device;
 227
 228         mv64x60_set_bus(&bh, 0, 0);
 229         bh.hose_a->first_busno = 0;
 230         bh.hose_a->last_busno = 0xff;
 231         bh.hose_a->last_busno = pciauto_bus_scan(bh.hose_a, 0);
 232 }
 233
 234 void __init
 235 chestnut_setup_peripherals(void)
 236 {
 237         mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN,
 238                         CHESTNUT_BOOT_8BIT_BASE, CHESTNUT_BOOT_8BIT_SIZE, 0);
 239         bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
 240
 241         mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN,
 242                         CHESTNUT_32BIT_BASE, CHESTNUT_32BIT_SIZE, 0);
 243         bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_0_WIN);
 244
 245         mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN,
 246                         CHESTNUT_CPLD_BASE, CHESTNUT_CPLD_SIZE, 0);
 247         bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN);
 248         cpld_base = ioremap(CHESTNUT_CPLD_BASE, CHESTNUT_CPLD_SIZE);
 249
 250         mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_2_WIN,
 251                         CHESTNUT_UART_BASE, CHESTNUT_UART_SIZE, 0);
 252         bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_2_WIN);
 253
 254         mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_3_WIN,
 255                         CHESTNUT_FRAM_BASE, CHESTNUT_FRAM_SIZE, 0);
 256         bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_3_WIN);
 257
 258         mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN,
 259                         CHESTNUT_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0);
 260         bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN);
 261
 262 #ifdef CONFIG_NOT_COHERENT_CACHE
 263         mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b0);
 264 #else
 265         mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b2);
 266 #endif
 267         sram_base = ioremap(CHESTNUT_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE);
 268         memset(sram_base, 0, MV64360_SRAM_SIZE);
 269
 270         /*
 271          * Configure MPP pins for PCI DMA
 272          *
 273          * PCI Slot     GNT pin         REQ pin
 274          *      0       MPP16           MPP17
 275          *      1       MPP18           MPP19
 276          *      2       MPP20           MPP21
 277          *      3       MPP22           MPP23
 278          */
 279         mv64x60_write(&bh, MV64x60_MPP_CNTL_2,
 280                         (0x1 << 0)  |   /* MPPSel16 PCI0_GNT[0] */
 281                         (0x1 << 4)  |   /* MPPSel17 PCI0_REQ[0] */
 282                         (0x1 << 8)  |   /* MPPSel18 PCI0_GNT[1] */
 283                         (0x1 << 12) |   /* MPPSel19 PCI0_REQ[1] */
 284                         (0x1 << 16) |   /* MPPSel20 PCI0_GNT[2] */
 285                         (0x1 << 20) |   /* MPPSel21 PCI0_REQ[2] */
 286                         (0x1 << 24) |   /* MPPSel22 PCI0_GNT[3] */
 287                         (0x1 << 28));   /* MPPSel23 PCI0_REQ[3] */
 288         /*
 289          * Set unused MPP pins for output, as per schematic note
 290          *
 291          * Unused Pins: MPP01, MPP02, MPP04, MPP05, MPP06
 292          *              MPP09, MPP10, MPP13, MPP14, MPP15
 293          */
 294         mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_0,
 295                         (0xf << 4)  |   /* MPPSel01 GPIO[1] */
 296                         (0xf << 8)  |   /* MPPSel02 GPIO[2] */
 297                         (0xf << 16) |   /* MPPSel04 GPIO[4] */
 298                         (0xf << 20) |   /* MPPSel05 GPIO[5] */
 299                         (0xf << 24));   /* MPPSel06 GPIO[6] */
 300         mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_1,
 301                         (0xf << 4)  |   /* MPPSel09 GPIO[9] */
 302                         (0xf << 8)  |   /* MPPSel10 GPIO[10] */
 303                         (0xf << 20) |   /* MPPSel13 GPIO[13] */
 304                         (0xf << 24) |   /* MPPSel14 GPIO[14] */
 305                         (0xf << 28));   /* MPPSel15 GPIO[15] */
 306         mv64x60_set_bits(&bh, MV64x60_GPP_IO_CNTL, /* Output */
 307                         BIT(1)  | BIT(2)  | BIT(4)  | BIT(5)  | BIT(6)  |
 308                         BIT(9)  | BIT(10) | BIT(13) | BIT(14) | BIT(15));
 309
 310         /*
 311          * Configure the following MPP pins to indicate a level
 312          * triggered interrupt
 313          *
 314          * MPP24 - Board Reset (just map the MPP & GPP for chestnut_reset)
 315          * MPP25 - UART A  (high)
 316          * MPP26 - UART B  (high)
 317          * MPP28 - PCI Slot 3 (low)
 318          * MPP29 - PCI Slot 2 (low)
 319          * MPP30 - PCI Slot 1 (low)
 320          * MPP31 - PCI Slot 0 (low)
 321          */
 322         mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_3,
 323                         BIT(3) | BIT(2) | BIT(1) | BIT(0)        | /* MPP 24 */
 324                         BIT(7) | BIT(6) | BIT(5) | BIT(4)        | /* MPP 25 */
 325                         BIT(11) | BIT(10) | BIT(9) | BIT(8)      | /* MPP 26 */
 326                         BIT(19) | BIT(18) | BIT(17) | BIT(16)    | /* MPP 28 */
 327                         BIT(23) | BIT(22) | BIT(21) | BIT(20)    | /* MPP 29 */
 328                         BIT(27) | BIT(26) | BIT(25) | BIT(24)    | /* MPP 30 */
 329                         BIT(31) | BIT(30) | BIT(29) | BIT(28));    /* MPP 31 */
 330
 331         /*
 332          * Define GPP 25 (high), 26 (high), 28 (low), 29 (low), 30 (low),
 333          * 31 (low) interrupt polarity input signal and level triggered
 334          */
 335         mv64x60_clr_bits(&bh, MV64x60_GPP_LEVEL_CNTL, BIT(25) | BIT(26));
 336         mv64x60_set_bits(&bh, MV64x60_GPP_LEVEL_CNTL,
 337                         BIT(28) | BIT(29) | BIT(30) | BIT(31));
 338         mv64x60_clr_bits(&bh, MV64x60_GPP_IO_CNTL,
 339                         BIT(25) | BIT(26) | BIT(28) | BIT(29) | BIT(30) |
 340                         BIT(31));
 341
 342         /* Config GPP interrupt controller to respond to level trigger */
 343         mv64x60_set_bits(&bh, MV64360_COMM_ARBITER_CNTL, BIT(10));
 344
 345         /*
 346          * Dismiss and then enable interrupt on GPP interrupt cause for CPU #0
 347          */
 348         mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE,
 349                         ~(BIT(25) | BIT(26) | BIT(28) | BIT(29) | BIT(30) |
 350                           BIT(31)));
 351         mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK,
 352                         BIT(25) | BIT(26) | BIT(28) | BIT(29) | BIT(30) |
 353                         BIT(31));
 354
 355         /*
 356          * Dismiss and then enable interrupt on CPU #0 high cause register
 357          * BIT27 summarizes GPP interrupts 24-31
 358          */
 359         mv64x60_set_bits(&bh, MV64360_IC_CPU0_INTR_MASK_HI, BIT(27));
 360
 361         if (ppc_md.progress)
 362                 ppc_md.progress("chestnut_setup_bridge: exit", 0);
 363 }
 364
 365 /**************************************************************************
 366  * FUNCTION: chestnut_setup_arch
 367  *
 368  * DESCRIPTION: ppc_md machine configuration callback
 369  *
 370  ****/
 371 static void __init
 372 chestnut_setup_arch(void)
 373 {
 374         if (ppc_md.progress)
 375                 ppc_md.progress("chestnut_setup_arch: enter", 0);
 376
 377         /* init to some ~sane value until calibrate_delay() runs */
 378         loops_per_jiffy = 50000000 / HZ;
 379
 380         /* if the time base value is greater than bus freq/4 (the TB and
 381         * decrementer tick rate) + signed integer rollover value, we
 382         * can spend a fair amount of time waiting for the rollover to
 383         * happen.  To get around this, initialize the time base register
 384         * to a "safe" value.
 385         */
 386         set_tb(0, 0);
 387
 388 #ifdef CONFIG_BLK_DEV_INITRD
 389         if (initrd_start)
 390                 ROOT_DEV = Root_RAM0;
 391         else
 392 #endif
 393 #ifdef CONFIG_ROOT_NFS
 394                 ROOT_DEV = Root_NFS;
 395 #else
 396                 ROOT_DEV = Root_SDA2;
 397 #endif
 398
 399         /*
 400         * Set up the L2CR register.
 401         */
 402         _set_L2CR(_get_L2CR() | L2CR_L2E);
 403
 404         chestnut_setup_bridge();
 405         chestnut_setup_peripherals();
 406
 407 #ifdef CONFIG_DUMMY_CONSOLE
 408         conswitchp = &dummy_con;
 409 #endif
 410
 411 #if defined(CONFIG_SERIAL_8250)
 412         chestnut_early_serial_map();
 413 #endif
 414
 415         /* Identify the system */
 416         printk(KERN_INFO "System Identification: IBM 750FX/GX Eval Board\n");
 417         printk(KERN_INFO "IBM 750FX/GX port (C) 2004 MontaVista Software, Inc."
 418                 " (source@mvista.com)\n");
 419
 420         if (ppc_md.progress)
 421                 ppc_md.progress("chestnut_setup_arch: exit", 0);
 422 }
 423
 424 #ifdef CONFIG_MTD_PHYSMAP
 425 static struct mtd_partition ptbl;
 426
 427 static int __init
 428 chestnut_setup_mtd(void)
 429 {
 430         memset(&ptbl, 0, sizeof(ptbl));
 431
 432         ptbl.name = "User FS";
 433         ptbl.size = CHESTNUT_32BIT_SIZE;
 434
 435         physmap_map.size = CHESTNUT_32BIT_SIZE;
 436         physmap_set_partitions(&ptbl, 1);
 437         return 0;
 438 }
 439
 440 arch_initcall(chestnut_setup_mtd);
 441 #endif
 442
 443 /**************************************************************************
 444  * FUNCTION: chestnut_restart
 445  *
 446  * DESCRIPTION: ppc_md machine reset callback
 447  *              reset the board via the CPLD command register
 448  *
 449  ****/
 450 static void
 451 chestnut_restart(char *cmd)
 452 {
 453         volatile ulong i = 10000000;
 454
 455         local_irq_disable();
 456
 457         /*
 458          * Set CPLD Reg 3 bit 0 to 1 to allow MPP signals on reset to work
 459          *
 460          * MPP24 - board reset
 461          */
 462         writeb(0x1, cpld_base + 3);
 463
 464         /* GPP pin tied to MPP earlier */
 465         mv64x60_set_bits(&bh, MV64x60_GPP_VALUE_SET, BIT(24));
 466
 467         while (i-- > 0);
 468         panic("restart failed\n");
 469 }
 470
 471 static void
 472 chestnut_halt(void)
 473 {
 474         local_irq_disable();
 475         for (;;);
 476         /* NOTREACHED */
 477 }
 478
 479 static void
 480 chestnut_power_off(void)
 481 {
 482         chestnut_halt();
 483         /* NOTREACHED */
 484 }
 485
 486 /**************************************************************************
 487  * FUNCTION: chestnut_map_io
 488  *
 489  * DESCRIPTION: configure fixed memory-mapped IO
 490  *
 491  ****/
 492 static void __init
 493 chestnut_map_io(void)
 494 {
 495 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
 496         io_block_mapping(CHESTNUT_UART_BASE, CHESTNUT_UART_BASE, 0x100000,
 497                 _PAGE_IO);
 498 #endif
 499 }
 500
 501 /**************************************************************************
 502  * FUNCTION: chestnut_set_bat
 503  *
 504  * DESCRIPTION: configures a (temporary) bat mapping for early access to
 505  *              device I/O
 506  *
 507  ****/
 508 static __inline__ void
 509 chestnut_set_bat(void)
 510 {
 511         mb();
 512         mtspr(SPRN_DBAT3U, 0xf0001ffe);
 513         mtspr(SPRN_DBAT3L, 0xf000002a);
 514         mb();
 515 }
 516
 517 /**************************************************************************
 518  * FUNCTION: platform_init
 519  *
 520  * DESCRIPTION: main entry point for configuring board-specific machine
 521  *              callbacks
 522  *
 523  ****/
 524 void __init
 525 platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
 526               unsigned long r6, unsigned long r7)
 527 {
 528         parse_bootinfo(find_bootinfo());
 529
 530         /* Copy the kernel command line arguments to a safe place. */
 531
 532         if (r6) {
 533                 *(char *) (r7 + KERNELBASE) = 0;
 534                 strcpy(cmd_line, (char *) (r6 + KERNELBASE));
 535         }
 536
 537         isa_mem_base = 0;
 538
 539         ppc_md.setup_arch = chestnut_setup_arch;
 540         ppc_md.show_cpuinfo = chestnut_show_cpuinfo;
 541         ppc_md.init_IRQ = mv64360_init_irq;
 542         ppc_md.get_irq = mv64360_get_irq;
 543         ppc_md.init = NULL;
 544
 545         ppc_md.find_end_of_memory = chestnut_find_end_of_memory;
 546         ppc_md.setup_io_mappings  = chestnut_map_io;
 547
 548         ppc_md.restart = chestnut_restart;
 549         ppc_md.power_off = chestnut_power_off;
 550         ppc_md.halt = chestnut_halt;
 551
 552         ppc_md.time_init = NULL;
 553         ppc_md.set_rtc_time = NULL;
 554         ppc_md.get_rtc_time = NULL;
 555         ppc_md.calibrate_decr = chestnut_calibrate_decr;
 556
 557         ppc_md.nvram_read_val = NULL;
 558         ppc_md.nvram_write_val = NULL;
 559
 560         ppc_md.heartbeat = NULL;
 561
 562         bh.p_base = CONFIG_MV64X60_NEW_BASE;
 563
 564         chestnut_set_bat();
 565
 566 #if defined(CONFIG_SERIAL_TEXT_DEBUG)
 567         ppc_md.progress = gen550_progress;
 568 #endif
 569 #if defined(CONFIG_KGDB)
 570         ppc_md.kgdb_map_scc = gen550_kgdb_map_scc;
 571 #endif
 572
 573         if (ppc_md.progress)
 574                 ppc_md.progress("chestnut_init(): exit", 0);
 575 }