arch/sh/drivers/dma/dma-sh.c

   1 /*
   2  * arch/sh/drivers/dma/dma-sh.c
   3  *
   4  * SuperH On-chip DMAC Support
   5  *
   6  * Copyright (C) 2000 Takashi YOSHII
   7  * Copyright (C) 2003, 2004 Paul Mundt
   8  * Copyright (C) 2005 Andriy Skulysh
   9  *
  10  * This file is subject to the terms and conditions of the GNU General Public
  11  * License.  See the file "COPYING" in the main directory of this archive
  12  * for more details.
  13  */
  14 #include <linux/init.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/module.h>
  17 #include <asm/dreamcast/dma.h>
  18 #include <asm/dma.h>
  19 #include <asm/io.h>
  20 #include "dma-sh.h"
  21
  22 static int dmte_irq_map[] = {
  23         DMTE0_IRQ,
  24         DMTE1_IRQ,
  25         DMTE2_IRQ,
  26         DMTE3_IRQ,
  27 #if defined(CONFIG_CPU_SUBTYPE_SH7720)  ||      \
  28     defined(CONFIG_CPU_SUBTYPE_SH7721)  ||      \
  29     defined(CONFIG_CPU_SUBTYPE_SH7751R) ||      \
  30     defined(CONFIG_CPU_SUBTYPE_SH7760)  ||      \
  31     defined(CONFIG_CPU_SUBTYPE_SH7709)  ||      \
  32     defined(CONFIG_CPU_SUBTYPE_SH7780)
  33         DMTE4_IRQ,
  34         DMTE5_IRQ,
  35 #endif
  36 #if defined(CONFIG_CPU_SUBTYPE_SH7751R) ||      \
  37     defined(CONFIG_CPU_SUBTYPE_SH7760)  ||      \
  38     defined(CONFIG_CPU_SUBTYPE_SH7780)
  39         DMTE6_IRQ,
  40         DMTE7_IRQ,
  41 #endif
  42 };
  43
  44 static inline unsigned int get_dmte_irq(unsigned int chan)
  45 {
  46         unsigned int irq = 0;
  47         if (chan < ARRAY_SIZE(dmte_irq_map))
  48                 irq = dmte_irq_map[chan];
  49         return irq;
  50 }
  51
  52 /*
  53  * We determine the correct shift size based off of the CHCR transmit size
  54  * for the given channel. Since we know that it will take:
  55  *
  56  *      info->count >> ts_shift[transmit_size]
  57  *
  58  * iterations to complete the transfer.
  59  */
  60 static inline unsigned int calc_xmit_shift(struct dma_channel *chan)
  61 {
  62         u32 chcr = ctrl_inl(CHCR[chan->chan]);
  63
  64         return ts_shift[(chcr & CHCR_TS_MASK)>>CHCR_TS_SHIFT];
  65 }
  66
  67 /*
  68  * The transfer end interrupt must read the chcr register to end the
  69  * hardware interrupt active condition.
  70  * Besides that it needs to waken any waiting process, which should handle
  71  * setting up the next transfer.
  72  */
  73 static irqreturn_t dma_tei(int irq, void *dev_id)
  74 {
  75         struct dma_channel *chan = dev_id;
  76         u32 chcr;
  77
  78         chcr = ctrl_inl(CHCR[chan->chan]);
  79
  80         if (!(chcr & CHCR_TE))
  81                 return IRQ_NONE;
  82
  83         chcr &= ~(CHCR_IE | CHCR_DE);
  84         ctrl_outl(chcr, CHCR[chan->chan]);
  85
  86         wake_up(&chan->wait_queue);
  87
  88         return IRQ_HANDLED;
  89 }
  90
  91 static int sh_dmac_request_dma(struct dma_channel *chan)
  92 {
  93 <<<<<<< HEAD:arch/sh/drivers/dma/dma-sh.c
  94         if (unlikely(!chan->flags & DMA_TEI_CAPABLE))
  95 =======
  96         if (unlikely(!(chan->flags & DMA_TEI_CAPABLE)))
  97 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/sh/drivers/dma/dma-sh.c
  98                 return 0;
  99
 100         return request_irq(get_dmte_irq(chan->chan), dma_tei,
 101                            IRQF_DISABLED, chan->dev_id, chan);
 102 }
 103
 104 static void sh_dmac_free_dma(struct dma_channel *chan)
 105 {
 106         free_irq(get_dmte_irq(chan->chan), chan);
 107 }
 108
 109 static int
 110 sh_dmac_configure_channel(struct dma_channel *chan, unsigned long chcr)
 111 {
 112         if (!chcr)
 113                 chcr = RS_DUAL | CHCR_IE;
 114
 115         if (chcr & CHCR_IE) {
 116                 chcr &= ~CHCR_IE;
 117                 chan->flags |= DMA_TEI_CAPABLE;
 118         } else {
 119                 chan->flags &= ~DMA_TEI_CAPABLE;
 120         }
 121
 122         ctrl_outl(chcr, CHCR[chan->chan]);
 123
 124         chan->flags |= DMA_CONFIGURED;
 125         return 0;
 126 }
 127
 128 static void sh_dmac_enable_dma(struct dma_channel *chan)
 129 {
 130         int irq;
 131         u32 chcr;
 132
 133         chcr = ctrl_inl(CHCR[chan->chan]);
 134         chcr |= CHCR_DE;
 135
 136         if (chan->flags & DMA_TEI_CAPABLE)
 137                 chcr |= CHCR_IE;
 138
 139         ctrl_outl(chcr, CHCR[chan->chan]);
 140
 141         if (chan->flags & DMA_TEI_CAPABLE) {
 142                 irq = get_dmte_irq(chan->chan);
 143                 enable_irq(irq);
 144         }
 145 }
 146
 147 static void sh_dmac_disable_dma(struct dma_channel *chan)
 148 {
 149         int irq;
 150         u32 chcr;
 151
 152         if (chan->flags & DMA_TEI_CAPABLE) {
 153                 irq = get_dmte_irq(chan->chan);
 154                 disable_irq(irq);
 155         }
 156
 157         chcr = ctrl_inl(CHCR[chan->chan]);
 158         chcr &= ~(CHCR_DE | CHCR_TE | CHCR_IE);
 159         ctrl_outl(chcr, CHCR[chan->chan]);
 160 }
 161
 162 static int sh_dmac_xfer_dma(struct dma_channel *chan)
 163 {
 164         /*
 165          * If we haven't pre-configured the channel with special flags, use
 166          * the defaults.
 167          */
 168         if (unlikely(!(chan->flags & DMA_CONFIGURED)))
 169                 sh_dmac_configure_channel(chan, 0);
 170
 171         sh_dmac_disable_dma(chan);
 172
 173         /*
 174          * Single-address mode usage note!
 175          *
 176          * It's important that we don't accidentally write any value to SAR/DAR
 177          * (this includes 0) that hasn't been directly specified by the user if
 178          * we're in single-address mode.
 179          *
 180          * In this case, only one address can be defined, anything else will
 181          * result in a DMA address error interrupt (at least on the SH-4),
 182          * which will subsequently halt the transfer.
 183          *
 184          * Channel 2 on the Dreamcast is a special case, as this is used for
 185          * cascading to the PVR2 DMAC. In this case, we still need to write
 186          * SAR and DAR, regardless of value, in order for cascading to work.
 187          */
 188         if (chan->sar || (mach_is_dreamcast() &&
 189                           chan->chan == PVR2_CASCADE_CHAN))
 190                 ctrl_outl(chan->sar, SAR[chan->chan]);
 191         if (chan->dar || (mach_is_dreamcast() &&
 192                           chan->chan == PVR2_CASCADE_CHAN))
 193                 ctrl_outl(chan->dar, DAR[chan->chan]);
 194
 195         ctrl_outl(chan->count >> calc_xmit_shift(chan), DMATCR[chan->chan]);
 196
 197         sh_dmac_enable_dma(chan);
 198
 199         return 0;
 200 }
 201
 202 static int sh_dmac_get_dma_residue(struct dma_channel *chan)
 203 {
 204         if (!(ctrl_inl(CHCR[chan->chan]) & CHCR_DE))
 205                 return 0;
 206
 207         return ctrl_inl(DMATCR[chan->chan]) << calc_xmit_shift(chan);
 208 }
 209
 210 #if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
 211     defined(CONFIG_CPU_SUBTYPE_SH7721) || \
 212     defined(CONFIG_CPU_SUBTYPE_SH7780)
 213 #define dmaor_read_reg()        ctrl_inw(DMAOR)
 214 #define dmaor_write_reg(data)   ctrl_outw(data, DMAOR)
 215 #else
 216 #define dmaor_read_reg()        ctrl_inl(DMAOR)
 217 #define dmaor_write_reg(data)   ctrl_outl(data, DMAOR)
 218 #endif
 219
 220 static inline int dmaor_reset(void)
 221 {
 222         unsigned long dmaor = dmaor_read_reg();
 223
 224         /* Try to clear the error flags first, incase they are set */
 225         dmaor &= ~(DMAOR_NMIF | DMAOR_AE);
 226         dmaor_write_reg(dmaor);
 227
 228         dmaor |= DMAOR_INIT;
 229         dmaor_write_reg(dmaor);
 230
 231         /* See if we got an error again */
 232         if ((dmaor_read_reg() & (DMAOR_AE | DMAOR_NMIF))) {
 233                 printk(KERN_ERR "dma-sh: Can't initialize DMAOR.\n");
 234                 return -EINVAL;
 235         }
 236
 237         return 0;
 238 }
 239
 240 #if defined(CONFIG_CPU_SH4)
 241 static irqreturn_t dma_err(int irq, void *dummy)
 242 {
 243         dmaor_reset();
 244         disable_irq(irq);
 245
 246         return IRQ_HANDLED;
 247 }
 248 #endif
 249
 250 static struct dma_ops sh_dmac_ops = {
 251         .request        = sh_dmac_request_dma,
 252         .free           = sh_dmac_free_dma,
 253         .get_residue    = sh_dmac_get_dma_residue,
 254         .xfer           = sh_dmac_xfer_dma,
 255         .configure      = sh_dmac_configure_channel,
 256 };
 257
 258 static struct dma_info sh_dmac_info = {
 259         .name           = "sh_dmac",
 260         .nr_channels    = CONFIG_NR_ONCHIP_DMA_CHANNELS,
 261         .ops            = &sh_dmac_ops,
 262         .flags          = DMAC_CHANNELS_TEI_CAPABLE,
 263 };
 264
 265 static int __init sh_dmac_init(void)
 266 {
 267         struct dma_info *info = &sh_dmac_info;
 268         int i;
 269
 270 #ifdef CONFIG_CPU_SH4
 271         i = request_irq(DMAE_IRQ, dma_err, IRQF_DISABLED, "DMAC Address Error", 0);
 272         if (unlikely(i < 0))
 273                 return i;
 274 #endif
 275
 276         /*
 277          * Initialize DMAOR, and clean up any error flags that may have
 278          * been set.
 279          */
 280         i = dmaor_reset();
 281         if (unlikely(i != 0))
 282                 return i;
 283
 284         return register_dmac(info);
 285 }
 286
 287 static void __exit sh_dmac_exit(void)
 288 {
 289 #ifdef CONFIG_CPU_SH4
 290         free_irq(DMAE_IRQ, 0);
 291 #endif
 292         unregister_dmac(&sh_dmac_info);
 293 }
 294
 295 subsys_initcall(sh_dmac_init);
 296 module_exit(sh_dmac_exit);
 297
 298 MODULE_AUTHOR("Takashi YOSHII, Paul Mundt, Andriy Skulysh");
 299 MODULE_DESCRIPTION("SuperH On-Chip DMAC Support");
 300 MODULE_LICENSE("GPL");