Merge git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
[wrt350n-kernel.git] / arch / sh / drivers / pci / pci-sh7780.c
blobb2a2bfa3c1bd244397ac17b5749abe2bf25172c5
1 /*
2 * Low-Level PCI Support for the SH7780
4 * Dustin McIntire (dustin@sensoria.com)
5 * Derived from arch/i386/kernel/pci-*.c which bore the message:
6 * (c) 1999--2000 Martin Mares <mj@ucw.cz>
8 * Ported to the new API by Paul Mundt <lethal@linux-sh.org>
9 * With cleanup by Paul van Gool <pvangool@mimotech.com>
11 * May be copied or modified under the terms of the GNU General Public
12 * License. See linux/COPYING for more information.
15 #undef DEBUG
17 #include <linux/types.h>
18 #include <linux/kernel.h>
19 #include <linux/init.h>
20 #include <linux/pci.h>
21 #include <linux/errno.h>
22 #include <linux/delay.h>
23 #include "pci-sh4.h"
25 #define INTC_BASE 0xffd00000
26 #define INTC_ICR0 (INTC_BASE+0x0)
27 #define INTC_ICR1 (INTC_BASE+0x1c)
28 #define INTC_INTPRI (INTC_BASE+0x10)
29 #define INTC_INTREQ (INTC_BASE+0x24)
30 #define INTC_INTMSK0 (INTC_BASE+0x44)
31 #define INTC_INTMSK1 (INTC_BASE+0x48)
32 #define INTC_INTMSK2 (INTC_BASE+0x40080)
33 #define INTC_INTMSKCLR0 (INTC_BASE+0x64)
34 #define INTC_INTMSKCLR1 (INTC_BASE+0x68)
35 #define INTC_INTMSKCLR2 (INTC_BASE+0x40084)
36 #define INTC_INT2MSKR (INTC_BASE+0x40038)
37 #define INTC_INT2MSKCR (INTC_BASE+0x4003c)
40 * Initialization. Try all known PCI access methods. Note that we support
41 * using both PCI BIOS and direct access: in such cases, we use I/O ports
42 * to access config space.
44 * Note that the platform specific initialization (BSC registers, and memory
45 * space mapping) will be called via the platform defined function
46 * pcibios_init_platform().
48 static int __init sh7780_pci_init(void)
50 unsigned int id;
51 int ret, match = 0;
53 pr_debug("PCI: Starting intialization.\n");
55 ctrl_outl(0x00000001, SH7780_PCI_VCR2); /* Enable PCIC */
57 /* check for SH7780/SH7780R hardware */
58 id = pci_read_reg(SH7780_PCIVID);
59 if ((id & 0xffff) == SH7780_VENDOR_ID) {
60 switch ((id >> 16) & 0xffff) {
61 case SH7763_DEVICE_ID:
62 case SH7780_DEVICE_ID:
63 case SH7781_DEVICE_ID:
64 case SH7785_DEVICE_ID:
65 match = 1;
66 break;
70 if (unlikely(!match)) {
71 printk(KERN_ERR "PCI: This is not an SH7780 (%x)\n", id);
72 return -ENODEV;
75 /* Setup the INTC */
76 if (mach_is_7780se()) {
77 /* ICR0: IRL=use separately */
78 ctrl_outl(0x00C00020, INTC_ICR0);
79 /* ICR1: detect low level(for 2ndcut) */
80 ctrl_outl(0xAAAA0000, INTC_ICR1);
81 /* INTPRI: priority=3(all) */
82 ctrl_outl(0x33333333, INTC_INTPRI);
85 if ((ret = sh4_pci_check_direct()) != 0)
86 return ret;
88 return pcibios_init_platform();
90 core_initcall(sh7780_pci_init);
92 int __init sh7780_pcic_init(struct sh4_pci_address_map *map)
94 u32 word;
97 * This code is unused for some boards as it is done in the
98 * bootloader and doing it here means the MAC addresses loaded
99 * by the bootloader get lost.
101 if (!(map->flags & SH4_PCIC_NO_RESET)) {
102 /* toggle PCI reset pin */
103 word = SH4_PCICR_PREFIX | SH4_PCICR_PRST;
104 pci_write_reg(word, SH4_PCICR);
105 /* Wait for a long time... not 1 sec. but long enough */
106 mdelay(100);
107 word = SH4_PCICR_PREFIX;
108 pci_write_reg(word, SH4_PCICR);
111 /* set the command/status bits to:
112 * Wait Cycle Control + Parity Enable + Bus Master +
113 * Mem space enable
115 pci_write_reg(0x00000046, SH7780_PCICMD);
117 /* define this host as the host bridge */
118 word = PCI_BASE_CLASS_BRIDGE << 24;
119 pci_write_reg(word, SH7780_PCIRID);
121 /* Set IO and Mem windows to local address
122 * Make PCI and local address the same for easy 1 to 1 mapping
123 * Window0 = map->window0.size @ non-cached area base = SDRAM
124 * Window1 = map->window1.size @ cached area base = SDRAM
126 word = ((map->window0.size - 1) & 0x1ff00001) | 0x01;
127 pci_write_reg(0x07f00001, SH4_PCILSR0);
128 word = ((map->window1.size - 1) & 0x1ff00001) | 0x01;
129 pci_write_reg(0x00000001, SH4_PCILSR1);
130 /* Set the values on window 0 PCI config registers */
131 word = P2SEGADDR(map->window0.base);
132 pci_write_reg(0xa8000000, SH4_PCILAR0);
133 pci_write_reg(0x08000000, SH7780_PCIMBAR0);
134 /* Set the values on window 1 PCI config registers */
135 word = P2SEGADDR(map->window1.base);
136 pci_write_reg(0x00000000, SH4_PCILAR1);
137 pci_write_reg(0x00000000, SH7780_PCIMBAR1);
139 /* Map IO space into PCI IO window
140 * The IO window is 64K-PCIBIOS_MIN_IO in size
141 * IO addresses will be translated to the
142 * PCI IO window base address
144 pr_debug("PCI: Mapping IO address 0x%x - 0x%x to base 0x%x\n",
145 PCIBIOS_MIN_IO, (64 << 10),
146 SH7780_PCI_IO_BASE + PCIBIOS_MIN_IO);
148 /* NOTE: I'm ignoring the PCI error IRQs for now..
149 * TODO: add support for the internal error interrupts and
150 * DMA interrupts...
153 /* Apply any last-minute PCIC fixups */
154 pci_fixup_pcic();
156 /* SH7780 init done, set central function init complete */
157 /* use round robin mode to stop a device starving/overruning */
158 word = SH4_PCICR_PREFIX | SH4_PCICR_CFIN | SH4_PCICR_FTO;
159 pci_write_reg(word, SH4_PCICR);
161 return 1;