arch/sh/kernel/cpu/sh3/setup-sh7720.c

   1 /*
   2  * SH7720 Setup
   3  *
   4  *  Copyright (C) 2007  Markus Brunner, Mark Jonas
   5  *
   6  *  Based on arch/sh/kernel/cpu/sh4/setup-sh7750.c:
   7  *
   8  *  Copyright (C) 2006  Paul Mundt
   9  *  Copyright (C) 2006  Jamie Lenehan
  10  *
  11  * This file is subject to the terms and conditions of the GNU General Public
  12  * License.  See the file "COPYING" in the main directory of this archive
  13  * for more details.
  14  */
  15 #include <linux/platform_device.h>
  16 #include <linux/init.h>
  17 #include <linux/serial.h>
  18 #include <linux/io.h>
  19 <<<<<<< HEAD:arch/sh/kernel/cpu/sh3/setup-sh7720.c
  20 #include <asm/sci.h>
  21 =======
  22 #include <linux/serial_sci.h>
  23 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/sh/kernel/cpu/sh3/setup-sh7720.c
  24 #include <asm/rtc.h>
  25
  26 #define INTC_ICR1       0xA4140010UL
  27 #define INTC_ICR_IRLM   0x4000
  28 #define INTC_ICR_IRQ    (~INTC_ICR_IRLM)
  29
  30 static struct resource rtc_resources[] = {
  31         [0] = {
  32                 .start  = 0xa413fec0,
  33                 .end    = 0xa413fec0 + 0x28 - 1,
  34                 .flags  = IORESOURCE_IO,
  35         },
  36         [1] = {
  37                 /* Period IRQ */
  38                 .start  = 21,
  39                 .flags  = IORESOURCE_IRQ,
  40         },
  41         [2] = {
  42                 /* Carry IRQ */
  43                 .start  = 22,
  44                 .flags  = IORESOURCE_IRQ,
  45         },
  46         [3] = {
  47                 /* Alarm IRQ */
  48                 .start  = 20,
  49                 .flags  = IORESOURCE_IRQ,
  50         },
  51 };
  52
  53 static struct sh_rtc_platform_info rtc_info = {
  54         .capabilities   = RTC_CAP_4_DIGIT_YEAR,
  55 };
  56
  57 static struct platform_device rtc_device = {
  58         .name           = "sh-rtc",
  59         .id             = -1,
  60         .num_resources  = ARRAY_SIZE(rtc_resources),
  61         .resource       = rtc_resources,
  62         .dev            = {
  63                 .platform_data = &rtc_info,
  64         },
  65 };
  66
  67 static struct plat_sci_port sci_platform_data[] = {
  68         {
  69                 .mapbase        = 0xa4430000,
  70                 .flags          = UPF_BOOT_AUTOCONF,
  71                 .type           = PORT_SCIF,
  72                 .irqs           = { 80, 80, 80, 80 },
  73         }, {
  74                 .mapbase        = 0xa4438000,
  75                 .flags          = UPF_BOOT_AUTOCONF,
  76                 .type           = PORT_SCIF,
  77                 .irqs           = { 81, 81, 81, 81 },
  78         }, {
  79
  80                 .flags = 0,
  81         }
  82 };
  83
  84 static struct platform_device sci_device = {
  85         .name           = "sh-sci",
  86         .id             = -1,
  87         .dev            = {
  88                 .platform_data  = sci_platform_data,
  89         },
  90 };
  91
  92 static struct resource usb_ohci_resources[] = {
  93         [0] = {
  94                 .start  = 0xA4428000,
  95                 .end    = 0xA44280FF,
  96                 .flags  = IORESOURCE_MEM,
  97         },
  98         [1] = {
  99                 .start  = 67,
 100                 .end    = 67,
 101                 .flags  = IORESOURCE_IRQ,
 102         },
 103 };
 104
 105 static u64 usb_ohci_dma_mask = 0xffffffffUL;
 106 static struct platform_device usb_ohci_device = {
 107         .name           = "sh_ohci",
 108         .id             = -1,
 109         .dev = {
 110                 .dma_mask               = &usb_ohci_dma_mask,
 111                 .coherent_dma_mask      = 0xffffffff,
 112         },
 113         .num_resources  = ARRAY_SIZE(usb_ohci_resources),
 114         .resource       = usb_ohci_resources,
 115 };
 116
 117 static struct resource usbf_resources[] = {
 118         [0] = {
 119                 .name   = "sh_udc",
 120                 .start  = 0xA4420000,
 121                 .end    = 0xA44200FF,
 122                 .flags  = IORESOURCE_MEM,
 123         },
 124         [1] = {
 125                 .name   = "sh_udc",
 126                 .start  = 65,
 127                 .end    = 65,
 128                 .flags  = IORESOURCE_IRQ,
 129         },
 130 };
 131
 132 static struct platform_device usbf_device = {
 133         .name           = "sh_udc",
 134         .id             = -1,
 135         .dev = {
 136                 .dma_mask               = NULL,
 137                 .coherent_dma_mask      = 0xffffffff,
 138         },
 139         .num_resources  = ARRAY_SIZE(usbf_resources),
 140         .resource       = usbf_resources,
 141 };
 142
 143 static struct platform_device *sh7720_devices[] __initdata = {
 144         &rtc_device,
 145         &sci_device,
 146         &usb_ohci_device,
 147         &usbf_device,
 148 };
 149
 150 static int __init sh7720_devices_setup(void)
 151 {
 152         return platform_add_devices(sh7720_devices,
 153                                     ARRAY_SIZE(sh7720_devices));
 154 }
 155 __initcall(sh7720_devices_setup);
 156
 157 enum {
 158         UNUSED = 0,
 159
 160         /* interrupt sources */
 161         TMU0, TMU1, TMU2, RTC_ATI, RTC_PRI, RTC_CUI,
 162         WDT, REF_RCMI, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEND,
 163         IRQ0, IRQ1, IRQ2, IRQ3,
 164         USBF_SPD, TMU_SUNI, IRQ5, IRQ4,
 165         DMAC1_DEI0, DMAC1_DEI1, DMAC1_DEI2, DMAC1_DEI3, LCDC, SSL,
 166         ADC, DMAC2_DEI4, DMAC2_DEI5, USBFI0, USBFI1, CMT,
 167         SCIF0, SCIF1,
 168         PINT07, PINT815, TPU0, TPU1, TPU2, TPU3, IIC,
 169         SIOF0, SIOF1, MMCI0, MMCI1, MMCI2, MMCI3, PCC,
 170         USBHI, AFEIF,
 171         H_UDI,
 172         /* interrupt groups */
 173         TMU, RTC, SIM, DMAC1, USBFI, DMAC2, USB, TPU, MMC,
 174 };
 175
 176 static struct intc_vect vectors[] __initdata = {
 177         INTC_VECT(TMU0, 0x400),       INTC_VECT(TMU1, 0x420),
 178         INTC_VECT(TMU2, 0x440),       INTC_VECT(RTC_ATI, 0x480),
 179         INTC_VECT(RTC_PRI, 0x4a0),    INTC_VECT(RTC_CUI, 0x4c0),
 180         INTC_VECT(SIM_ERI, 0x4e0),    INTC_VECT(SIM_RXI, 0x500),
 181         INTC_VECT(SIM_TXI, 0x520),    INTC_VECT(SIM_TEND, 0x540),
 182         INTC_VECT(WDT, 0x560),        INTC_VECT(REF_RCMI, 0x580),
 183         /* H_UDI cannot be masked */  INTC_VECT(TMU_SUNI, 0x6c0),
 184         INTC_VECT(USBF_SPD, 0x6e0),   INTC_VECT(DMAC1_DEI0, 0x800),
 185         INTC_VECT(DMAC1_DEI1, 0x820), INTC_VECT(DMAC1_DEI2, 0x840),
 186         INTC_VECT(DMAC1_DEI3, 0x860), INTC_VECT(LCDC, 0x900),
 187 #if defined(CONFIG_CPU_SUBTYPE_SH7720)
 188         INTC_VECT(SSL, 0x980),
 189 #endif
 190         INTC_VECT(USBFI0, 0xa20),     INTC_VECT(USBFI1, 0xa40),
 191         INTC_VECT(USBHI, 0xa60),
 192         INTC_VECT(DMAC2_DEI4, 0xb80), INTC_VECT(DMAC2_DEI5, 0xba0),
 193         INTC_VECT(ADC, 0xbe0),        INTC_VECT(SCIF0, 0xc00),
 194         INTC_VECT(SCIF1, 0xc20),      INTC_VECT(PINT07, 0xc80),
 195         INTC_VECT(PINT815, 0xca0),    INTC_VECT(SIOF0, 0xd00),
 196         INTC_VECT(SIOF1, 0xd20),      INTC_VECT(TPU0, 0xd80),
 197         INTC_VECT(TPU1, 0xda0),       INTC_VECT(TPU2, 0xdc0),
 198         INTC_VECT(TPU3, 0xde0),       INTC_VECT(IIC, 0xe00),
 199         INTC_VECT(MMCI0, 0xe80),      INTC_VECT(MMCI1, 0xea0),
 200         INTC_VECT(MMCI2, 0xec0),      INTC_VECT(MMCI3, 0xee0),
 201         INTC_VECT(CMT, 0xf00),        INTC_VECT(PCC, 0xf60),
 202         INTC_VECT(AFEIF, 0xfe0),
 203 };
 204
 205 static struct intc_group groups[] __initdata = {
 206         INTC_GROUP(TMU, TMU0, TMU1, TMU2),
 207         INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
 208         INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEND),
 209         INTC_GROUP(DMAC1, DMAC1_DEI0, DMAC1_DEI1, DMAC1_DEI2, DMAC1_DEI3),
 210         INTC_GROUP(USBFI, USBFI0, USBFI1),
 211         INTC_GROUP(DMAC2, DMAC2_DEI4, DMAC2_DEI5),
 212         INTC_GROUP(TPU, TPU0, TPU1, TPU2, TPU3),
 213         INTC_GROUP(MMC, MMCI0, MMCI1, MMCI2, MMCI3),
 214 };
 215
 216 static struct intc_prio_reg prio_registers[] __initdata = {
 217         { 0xA414FEE2UL, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
 218         { 0xA414FEE4UL, 0, 16, 4, /* IPRB */ { WDT, REF_RCMI, SIM, 0 } },
 219         { 0xA4140016UL, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } },
 220         { 0xA4140018UL, 0, 16, 4, /* IPRD */ { USBF_SPD, TMU_SUNI, IRQ5, IRQ4 } },
 221 #if defined(CONFIG_CPU_SUBTYPE_SH7720)
 222         { 0xA414001AUL, 0, 16, 4, /* IPRE */ { DMAC1, 0, LCDC, SSL } },
 223 #else
 224         { 0xA414001AUL, 0, 16, 4, /* IPRE */ { DMAC1, 0, LCDC, 0 } },
 225 #endif
 226         { 0xA4080000UL, 0, 16, 4, /* IPRF */ { ADC, DMAC2, USBFI, CMT } },
 227         { 0xA4080002UL, 0, 16, 4, /* IPRG */ { SCIF0, SCIF1, 0, 0 } },
 228         { 0xA4080004UL, 0, 16, 4, /* IPRH */ { PINT07, PINT815, TPU, IIC } },
 229         { 0xA4080006UL, 0, 16, 4, /* IPRI */ { SIOF0, SIOF1, MMC, PCC } },
 230         { 0xA4080008UL, 0, 16, 4, /* IPRJ */ { 0, USBHI, 0, AFEIF } },
 231 };
 232
 233 static DECLARE_INTC_DESC(intc_desc, "sh7720", vectors, groups,
 234                 NULL, prio_registers, NULL);
 235
 236 static struct intc_sense_reg sense_registers[] __initdata = {
 237         { INTC_ICR1, 16, 2, { 0, 0, IRQ5, IRQ4, IRQ3, IRQ2, IRQ1, IRQ0 } },
 238 };
 239
 240 static struct intc_vect vectors_irq[] __initdata = {
 241         INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
 242         INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
 243         INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
 244 };
 245
 246 static DECLARE_INTC_DESC(intc_irq_desc, "sh7720-irq", vectors_irq,
 247                 NULL, NULL, prio_registers, sense_registers);
 248
 249 void __init plat_irq_setup_pins(int mode)
 250 {
 251         switch (mode) {
 252         case IRQ_MODE_IRQ:
 253                 ctrl_outw(ctrl_inw(INTC_ICR1) & INTC_ICR_IRQ, INTC_ICR1);
 254                 register_intc_controller(&intc_irq_desc);
 255                 break;
 256         default:
 257                 BUG();
 258         }
 259 }
 260
 261 void __init plat_irq_setup(void)
 262 {
 263         register_intc_controller(&intc_desc);
 264 }