arch/sh/kernel/cpu/sh4/setup-sh7750.c

   1 /*
   2  * SH7750/SH7751 Setup
   3  *
   4  *  Copyright (C) 2006  Paul Mundt
   5  *  Copyright (C) 2006  Jamie Lenehan
   6  *
   7  * This file is subject to the terms and conditions of the GNU General Public
   8  * License.  See the file "COPYING" in the main directory of this archive
   9  * for more details.
  10  */
  11 #include <linux/platform_device.h>
  12 #include <linux/init.h>
  13 #include <linux/serial.h>
  14 #include <linux/io.h>
  15 <<<<<<< HEAD:arch/sh/kernel/cpu/sh4/setup-sh7750.c
  16 #include <asm/sci.h>
  17 =======
  18 #include <linux/serial_sci.h>
  19 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/sh/kernel/cpu/sh4/setup-sh7750.c
  20
  21 static struct resource rtc_resources[] = {
  22         [0] = {
  23                 .start  = 0xffc80000,
  24                 .end    = 0xffc80000 + 0x58 - 1,
  25                 .flags  = IORESOURCE_IO,
  26         },
  27         [1] = {
  28                 /* Period IRQ */
  29                 .start  = 21,
  30                 .flags  = IORESOURCE_IRQ,
  31         },
  32         [2] = {
  33                 /* Carry IRQ */
  34                 .start  = 22,
  35                 .flags  = IORESOURCE_IRQ,
  36         },
  37         [3] = {
  38                 /* Alarm IRQ */
  39                 .start  = 20,
  40                 .flags  = IORESOURCE_IRQ,
  41         },
  42 };
  43
  44 static struct platform_device rtc_device = {
  45         .name           = "sh-rtc",
  46         .id             = -1,
  47         .num_resources  = ARRAY_SIZE(rtc_resources),
  48         .resource       = rtc_resources,
  49 };
  50
  51 static struct plat_sci_port sci_platform_data[] = {
  52         {
  53 #ifndef CONFIG_SH_RTS7751R2D
  54                 .mapbase        = 0xffe00000,
  55                 .flags          = UPF_BOOT_AUTOCONF,
  56                 .type           = PORT_SCI,
  57                 .irqs           = { 23, 24, 25, 0 },
  58         }, {
  59 #endif
  60                 .mapbase        = 0xffe80000,
  61                 .flags          = UPF_BOOT_AUTOCONF,
  62                 .type           = PORT_SCIF,
  63                 .irqs           = { 40, 41, 43, 42 },
  64         }, {
  65                 .flags = 0,
  66         }
  67 };
  68
  69 static struct platform_device sci_device = {
  70         .name           = "sh-sci",
  71         .id             = -1,
  72         .dev            = {
  73                 .platform_data  = sci_platform_data,
  74         },
  75 };
  76
  77 static struct platform_device *sh7750_devices[] __initdata = {
  78         &rtc_device,
  79         &sci_device,
  80 };
  81
  82 static int __init sh7750_devices_setup(void)
  83 {
  84         return platform_add_devices(sh7750_devices,
  85                                     ARRAY_SIZE(sh7750_devices));
  86 }
  87 __initcall(sh7750_devices_setup);
  88
  89 enum {
  90         UNUSED = 0,
  91
  92         /* interrupt sources */
  93         IRL0, IRL1, IRL2, IRL3, /* only IRLM mode supported */
  94         HUDI, GPIOI,
  95         DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, DMAC_DMTE3,
  96         DMAC_DMTE4, DMAC_DMTE5, DMAC_DMTE6, DMAC_DMTE7,
  97         DMAC_DMAE,
  98         PCIC0_PCISERR, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
  99         PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3,
 100         TMU3, TMU4, TMU0, TMU1, TMU2_TUNI, TMU2_TICPI,
 101         RTC_ATI, RTC_PRI, RTC_CUI,
 102         SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI,
 103         SCIF_ERI, SCIF_RXI, SCIF_BRI, SCIF_TXI,
 104         WDT,
 105         REF_RCMI, REF_ROVI,
 106
 107         /* interrupt groups */
 108         DMAC, PCIC1, TMU2, RTC, SCI1, SCIF, REF,
 109 };
 110
 111 static struct intc_vect vectors[] __initdata = {
 112         INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620),
 113         INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
 114         INTC_VECT(TMU2_TUNI, 0x440), INTC_VECT(TMU2_TICPI, 0x460),
 115         INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0),
 116         INTC_VECT(RTC_CUI, 0x4c0),
 117         INTC_VECT(SCI1_ERI, 0x4e0), INTC_VECT(SCI1_RXI, 0x500),
 118         INTC_VECT(SCI1_TXI, 0x520), INTC_VECT(SCI1_TEI, 0x540),
 119         INTC_VECT(SCIF_ERI, 0x700), INTC_VECT(SCIF_RXI, 0x720),
 120         INTC_VECT(SCIF_BRI, 0x740), INTC_VECT(SCIF_TXI, 0x760),
 121         INTC_VECT(WDT, 0x560),
 122         INTC_VECT(REF_RCMI, 0x580), INTC_VECT(REF_ROVI, 0x5a0),
 123 };
 124
 125 static struct intc_group groups[] __initdata = {
 126         INTC_GROUP(TMU2, TMU2_TUNI, TMU2_TICPI),
 127         INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
 128         INTC_GROUP(SCI1, SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI),
 129         INTC_GROUP(SCIF, SCIF_ERI, SCIF_RXI, SCIF_BRI, SCIF_TXI),
 130         INTC_GROUP(REF, REF_RCMI, REF_ROVI),
 131 };
 132
 133 static struct intc_prio_reg prio_registers[] __initdata = {
 134         { 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
 135         { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, SCI1, 0 } },
 136         { 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, SCIF, HUDI } },
 137         { 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } },
 138         { 0xfe080000, 0, 32, 4, /* INTPRI00 */ { 0, 0, 0, 0,
 139                                                  TMU4, TMU3,
 140                                                  PCIC1, PCIC0_PCISERR } },
 141 };
 142
 143 static DECLARE_INTC_DESC(intc_desc, "sh7750", vectors, groups,
 144                          NULL, prio_registers, NULL);
 145
 146 /* SH7750, SH7750S, SH7751 and SH7091 all have 4-channel DMA controllers */
 147 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || \
 148         defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
 149         defined(CONFIG_CPU_SUBTYPE_SH7751) || \
 150         defined(CONFIG_CPU_SUBTYPE_SH7091)
 151 static struct intc_vect vectors_dma4[] __initdata = {
 152         INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660),
 153         INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0),
 154         INTC_VECT(DMAC_DMAE, 0x6c0),
 155 };
 156
 157 static struct intc_group groups_dma4[] __initdata = {
 158         INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2,
 159                    DMAC_DMTE3, DMAC_DMAE),
 160 };
 161
 162 static DECLARE_INTC_DESC(intc_desc_dma4, "sh7750_dma4",
 163                          vectors_dma4, groups_dma4,
 164                          NULL, prio_registers, NULL);
 165 #endif
 166
 167 /* SH7750R and SH7751R both have 8-channel DMA controllers */
 168 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || defined(CONFIG_CPU_SUBTYPE_SH7751R)
 169 static struct intc_vect vectors_dma8[] __initdata = {
 170         INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660),
 171         INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0),
 172         INTC_VECT(DMAC_DMTE4, 0x780), INTC_VECT(DMAC_DMTE5, 0x7a0),
 173         INTC_VECT(DMAC_DMTE6, 0x7c0), INTC_VECT(DMAC_DMTE7, 0x7e0),
 174         INTC_VECT(DMAC_DMAE, 0x6c0),
 175 };
 176
 177 static struct intc_group groups_dma8[] __initdata = {
 178         INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2,
 179                    DMAC_DMTE3, DMAC_DMTE4, DMAC_DMTE5,
 180                    DMAC_DMTE6, DMAC_DMTE7, DMAC_DMAE),
 181 };
 182
 183 static DECLARE_INTC_DESC(intc_desc_dma8, "sh7750_dma8",
 184                          vectors_dma8, groups_dma8,
 185                          NULL, prio_registers, NULL);
 186 #endif
 187
 188 /* SH7750R, SH7751 and SH7751R all have two extra timer channels */
 189 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
 190         defined(CONFIG_CPU_SUBTYPE_SH7751) || \
 191         defined(CONFIG_CPU_SUBTYPE_SH7751R)
 192 static struct intc_vect vectors_tmu34[] __initdata = {
 193         INTC_VECT(TMU3, 0xb00), INTC_VECT(TMU4, 0xb80),
 194 };
 195
 196 static struct intc_mask_reg mask_registers[] __initdata = {
 197         { 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */
 198           { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 199             0, 0, 0, 0, 0, 0, TMU4, TMU3,
 200             PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
 201             PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2,
 202             PCIC1_PCIDMA3, PCIC0_PCISERR } },
 203 };
 204
 205 static DECLARE_INTC_DESC(intc_desc_tmu34, "sh7750_tmu34",
 206                          vectors_tmu34, NULL,
 207                          mask_registers, prio_registers, NULL);
 208 #endif
 209
 210 /* SH7750S, SH7750R, SH7751 and SH7751R all have IRLM priority registers */
 211 static struct intc_vect vectors_irlm[] __initdata = {
 212         INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0),
 213         INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360),
 214 };
 215
 216 static DECLARE_INTC_DESC(intc_desc_irlm, "sh7750_irlm", vectors_irlm, NULL,
 217                          NULL, prio_registers, NULL);
 218
 219 /* SH7751 and SH7751R both have PCI */
 220 #if defined(CONFIG_CPU_SUBTYPE_SH7751) || defined(CONFIG_CPU_SUBTYPE_SH7751R)
 221 static struct intc_vect vectors_pci[] __initdata = {
 222         INTC_VECT(PCIC0_PCISERR, 0xa00), INTC_VECT(PCIC1_PCIERR, 0xae0),
 223         INTC_VECT(PCIC1_PCIPWDWN, 0xac0), INTC_VECT(PCIC1_PCIPWON, 0xaa0),
 224         INTC_VECT(PCIC1_PCIDMA0, 0xa80), INTC_VECT(PCIC1_PCIDMA1, 0xa60),
 225         INTC_VECT(PCIC1_PCIDMA2, 0xa40), INTC_VECT(PCIC1_PCIDMA3, 0xa20),
 226 };
 227
 228 static struct intc_group groups_pci[] __initdata = {
 229         INTC_GROUP(PCIC1, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
 230                    PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3),
 231 };
 232
 233 static DECLARE_INTC_DESC(intc_desc_pci, "sh7750_pci", vectors_pci, groups_pci,
 234                          mask_registers, prio_registers, NULL);
 235 #endif
 236
 237 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || \
 238         defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
 239         defined(CONFIG_CPU_SUBTYPE_SH7091)
 240 void __init plat_irq_setup(void)
 241 {
 242         /*
 243          * same vectors for SH7750, SH7750S and SH7091 except for IRLM,
 244          * see below..
 245          */
 246         register_intc_controller(&intc_desc);
 247         register_intc_controller(&intc_desc_dma4);
 248 }
 249 #endif
 250
 251 #if defined(CONFIG_CPU_SUBTYPE_SH7750R)
 252 void __init plat_irq_setup(void)
 253 {
 254         register_intc_controller(&intc_desc);
 255         register_intc_controller(&intc_desc_dma8);
 256         register_intc_controller(&intc_desc_tmu34);
 257 }
 258 #endif
 259
 260 #if defined(CONFIG_CPU_SUBTYPE_SH7751)
 261 void __init plat_irq_setup(void)
 262 {
 263         register_intc_controller(&intc_desc);
 264         register_intc_controller(&intc_desc_dma4);
 265         register_intc_controller(&intc_desc_tmu34);
 266         register_intc_controller(&intc_desc_pci);
 267 }
 268 #endif
 269
 270 #if defined(CONFIG_CPU_SUBTYPE_SH7751R)
 271 void __init plat_irq_setup(void)
 272 {
 273         register_intc_controller(&intc_desc);
 274         register_intc_controller(&intc_desc_dma8);
 275         register_intc_controller(&intc_desc_tmu34);
 276         register_intc_controller(&intc_desc_pci);
 277 }
 278 #endif
 279
 280 #define INTC_ICR        0xffd00000UL
 281 #define INTC_ICR_IRLM   (1<<7)
 282
 283 void __init plat_irq_setup_pins(int mode)
 284 {
 285 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7091)
 286         BUG(); /* impossible to mask interrupts on SH7750 and SH7091 */
 287         return;
 288 #endif
 289
 290         switch (mode) {
 291         case IRQ_MODE_IRQ: /* individual interrupt mode for IRL3-0 */
 292                 ctrl_outw(ctrl_inw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
 293                 register_intc_controller(&intc_desc_irlm);
 294                 break;
 295         default:
 296                 BUG();
 297         }
 298 }