arch/sh/kernel/cpu/sh4/setup-sh7760.c

   1 /*
   2  * SH7760 Setup
   3  *
   4  *  Copyright (C) 2006  Paul Mundt
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License.  See the file "COPYING" in the main directory of this archive
   8  * for more details.
   9  */
  10 #include <linux/platform_device.h>
  11 #include <linux/init.h>
  12 #include <linux/serial.h>
  13 <<<<<<< HEAD:arch/sh/kernel/cpu/sh4/setup-sh7760.c
  14 #include <asm/sci.h>
  15 =======
  16 #include <linux/serial_sci.h>
  17 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/sh/kernel/cpu/sh4/setup-sh7760.c
  18
  19 enum {
  20         UNUSED = 0,
  21
  22         /* interrupt sources */
  23         IRL0, IRL1, IRL2, IRL3,
  24         HUDI, GPIOI,
  25         DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, DMAC_DMTE3,
  26         DMAC_DMTE4, DMAC_DMTE5, DMAC_DMTE6, DMAC_DMTE7,
  27         DMAC_DMAE,
  28         IRQ4, IRQ5, IRQ6, IRQ7,
  29         HCAN20, HCAN21,
  30         SSI0, SSI1,
  31         HAC0, HAC1,
  32         I2C0, I2C1,
  33         USB, LCDC,
  34         DMABRG0, DMABRG1, DMABRG2,
  35         SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
  36         SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI,
  37         SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI,
  38         SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
  39         HSPI,
  40         MMCIF0, MMCIF1, MMCIF2, MMCIF3,
  41         MFI, ADC, CMT,
  42         TMU0, TMU1, TMU2_TUNI, TMU2_TICPI,
  43         WDT,
  44         REF_RCMI, REF_ROVI,
  45
  46         /* interrupt groups */
  47         DMAC, DMABRG, SCIF0, SCIF1, SCIF2, SIM, MMCIF, TMU2, REF,
  48 };
  49
  50 static struct intc_vect vectors[] __initdata = {
  51         INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620),
  52         INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660),
  53         INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0),
  54         INTC_VECT(DMAC_DMTE4, 0x780), INTC_VECT(DMAC_DMTE5, 0x7a0),
  55         INTC_VECT(DMAC_DMTE6, 0x7c0), INTC_VECT(DMAC_DMTE7, 0x7e0),
  56         INTC_VECT(DMAC_DMAE, 0x6c0),
  57         INTC_VECT(IRQ4, 0x800), INTC_VECT(IRQ5, 0x820),
  58         INTC_VECT(IRQ6, 0x840), INTC_VECT(IRQ6, 0x860),
  59         INTC_VECT(HCAN20, 0x900), INTC_VECT(HCAN21, 0x920),
  60         INTC_VECT(SSI0, 0x940), INTC_VECT(SSI1, 0x960),
  61         INTC_VECT(HAC0, 0x980), INTC_VECT(HAC1, 0x9a0),
  62         INTC_VECT(I2C0, 0x9c0), INTC_VECT(I2C1, 0x9e0),
  63         INTC_VECT(USB, 0xa00), INTC_VECT(LCDC, 0xa20),
  64         INTC_VECT(DMABRG0, 0xa80), INTC_VECT(DMABRG1, 0xaa0),
  65         INTC_VECT(DMABRG2, 0xac0),
  66         INTC_VECT(SCIF0_ERI, 0x880), INTC_VECT(SCIF0_RXI, 0x8a0),
  67         INTC_VECT(SCIF0_BRI, 0x8c0), INTC_VECT(SCIF0_TXI, 0x8e0),
  68         INTC_VECT(SCIF1_ERI, 0xb00), INTC_VECT(SCIF1_RXI, 0xb20),
  69         INTC_VECT(SCIF1_BRI, 0xb40), INTC_VECT(SCIF1_TXI, 0xb60),
  70         INTC_VECT(SCIF2_ERI, 0xb80), INTC_VECT(SCIF2_RXI, 0xba0),
  71         INTC_VECT(SCIF2_BRI, 0xbc0), INTC_VECT(SCIF2_TXI, 0xbe0),
  72         INTC_VECT(SIM_ERI, 0xc00), INTC_VECT(SIM_RXI, 0xc20),
  73         INTC_VECT(SIM_TXI, 0xc40), INTC_VECT(SIM_TEI, 0xc60),
  74         INTC_VECT(HSPI, 0xc80),
  75         INTC_VECT(MMCIF0, 0xd00), INTC_VECT(MMCIF1, 0xd20),
  76         INTC_VECT(MMCIF2, 0xd40), INTC_VECT(MMCIF3, 0xd60),
  77         INTC_VECT(MFI, 0xe80), /* 0xf80 according to data sheet */
  78         INTC_VECT(ADC, 0xf80), INTC_VECT(CMT, 0xfa0),
  79         INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
  80         INTC_VECT(TMU2_TUNI, 0x440), INTC_VECT(TMU2_TICPI, 0x460),
  81         INTC_VECT(WDT, 0x560),
  82         INTC_VECT(REF_RCMI, 0x580), INTC_VECT(REF_ROVI, 0x5a0),
  83 };
  84
  85 static struct intc_group groups[] __initdata = {
  86         INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2,
  87                    DMAC_DMTE3, DMAC_DMTE4, DMAC_DMTE5,
  88                    DMAC_DMTE6, DMAC_DMTE7, DMAC_DMAE),
  89         INTC_GROUP(DMABRG, DMABRG0, DMABRG1, DMABRG2),
  90         INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
  91         INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI),
  92         INTC_GROUP(SCIF2, SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI),
  93         INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI),
  94         INTC_GROUP(MMCIF, MMCIF0, MMCIF1, MMCIF2, MMCIF3),
  95         INTC_GROUP(TMU2, TMU2_TUNI, TMU2_TICPI),
  96         INTC_GROUP(REF, REF_RCMI, REF_ROVI),
  97 };
  98
  99 static struct intc_mask_reg mask_registers[] __initdata = {
 100         { 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */
 101           { IRQ4, IRQ5, IRQ6, IRQ7, 0, 0, HCAN20, HCAN21,
 102             SSI0, SSI1, HAC0, HAC1, I2C0, I2C1, USB, LCDC,
 103             0, DMABRG0, DMABRG1, DMABRG2,
 104             SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
 105             SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI,
 106             SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI, } },
 107         { 0xfe080044, 0xfe080064, 32, /* INTMSK04 / INTMSKCLR04 */
 108           { 0, 0, 0, 0, 0, 0, 0, 0,
 109             SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
 110             HSPI, MMCIF0, MMCIF1, MMCIF2,
 111             MMCIF3, 0, 0, 0, 0, 0, 0, 0,
 112             0, MFI, 0, 0, 0, 0, ADC, CMT, } },
 113 };
 114
 115 static struct intc_prio_reg prio_registers[] __initdata = {
 116         { 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2 } },
 117         { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, 0, 0 } },
 118         { 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, 0, HUDI } },
 119         { 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } },
 120         { 0xfe080000, 0, 32, 4, /* INTPRI00 */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
 121         { 0xfe080004, 0, 32, 4, /* INTPRI04 */ { HCAN20, HCAN21, SSI0, SSI1,
 122                                                  HAC0, HAC1, I2C0, I2C1 } },
 123         { 0xfe080008, 0, 32, 4, /* INTPRI08 */ { USB, LCDC, DMABRG, SCIF0,
 124                                                  SCIF1, SCIF2, SIM, HSPI } },
 125         { 0xfe08000c, 0, 32, 4, /* INTPRI0C */ { 0, 0, MMCIF, 0,
 126                                                  MFI, 0, ADC, CMT } },
 127 };
 128
 129 static DECLARE_INTC_DESC(intc_desc, "sh7760", vectors, groups,
 130                          mask_registers, prio_registers, NULL);
 131
 132 static struct intc_vect vectors_irq[] __initdata = {
 133         INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0),
 134         INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360),
 135 };
 136
 137 static DECLARE_INTC_DESC(intc_desc_irq, "sh7760-irq", vectors_irq, groups,
 138                          mask_registers, prio_registers, NULL);
 139
 140 static struct plat_sci_port sci_platform_data[] = {
 141         {
 142                 .mapbase        = 0xfe600000,
 143                 .flags          = UPF_BOOT_AUTOCONF,
 144                 .type           = PORT_SCIF,
 145                 .irqs           = { 52, 53, 55, 54 },
 146         }, {
 147                 .mapbase        = 0xfe610000,
 148                 .flags          = UPF_BOOT_AUTOCONF,
 149                 .type           = PORT_SCIF,
 150                 .irqs           = { 72, 73, 75, 74 },
 151         }, {
 152                 .mapbase        = 0xfe620000,
 153                 .flags          = UPF_BOOT_AUTOCONF,
 154                 .type           = PORT_SCIF,
 155                 .irqs           = { 76, 77, 79, 78 },
 156         }, {
 157                 .mapbase        = 0xfe480000,
 158                 .flags          = UPF_BOOT_AUTOCONF,
 159                 .type           = PORT_SCI,
 160                 .irqs           = { 80, 81, 82, 0 },
 161         }, {
 162                 .flags = 0,
 163         }
 164 };
 165
 166 static struct platform_device sci_device = {
 167         .name           = "sh-sci",
 168         .id             = -1,
 169         .dev            = {
 170                 .platform_data  = sci_platform_data,
 171         },
 172 };
 173
 174 static struct platform_device *sh7760_devices[] __initdata = {
 175         &sci_device,
 176 };
 177
 178 static int __init sh7760_devices_setup(void)
 179 {
 180         return platform_add_devices(sh7760_devices,
 181                                     ARRAY_SIZE(sh7760_devices));
 182 }
 183 __initcall(sh7760_devices_setup);
 184
 185 void __init plat_irq_setup_pins(int mode)
 186 {
 187         switch (mode) {
 188         case IRQ_MODE_IRQ:
 189                 register_intc_controller(&intc_desc_irq);
 190                 break;
 191         default:
 192                 BUG();
 193         }
 194 }
 195
 196 void __init plat_irq_setup(void)
 197 {
 198         register_intc_controller(&intc_desc);
 199 }