arch/sh/kernel/cpu/sh4a/setup-sh7785.c

   1 /*
   2  * SH7785 Setup
   3  *
   4  *  Copyright (C) 2007  Paul Mundt
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License.  See the file "COPYING" in the main directory of this archive
   8  * for more details.
   9  */
  10 #include <linux/platform_device.h>
  11 #include <linux/init.h>
  12 #include <linux/serial.h>
  13 <<<<<<< HEAD:arch/sh/kernel/cpu/sh4a/setup-sh7785.c
  14 =======
  15 #include <linux/serial_sci.h>
  16 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/sh/kernel/cpu/sh4a/setup-sh7785.c
  17 #include <linux/io.h>
  18 #include <linux/mm.h>
  19 #include <asm/mmzone.h>
  20 <<<<<<< HEAD:arch/sh/kernel/cpu/sh4a/setup-sh7785.c
  21 #include <asm/sci.h>
  22 =======
  23 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/sh/kernel/cpu/sh4a/setup-sh7785.c
  24
  25 static struct plat_sci_port sci_platform_data[] = {
  26         {
  27                 .mapbase        = 0xffea0000,
  28                 .flags          = UPF_BOOT_AUTOCONF,
  29                 .type           = PORT_SCIF,
  30                 .irqs           = { 40, 41, 43, 42 },
  31         }, {
  32                 .mapbase        = 0xffeb0000,
  33                 .flags          = UPF_BOOT_AUTOCONF,
  34                 .type           = PORT_SCIF,
  35                 .irqs           = { 44, 45, 47, 46 },
  36         },
  37
  38         /*
  39          * The rest of these all have multiplexed IRQs
  40          */
  41         {
  42                 .mapbase        = 0xffec0000,
  43                 .flags          = UPF_BOOT_AUTOCONF,
  44                 .type           = PORT_SCIF,
  45                 .irqs           = { 60, 60, 60, 60 },
  46         }, {
  47                 .mapbase        = 0xffed0000,
  48                 .flags          = UPF_BOOT_AUTOCONF,
  49                 .type           = PORT_SCIF,
  50                 .irqs           = { 61, 61, 61, 61 },
  51         }, {
  52                 .mapbase        = 0xffee0000,
  53                 .flags          = UPF_BOOT_AUTOCONF,
  54                 .type           = PORT_SCIF,
  55                 .irqs           = { 62, 62, 62, 62 },
  56         }, {
  57                 .mapbase        = 0xffef0000,
  58                 .flags          = UPF_BOOT_AUTOCONF,
  59                 .type           = PORT_SCIF,
  60                 .irqs           = { 63, 63, 63, 63 },
  61         }, {
  62                 .flags = 0,
  63         }
  64 };
  65
  66 static struct platform_device sci_device = {
  67         .name           = "sh-sci",
  68         .id             = -1,
  69         .dev            = {
  70                 .platform_data  = sci_platform_data,
  71         },
  72 };
  73
  74 static struct platform_device *sh7785_devices[] __initdata = {
  75         &sci_device,
  76 };
  77
  78 static int __init sh7785_devices_setup(void)
  79 {
  80         return platform_add_devices(sh7785_devices,
  81                                     ARRAY_SIZE(sh7785_devices));
  82 }
  83 __initcall(sh7785_devices_setup);
  84
  85 enum {
  86         UNUSED = 0,
  87
  88         /* interrupt sources */
  89
  90         IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
  91         IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
  92         IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
  93         IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
  94
  95         IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
  96         IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
  97         IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
  98         IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
  99
 100         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
 101         WDT,
 102         TMU0, TMU1, TMU2, TMU2_TICPI,
 103         HUDI,
 104         DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2, DMAC0_DMINT3,
 105         DMAC0_DMINT4, DMAC0_DMINT5, DMAC0_DMAE,
 106         SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
 107         SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI,
 108         DMAC1_DMINT6, DMAC1_DMINT7, DMAC1_DMINT8, DMAC1_DMINT9,
 109         DMAC1_DMINT10, DMAC1_DMINT11, DMAC1_DMAE,
 110         HSPI,
 111         SCIF2, SCIF3, SCIF4, SCIF5,
 112         PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD,
 113         PCIERR, PCIPWD3, PCIPWD2, PCIPWD1, PCIPWD0,
 114         SIOF,
 115         MMCIF_FSTAT, MMCIF_TRAN, MMCIF_ERR, MMCIF_FRDY,
 116         DU,
 117         GDTA_GACLI, GDTA_GAMCI, GDTA_GAERI,
 118         TMU3, TMU4, TMU5,
 119         SSI0, SSI1,
 120         HAC0, HAC1,
 121         FLCTL_FLSTE, FLCTL_FLEND, FLCTL_FLTRQ0, FLCTL_FLTRQ1,
 122         GPIOI0, GPIOI1, GPIOI2, GPIOI3,
 123
 124         /* interrupt groups */
 125
 126         TMU012, DMAC0, SCIF0, SCIF1, DMAC1,
 127         PCIC5, MMCIF, GDTA, TMU345, FLCTL, GPIO
 128 };
 129
 130 static struct intc_vect vectors[] __initdata = {
 131         INTC_VECT(WDT, 0x560),
 132         INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
 133         INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
 134         INTC_VECT(HUDI, 0x600),
 135         INTC_VECT(DMAC0_DMINT0, 0x620), INTC_VECT(DMAC0_DMINT1, 0x640),
 136         INTC_VECT(DMAC0_DMINT2, 0x660), INTC_VECT(DMAC0_DMINT3, 0x680),
 137         INTC_VECT(DMAC0_DMINT4, 0x6a0), INTC_VECT(DMAC0_DMINT5, 0x6c0),
 138         INTC_VECT(DMAC0_DMAE, 0x6e0),
 139         INTC_VECT(SCIF0_ERI, 0x700), INTC_VECT(SCIF0_RXI, 0x720),
 140         INTC_VECT(SCIF0_BRI, 0x740), INTC_VECT(SCIF0_TXI, 0x760),
 141         INTC_VECT(SCIF1_ERI, 0x780), INTC_VECT(SCIF1_RXI, 0x7a0),
 142         INTC_VECT(SCIF1_BRI, 0x7c0), INTC_VECT(SCIF1_TXI, 0x7e0),
 143         INTC_VECT(DMAC1_DMINT6, 0x880), INTC_VECT(DMAC1_DMINT7, 0x8a0),
 144         INTC_VECT(DMAC1_DMINT8, 0x8c0), INTC_VECT(DMAC1_DMINT9, 0x8e0),
 145         INTC_VECT(DMAC1_DMINT10, 0x900), INTC_VECT(DMAC1_DMINT11, 0x920),
 146         INTC_VECT(DMAC1_DMAE, 0x940),
 147         INTC_VECT(HSPI, 0x960),
 148         INTC_VECT(SCIF2, 0x980), INTC_VECT(SCIF3, 0x9a0),
 149         INTC_VECT(SCIF4, 0x9c0), INTC_VECT(SCIF5, 0x9e0),
 150         INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20),
 151         INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60),
 152         INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIERR, 0xaa0),
 153         INTC_VECT(PCIPWD3, 0xac0), INTC_VECT(PCIPWD2, 0xae0),
 154         INTC_VECT(PCIPWD1, 0xb00), INTC_VECT(PCIPWD0, 0xb20),
 155         INTC_VECT(SIOF, 0xc00),
 156         INTC_VECT(MMCIF_FSTAT, 0xd00), INTC_VECT(MMCIF_TRAN, 0xd20),
 157         INTC_VECT(MMCIF_ERR, 0xd40), INTC_VECT(MMCIF_FRDY, 0xd60),
 158         INTC_VECT(DU, 0xd80),
 159         INTC_VECT(GDTA_GACLI, 0xda0), INTC_VECT(GDTA_GAMCI, 0xdc0),
 160         INTC_VECT(GDTA_GAERI, 0xde0),
 161         INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
 162         INTC_VECT(TMU5, 0xe40),
 163         INTC_VECT(SSI0, 0xe80), INTC_VECT(SSI1, 0xea0),
 164         INTC_VECT(HAC0, 0xec0), INTC_VECT(HAC1, 0xee0),
 165         INTC_VECT(FLCTL_FLSTE, 0xf00), INTC_VECT(FLCTL_FLEND, 0xf20),
 166         INTC_VECT(FLCTL_FLTRQ0, 0xf40), INTC_VECT(FLCTL_FLTRQ1, 0xf60),
 167         INTC_VECT(GPIOI0, 0xf80), INTC_VECT(GPIOI1, 0xfa0),
 168         INTC_VECT(GPIOI2, 0xfc0), INTC_VECT(GPIOI3, 0xfe0),
 169 };
 170
 171 static struct intc_group groups[] __initdata = {
 172         INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
 173         INTC_GROUP(DMAC0, DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2,
 174                    DMAC0_DMINT3, DMAC0_DMINT4, DMAC0_DMINT5, DMAC0_DMAE),
 175         INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
 176         INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI),
 177         INTC_GROUP(DMAC1, DMAC1_DMINT6, DMAC1_DMINT7, DMAC1_DMINT8,
 178                    DMAC1_DMINT9, DMAC1_DMINT10, DMAC1_DMINT11, DMAC1_DMAE),
 179         INTC_GROUP(PCIC5, PCIERR, PCIPWD3, PCIPWD2, PCIPWD1, PCIPWD0),
 180         INTC_GROUP(MMCIF, MMCIF_FSTAT, MMCIF_TRAN, MMCIF_ERR, MMCIF_FRDY),
 181         INTC_GROUP(GDTA, GDTA_GACLI, GDTA_GAMCI, GDTA_GAERI),
 182         INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
 183         INTC_GROUP(FLCTL, FLCTL_FLSTE, FLCTL_FLEND,
 184                    FLCTL_FLTRQ0, FLCTL_FLTRQ1),
 185         INTC_GROUP(GPIO, GPIOI0, GPIOI1, GPIOI2, GPIOI3),
 186 };
 187
 188 static struct intc_mask_reg mask_registers[] __initdata = {
 189         { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
 190           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 191
 192         { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
 193           { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
 194             IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
 195             IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
 196             IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0,
 197             IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
 198             IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
 199             IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
 200             IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
 201
 202         { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
 203           { 0, 0, 0, GDTA, DU, SSI0, SSI1, GPIO,
 204             FLCTL, MMCIF, HSPI, SIOF, PCIC5, PCIINTD, PCIINTC, PCIINTB,
 205             PCIINTA, PCISERR, HAC1, HAC0, DMAC1, DMAC0, HUDI, WDT,
 206             SCIF5, SCIF4, SCIF3, SCIF2, SCIF1, SCIF0, TMU345, TMU012 } },
 207 };
 208
 209 static struct intc_prio_reg prio_registers[] __initdata = {
 210         { 0xffd00010, 0, 32, 4, /* INTPRI */   { IRQ0, IRQ1, IRQ2, IRQ3,
 211                                                  IRQ4, IRQ5, IRQ6, IRQ7 } },
 212         { 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1,
 213                                                  TMU2, TMU2_TICPI } },
 214         { 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, } },
 215         { 0xffd40008, 0, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1,
 216                                                  SCIF2, SCIF3 } },
 217         { 0xffd4000c, 0, 32, 8, /* INT2PRI3 */ { SCIF4, SCIF5, WDT, } },
 218         { 0xffd40010, 0, 32, 8, /* INT2PRI4 */ { HUDI, DMAC0, DMAC1, } },
 219         { 0xffd40014, 0, 32, 8, /* INT2PRI5 */ { HAC0, HAC1,
 220                                                  PCISERR, PCIINTA } },
 221         { 0xffd40018, 0, 32, 8, /* INT2PRI6 */ { PCIINTB, PCIINTC,
 222                                                  PCIINTD, PCIC5 } },
 223         { 0xffd4001c, 0, 32, 8, /* INT2PRI7 */ { SIOF, HSPI, MMCIF, } },
 224         { 0xffd40020, 0, 32, 8, /* INT2PRI8 */ { FLCTL, GPIO, SSI0, SSI1, } },
 225         { 0xffd40024, 0, 32, 8, /* INT2PRI9 */ { DU, GDTA, } },
 226 };
 227
 228 static DECLARE_INTC_DESC(intc_desc, "sh7785", vectors, groups,
 229                          mask_registers, prio_registers, NULL);
 230
 231 /* Support for external interrupt pins in IRQ mode */
 232
 233 static struct intc_vect vectors_irq0123[] __initdata = {
 234         INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
 235         INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
 236 };
 237
 238 static struct intc_vect vectors_irq4567[] __initdata = {
 239         INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
 240         INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
 241 };
 242
 243 static struct intc_sense_reg sense_registers[] __initdata = {
 244         { 0xffd0001c, 32, 2, /* ICR1 */   { IRQ0, IRQ1, IRQ2, IRQ3,
 245                                             IRQ4, IRQ5, IRQ6, IRQ7 } },
 246 };
 247
 248 static DECLARE_INTC_DESC(intc_desc_irq0123, "sh7785-irq0123", vectors_irq0123,
 249                          NULL, mask_registers, prio_registers,
 250                          sense_registers);
 251
 252 static DECLARE_INTC_DESC(intc_desc_irq4567, "sh7785-irq4567", vectors_irq4567,
 253                          NULL, mask_registers, prio_registers,
 254                          sense_registers);
 255
 256 /* External interrupt pins in IRL mode */
 257
 258 static struct intc_vect vectors_irl0123[] __initdata = {
 259         INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
 260         INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
 261         INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
 262         INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
 263         INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
 264         INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
 265         INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
 266         INTC_VECT(IRL0_HHHL, 0x3c0),
 267 };
 268
 269 static struct intc_vect vectors_irl4567[] __initdata = {
 270         INTC_VECT(IRL4_LLLL, 0xb00), INTC_VECT(IRL4_LLLH, 0xb20),
 271         INTC_VECT(IRL4_LLHL, 0xb40), INTC_VECT(IRL4_LLHH, 0xb60),
 272         INTC_VECT(IRL4_LHLL, 0xb80), INTC_VECT(IRL4_LHLH, 0xba0),
 273         INTC_VECT(IRL4_LHHL, 0xbc0), INTC_VECT(IRL4_LHHH, 0xbe0),
 274         INTC_VECT(IRL4_HLLL, 0xc00), INTC_VECT(IRL4_HLLH, 0xc20),
 275         INTC_VECT(IRL4_HLHL, 0xc40), INTC_VECT(IRL4_HLHH, 0xc60),
 276         INTC_VECT(IRL4_HHLL, 0xc80), INTC_VECT(IRL4_HHLH, 0xca0),
 277         INTC_VECT(IRL4_HHHL, 0xcc0),
 278 };
 279
 280 static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7785-irl0123", vectors_irl0123,
 281                          NULL, mask_registers, NULL, NULL);
 282
 283 static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7785-irl4567", vectors_irl4567,
 284                          NULL, mask_registers, NULL, NULL);
 285
 286 #define INTC_ICR0       0xffd00000
 287 #define INTC_INTMSK0    0xffd00044
 288 #define INTC_INTMSK1    0xffd00048
 289 #define INTC_INTMSK2    0xffd40080
 290 #define INTC_INTMSKCLR1 0xffd00068
 291 #define INTC_INTMSKCLR2 0xffd40084
 292
 293 void __init plat_irq_setup(void)
 294 {
 295         /* disable IRQ3-0 + IRQ7-4 */
 296         ctrl_outl(0xff000000, INTC_INTMSK0);
 297
 298         /* disable IRL3-0 + IRL7-4 */
 299         ctrl_outl(0xc0000000, INTC_INTMSK1);
 300         ctrl_outl(0xfffefffe, INTC_INTMSK2);
 301
 302         /* select IRL mode for IRL3-0 + IRL7-4 */
 303         ctrl_outl(ctrl_inl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
 304
 305         /* disable holding function, ie enable "SH-4 Mode" */
 306         ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00200000, INTC_ICR0);
 307
 308         register_intc_controller(&intc_desc);
 309 }
 310
 311 void __init plat_irq_setup_pins(int mode)
 312 {
 313         switch (mode) {
 314         case IRQ_MODE_IRQ7654:
 315                 /* select IRQ mode for IRL7-4 */
 316                 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00400000, INTC_ICR0);
 317                 register_intc_controller(&intc_desc_irq4567);
 318                 break;
 319         case IRQ_MODE_IRQ3210:
 320                 /* select IRQ mode for IRL3-0 */
 321                 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00800000, INTC_ICR0);
 322                 register_intc_controller(&intc_desc_irq0123);
 323                 break;
 324         case IRQ_MODE_IRL7654:
 325                 /* enable IRL7-4 but don't provide any masking */
 326                 ctrl_outl(0x40000000, INTC_INTMSKCLR1);
 327                 ctrl_outl(0x0000fffe, INTC_INTMSKCLR2);
 328                 break;
 329         case IRQ_MODE_IRL3210:
 330                 /* enable IRL0-3 but don't provide any masking */
 331                 ctrl_outl(0x80000000, INTC_INTMSKCLR1);
 332                 ctrl_outl(0xfffe0000, INTC_INTMSKCLR2);
 333                 break;
 334         case IRQ_MODE_IRL7654_MASK:
 335                 /* enable IRL7-4 and mask using cpu intc controller */
 336                 ctrl_outl(0x40000000, INTC_INTMSKCLR1);
 337                 register_intc_controller(&intc_desc_irl4567);
 338                 break;
 339         case IRQ_MODE_IRL3210_MASK:
 340                 /* enable IRL0-3 and mask using cpu intc controller */
 341                 ctrl_outl(0x80000000, INTC_INTMSKCLR1);
 342                 register_intc_controller(&intc_desc_irl0123);
 343                 break;
 344         default:
 345                 BUG();
 346         }
 347 }
 348
 349 void __init plat_mem_setup(void)
 350 {
 351         /* Register the URAM space as Node 1 */
 352         setup_bootmem_node(1, 0xe55f0000, 0xe5610000);
 353 }