arch/sh/kernel/cpu/sh4a/setup-shx3.c

   1 /*
   2  * SH-X3 Setup
   3  *
   4  *  Copyright (C) 2007  Paul Mundt
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License.  See the file "COPYING" in the main directory of this archive
   8  * for more details.
   9  */
  10 #include <linux/platform_device.h>
  11 #include <linux/init.h>
  12 #include <linux/serial.h>
  13 <<<<<<< HEAD:arch/sh/kernel/cpu/sh4a/setup-shx3.c
  14 =======
  15 #include <linux/serial_sci.h>
  16 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/sh/kernel/cpu/sh4a/setup-shx3.c
  17 #include <linux/io.h>
  18 #include <asm/mmzone.h>
  19 <<<<<<< HEAD:arch/sh/kernel/cpu/sh4a/setup-shx3.c
  20 #include <asm/sci.h>
  21 =======
  22 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/sh/kernel/cpu/sh4a/setup-shx3.c
  23
  24 static struct plat_sci_port sci_platform_data[] = {
  25         {
  26                 .mapbase        = 0xffc30000,
  27                 .flags          = UPF_BOOT_AUTOCONF,
  28                 .type           = PORT_SCIF,
  29                 .irqs           = { 40, 41, 43, 42 },
  30         }, {
  31                 .mapbase        = 0xffc40000,
  32                 .flags          = UPF_BOOT_AUTOCONF,
  33                 .type           = PORT_SCIF,
  34                 .irqs           = { 44, 45, 47, 46 },
  35         }, {
  36                 .mapbase        = 0xffc50000,
  37                 .flags          = UPF_BOOT_AUTOCONF,
  38                 .type           = PORT_SCIF,
  39                 .irqs           = { 48, 49, 51, 50 },
  40         }, {
  41                 .mapbase        = 0xffc60000,
  42                 .flags          = UPF_BOOT_AUTOCONF,
  43                 .type           = PORT_SCIF,
  44                 .irqs           = { 52, 53, 55, 54 },
  45         }, {
  46                 .flags = 0,
  47         }
  48 };
  49
  50 static struct platform_device sci_device = {
  51         .name           = "sh-sci",
  52         .id             = -1,
  53         .dev            = {
  54                 .platform_data  = sci_platform_data,
  55         },
  56 };
  57
  58 static struct platform_device *shx3_devices[] __initdata = {
  59         &sci_device,
  60 };
  61
  62 static int __init shx3_devices_setup(void)
  63 {
  64         return platform_add_devices(shx3_devices,
  65                                     ARRAY_SIZE(shx3_devices));
  66 }
  67 __initcall(shx3_devices_setup);
  68
  69 enum {
  70         UNUSED = 0,
  71
  72         /* interrupt sources */
  73         IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
  74         IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
  75         IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
  76         IRL_HHLL, IRL_HHLH, IRL_HHHL,
  77         IRQ0, IRQ1, IRQ2, IRQ3,
  78         HUDII,
  79         TMU0, TMU1, TMU2, TMU3, TMU4, TMU5,
  80         PCII0, PCII1, PCII2, PCII3, PCII4,
  81         PCII5, PCII6, PCII7, PCII8, PCII9,
  82         SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
  83         SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI,
  84         SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI,
  85         SCIF3_ERI, SCIF3_RXI, SCIF3_BRI, SCIF3_TXI,
  86         DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2, DMAC0_DMINT3,
  87         DMAC0_DMINT4, DMAC0_DMINT5, DMAC0_DMAE,
  88         DU,
  89         DMAC1_DMINT6, DMAC1_DMINT7, DMAC1_DMINT8, DMAC1_DMINT9,
  90         DMAC1_DMINT10, DMAC1_DMINT11, DMAC1_DMAE,
  91         IIC, VIN0, VIN1, VCORE0, ATAPI,
  92         DTU0_TEND, DTU0_AE, DTU0_TMISS,
  93         DTU1_TEND, DTU1_AE, DTU1_TMISS,
  94         DTU2_TEND, DTU2_AE, DTU2_TMISS,
  95         DTU3_TEND, DTU3_AE, DTU3_TMISS,
  96         FE0, FE1,
  97         GPIO0, GPIO1, GPIO2, GPIO3,
  98         PAM, IRM,
  99         INTICI0, INTICI1, INTICI2, INTICI3,
 100         INTICI4, INTICI5, INTICI6, INTICI7,
 101
 102         /* interrupt groups */
 103         IRL, PCII56789, SCIF0, SCIF1, SCIF2, SCIF3,
 104         DMAC0, DMAC1, DTU0, DTU1, DTU2, DTU3,
 105 };
 106
 107 static struct intc_vect vectors[] __initdata = {
 108         INTC_VECT(HUDII, 0x3e0),
 109         INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
 110         INTC_VECT(TMU2, 0x440), INTC_VECT(TMU3, 0x460),
 111         INTC_VECT(TMU4, 0x480), INTC_VECT(TMU5, 0x4a0),
 112         INTC_VECT(PCII0, 0x500), INTC_VECT(PCII1, 0x520),
 113         INTC_VECT(PCII2, 0x540), INTC_VECT(PCII3, 0x560),
 114         INTC_VECT(PCII4, 0x580), INTC_VECT(PCII5, 0x5a0),
 115         INTC_VECT(PCII6, 0x5c0), INTC_VECT(PCII7, 0x5e0),
 116         INTC_VECT(PCII8, 0x600), INTC_VECT(PCII9, 0x620),
 117         INTC_VECT(SCIF0_ERI, 0x700), INTC_VECT(SCIF0_RXI, 0x720),
 118         INTC_VECT(SCIF0_BRI, 0x740), INTC_VECT(SCIF0_TXI, 0x760),
 119         INTC_VECT(SCIF1_ERI, 0x780), INTC_VECT(SCIF1_RXI, 0x7a0),
 120         INTC_VECT(SCIF1_BRI, 0x7c0), INTC_VECT(SCIF1_TXI, 0x7e0),
 121         INTC_VECT(SCIF2_ERI, 0x800), INTC_VECT(SCIF2_RXI, 0x820),
 122         INTC_VECT(SCIF2_BRI, 0x840), INTC_VECT(SCIF2_TXI, 0x860),
 123         INTC_VECT(SCIF3_ERI, 0x880), INTC_VECT(SCIF3_RXI, 0x8a0),
 124         INTC_VECT(SCIF3_BRI, 0x8c0), INTC_VECT(SCIF3_TXI, 0x8e0),
 125         INTC_VECT(DMAC0_DMINT0, 0x900), INTC_VECT(DMAC0_DMINT1, 0x920),
 126         INTC_VECT(DMAC0_DMINT2, 0x940), INTC_VECT(DMAC0_DMINT3, 0x960),
 127         INTC_VECT(DMAC0_DMINT4, 0x980), INTC_VECT(DMAC0_DMINT5, 0x9a0),
 128         INTC_VECT(DMAC0_DMAE, 0x9c0),
 129         INTC_VECT(DU, 0x9e0),
 130         INTC_VECT(DMAC1_DMINT6, 0xa00), INTC_VECT(DMAC1_DMINT7, 0xa20),
 131         INTC_VECT(DMAC1_DMINT8, 0xa40), INTC_VECT(DMAC1_DMINT9, 0xa60),
 132         INTC_VECT(DMAC1_DMINT10, 0xa80), INTC_VECT(DMAC1_DMINT11, 0xaa0),
 133         INTC_VECT(DMAC1_DMAE, 0xac0),
 134         INTC_VECT(IIC, 0xae0),
 135         INTC_VECT(VIN0, 0xb00), INTC_VECT(VIN1, 0xb20),
 136         INTC_VECT(VCORE0, 0xb00), INTC_VECT(ATAPI, 0xb60),
 137         INTC_VECT(DTU0_TEND, 0xc00), INTC_VECT(DTU0_AE, 0xc20),
 138         INTC_VECT(DTU0_TMISS, 0xc40),
 139         INTC_VECT(DTU1_TEND, 0xc60), INTC_VECT(DTU1_AE, 0xc80),
 140         INTC_VECT(DTU1_TMISS, 0xca0),
 141         INTC_VECT(DTU2_TEND, 0xcc0), INTC_VECT(DTU2_AE, 0xce0),
 142         INTC_VECT(DTU2_TMISS, 0xd00),
 143         INTC_VECT(DTU3_TEND, 0xd20), INTC_VECT(DTU3_AE, 0xd40),
 144         INTC_VECT(DTU3_TMISS, 0xd60),
 145         INTC_VECT(FE0, 0xe00), INTC_VECT(FE1, 0xe20),
 146         INTC_VECT(GPIO0, 0xe40), INTC_VECT(GPIO1, 0xe60),
 147         INTC_VECT(GPIO2, 0xe80), INTC_VECT(GPIO3, 0xea0),
 148         INTC_VECT(PAM, 0xec0), INTC_VECT(IRM, 0xee0),
 149         INTC_VECT(INTICI0, 0xf00), INTC_VECT(INTICI1, 0xf20),
 150         INTC_VECT(INTICI2, 0xf40), INTC_VECT(INTICI3, 0xf60),
 151         INTC_VECT(INTICI4, 0xf80), INTC_VECT(INTICI5, 0xfa0),
 152         INTC_VECT(INTICI6, 0xfc0), INTC_VECT(INTICI7, 0xfe0),
 153 };
 154
 155 static struct intc_group groups[] __initdata = {
 156         INTC_GROUP(IRL, IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
 157                    IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
 158                    IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
 159                    IRL_HHLL, IRL_HHLH, IRL_HHHL),
 160         INTC_GROUP(PCII56789, PCII5, PCII6, PCII7, PCII8, PCII9),
 161         INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
 162         INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI),
 163         INTC_GROUP(SCIF2, SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI),
 164         INTC_GROUP(SCIF3, SCIF3_ERI, SCIF3_RXI, SCIF3_BRI, SCIF3_TXI),
 165         INTC_GROUP(DMAC0, DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2,
 166                    DMAC0_DMINT3, DMAC0_DMINT4, DMAC0_DMINT5, DMAC0_DMAE),
 167         INTC_GROUP(DMAC1, DMAC1_DMINT6, DMAC1_DMINT7, DMAC1_DMINT8,
 168                    DMAC1_DMINT9, DMAC1_DMINT10, DMAC1_DMINT11),
 169         INTC_GROUP(DTU0, DTU0_TEND, DTU0_AE, DTU0_TMISS),
 170         INTC_GROUP(DTU1, DTU1_TEND, DTU1_AE, DTU1_TMISS),
 171         INTC_GROUP(DTU2, DTU2_TEND, DTU2_AE, DTU2_TMISS),
 172         INTC_GROUP(DTU3, DTU3_TEND, DTU3_AE, DTU3_TMISS),
 173 };
 174
 175 static struct intc_mask_reg mask_registers[] __initdata = {
 176         { 0xfe410030, 0xfe410050, 32, /* CnINTMSK0 / CnINTMSKCLR0 */
 177           { IRQ0, IRQ1, IRQ2, IRQ3 } },
 178         { 0xfe410040, 0xfe410060, 32, /* CnINTMSK1 / CnINTMSKCLR1 */
 179           { IRL } },
 180         { 0xfe410820, 0xfe410850, 32, /* CnINT2MSK0 / CnINT2MSKCLR0 */
 181           { FE1, FE0, 0, ATAPI, VCORE0, VIN1, VIN0, IIC,
 182             DU, GPIO3, GPIO2, GPIO1, GPIO0, PAM, 0, 0,
 183             0, 0, 0, 0, 0, 0, 0, 0, /* HUDI bits ignored */
 184             0, TMU5, TMU4, TMU3, TMU2, TMU1, TMU0, 0, } },
 185         { 0xfe410830, 0xfe410860, 32, /* CnINT2MSK1 / CnINT2MSKCLR1 */
 186           { 0, 0, 0, 0, DTU3, DTU2, DTU1, DTU0, /* IRM bits ignored */
 187             PCII9, PCII8, PCII7, PCII6, PCII5, PCII4, PCII3, PCII2,
 188             PCII1, PCII0, DMAC1_DMAE, DMAC1_DMINT11,
 189             DMAC1_DMINT10, DMAC1_DMINT9, DMAC1_DMINT8, DMAC1_DMINT7,
 190             DMAC1_DMINT6, DMAC0_DMAE, DMAC0_DMINT5, DMAC0_DMINT4,
 191             DMAC0_DMINT3, DMAC0_DMINT2, DMAC0_DMINT1, DMAC0_DMINT0 } },
 192         { 0xfe410840, 0xfe410870, 32, /* CnINT2MSK2 / CnINT2MSKCLR2 */
 193           { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 194             SCIF3_TXI, SCIF3_BRI, SCIF3_RXI, SCIF3_ERI,
 195             SCIF2_TXI, SCIF2_BRI, SCIF2_RXI, SCIF2_ERI,
 196             SCIF1_TXI, SCIF1_BRI, SCIF1_RXI, SCIF1_ERI,
 197             SCIF0_TXI, SCIF0_BRI, SCIF0_RXI, SCIF0_ERI } },
 198 };
 199
 200 static struct intc_prio_reg prio_registers[] __initdata = {
 201         { 0xfe410010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
 202
 203         { 0xfe410800, 0, 32, 4, /* INT2PRI0 */ { 0, HUDII, TMU5, TMU4,
 204                                                  TMU3, TMU2, TMU1, TMU0 } },
 205         { 0xfe410804, 0, 32, 4, /* INT2PRI1 */ { DTU3, DTU2, DTU1, DTU0,
 206                                                  SCIF3, SCIF2,
 207                                                  SCIF1, SCIF0 } },
 208         { 0xfe410808, 0, 32, 4, /* INT2PRI2 */ { DMAC1, DMAC0,
 209                                                  PCII56789, PCII4,
 210                                                  PCII3, PCII2,
 211                                                  PCII1, PCII0 } },
 212         { 0xfe41080c, 0, 32, 4, /* INT2PRI3 */ { FE1, FE0, ATAPI, VCORE0,
 213                                                  VIN1, VIN0, IIC, DU} },
 214         { 0xfe410810, 0, 32, 4, /* INT2PRI4 */ { 0, 0, PAM, GPIO3,
 215                                                  GPIO2, GPIO1, GPIO0, IRM } },
 216         { 0xfe410090, 0xfe4100a0, 32, 4, /* CnICIPRI / CnICIPRICLR */
 217           { INTICI7, INTICI6, INTICI5, INTICI4,
 218             INTICI3, INTICI2, INTICI1, INTICI0 }, INTC_SMP(4, 4) },
 219 };
 220
 221 static DECLARE_INTC_DESC(intc_desc, "shx3", vectors, groups,
 222                          mask_registers, prio_registers, NULL);
 223
 224 /* Support for external interrupt pins in IRQ mode */
 225 static struct intc_vect vectors_irq[] __initdata = {
 226         INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
 227         INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
 228 };
 229
 230 static struct intc_sense_reg sense_registers[] __initdata = {
 231         { 0xfe41001c, 32, 2, /* ICR1 */   { IRQ0, IRQ1, IRQ2, IRQ3 } },
 232 };
 233
 234 static DECLARE_INTC_DESC(intc_desc_irq, "shx3-irq", vectors_irq, groups,
 235                          mask_registers, prio_registers, sense_registers);
 236
 237 /* External interrupt pins in IRL mode */
 238 static struct intc_vect vectors_irl[] __initdata = {
 239         INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220),
 240         INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260),
 241         INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0),
 242         INTC_VECT(IRL_LHHL, 0x2c0), INTC_VECT(IRL_LHHH, 0x2e0),
 243         INTC_VECT(IRL_HLLL, 0x300), INTC_VECT(IRL_HLLH, 0x320),
 244         INTC_VECT(IRL_HLHL, 0x340), INTC_VECT(IRL_HLHH, 0x360),
 245         INTC_VECT(IRL_HHLL, 0x380), INTC_VECT(IRL_HHLH, 0x3a0),
 246         INTC_VECT(IRL_HHHL, 0x3c0),
 247 };
 248
 249 static DECLARE_INTC_DESC(intc_desc_irl, "shx3-irl", vectors_irl, groups,
 250                          mask_registers, prio_registers, NULL);
 251
 252 void __init plat_irq_setup_pins(int mode)
 253 {
 254         switch (mode) {
 255         case IRQ_MODE_IRQ:
 256                 register_intc_controller(&intc_desc_irq);
 257                 break;
 258         case IRQ_MODE_IRL3210:
 259                 register_intc_controller(&intc_desc_irl);
 260                 break;
 261         default:
 262                 BUG();
 263         }
 264 }
 265
 266 void __init plat_irq_setup(void)
 267 {
 268         register_intc_controller(&intc_desc);
 269 }
 270
 271 void __init plat_mem_setup(void)
 272 {
 273         unsigned int nid = 1;
 274
 275         /* Register CPU#0 URAM space as Node 1 */
 276         setup_bootmem_node(nid++, 0x145f0000, 0x14610000);      /* CPU0 */
 277
 278 #if 0
 279         /* XXX: Not yet.. */
 280         setup_bootmem_node(nid++, 0x14df0000, 0x14e10000);      /* CPU1 */
 281         setup_bootmem_node(nid++, 0x155f0000, 0x15610000);      /* CPU2 */
 282         setup_bootmem_node(nid++, 0x15df0000, 0x15e10000);      /* CPU3 */
 283 #endif
 284
 285         setup_bootmem_node(nid++, 0x16000000, 0x16020000);      /* CSM */
 286 }