arch/sh/kernel/timers/timer-mtu2.c

   1 /*
   2  * arch/sh/kernel/timers/timer-mtu2.c - MTU2 Timer Support
   3  *
   4  *  Copyright (C) 2005  Paul Mundt
   5  *
   6  * Based off of arch/sh/kernel/timers/timer-tmu.c
   7  *
   8  * This file is subject to the terms and conditions of the GNU General Public
   9  * License.  See the file "COPYING" in the main directory of this archive
  10  * for more details.
  11  */
  12 #include <linux/init.h>
  13 #include <linux/kernel.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/seqlock.h>
  16 #include <asm/timer.h>
  17 #include <asm/io.h>
  18 #include <asm/irq.h>
  19 #include <asm/clock.h>
  20
  21 /*
  22  * We use channel 1 for our lowly system timer. Channel 2 would be the other
  23  * likely candidate, but we leave it alone as it has higher divisors that
  24  * would be of more use to other more interesting applications.
  25  *
  26  * TODO: Presently we only implement a 16-bit single-channel system timer.
  27  * However, we can implement channel cascade if we go the overflow route and
  28  * get away with using 2 MTU2 channels as a 32-bit timer.
  29  */
  30 #define MTU2_TSTR       0xfffe4280
  31 #define MTU2_TCR_1      0xfffe4380
  32 #define MTU2_TMDR_1     0xfffe4381
  33 #define MTU2_TIOR_1     0xfffe4382
  34 #define MTU2_TIER_1     0xfffe4384
  35 #define MTU2_TSR_1      0xfffe4385
  36 #define MTU2_TCNT_1     0xfffe4386      /* 16-bit counter */
  37 #define MTU2_TGRA_1     0xfffe438a
  38
  39 #define STBCR3          0xfffe0408
  40
  41 #define MTU2_TSTR_CST1  (1 << 1)        /* Counter Start 1 */
  42
  43 #define MTU2_TSR_TGFA   (1 << 0)        /* GRA compare match */
  44
  45 #define MTU2_TIER_TGIEA (1 << 0)        /* GRA compare match  interrupt enable */
  46
  47 #define MTU2_TCR_INIT   0x22
  48
  49 #define MTU2_TCR_CALIB  0x00
  50
  51 static unsigned long mtu2_timer_get_offset(void)
  52 {
  53         int count;
  54         static int count_p = 0x7fff;    /* for the first call after boot */
  55         static unsigned long jiffies_p = 0;
  56
  57         /*
  58          * cache volatile jiffies temporarily; we have IRQs turned off.
  59          */
  60         unsigned long jiffies_t;
  61
  62         /* timer count may underflow right here */
  63         count = ctrl_inw(MTU2_TCNT_1);  /* read the latched count */
  64
  65         jiffies_t = jiffies;
  66
  67         /*
  68          * avoiding timer inconsistencies (they are rare, but they happen)...
  69          * there is one kind of problem that must be avoided here:
  70          *  1. the timer counter underflows
  71          */
  72
  73         if (jiffies_t == jiffies_p) {
  74                 if (count > count_p) {
  75                         if (ctrl_inb(MTU2_TSR_1) & MTU2_TSR_TGFA) {
  76                                 count -= LATCH;
  77                         } else {
  78                                 printk("%s (): hardware timer problem?\n",
  79 <<<<<<< HEAD:arch/sh/kernel/timers/timer-mtu2.c
  80                                        __FUNCTION__);
  81 =======
  82                                        __func__);
  83 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/sh/kernel/timers/timer-mtu2.c
  84                         }
  85                 }
  86         } else
  87                 jiffies_p = jiffies_t;
  88
  89         count_p = count;
  90
  91         count = ((LATCH-1) - count) * TICK_SIZE;
  92         count = (count + LATCH/2) / LATCH;
  93
  94         return count;
  95 }
  96
  97 static irqreturn_t mtu2_timer_interrupt(int irq, void *dev_id)
  98 {
  99         unsigned long timer_status;
 100
 101         /* Clear TGFA bit */
 102         timer_status = ctrl_inb(MTU2_TSR_1);
 103         timer_status &= ~MTU2_TSR_TGFA;
 104         ctrl_outb(timer_status, MTU2_TSR_1);
 105
 106         /* Do timer tick */
 107         handle_timer_tick();
 108
 109         return IRQ_HANDLED;
 110 }
 111
 112 static struct irqaction mtu2_irq = {
 113         .name           = "timer",
 114         .handler        = mtu2_timer_interrupt,
 115         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 116         .mask           = CPU_MASK_NONE,
 117 };
 118
 119 static unsigned int divisors[] = { 1, 4, 16, 64, 1, 1, 256 };
 120
 121 static void mtu2_clk_init(struct clk *clk)
 122 {
 123         u8 idx = MTU2_TCR_INIT & 0x7;
 124
 125         clk->rate = clk->parent->rate / divisors[idx];
 126         /* Start TCNT counting */
 127         ctrl_outb(ctrl_inb(MTU2_TSTR) | MTU2_TSTR_CST1, MTU2_TSTR);
 128
 129 }
 130
 131 static void mtu2_clk_recalc(struct clk *clk)
 132 {
 133         u8 idx = ctrl_inb(MTU2_TCR_1) & 0x7;
 134         clk->rate = clk->parent->rate / divisors[idx];
 135 }
 136
 137 static struct clk_ops mtu2_clk_ops = {
 138         .init           = mtu2_clk_init,
 139         .recalc         = mtu2_clk_recalc,
 140 };
 141
 142 static struct clk mtu2_clk1 = {
 143         .name           = "mtu2_clk1",
 144         .ops            = &mtu2_clk_ops,
 145 };
 146
 147 static int mtu2_timer_start(void)
 148 {
 149         ctrl_outb(ctrl_inb(MTU2_TSTR) | MTU2_TSTR_CST1, MTU2_TSTR);
 150         return 0;
 151 }
 152
 153 static int mtu2_timer_stop(void)
 154 {
 155         ctrl_outb(ctrl_inb(MTU2_TSTR) & ~MTU2_TSTR_CST1, MTU2_TSTR);
 156         return 0;
 157 }
 158
 159 static int mtu2_timer_init(void)
 160 {
 161         unsigned long interval;
 162
 163         setup_irq(CONFIG_SH_TIMER_IRQ, &mtu2_irq);
 164
 165         mtu2_clk1.parent = clk_get(NULL, "module_clk");
 166
 167         ctrl_outb(ctrl_inb(STBCR3) & (~0x20), STBCR3);
 168
 169         /* Normal operation */
 170         ctrl_outb(0, MTU2_TMDR_1);
 171         ctrl_outb(MTU2_TCR_INIT, MTU2_TCR_1);
 172         ctrl_outb(0x01, MTU2_TIOR_1);
 173
 174         /* Enable underflow interrupt */
 175         ctrl_outb(ctrl_inb(MTU2_TIER_1) | MTU2_TIER_TGIEA, MTU2_TIER_1);
 176
 177         interval = CONFIG_SH_PCLK_FREQ / 16 / HZ;
 178         printk(KERN_INFO "Interval = %ld\n", interval);
 179
 180         ctrl_outw(interval, MTU2_TGRA_1);
 181         ctrl_outw(0, MTU2_TCNT_1);
 182
 183         clk_register(&mtu2_clk1);
 184         clk_enable(&mtu2_clk1);
 185
 186         return 0;
 187 }
 188
 189 struct sys_timer_ops mtu2_timer_ops = {
 190         .init           = mtu2_timer_init,
 191         .start          = mtu2_timer_start,
 192         .stop           = mtu2_timer_stop,
 193 #ifndef CONFIG_GENERIC_TIME
 194         .get_offset     = mtu2_timer_get_offset,
 195 #endif
 196 };
 197
 198 struct sys_timer mtu2_timer = {
 199         .name   = "mtu2",
 200         .ops    = &mtu2_timer_ops,
 201 };