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Merge git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
[wrt350n-kernel.git] / arch / sh / kernel / traps_64.c
blob45007128984f02356d1458e1fbd1b289ea929231
1 /*
2 * arch/sh/kernel/traps_64.c
3 *
4 * Copyright (C) 2000, 2001 Paolo Alberelli
5 * Copyright (C) 2003, 2004 Paul Mundt
6 * Copyright (C) 2003, 2004 Richard Curnow
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
12 #include <linux/sched.h>
13 #include <linux/kernel.h>
14 #include <linux/string.h>
15 #include <linux/errno.h>
16 #include <linux/ptrace.h>
17 #include <linux/timer.h>
18 #include <linux/mm.h>
19 #include <linux/smp.h>
20 #include <linux/init.h>
21 #include <linux/delay.h>
22 #include <linux/spinlock.h>
23 #include <linux/kallsyms.h>
24 #include <linux/interrupt.h>
25 #include <linux/sysctl.h>
26 #include <linux/module.h>
27 #include <asm/system.h>
28 #include <asm/uaccess.h>
29 #include <asm/io.h>
30 #include <asm/atomic.h>
31 #include <asm/processor.h>
32 #include <asm/pgtable.h>
33
34 #undef DEBUG_EXCEPTION
35 #ifdef DEBUG_EXCEPTION
36 /* implemented in ../lib/dbg.c */
37 extern void show_excp_regs(char *fname, int trapnr, int signr,
38 struct pt_regs *regs);
39 #else
40 #define show_excp_regs(a, b, c, d)
41 #endif
42
43 static void do_unhandled_exception(int trapnr, int signr, char *str, char *fn_name,
44 unsigned long error_code, struct pt_regs *regs, struct task_struct *tsk);
45
46 #define DO_ERROR(trapnr, signr, str, name, tsk) \
47 asmlinkage void do_##name(unsigned long error_code, struct pt_regs *regs) \
48 { \
49 do_unhandled_exception(trapnr, signr, str, __stringify(name), error_code, regs, current); \
50 }
51
52 spinlock_t die_lock;
53
54 void die(const char * str, struct pt_regs * regs, long err)
55 {
56 console_verbose();
57 spin_lock_irq(&die_lock);
58 printk("%s: %lx\n", str, (err & 0xffffff));
59 show_regs(regs);
60 spin_unlock_irq(&die_lock);
61 do_exit(SIGSEGV);
62 }
63
64 static inline void die_if_kernel(const char * str, struct pt_regs * regs, long err)
65 {
66 if (!user_mode(regs))
67 die(str, regs, err);
68 }
69
70 static void die_if_no_fixup(const char * str, struct pt_regs * regs, long err)
71 {
72 if (!user_mode(regs)) {
73 const struct exception_table_entry *fixup;
74 fixup = search_exception_tables(regs->pc);
75 if (fixup) {
76 regs->pc = fixup->fixup;
77 return;
78 }
79 die(str, regs, err);
80 }
81 }
82
83 DO_ERROR(13, SIGILL, "illegal slot instruction", illegal_slot_inst, current)
84 DO_ERROR(87, SIGSEGV, "address error (exec)", address_error_exec, current)
85
86
87 /* Implement misaligned load/store handling for kernel (and optionally for user
88 mode too). Limitation : only SHmedia mode code is handled - there is no
89 handling at all for misaligned accesses occurring in SHcompact code yet. */
90
91 static int misaligned_fixup(struct pt_regs *regs);
92
93 asmlinkage void do_address_error_load(unsigned long error_code, struct pt_regs *regs)
94 {
95 if (misaligned_fixup(regs) < 0) {
96 do_unhandled_exception(7, SIGSEGV, "address error(load)",
97 "do_address_error_load",
98 error_code, regs, current);
99 }
100 return;
101 }
102
103 asmlinkage void do_address_error_store(unsigned long error_code, struct pt_regs *regs)
104 {
105 if (misaligned_fixup(regs) < 0) {
106 do_unhandled_exception(8, SIGSEGV, "address error(store)",
107 "do_address_error_store",
108 error_code, regs, current);
109 }
110 return;
111 }
112
113 #if defined(CONFIG_SH64_ID2815_WORKAROUND)
114
115 #define OPCODE_INVALID 0
116 #define OPCODE_USER_VALID 1
117 #define OPCODE_PRIV_VALID 2
118
119 /* getcon/putcon - requires checking which control register is referenced. */
120 #define OPCODE_CTRL_REG 3
121
122 /* Table of valid opcodes for SHmedia mode.
123 Form a 10-bit value by concatenating the major/minor opcodes i.e.
124 opcode[31:26,20:16]. The 6 MSBs of this value index into the following
125 array. The 4 LSBs select the bit-pair in the entry (bits 1:0 correspond to
126 LSBs==4'b0000 etc). */
127 static unsigned long shmedia_opcode_table[64] = {
128 0x55554044,0x54445055,0x15141514,0x14541414,0x00000000,0x10001000,0x01110055,0x04050015,
129 0x00000444,0xc0000000,0x44545515,0x40405555,0x55550015,0x10005555,0x55555505,0x04050000,
130 0x00000555,0x00000404,0x00040445,0x15151414,0x00000000,0x00000000,0x00000000,0x00000000,
131 0x00000055,0x40404444,0x00000404,0xc0009495,0x00000000,0x00000000,0x00000000,0x00000000,
132 0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,
133 0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,
134 0x80005050,0x04005055,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,
135 0x81055554,0x00000404,0x55555555,0x55555555,0x00000000,0x00000000,0x00000000,0x00000000
136 };
137
138 void do_reserved_inst(unsigned long error_code, struct pt_regs *regs)
139 {
140 /* Workaround SH5-101 cut2 silicon defect #2815 :
141 in some situations, inter-mode branches from SHcompact -> SHmedia
142 which should take ITLBMISS or EXECPROT exceptions at the target
143 falsely take RESINST at the target instead. */
144
145 unsigned long opcode = 0x6ff4fff0; /* guaranteed reserved opcode */
146 unsigned long pc, aligned_pc;
147 int get_user_error;
148 int trapnr = 12;
149 int signr = SIGILL;
150 char *exception_name = "reserved_instruction";
151
152 pc = regs->pc;
153 if ((pc & 3) == 1) {
154 /* SHmedia : check for defect. This requires executable vmas
155 to be readable too. */
156 aligned_pc = pc & ~3;
157 if (!access_ok(VERIFY_READ, aligned_pc, sizeof(unsigned long))) {
158 get_user_error = -EFAULT;
159 } else {
160 get_user_error = __get_user(opcode, (unsigned long *)aligned_pc);
161 }
162 if (get_user_error >= 0) {
163 unsigned long index, shift;
164 unsigned long major, minor, combined;
165 unsigned long reserved_field;
166 reserved_field = opcode & 0xf; /* These bits are currently reserved as zero in all valid opcodes */
167 major = (opcode >> 26) & 0x3f;
168 minor = (opcode >> 16) & 0xf;
169 combined = (major << 4) | minor;
170 index = major;
171 shift = minor << 1;
172 if (reserved_field == 0) {
173 int opcode_state = (shmedia_opcode_table[index] >> shift) & 0x3;
174 switch (opcode_state) {
175 case OPCODE_INVALID:
176 /* Trap. */
177 break;
178 case OPCODE_USER_VALID:
179 /* Restart the instruction : the branch to the instruction will now be from an RTE
180 not from SHcompact so the silicon defect won't be triggered. */
181 return;
182 case OPCODE_PRIV_VALID:
183 if (!user_mode(regs)) {
184 /* Should only ever get here if a module has
185 SHcompact code inside it. If so, the same fix up is needed. */
186 return; /* same reason */
187 }
188 /* Otherwise, user mode trying to execute a privileged instruction -
189 fall through to trap. */
190 break;
191 case OPCODE_CTRL_REG:
192 /* If in privileged mode, return as above. */
193 if (!user_mode(regs)) return;
194 /* In user mode ... */
195 if (combined == 0x9f) { /* GETCON */
196 unsigned long regno = (opcode >> 20) & 0x3f;
197 if (regno >= 62) {
198 return;
199 }
200 /* Otherwise, reserved or privileged control register, => trap */
201 } else if (combined == 0x1bf) { /* PUTCON */
202 unsigned long regno = (opcode >> 4) & 0x3f;
203 if (regno >= 62) {
204 return;
205 }
206 /* Otherwise, reserved or privileged control register, => trap */
207 } else {
208 /* Trap */
209 }
210 break;
211 default:
212 /* Fall through to trap. */
213 break;
214 }
215 }
216 /* fall through to normal resinst processing */
217 } else {
218 /* Error trying to read opcode. This typically means a
219 real fault, not a RESINST any more. So change the
220 codes. */
221 trapnr = 87;
222 exception_name = "address error (exec)";
223 signr = SIGSEGV;
224 }
225 }
226
227 do_unhandled_exception(trapnr, signr, exception_name, "do_reserved_inst", error_code, regs, current);
228 }
229
230 #else /* CONFIG_SH64_ID2815_WORKAROUND */
231
232 /* If the workaround isn't needed, this is just a straightforward reserved
233 instruction */
234 DO_ERROR(12, SIGILL, "reserved instruction", reserved_inst, current)
235
236 #endif /* CONFIG_SH64_ID2815_WORKAROUND */
237
238 /* Called with interrupts disabled */
239 asmlinkage void do_exception_error(unsigned long ex, struct pt_regs *regs)
240 {
241 <<<<<<< HEAD:arch/sh/kernel/traps_64.c
242 show_excp_regs(__FUNCTION__, -1, -1, regs);
243 =======
244 show_excp_regs(__func__, -1, -1, regs);
245 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/sh/kernel/traps_64.c
246 die_if_kernel("exception", regs, ex);
247 }
248
249 int do_unknown_trapa(unsigned long scId, struct pt_regs *regs)
250 {
251 /* Syscall debug */
252 printk("System call ID error: [0x1#args:8 #syscall:16 0x%lx]\n", scId);
253
254 die_if_kernel("unknown trapa", regs, scId);
255
256 return -ENOSYS;
257 }
258
259 void show_stack(struct task_struct *tsk, unsigned long *sp)
260 {
261 #ifdef CONFIG_KALLSYMS
262 extern void sh64_unwind(struct pt_regs *regs);
263 struct pt_regs *regs;
264
265 regs = tsk ? tsk->thread.kregs : NULL;
266
267 sh64_unwind(regs);
268 #else
269 printk(KERN_ERR "Can't backtrace on sh64 without CONFIG_KALLSYMS\n");
270 #endif
271 }
272
273 void show_task(unsigned long *sp)
274 {
275 show_stack(NULL, sp);
276 }
277
278 void dump_stack(void)
279 {
280 show_task(NULL);
281 }
282 /* Needed by any user of WARN_ON in view of the defn in include/asm-sh/bug.h */
283 EXPORT_SYMBOL(dump_stack);
284
285 static void do_unhandled_exception(int trapnr, int signr, char *str, char *fn_name,
286 unsigned long error_code, struct pt_regs *regs, struct task_struct *tsk)
287 {
288 show_excp_regs(fn_name, trapnr, signr, regs);
289 tsk->thread.error_code = error_code;
290 tsk->thread.trap_no = trapnr;
291
292 if (user_mode(regs))
293 force_sig(signr, tsk);
294
295 die_if_no_fixup(str, regs, error_code);
296 }
297
298 static int read_opcode(unsigned long long pc, unsigned long *result_opcode, int from_user_mode)
299 {
300 int get_user_error;
301 unsigned long aligned_pc;
302 unsigned long opcode;
303
304 if ((pc & 3) == 1) {
305 /* SHmedia */
306 aligned_pc = pc & ~3;
307 if (from_user_mode) {
308 if (!access_ok(VERIFY_READ, aligned_pc, sizeof(unsigned long))) {
309 get_user_error = -EFAULT;
310 } else {
311 get_user_error = __get_user(opcode, (unsigned long *)aligned_pc);
312 *result_opcode = opcode;
313 }
314 return get_user_error;
315 } else {
316 /* If the fault was in the kernel, we can either read
317 * this directly, or if not, we fault.
318 */
319 *result_opcode = *(unsigned long *) aligned_pc;
320 return 0;
321 }
322 } else if ((pc & 1) == 0) {
323 /* SHcompact */
324 /* TODO : provide handling for this. We don't really support
325 user-mode SHcompact yet, and for a kernel fault, this would
326 have to come from a module built for SHcompact. */
327 return -EFAULT;
328 } else {
329 /* misaligned */
330 return -EFAULT;
331 }
332 }
333
334 static int address_is_sign_extended(__u64 a)
335 {
336 __u64 b;
337 #if (NEFF == 32)
338 b = (__u64)(__s64)(__s32)(a & 0xffffffffUL);
339 return (b == a) ? 1 : 0;
340 #else
341 #error "Sign extend check only works for NEFF==32"
342 #endif
343 }
344
345 static int generate_and_check_address(struct pt_regs *regs,
346 __u32 opcode,
347 int displacement_not_indexed,
348 int width_shift,
349 __u64 *address)
350 {
351 /* return -1 for fault, 0 for OK */
352
353 __u64 base_address, addr;
354 int basereg;
355
356 basereg = (opcode >> 20) & 0x3f;
357 base_address = regs->regs[basereg];
358 if (displacement_not_indexed) {
359 __s64 displacement;
360 displacement = (opcode >> 10) & 0x3ff;
361 displacement = ((displacement << 54) >> 54); /* sign extend */
362 addr = (__u64)((__s64)base_address + (displacement << width_shift));
363 } else {
364 __u64 offset;
365 int offsetreg;
366 offsetreg = (opcode >> 10) & 0x3f;
367 offset = regs->regs[offsetreg];
368 addr = base_address + offset;
369 }
370
371 /* Check sign extended */
372 if (!address_is_sign_extended(addr)) {
373 return -1;
374 }
375
376 #if defined(CONFIG_SH64_USER_MISALIGNED_FIXUP)
377 /* Check accessible. For misaligned access in the kernel, assume the
378 address is always accessible (and if not, just fault when the
379 load/store gets done.) */
380 if (user_mode(regs)) {
381 if (addr >= TASK_SIZE) {
382 return -1;
383 }
384 /* Do access_ok check later - it depends on whether it's a load or a store. */
385 }
386 #endif
387
388 *address = addr;
389 return 0;
390 }
391
392 /* Default value as for sh */
393 #if defined(CONFIG_SH64_USER_MISALIGNED_FIXUP)
394 static int user_mode_unaligned_fixup_count = 10;
395 static int user_mode_unaligned_fixup_enable = 1;
396 #endif
397
398 static int kernel_mode_unaligned_fixup_count = 32;
399
400 static void misaligned_kernel_word_load(__u64 address, int do_sign_extend, __u64 *result)
401 {
402 unsigned short x;
403 unsigned char *p, *q;
404 p = (unsigned char *) (int) address;
405 q = (unsigned char *) &x;
406 q[0] = p[0];
407 q[1] = p[1];
408
409 if (do_sign_extend) {
410 *result = (__u64)(__s64) *(short *) &x;
411 } else {
412 *result = (__u64) x;
413 }
414 }
415
416 static void misaligned_kernel_word_store(__u64 address, __u64 value)
417 {
418 unsigned short x;
419 unsigned char *p, *q;
420 p = (unsigned char *) (int) address;
421 q = (unsigned char *) &x;
422
423 x = (__u16) value;
424 p[0] = q[0];
425 p[1] = q[1];
426 }
427
428 static int misaligned_load(struct pt_regs *regs,
429 __u32 opcode,
430 int displacement_not_indexed,
431 int width_shift,
432 int do_sign_extend)
433 {
434 /* Return -1 for a fault, 0 for OK */
435 int error;
436 int destreg;
437 __u64 address;
438
439 error = generate_and_check_address(regs, opcode,
440 displacement_not_indexed, width_shift, &address);
441 if (error < 0) {
442 return error;
443 }
444
445 destreg = (opcode >> 4) & 0x3f;
446 #if defined(CONFIG_SH64_USER_MISALIGNED_FIXUP)
447 if (user_mode(regs)) {
448 __u64 buffer;
449
450 if (!access_ok(VERIFY_READ, (unsigned long) address, 1UL<<width_shift)) {
451 return -1;
452 }
453
454 if (__copy_user(&buffer, (const void *)(int)address, (1 << width_shift)) > 0) {
455 return -1; /* fault */
456 }
457 switch (width_shift) {
458 case 1:
459 if (do_sign_extend) {
460 regs->regs[destreg] = (__u64)(__s64) *(__s16 *) &buffer;
461 } else {
462 regs->regs[destreg] = (__u64) *(__u16 *) &buffer;
463 }
464 break;
465 case 2:
466 regs->regs[destreg] = (__u64)(__s64) *(__s32 *) &buffer;
467 break;
468 case 3:
469 regs->regs[destreg] = buffer;
470 break;
471 default:
472 printk("Unexpected width_shift %d in misaligned_load, PC=%08lx\n",
473 width_shift, (unsigned long) regs->pc);
474 break;
475 }
476 } else
477 #endif
478 {
479 /* kernel mode - we can take short cuts since if we fault, it's a genuine bug */
480 __u64 lo, hi;
481
482 switch (width_shift) {
483 case 1:
484 misaligned_kernel_word_load(address, do_sign_extend, &regs->regs[destreg]);
485 break;
486 case 2:
487 asm ("ldlo.l %1, 0, %0" : "=r" (lo) : "r" (address));
488 asm ("ldhi.l %1, 3, %0" : "=r" (hi) : "r" (address));
489 regs->regs[destreg] = lo | hi;
490 break;
491 case 3:
492 asm ("ldlo.q %1, 0, %0" : "=r" (lo) : "r" (address));
493 asm ("ldhi.q %1, 7, %0" : "=r" (hi) : "r" (address));
494 regs->regs[destreg] = lo | hi;
495 break;
496
497 default:
498 printk("Unexpected width_shift %d in misaligned_load, PC=%08lx\n",
499 width_shift, (unsigned long) regs->pc);
500 break;
501 }
502 }
503
504 return 0;
505
506 }
507
508 static int misaligned_store(struct pt_regs *regs,
509 __u32 opcode,
510 int displacement_not_indexed,
511 int width_shift)
512 {
513 /* Return -1 for a fault, 0 for OK */
514 int error;
515 int srcreg;
516 __u64 address;
517
518 error = generate_and_check_address(regs, opcode,
519 displacement_not_indexed, width_shift, &address);
520 if (error < 0) {
521 return error;
522 }
523
524 srcreg = (opcode >> 4) & 0x3f;
525 #if defined(CONFIG_SH64_USER_MISALIGNED_FIXUP)
526 if (user_mode(regs)) {
527 __u64 buffer;
528
529 if (!access_ok(VERIFY_WRITE, (unsigned long) address, 1UL<<width_shift)) {
530 return -1;
531 }
532
533 switch (width_shift) {
534 case 1:
535 *(__u16 *) &buffer = (__u16) regs->regs[srcreg];
536 break;
537 case 2:
538 *(__u32 *) &buffer = (__u32) regs->regs[srcreg];
539 break;
540 case 3:
541 buffer = regs->regs[srcreg];
542 break;
543 default:
544 printk("Unexpected width_shift %d in misaligned_store, PC=%08lx\n",
545 width_shift, (unsigned long) regs->pc);
546 break;
547 }
548
549 if (__copy_user((void *)(int)address, &buffer, (1 << width_shift)) > 0) {
550 return -1; /* fault */
551 }
552 } else
553 #endif
554 {
555 /* kernel mode - we can take short cuts since if we fault, it's a genuine bug */
556 __u64 val = regs->regs[srcreg];
557
558 switch (width_shift) {
559 case 1:
560 misaligned_kernel_word_store(address, val);
561 break;
562 case 2:
563 asm ("stlo.l %1, 0, %0" : : "r" (val), "r" (address));
564 asm ("sthi.l %1, 3, %0" : : "r" (val), "r" (address));
565 break;
566 case 3:
567 asm ("stlo.q %1, 0, %0" : : "r" (val), "r" (address));
568 asm ("sthi.q %1, 7, %0" : : "r" (val), "r" (address));
569 break;
570
571 default:
572 printk("Unexpected width_shift %d in misaligned_store, PC=%08lx\n",
573 width_shift, (unsigned long) regs->pc);
574 break;
575 }
576 }
577
578 return 0;
579
580 }
581
582 #if defined(CONFIG_SH64_USER_MISALIGNED_FIXUP)
583 /* Never need to fix up misaligned FPU accesses within the kernel since that's a real
584 error. */
585 static int misaligned_fpu_load(struct pt_regs *regs,
586 __u32 opcode,
587 int displacement_not_indexed,
588 int width_shift,
589 int do_paired_load)
590 {
591 /* Return -1 for a fault, 0 for OK */
592 int error;
593 int destreg;
594 __u64 address;
595
596 error = generate_and_check_address(regs, opcode,
597 displacement_not_indexed, width_shift, &address);
598 if (error < 0) {
599 return error;
600 }
601
602 destreg = (opcode >> 4) & 0x3f;
603 if (user_mode(regs)) {
604 __u64 buffer;
605 __u32 buflo, bufhi;
606
607 if (!access_ok(VERIFY_READ, (unsigned long) address, 1UL<<width_shift)) {
608 return -1;
609 }
610
611 if (__copy_user(&buffer, (const void *)(int)address, (1 << width_shift)) > 0) {
612 return -1; /* fault */
613 }
614 /* 'current' may be the current owner of the FPU state, so
615 context switch the registers into memory so they can be
616 indexed by register number. */
617 if (last_task_used_math == current) {
618 enable_fpu();
619 save_fpu(current, regs);
620 disable_fpu();
621 last_task_used_math = NULL;
622 regs->sr |= SR_FD;
623 }
624
625 buflo = *(__u32*) &buffer;
626 bufhi = *(1 + (__u32*) &buffer);
627
628 switch (width_shift) {
629 case 2:
630 current->thread.fpu.hard.fp_regs[destreg] = buflo;
631 break;
632 case 3:
633 if (do_paired_load) {
634 current->thread.fpu.hard.fp_regs[destreg] = buflo;
635 current->thread.fpu.hard.fp_regs[destreg+1] = bufhi;
636 } else {
637 #if defined(CONFIG_CPU_LITTLE_ENDIAN)
638 current->thread.fpu.hard.fp_regs[destreg] = bufhi;
639 current->thread.fpu.hard.fp_regs[destreg+1] = buflo;
640 #else
641 current->thread.fpu.hard.fp_regs[destreg] = buflo;
642 current->thread.fpu.hard.fp_regs[destreg+1] = bufhi;
643 #endif
644 }
645 break;
646 default:
647 printk("Unexpected width_shift %d in misaligned_fpu_load, PC=%08lx\n",
648 width_shift, (unsigned long) regs->pc);
649 break;
650 }
651 return 0;
652 } else {
653 die ("Misaligned FPU load inside kernel", regs, 0);
654 return -1;
655 }
656
657
658 }
659
660 static int misaligned_fpu_store(struct pt_regs *regs,
661 __u32 opcode,
662 int displacement_not_indexed,
663 int width_shift,
664 int do_paired_load)
665 {
666 /* Return -1 for a fault, 0 for OK */
667 int error;
668 int srcreg;
669 __u64 address;
670
671 error = generate_and_check_address(regs, opcode,
672 displacement_not_indexed, width_shift, &address);
673 if (error < 0) {
674 return error;
675 }
676
677 srcreg = (opcode >> 4) & 0x3f;
678 if (user_mode(regs)) {
679 __u64 buffer;
680 /* Initialise these to NaNs. */
681 __u32 buflo=0xffffffffUL, bufhi=0xffffffffUL;
682
683 if (!access_ok(VERIFY_WRITE, (unsigned long) address, 1UL<<width_shift)) {
684 return -1;
685 }
686
687 /* 'current' may be the current owner of the FPU state, so
688 context switch the registers into memory so they can be
689 indexed by register number. */
690 if (last_task_used_math == current) {
691 enable_fpu();
692 save_fpu(current, regs);
693 disable_fpu();
694 last_task_used_math = NULL;
695 regs->sr |= SR_FD;
696 }
697
698 switch (width_shift) {
699 case 2:
700 buflo = current->thread.fpu.hard.fp_regs[srcreg];
701 break;
702 case 3:
703 if (do_paired_load) {
704 buflo = current->thread.fpu.hard.fp_regs[srcreg];
705 bufhi = current->thread.fpu.hard.fp_regs[srcreg+1];
706 } else {
707 #if defined(CONFIG_CPU_LITTLE_ENDIAN)
708 bufhi = current->thread.fpu.hard.fp_regs[srcreg];
709 buflo = current->thread.fpu.hard.fp_regs[srcreg+1];
710 #else
711 buflo = current->thread.fpu.hard.fp_regs[srcreg];
712 bufhi = current->thread.fpu.hard.fp_regs[srcreg+1];
713 #endif
714 }
715 break;
716 default:
717 printk("Unexpected width_shift %d in misaligned_fpu_store, PC=%08lx\n",
718 width_shift, (unsigned long) regs->pc);
719 break;
720 }
721
722 *(__u32*) &buffer = buflo;
723 *(1 + (__u32*) &buffer) = bufhi;
724 if (__copy_user((void *)(int)address, &buffer, (1 << width_shift)) > 0) {
725 return -1; /* fault */
726 }
727 return 0;
728 } else {
729 die ("Misaligned FPU load inside kernel", regs, 0);
730 return -1;
731 }
732 }
733 #endif
734
735 static int misaligned_fixup(struct pt_regs *regs)
736 {
737 unsigned long opcode;
738 int error;
739 int major, minor;
740
741 #if !defined(CONFIG_SH64_USER_MISALIGNED_FIXUP)
742 /* Never fixup user mode misaligned accesses without this option enabled. */
743 return -1;
744 #else
745 if (!user_mode_unaligned_fixup_enable) return -1;
746 #endif
747
748 error = read_opcode(regs->pc, &opcode, user_mode(regs));
749 if (error < 0) {
750 return error;
751 }
752 major = (opcode >> 26) & 0x3f;
753 minor = (opcode >> 16) & 0xf;
754
755 #if defined(CONFIG_SH64_USER_MISALIGNED_FIXUP)
756 if (user_mode(regs) && (user_mode_unaligned_fixup_count > 0)) {
757 --user_mode_unaligned_fixup_count;
758 /* Only do 'count' worth of these reports, to remove a potential DoS against syslog */
759 printk("Fixing up unaligned userspace access in \"%s\" pid=%d pc=0x%08x ins=0x%08lx\n",
760 current->comm, task_pid_nr(current), (__u32)regs->pc, opcode);
761 } else
762 #endif
763 if (!user_mode(regs) && (kernel_mode_unaligned_fixup_count > 0)) {
764 --kernel_mode_unaligned_fixup_count;
765 if (in_interrupt()) {
766 printk("Fixing up unaligned kernelspace access in interrupt pc=0x%08x ins=0x%08lx\n",
767 (__u32)regs->pc, opcode);
768 } else {
769 printk("Fixing up unaligned kernelspace access in \"%s\" pid=%d pc=0x%08x ins=0x%08lx\n",
770 current->comm, task_pid_nr(current), (__u32)regs->pc, opcode);
771 }
772 }
773
774
775 switch (major) {
776 case (0x84>>2): /* LD.W */
777 error = misaligned_load(regs, opcode, 1, 1, 1);
778 break;
779 case (0xb0>>2): /* LD.UW */
780 error = misaligned_load(regs, opcode, 1, 1, 0);
781 break;
782 case (0x88>>2): /* LD.L */
783 error = misaligned_load(regs, opcode, 1, 2, 1);
784 break;
785 case (0x8c>>2): /* LD.Q */
786 error = misaligned_load(regs, opcode, 1, 3, 0);
787 break;
788
789 case (0xa4>>2): /* ST.W */
790 error = misaligned_store(regs, opcode, 1, 1);
791 break;
792 case (0xa8>>2): /* ST.L */
793 error = misaligned_store(regs, opcode, 1, 2);
794 break;
795 case (0xac>>2): /* ST.Q */
796 error = misaligned_store(regs, opcode, 1, 3);
797 break;
798
799 case (0x40>>2): /* indexed loads */
800 switch (minor) {
801 case 0x1: /* LDX.W */
802 error = misaligned_load(regs, opcode, 0, 1, 1);
803 break;
804 case 0x5: /* LDX.UW */
805 error = misaligned_load(regs, opcode, 0, 1, 0);
806 break;
807 case 0x2: /* LDX.L */
808 error = misaligned_load(regs, opcode, 0, 2, 1);
809 break;
810 case 0x3: /* LDX.Q */
811 error = misaligned_load(regs, opcode, 0, 3, 0);
812 break;
813 default:
814 error = -1;
815 break;
816 }
817 break;
818
819 case (0x60>>2): /* indexed stores */
820 switch (minor) {
821 case 0x1: /* STX.W */
822 error = misaligned_store(regs, opcode, 0, 1);
823 break;
824 case 0x2: /* STX.L */
825 error = misaligned_store(regs, opcode, 0, 2);
826 break;
827 case 0x3: /* STX.Q */
828 error = misaligned_store(regs, opcode, 0, 3);
829 break;
830 default:
831 error = -1;
832 break;
833 }
834 break;
835
836 #if defined(CONFIG_SH64_USER_MISALIGNED_FIXUP)
837 case (0x94>>2): /* FLD.S */
838 error = misaligned_fpu_load(regs, opcode, 1, 2, 0);
839 break;
840 case (0x98>>2): /* FLD.P */
841 error = misaligned_fpu_load(regs, opcode, 1, 3, 1);
842 break;
843 case (0x9c>>2): /* FLD.D */
844 error = misaligned_fpu_load(regs, opcode, 1, 3, 0);
845 break;
846 case (0x1c>>2): /* floating indexed loads */
847 switch (minor) {
848 case 0x8: /* FLDX.S */
849 error = misaligned_fpu_load(regs, opcode, 0, 2, 0);
850 break;
851 case 0xd: /* FLDX.P */
852 error = misaligned_fpu_load(regs, opcode, 0, 3, 1);
853 break;
854 case 0x9: /* FLDX.D */
855 error = misaligned_fpu_load(regs, opcode, 0, 3, 0);
856 break;
857 default:
858 error = -1;
859 break;
860 }
861 break;
862 case (0xb4>>2): /* FLD.S */
863 error = misaligned_fpu_store(regs, opcode, 1, 2, 0);
864 break;
865 case (0xb8>>2): /* FLD.P */
866 error = misaligned_fpu_store(regs, opcode, 1, 3, 1);
867 break;
868 case (0xbc>>2): /* FLD.D */
869 error = misaligned_fpu_store(regs, opcode, 1, 3, 0);
870 break;
871 case (0x3c>>2): /* floating indexed stores */
872 switch (minor) {
873 case 0x8: /* FSTX.S */
874 error = misaligned_fpu_store(regs, opcode, 0, 2, 0);
875 break;
876 case 0xd: /* FSTX.P */
877 error = misaligned_fpu_store(regs, opcode, 0, 3, 1);
878 break;
879 case 0x9: /* FSTX.D */
880 error = misaligned_fpu_store(regs, opcode, 0, 3, 0);
881 break;
882 default:
883 error = -1;
884 break;
885 }
886 break;
887 #endif
888
889 default:
890 /* Fault */
891 error = -1;
892 break;
893 }
894
895 if (error < 0) {
896 return error;
897 } else {
898 regs->pc += 4; /* Skip the instruction that's just been emulated */
899 return 0;
900 }
901
902 }
903
904 static ctl_table unaligned_table[] = {
905 {
906 .ctl_name = CTL_UNNUMBERED,
907 .procname = "kernel_reports",
908 .data = &kernel_mode_unaligned_fixup_count,
909 .maxlen = sizeof(int),
910 .mode = 0644,
911 .proc_handler = &proc_dointvec
912 },
913 #if defined(CONFIG_SH64_USER_MISALIGNED_FIXUP)
914 {
915 .ctl_name = CTL_UNNUMBERED,
916 .procname = "user_reports",
917 .data = &user_mode_unaligned_fixup_count,
918 .maxlen = sizeof(int),
919 .mode = 0644,
920 .proc_handler = &proc_dointvec
921 },
922 {
923 .ctl_name = CTL_UNNUMBERED,
924 .procname = "user_enable",
925 .data = &user_mode_unaligned_fixup_enable,
926 .maxlen = sizeof(int),
927 .mode = 0644,
928 .proc_handler = &proc_dointvec},
929 #endif
930 {}
931 };
932
933 static ctl_table unaligned_root[] = {
934 {
935 .ctl_name = CTL_UNNUMBERED,
936 .procname = "unaligned_fixup",
937 .mode = 0555,
938 unaligned_table
939 },
940 {}
941 };
942
943 static ctl_table sh64_root[] = {
944 {
945 .ctl_name = CTL_UNNUMBERED,
946 .procname = "sh64",
947 .mode = 0555,
948 .child = unaligned_root
949 },
950 {}
951 };
952 static struct ctl_table_header *sysctl_header;
953 static int __init init_sysctl(void)
954 {
955 sysctl_header = register_sysctl_table(sh64_root);
956 return 0;
957 }
958
959 __initcall(init_sysctl);
960
961
962 asmlinkage void do_debug_interrupt(unsigned long code, struct pt_regs *regs)
963 {
964 u64 peek_real_address_q(u64 addr);
965 u64 poke_real_address_q(u64 addr, u64 val);
966 unsigned long long DM_EXP_CAUSE_PHY = 0x0c100010;
967 unsigned long long exp_cause;
968 /* It's not worth ioremapping the debug module registers for the amount
969 of access we make to them - just go direct to their physical
970 addresses. */
971 exp_cause = peek_real_address_q(DM_EXP_CAUSE_PHY);
972 if (exp_cause & ~4) {
973 printk("DM.EXP_CAUSE had unexpected bits set (=%08lx)\n",
974 (unsigned long)(exp_cause & 0xffffffff));
975 }
976 show_state();
977 /* Clear all DEBUGINT causes */
978 poke_real_address_q(DM_EXP_CAUSE_PHY, 0x0);
979 }
WRT350N Kernel Patches