arch/sparc64/kernel/cpu.c

   1 /* cpu.c: Dinky routines to look for the kind of Sparc cpu
   2  *        we are on.
   3  *
   4  * Copyright (C) 1996, 2007 David S. Miller (davem@davemloft.net)
   5  */
   6
   7 #include <linux/kernel.h>
   8 #include <linux/init.h>
   9 #include <linux/sched.h>
  10 #include <linux/smp.h>
  11 #include <asm/asi.h>
  12 #include <asm/system.h>
  13 #include <asm/fpumacro.h>
  14 #include <asm/cpudata.h>
  15 #include <asm/spitfire.h>
  16 #include <asm/oplib.h>
  17
  18 DEFINE_PER_CPU(cpuinfo_sparc, __cpu_data) = { 0 };
  19
  20 struct cpu_iu_info {
  21   short manuf;
  22   short impl;
  23   char* cpu_name;   /* should be enough I hope... */
  24 };
  25
  26 struct cpu_fp_info {
  27   short manuf;
  28   short impl;
  29   char fpu_vers;
  30   char* fp_name;
  31 };
  32
  33 <<<<<<< HEAD:arch/sparc64/kernel/cpu.c
  34 struct cpu_fp_info linux_sparc_fpu[] = {
  35 =======
  36 static struct cpu_fp_info linux_sparc_fpu[] = {
  37 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/sparc64/kernel/cpu.c
  38   { 0x17, 0x10, 0, "UltraSparc I integrated FPU"},
  39   { 0x22, 0x10, 0, "UltraSparc I integrated FPU"},
  40   { 0x17, 0x11, 0, "UltraSparc II integrated FPU"},
  41   { 0x17, 0x12, 0, "UltraSparc IIi integrated FPU"},
  42   { 0x17, 0x13, 0, "UltraSparc IIe integrated FPU"},
  43   { 0x3e, 0x14, 0, "UltraSparc III integrated FPU"},
  44   { 0x3e, 0x15, 0, "UltraSparc III+ integrated FPU"},
  45   { 0x3e, 0x16, 0, "UltraSparc IIIi integrated FPU"},
  46   { 0x3e, 0x18, 0, "UltraSparc IV integrated FPU"},
  47   { 0x3e, 0x19, 0, "UltraSparc IV+ integrated FPU"},
  48   { 0x3e, 0x22, 0, "UltraSparc IIIi+ integrated FPU"},
  49 };
  50
  51 #define NSPARCFPU  ARRAY_SIZE(linux_sparc_fpu)
  52
  53 <<<<<<< HEAD:arch/sparc64/kernel/cpu.c
  54 struct cpu_iu_info linux_sparc_chips[] = {
  55 =======
  56 static struct cpu_iu_info linux_sparc_chips[] = {
  57 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/sparc64/kernel/cpu.c
  58   { 0x17, 0x10, "TI UltraSparc I   (SpitFire)"},
  59   { 0x22, 0x10, "TI UltraSparc I   (SpitFire)"},
  60   { 0x17, 0x11, "TI UltraSparc II  (BlackBird)"},
  61   { 0x17, 0x12, "TI UltraSparc IIi (Sabre)"},
  62   { 0x17, 0x13, "TI UltraSparc IIe (Hummingbird)"},
  63   { 0x3e, 0x14, "TI UltraSparc III (Cheetah)"},
  64   { 0x3e, 0x15, "TI UltraSparc III+ (Cheetah+)"},
  65   { 0x3e, 0x16, "TI UltraSparc IIIi (Jalapeno)"},
  66   { 0x3e, 0x18, "TI UltraSparc IV (Jaguar)"},
  67   { 0x3e, 0x19, "TI UltraSparc IV+ (Panther)"},
  68   { 0x3e, 0x22, "TI UltraSparc IIIi+ (Serrano)"},
  69 };
  70
  71 #define NSPARCCHIPS  ARRAY_SIZE(linux_sparc_chips)
  72
  73 char *sparc_cpu_type;
  74 char *sparc_fpu_type;
  75
  76 unsigned int fsr_storage;
  77
  78 static void __init sun4v_cpu_probe(void)
  79 {
  80         switch (sun4v_chip_type) {
  81         case SUN4V_CHIP_NIAGARA1:
  82                 sparc_cpu_type = "UltraSparc T1 (Niagara)";
  83                 sparc_fpu_type = "UltraSparc T1 integrated FPU";
  84                 break;
  85
  86         case SUN4V_CHIP_NIAGARA2:
  87                 sparc_cpu_type = "UltraSparc T2 (Niagara2)";
  88                 sparc_fpu_type = "UltraSparc T2 integrated FPU";
  89                 break;
  90
  91         default:
  92                 printk(KERN_WARNING "CPU: Unknown sun4v cpu type [%s]\n",
  93                        prom_cpu_compatible);
  94                 sparc_cpu_type = "Unknown SUN4V CPU";
  95                 sparc_fpu_type = "Unknown SUN4V FPU";
  96                 break;
  97         }
  98 }
  99
 100 void __init cpu_probe(void)
 101 {
 102         unsigned long ver, fpu_vers, manuf, impl, fprs;
 103         int i;
 104
 105         if (tlb_type == hypervisor)
 106                 return sun4v_cpu_probe();
 107
 108         fprs = fprs_read();
 109         fprs_write(FPRS_FEF);
 110         __asm__ __volatile__ ("rdpr %%ver, %0; stx %%fsr, [%1]"
 111                               : "=&r" (ver)
 112                               : "r" (&fpu_vers));
 113         fprs_write(fprs);
 114
 115         manuf = ((ver >> 48) & 0xffff);
 116         impl = ((ver >> 32) & 0xffff);
 117
 118         fpu_vers = ((fpu_vers >> 17) & 0x7);
 119
 120 retry:
 121         for (i = 0; i < NSPARCCHIPS; i++) {
 122                 if (linux_sparc_chips[i].manuf == manuf) {
 123                         if (linux_sparc_chips[i].impl == impl) {
 124                                 sparc_cpu_type =
 125                                         linux_sparc_chips[i].cpu_name;
 126                                 break;
 127                         }
 128                 }
 129         }
 130
 131         if (i == NSPARCCHIPS) {
 132                 /* Maybe it is a cheetah+ derivative, report it as cheetah+
 133                  * in that case until we learn the real names.
 134                  */
 135                 if (manuf == 0x3e &&
 136                     impl > 0x15) {
 137                         impl = 0x15;
 138                         goto retry;
 139                 } else {
 140                         printk("DEBUG: manuf[%lx] impl[%lx]\n",
 141                                manuf, impl);
 142                 }
 143                 sparc_cpu_type = "Unknown CPU";
 144         }
 145
 146         for (i = 0; i < NSPARCFPU; i++) {
 147                 if (linux_sparc_fpu[i].manuf == manuf &&
 148                     linux_sparc_fpu[i].impl == impl) {
 149                         if (linux_sparc_fpu[i].fpu_vers == fpu_vers) {
 150                                 sparc_fpu_type =
 151                                         linux_sparc_fpu[i].fp_name;
 152                                 break;
 153                         }
 154                 }
 155         }
 156
 157         if (i == NSPARCFPU) {
 158                 printk("DEBUG: manuf[%lx] impl[%lx] fsr.vers[%lx]\n",
 159                        manuf, impl, fpu_vers);
 160                 sparc_fpu_type = "Unknown FPU";
 161         }
 162 }