arch/x86/kernel/cpu/mtrr/state.c

   1 #include <linux/mm.h>
   2 #include <linux/init.h>
   3 #include <asm/io.h>
   4 #include <asm/mtrr.h>
   5 #include <asm/msr.h>
   6 #include <asm/processor-cyrix.h>
   7 #include <asm/processor-flags.h>
   8 #include "mtrr.h"
   9
  10
  11 /*  Put the processor into a state where MTRRs can be safely set  */
  12 void set_mtrr_prepare_save(struct set_mtrr_context *ctxt)
  13 {
  14         unsigned int cr0;
  15
  16         /*  Disable interrupts locally  */
  17         local_irq_save(ctxt->flags);
  18
  19         if (use_intel() || is_cpu(CYRIX)) {
  20
  21                 /*  Save value of CR4 and clear Page Global Enable (bit 7)  */
  22                 if ( cpu_has_pge ) {
  23                         ctxt->cr4val = read_cr4();
  24                         write_cr4(ctxt->cr4val & ~X86_CR4_PGE);
  25                 }
  26
  27                 /*  Disable and flush caches. Note that wbinvd flushes the TLBs as
  28                     a side-effect  */
  29                 cr0 = read_cr0() | X86_CR0_CD;
  30                 wbinvd();
  31                 write_cr0(cr0);
  32                 wbinvd();
  33
  34                 if (use_intel())
  35                         /*  Save MTRR state */
  36                         rdmsr(MTRRdefType_MSR, ctxt->deftype_lo, ctxt->deftype_hi);
  37                 else
  38                         /* Cyrix ARRs - everything else were excluded at the top */
  39                         ctxt->ccr3 = getCx86(CX86_CCR3);
  40         }
  41 }
  42
  43 void set_mtrr_cache_disable(struct set_mtrr_context *ctxt)
  44 {
  45         if (use_intel())
  46                 /*  Disable MTRRs, and set the default type to uncached  */
  47                 mtrr_wrmsr(MTRRdefType_MSR, ctxt->deftype_lo & 0xf300UL,
  48                       ctxt->deftype_hi);
  49         else if (is_cpu(CYRIX))
  50                 /* Cyrix ARRs - everything else were excluded at the top */
  51                 setCx86(CX86_CCR3, (ctxt->ccr3 & 0x0f) | 0x10);
  52 }
  53
  54 /*  Restore the processor after a set_mtrr_prepare  */
  55 void set_mtrr_done(struct set_mtrr_context *ctxt)
  56 {
  57         if (use_intel() || is_cpu(CYRIX)) {
  58
  59                 /*  Flush caches and TLBs  */
  60                 wbinvd();
  61
  62                 /*  Restore MTRRdefType  */
  63                 if (use_intel())
  64                         /* Intel (P6) standard MTRRs */
  65                         mtrr_wrmsr(MTRRdefType_MSR, ctxt->deftype_lo, ctxt->deftype_hi);
  66                 else
  67                         /* Cyrix ARRs - everything else was excluded at the top */
  68                         setCx86(CX86_CCR3, ctxt->ccr3);
  69
  70                 /*  Enable caches  */
  71                 write_cr0(read_cr0() & 0xbfffffff);
  72
  73                 /*  Restore value of CR4  */
  74                 if ( cpu_has_pge )
  75                         write_cr4(ctxt->cr4val);
  76         }
  77         /*  Re-enable interrupts locally (if enabled previously)  */
  78         local_irq_restore(ctxt->flags);
  79 }
  80