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Merge git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
[wrt350n-kernel.git] / arch / x86 / kernel / io_apic_64.c
blob1627c0d53e0b4f63b927184d40e56145d0012e38
1 /*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
22
23 #include <linux/mm.h>
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/acpi.h>
31 #include <linux/sysdev.h>
32 #include <linux/msi.h>
33 #include <linux/htirq.h>
34 #include <linux/dmar.h>
35 #include <linux/jiffies.h>
36 #ifdef CONFIG_ACPI
37 #include <acpi/acpi_bus.h>
38 #endif
39 #include <linux/bootmem.h>
40
41 #include <asm/idle.h>
42 #include <asm/io.h>
43 #include <asm/smp.h>
44 #include <asm/desc.h>
45 #include <asm/proto.h>
46 #include <asm/mach_apic.h>
47 #include <asm/acpi.h>
48 #include <asm/dma.h>
49 #include <asm/nmi.h>
50 #include <asm/msidef.h>
51 #include <asm/hypertransport.h>
52
53 struct irq_cfg {
54 cpumask_t domain;
55 cpumask_t old_domain;
56 unsigned move_cleanup_count;
57 u8 vector;
58 u8 move_in_progress : 1;
59 };
60
61 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
62 struct irq_cfg irq_cfg[NR_IRQS] __read_mostly = {
63 [0] = { .domain = CPU_MASK_ALL, .vector = IRQ0_VECTOR, },
64 [1] = { .domain = CPU_MASK_ALL, .vector = IRQ1_VECTOR, },
65 [2] = { .domain = CPU_MASK_ALL, .vector = IRQ2_VECTOR, },
66 [3] = { .domain = CPU_MASK_ALL, .vector = IRQ3_VECTOR, },
67 [4] = { .domain = CPU_MASK_ALL, .vector = IRQ4_VECTOR, },
68 [5] = { .domain = CPU_MASK_ALL, .vector = IRQ5_VECTOR, },
69 [6] = { .domain = CPU_MASK_ALL, .vector = IRQ6_VECTOR, },
70 [7] = { .domain = CPU_MASK_ALL, .vector = IRQ7_VECTOR, },
71 [8] = { .domain = CPU_MASK_ALL, .vector = IRQ8_VECTOR, },
72 [9] = { .domain = CPU_MASK_ALL, .vector = IRQ9_VECTOR, },
73 [10] = { .domain = CPU_MASK_ALL, .vector = IRQ10_VECTOR, },
74 [11] = { .domain = CPU_MASK_ALL, .vector = IRQ11_VECTOR, },
75 [12] = { .domain = CPU_MASK_ALL, .vector = IRQ12_VECTOR, },
76 [13] = { .domain = CPU_MASK_ALL, .vector = IRQ13_VECTOR, },
77 [14] = { .domain = CPU_MASK_ALL, .vector = IRQ14_VECTOR, },
78 [15] = { .domain = CPU_MASK_ALL, .vector = IRQ15_VECTOR, },
79 };
80
81 static int assign_irq_vector(int irq, cpumask_t mask);
82
83 #define __apicdebuginit __init
84
85 int sis_apic_bug; /* not actually supported, dummy for compile */
86
87 static int no_timer_check;
88
89 static int disable_timer_pin_1 __initdata;
90
91 int timer_over_8254 __initdata = 1;
92
93 /* Where if anywhere is the i8259 connect in external int mode */
94 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
95
96 static DEFINE_SPINLOCK(ioapic_lock);
97 DEFINE_SPINLOCK(vector_lock);
98
99 /*
100 * # of IRQ routing registers
101 */
102 int nr_ioapic_registers[MAX_IO_APICS];
103
104 /*
105 * Rough estimation of how many shared IRQs there are, can
106 * be changed anytime.
107 */
108 #define MAX_PLUS_SHARED_IRQS NR_IRQS
109 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
110
111 /*
112 * This is performance-critical, we want to do it O(1)
113 *
114 * the indexing order of this array favors 1:1 mappings
115 * between pins and IRQs.
116 */
117
118 static struct irq_pin_list {
119 short apic, pin, next;
120 } irq_2_pin[PIN_MAP_SIZE];
121
122 struct io_apic {
123 unsigned int index;
124 unsigned int unused[3];
125 unsigned int data;
126 };
127
128 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
129 {
130 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
131 + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK);
132 }
133
134 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
135 {
136 struct io_apic __iomem *io_apic = io_apic_base(apic);
137 writel(reg, &io_apic->index);
138 return readl(&io_apic->data);
139 }
140
141 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
142 {
143 struct io_apic __iomem *io_apic = io_apic_base(apic);
144 writel(reg, &io_apic->index);
145 writel(value, &io_apic->data);
146 }
147
148 /*
149 * Re-write a value: to be used for read-modify-write
150 * cycles where the read already set up the index register.
151 */
152 static inline void io_apic_modify(unsigned int apic, unsigned int value)
153 {
154 struct io_apic __iomem *io_apic = io_apic_base(apic);
155 writel(value, &io_apic->data);
156 }
157
158 static int io_apic_level_ack_pending(unsigned int irq)
159 {
160 struct irq_pin_list *entry;
161 unsigned long flags;
162 int pending = 0;
163
164 spin_lock_irqsave(&ioapic_lock, flags);
165 entry = irq_2_pin + irq;
166 for (;;) {
167 unsigned int reg;
168 int pin;
169
170 pin = entry->pin;
171 if (pin == -1)
172 break;
173 reg = io_apic_read(entry->apic, 0x10 + pin*2);
174 /* Is the remote IRR bit set? */
175 pending |= (reg >> 14) & 1;
176 if (!entry->next)
177 break;
178 entry = irq_2_pin + entry->next;
179 }
180 spin_unlock_irqrestore(&ioapic_lock, flags);
181 return pending;
182 }
183
184 /*
185 * Synchronize the IO-APIC and the CPU by doing
186 * a dummy read from the IO-APIC
187 */
188 static inline void io_apic_sync(unsigned int apic)
189 {
190 struct io_apic __iomem *io_apic = io_apic_base(apic);
191 readl(&io_apic->data);
192 }
193
194 #define __DO_ACTION(R, ACTION, FINAL) \
195 \
196 { \
197 int pin; \
198 struct irq_pin_list *entry = irq_2_pin + irq; \
199 \
200 BUG_ON(irq >= NR_IRQS); \
201 for (;;) { \
202 unsigned int reg; \
203 pin = entry->pin; \
204 if (pin == -1) \
205 break; \
206 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
207 reg ACTION; \
208 io_apic_modify(entry->apic, reg); \
209 FINAL; \
210 if (!entry->next) \
211 break; \
212 entry = irq_2_pin + entry->next; \
213 } \
214 }
215
216 union entry_union {
217 struct { u32 w1, w2; };
218 struct IO_APIC_route_entry entry;
219 };
220
221 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
222 {
223 union entry_union eu;
224 unsigned long flags;
225 spin_lock_irqsave(&ioapic_lock, flags);
226 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
227 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
228 spin_unlock_irqrestore(&ioapic_lock, flags);
229 return eu.entry;
230 }
231
232 /*
233 * When we write a new IO APIC routing entry, we need to write the high
234 * word first! If the mask bit in the low word is clear, we will enable
235 * the interrupt, and we need to make sure the entry is fully populated
236 * before that happens.
237 */
238 static void
239 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
240 {
241 union entry_union eu;
242 eu.entry = e;
243 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
244 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
245 }
246
247 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
248 {
249 unsigned long flags;
250 spin_lock_irqsave(&ioapic_lock, flags);
251 __ioapic_write_entry(apic, pin, e);
252 spin_unlock_irqrestore(&ioapic_lock, flags);
253 }
254
255 /*
256 * When we mask an IO APIC routing entry, we need to write the low
257 * word first, in order to set the mask bit before we change the
258 * high bits!
259 */
260 static void ioapic_mask_entry(int apic, int pin)
261 {
262 unsigned long flags;
263 union entry_union eu = { .entry.mask = 1 };
264
265 spin_lock_irqsave(&ioapic_lock, flags);
266 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
267 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
268 spin_unlock_irqrestore(&ioapic_lock, flags);
269 }
270
271 #ifdef CONFIG_SMP
272 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector)
273 {
274 int apic, pin;
275 struct irq_pin_list *entry = irq_2_pin + irq;
276
277 BUG_ON(irq >= NR_IRQS);
278 for (;;) {
279 unsigned int reg;
280 apic = entry->apic;
281 pin = entry->pin;
282 if (pin == -1)
283 break;
284 io_apic_write(apic, 0x11 + pin*2, dest);
285 reg = io_apic_read(apic, 0x10 + pin*2);
286 reg &= ~0x000000ff;
287 reg |= vector;
288 io_apic_modify(apic, reg);
289 if (!entry->next)
290 break;
291 entry = irq_2_pin + entry->next;
292 }
293 }
294
295 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
296 {
297 struct irq_cfg *cfg = irq_cfg + irq;
298 unsigned long flags;
299 unsigned int dest;
300 cpumask_t tmp;
301
302 cpus_and(tmp, mask, cpu_online_map);
303 if (cpus_empty(tmp))
304 return;
305
306 if (assign_irq_vector(irq, mask))
307 return;
308
309 cpus_and(tmp, cfg->domain, mask);
310 dest = cpu_mask_to_apicid(tmp);
311
312 /*
313 * Only the high 8 bits are valid.
314 */
315 dest = SET_APIC_LOGICAL_ID(dest);
316
317 spin_lock_irqsave(&ioapic_lock, flags);
318 __target_IO_APIC_irq(irq, dest, cfg->vector);
319 irq_desc[irq].affinity = mask;
320 spin_unlock_irqrestore(&ioapic_lock, flags);
321 }
322 #endif
323
324 /*
325 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
326 * shared ISA-space IRQs, so we have to support them. We are super
327 * fast in the common case, and fast for shared ISA-space IRQs.
328 */
329 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
330 {
331 static int first_free_entry = NR_IRQS;
332 struct irq_pin_list *entry = irq_2_pin + irq;
333
334 BUG_ON(irq >= NR_IRQS);
335 while (entry->next)
336 entry = irq_2_pin + entry->next;
337
338 if (entry->pin != -1) {
339 entry->next = first_free_entry;
340 entry = irq_2_pin + entry->next;
341 if (++first_free_entry >= PIN_MAP_SIZE)
342 panic("io_apic.c: ran out of irq_2_pin entries!");
343 }
344 entry->apic = apic;
345 entry->pin = pin;
346 }
347
348
349 #define DO_ACTION(name,R,ACTION, FINAL) \
350 \
351 static void name##_IO_APIC_irq (unsigned int irq) \
352 __DO_ACTION(R, ACTION, FINAL)
353
354 DO_ACTION( __mask, 0, |= 0x00010000, io_apic_sync(entry->apic) )
355 /* mask = 1 */
356 DO_ACTION( __unmask, 0, &= 0xfffeffff, )
357 /* mask = 0 */
358
359 static void mask_IO_APIC_irq (unsigned int irq)
360 {
361 unsigned long flags;
362
363 spin_lock_irqsave(&ioapic_lock, flags);
364 __mask_IO_APIC_irq(irq);
365 spin_unlock_irqrestore(&ioapic_lock, flags);
366 }
367
368 static void unmask_IO_APIC_irq (unsigned int irq)
369 {
370 unsigned long flags;
371
372 spin_lock_irqsave(&ioapic_lock, flags);
373 __unmask_IO_APIC_irq(irq);
374 spin_unlock_irqrestore(&ioapic_lock, flags);
375 }
376
377 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
378 {
379 struct IO_APIC_route_entry entry;
380
381 /* Check delivery_mode to be sure we're not clearing an SMI pin */
382 entry = ioapic_read_entry(apic, pin);
383 if (entry.delivery_mode == dest_SMI)
384 return;
385 /*
386 * Disable it in the IO-APIC irq-routing table:
387 */
388 ioapic_mask_entry(apic, pin);
389 }
390
391 static void clear_IO_APIC (void)
392 {
393 int apic, pin;
394
395 for (apic = 0; apic < nr_ioapics; apic++)
396 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
397 clear_IO_APIC_pin(apic, pin);
398 }
399
400 int skip_ioapic_setup;
401 int ioapic_force;
402
403 static int __init parse_noapic(char *str)
404 {
405 disable_ioapic_setup();
406 return 0;
407 }
408 early_param("noapic", parse_noapic);
409
410 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
411 static int __init disable_timer_pin_setup(char *arg)
412 {
413 disable_timer_pin_1 = 1;
414 return 1;
415 }
416 __setup("disable_timer_pin_1", disable_timer_pin_setup);
417
418 static int __init setup_disable_8254_timer(char *s)
419 {
420 timer_over_8254 = -1;
421 return 1;
422 }
423 static int __init setup_enable_8254_timer(char *s)
424 {
425 timer_over_8254 = 2;
426 return 1;
427 }
428
429 __setup("disable_8254_timer", setup_disable_8254_timer);
430 __setup("enable_8254_timer", setup_enable_8254_timer);
431
432
433 /*
434 * Find the IRQ entry number of a certain pin.
435 */
436 static int find_irq_entry(int apic, int pin, int type)
437 {
438 int i;
439
440 for (i = 0; i < mp_irq_entries; i++)
441 if (mp_irqs[i].mpc_irqtype == type &&
442 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
443 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
444 mp_irqs[i].mpc_dstirq == pin)
445 return i;
446
447 return -1;
448 }
449
450 /*
451 * Find the pin to which IRQ[irq] (ISA) is connected
452 */
453 static int __init find_isa_irq_pin(int irq, int type)
454 {
455 int i;
456
457 for (i = 0; i < mp_irq_entries; i++) {
458 int lbus = mp_irqs[i].mpc_srcbus;
459
460 if (test_bit(lbus, mp_bus_not_pci) &&
461 (mp_irqs[i].mpc_irqtype == type) &&
462 (mp_irqs[i].mpc_srcbusirq == irq))
463
464 return mp_irqs[i].mpc_dstirq;
465 }
466 return -1;
467 }
468
469 static int __init find_isa_irq_apic(int irq, int type)
470 {
471 int i;
472
473 for (i = 0; i < mp_irq_entries; i++) {
474 int lbus = mp_irqs[i].mpc_srcbus;
475
476 if (test_bit(lbus, mp_bus_not_pci) &&
477 (mp_irqs[i].mpc_irqtype == type) &&
478 (mp_irqs[i].mpc_srcbusirq == irq))
479 break;
480 }
481 if (i < mp_irq_entries) {
482 int apic;
483 for(apic = 0; apic < nr_ioapics; apic++) {
484 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
485 return apic;
486 }
487 }
488
489 return -1;
490 }
491
492 /*
493 * Find a specific PCI IRQ entry.
494 * Not an __init, possibly needed by modules
495 */
496 static int pin_2_irq(int idx, int apic, int pin);
497
498 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
499 {
500 int apic, i, best_guess = -1;
501
502 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
503 bus, slot, pin);
504 if (mp_bus_id_to_pci_bus[bus] == -1) {
505 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
506 return -1;
507 }
508 for (i = 0; i < mp_irq_entries; i++) {
509 int lbus = mp_irqs[i].mpc_srcbus;
510
511 for (apic = 0; apic < nr_ioapics; apic++)
512 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
513 mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
514 break;
515
516 if (!test_bit(lbus, mp_bus_not_pci) &&
517 !mp_irqs[i].mpc_irqtype &&
518 (bus == lbus) &&
519 (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
520 int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
521
522 if (!(apic || IO_APIC_IRQ(irq)))
523 continue;
524
525 if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
526 return irq;
527 /*
528 * Use the first all-but-pin matching entry as a
529 * best-guess fuzzy result for broken mptables.
530 */
531 if (best_guess < 0)
532 best_guess = irq;
533 }
534 }
535 BUG_ON(best_guess >= NR_IRQS);
536 return best_guess;
537 }
538
539 /* ISA interrupts are always polarity zero edge triggered,
540 * when listed as conforming in the MP table. */
541
542 #define default_ISA_trigger(idx) (0)
543 #define default_ISA_polarity(idx) (0)
544
545 /* PCI interrupts are always polarity one level triggered,
546 * when listed as conforming in the MP table. */
547
548 #define default_PCI_trigger(idx) (1)
549 #define default_PCI_polarity(idx) (1)
550
551 static int MPBIOS_polarity(int idx)
552 {
553 int bus = mp_irqs[idx].mpc_srcbus;
554 int polarity;
555
556 /*
557 * Determine IRQ line polarity (high active or low active):
558 */
559 switch (mp_irqs[idx].mpc_irqflag & 3)
560 {
561 case 0: /* conforms, ie. bus-type dependent polarity */
562 if (test_bit(bus, mp_bus_not_pci))
563 polarity = default_ISA_polarity(idx);
564 else
565 polarity = default_PCI_polarity(idx);
566 break;
567 case 1: /* high active */
568 {
569 polarity = 0;
570 break;
571 }
572 case 2: /* reserved */
573 {
574 printk(KERN_WARNING "broken BIOS!!\n");
575 polarity = 1;
576 break;
577 }
578 case 3: /* low active */
579 {
580 polarity = 1;
581 break;
582 }
583 default: /* invalid */
584 {
585 printk(KERN_WARNING "broken BIOS!!\n");
586 polarity = 1;
587 break;
588 }
589 }
590 return polarity;
591 }
592
593 static int MPBIOS_trigger(int idx)
594 {
595 int bus = mp_irqs[idx].mpc_srcbus;
596 int trigger;
597
598 /*
599 * Determine IRQ trigger mode (edge or level sensitive):
600 */
601 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
602 {
603 case 0: /* conforms, ie. bus-type dependent */
604 if (test_bit(bus, mp_bus_not_pci))
605 trigger = default_ISA_trigger(idx);
606 else
607 trigger = default_PCI_trigger(idx);
608 break;
609 case 1: /* edge */
610 {
611 trigger = 0;
612 break;
613 }
614 case 2: /* reserved */
615 {
616 printk(KERN_WARNING "broken BIOS!!\n");
617 trigger = 1;
618 break;
619 }
620 case 3: /* level */
621 {
622 trigger = 1;
623 break;
624 }
625 default: /* invalid */
626 {
627 printk(KERN_WARNING "broken BIOS!!\n");
628 trigger = 0;
629 break;
630 }
631 }
632 return trigger;
633 }
634
635 static inline int irq_polarity(int idx)
636 {
637 return MPBIOS_polarity(idx);
638 }
639
640 static inline int irq_trigger(int idx)
641 {
642 return MPBIOS_trigger(idx);
643 }
644
645 static int pin_2_irq(int idx, int apic, int pin)
646 {
647 int irq, i;
648 int bus = mp_irqs[idx].mpc_srcbus;
649
650 /*
651 * Debugging check, we are in big trouble if this message pops up!
652 */
653 if (mp_irqs[idx].mpc_dstirq != pin)
654 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
655
656 if (test_bit(bus, mp_bus_not_pci)) {
657 irq = mp_irqs[idx].mpc_srcbusirq;
658 } else {
659 /*
660 * PCI IRQs are mapped in order
661 */
662 i = irq = 0;
663 while (i < apic)
664 irq += nr_ioapic_registers[i++];
665 irq += pin;
666 }
667 BUG_ON(irq >= NR_IRQS);
668 return irq;
669 }
670
671 static int __assign_irq_vector(int irq, cpumask_t mask)
672 {
673 /*
674 * NOTE! The local APIC isn't very good at handling
675 * multiple interrupts at the same interrupt level.
676 * As the interrupt level is determined by taking the
677 * vector number and shifting that right by 4, we
678 * want to spread these out a bit so that they don't
679 * all fall in the same interrupt level.
680 *
681 * Also, we've got to be careful not to trash gate
682 * 0x80, because int 0x80 is hm, kind of importantish. ;)
683 */
684 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
685 unsigned int old_vector;
686 int cpu;
687 struct irq_cfg *cfg;
688
689 BUG_ON((unsigned)irq >= NR_IRQS);
690 cfg = &irq_cfg[irq];
691
692 /* Only try and allocate irqs on cpus that are present */
693 cpus_and(mask, mask, cpu_online_map);
694
695 if ((cfg->move_in_progress) || cfg->move_cleanup_count)
696 return -EBUSY;
697
698 old_vector = cfg->vector;
699 if (old_vector) {
700 cpumask_t tmp;
701 cpus_and(tmp, cfg->domain, mask);
702 if (!cpus_empty(tmp))
703 return 0;
704 }
705
706 for_each_cpu_mask(cpu, mask) {
707 cpumask_t domain, new_mask;
708 int new_cpu;
709 int vector, offset;
710
711 domain = vector_allocation_domain(cpu);
712 cpus_and(new_mask, domain, cpu_online_map);
713
714 vector = current_vector;
715 offset = current_offset;
716 next:
717 vector += 8;
718 if (vector >= FIRST_SYSTEM_VECTOR) {
719 /* If we run out of vectors on large boxen, must share them. */
720 offset = (offset + 1) % 8;
721 vector = FIRST_DEVICE_VECTOR + offset;
722 }
723 if (unlikely(current_vector == vector))
724 continue;
725 if (vector == IA32_SYSCALL_VECTOR)
726 goto next;
727 for_each_cpu_mask(new_cpu, new_mask)
728 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
729 goto next;
730 /* Found one! */
731 current_vector = vector;
732 current_offset = offset;
733 if (old_vector) {
734 cfg->move_in_progress = 1;
735 cfg->old_domain = cfg->domain;
736 }
737 for_each_cpu_mask(new_cpu, new_mask)
738 per_cpu(vector_irq, new_cpu)[vector] = irq;
739 cfg->vector = vector;
740 cfg->domain = domain;
741 return 0;
742 }
743 return -ENOSPC;
744 }
745
746 static int assign_irq_vector(int irq, cpumask_t mask)
747 {
748 int err;
749 unsigned long flags;
750
751 spin_lock_irqsave(&vector_lock, flags);
752 err = __assign_irq_vector(irq, mask);
753 spin_unlock_irqrestore(&vector_lock, flags);
754 return err;
755 }
756
757 static void __clear_irq_vector(int irq)
758 {
759 struct irq_cfg *cfg;
760 cpumask_t mask;
761 int cpu, vector;
762
763 BUG_ON((unsigned)irq >= NR_IRQS);
764 cfg = &irq_cfg[irq];
765 BUG_ON(!cfg->vector);
766
767 vector = cfg->vector;
768 cpus_and(mask, cfg->domain, cpu_online_map);
769 for_each_cpu_mask(cpu, mask)
770 per_cpu(vector_irq, cpu)[vector] = -1;
771
772 cfg->vector = 0;
773 cfg->domain = CPU_MASK_NONE;
774 }
775
776 void __setup_vector_irq(int cpu)
777 {
778 /* Initialize vector_irq on a new cpu */
779 /* This function must be called with vector_lock held */
780 int irq, vector;
781
782 /* Mark the inuse vectors */
783 for (irq = 0; irq < NR_IRQS; ++irq) {
784 if (!cpu_isset(cpu, irq_cfg[irq].domain))
785 continue;
786 vector = irq_cfg[irq].vector;
787 per_cpu(vector_irq, cpu)[vector] = irq;
788 }
789 /* Mark the free vectors */
790 for (vector = 0; vector < NR_VECTORS; ++vector) {
791 irq = per_cpu(vector_irq, cpu)[vector];
792 if (irq < 0)
793 continue;
794 if (!cpu_isset(cpu, irq_cfg[irq].domain))
795 per_cpu(vector_irq, cpu)[vector] = -1;
796 }
797 }
798
799
800 static struct irq_chip ioapic_chip;
801
802 static void ioapic_register_intr(int irq, unsigned long trigger)
803 {
804 if (trigger) {
805 irq_desc[irq].status |= IRQ_LEVEL;
806 set_irq_chip_and_handler_name(irq, &ioapic_chip,
807 handle_fasteoi_irq, "fasteoi");
808 } else {
809 irq_desc[irq].status &= ~IRQ_LEVEL;
810 set_irq_chip_and_handler_name(irq, &ioapic_chip,
811 handle_edge_irq, "edge");
812 }
813 }
814
815 static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq,
816 int trigger, int polarity)
817 {
818 struct irq_cfg *cfg = irq_cfg + irq;
819 struct IO_APIC_route_entry entry;
820 cpumask_t mask;
821
822 if (!IO_APIC_IRQ(irq))
823 return;
824
825 mask = TARGET_CPUS;
826 if (assign_irq_vector(irq, mask))
827 return;
828
829 cpus_and(mask, cfg->domain, mask);
830
831 apic_printk(APIC_VERBOSE,KERN_DEBUG
832 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
833 "IRQ %d Mode:%i Active:%i)\n",
834 apic, mp_ioapics[apic].mpc_apicid, pin, cfg->vector,
835 irq, trigger, polarity);
836
837 /*
838 * add it to the IO-APIC irq-routing table:
839 */
840 memset(&entry,0,sizeof(entry));
841
842 entry.delivery_mode = INT_DELIVERY_MODE;
843 entry.dest_mode = INT_DEST_MODE;
844 entry.dest = cpu_mask_to_apicid(mask);
845 entry.mask = 0; /* enable IRQ */
846 entry.trigger = trigger;
847 entry.polarity = polarity;
848 entry.vector = cfg->vector;
849
850 /* Mask level triggered irqs.
851 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
852 */
853 if (trigger)
854 entry.mask = 1;
855
856 ioapic_register_intr(irq, trigger);
857 if (irq < 16)
858 disable_8259A_irq(irq);
859
860 ioapic_write_entry(apic, pin, entry);
861 }
862
863 static void __init setup_IO_APIC_irqs(void)
864 {
865 int apic, pin, idx, irq, first_notcon = 1;
866
867 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
868
869 for (apic = 0; apic < nr_ioapics; apic++) {
870 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
871
872 idx = find_irq_entry(apic,pin,mp_INT);
873 if (idx == -1) {
874 if (first_notcon) {
875 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
876 first_notcon = 0;
877 } else
878 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
879 continue;
880 }
881 if (!first_notcon) {
882 apic_printk(APIC_VERBOSE, " not connected.\n");
883 first_notcon = 1;
884 }
885
886 irq = pin_2_irq(idx, apic, pin);
887 add_pin_to_irq(irq, apic, pin);
888
889 setup_IO_APIC_irq(apic, pin, irq,
890 irq_trigger(idx), irq_polarity(idx));
891 }
892 }
893
894 if (!first_notcon)
895 apic_printk(APIC_VERBOSE, " not connected.\n");
896 }
897
898 /*
899 * Set up the 8259A-master output pin as broadcast to all
900 * CPUs.
901 */
902 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
903 {
904 struct IO_APIC_route_entry entry;
905 unsigned long flags;
906
907 memset(&entry,0,sizeof(entry));
908
909 disable_8259A_irq(0);
910
911 /* mask LVT0 */
912 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
913
914 /*
915 * We use logical delivery to get the timer IRQ
916 * to the first CPU.
917 */
918 entry.dest_mode = INT_DEST_MODE;
919 entry.mask = 0; /* unmask IRQ now */
920 entry.dest = cpu_mask_to_apicid(TARGET_CPUS);
921 entry.delivery_mode = INT_DELIVERY_MODE;
922 entry.polarity = 0;
923 entry.trigger = 0;
924 entry.vector = vector;
925
926 /*
927 * The timer IRQ doesn't have to know that behind the
928 * scene we have a 8259A-master in AEOI mode ...
929 */
930 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
931
932 /*
933 * Add it to the IO-APIC irq-routing table:
934 */
935 spin_lock_irqsave(&ioapic_lock, flags);
936 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
937 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
938 spin_unlock_irqrestore(&ioapic_lock, flags);
939
940 enable_8259A_irq(0);
941 }
942
943 void __apicdebuginit print_IO_APIC(void)
944 {
945 int apic, i;
946 union IO_APIC_reg_00 reg_00;
947 union IO_APIC_reg_01 reg_01;
948 union IO_APIC_reg_02 reg_02;
949 unsigned long flags;
950
951 if (apic_verbosity == APIC_QUIET)
952 return;
953
954 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
955 for (i = 0; i < nr_ioapics; i++)
956 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
957 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
958
959 /*
960 * We are a bit conservative about what we expect. We have to
961 * know about every hardware change ASAP.
962 */
963 printk(KERN_INFO "testing the IO APIC.......................\n");
964
965 for (apic = 0; apic < nr_ioapics; apic++) {
966
967 spin_lock_irqsave(&ioapic_lock, flags);
968 reg_00.raw = io_apic_read(apic, 0);
969 reg_01.raw = io_apic_read(apic, 1);
970 if (reg_01.bits.version >= 0x10)
971 reg_02.raw = io_apic_read(apic, 2);
972 spin_unlock_irqrestore(&ioapic_lock, flags);
973
974 printk("\n");
975 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
976 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
977 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
978
979 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
980 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
981
982 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
983 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
984
985 if (reg_01.bits.version >= 0x10) {
986 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
987 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
988 }
989
990 printk(KERN_DEBUG ".... IRQ redirection table:\n");
991
992 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
993 " Stat Dmod Deli Vect: \n");
994
995 for (i = 0; i <= reg_01.bits.entries; i++) {
996 struct IO_APIC_route_entry entry;
997
998 entry = ioapic_read_entry(apic, i);
999
1000 printk(KERN_DEBUG " %02x %03X ",
1001 i,
1002 entry.dest
1003 );
1004
1005 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1006 entry.mask,
1007 entry.trigger,
1008 entry.irr,
1009 entry.polarity,
1010 entry.delivery_status,
1011 entry.dest_mode,
1012 entry.delivery_mode,
1013 entry.vector
1014 );
1015 }
1016 }
1017 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1018 for (i = 0; i < NR_IRQS; i++) {
1019 struct irq_pin_list *entry = irq_2_pin + i;
1020 if (entry->pin < 0)
1021 continue;
1022 printk(KERN_DEBUG "IRQ%d ", i);
1023 for (;;) {
1024 printk("-> %d:%d", entry->apic, entry->pin);
1025 if (!entry->next)
1026 break;
1027 entry = irq_2_pin + entry->next;
1028 }
1029 printk("\n");
1030 }
1031
1032 printk(KERN_INFO ".................................... done.\n");
1033
1034 return;
1035 }
1036
1037 #if 0
1038
1039 static __apicdebuginit void print_APIC_bitfield (int base)
1040 {
1041 unsigned int v;
1042 int i, j;
1043
1044 if (apic_verbosity == APIC_QUIET)
1045 return;
1046
1047 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1048 for (i = 0; i < 8; i++) {
1049 v = apic_read(base + i*0x10);
1050 for (j = 0; j < 32; j++) {
1051 if (v & (1<<j))
1052 printk("1");
1053 else
1054 printk("0");
1055 }
1056 printk("\n");
1057 }
1058 }
1059
1060 void __apicdebuginit print_local_APIC(void * dummy)
1061 {
1062 unsigned int v, ver, maxlvt;
1063
1064 if (apic_verbosity == APIC_QUIET)
1065 return;
1066
1067 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1068 smp_processor_id(), hard_smp_processor_id());
1069 v = apic_read(APIC_ID);
1070 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(v));
1071 v = apic_read(APIC_LVR);
1072 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1073 ver = GET_APIC_VERSION(v);
1074 maxlvt = lapic_get_maxlvt();
1075
1076 v = apic_read(APIC_TASKPRI);
1077 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1078
1079 v = apic_read(APIC_ARBPRI);
1080 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1081 v & APIC_ARBPRI_MASK);
1082 v = apic_read(APIC_PROCPRI);
1083 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1084
1085 v = apic_read(APIC_EOI);
1086 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1087 v = apic_read(APIC_RRR);
1088 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1089 v = apic_read(APIC_LDR);
1090 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1091 v = apic_read(APIC_DFR);
1092 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1093 v = apic_read(APIC_SPIV);
1094 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1095
1096 printk(KERN_DEBUG "... APIC ISR field:\n");
1097 print_APIC_bitfield(APIC_ISR);
1098 printk(KERN_DEBUG "... APIC TMR field:\n");
1099 print_APIC_bitfield(APIC_TMR);
1100 printk(KERN_DEBUG "... APIC IRR field:\n");
1101 print_APIC_bitfield(APIC_IRR);
1102
1103 v = apic_read(APIC_ESR);
1104 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1105
1106 v = apic_read(APIC_ICR);
1107 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1108 v = apic_read(APIC_ICR2);
1109 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1110
1111 v = apic_read(APIC_LVTT);
1112 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1113
1114 if (maxlvt > 3) { /* PC is LVT#4. */
1115 v = apic_read(APIC_LVTPC);
1116 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1117 }
1118 v = apic_read(APIC_LVT0);
1119 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1120 v = apic_read(APIC_LVT1);
1121 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1122
1123 if (maxlvt > 2) { /* ERR is LVT#3. */
1124 v = apic_read(APIC_LVTERR);
1125 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1126 }
1127
1128 v = apic_read(APIC_TMICT);
1129 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1130 v = apic_read(APIC_TMCCT);
1131 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1132 v = apic_read(APIC_TDCR);
1133 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1134 printk("\n");
1135 }
1136
1137 void print_all_local_APICs (void)
1138 {
1139 on_each_cpu(print_local_APIC, NULL, 1, 1);
1140 }
1141
1142 void __apicdebuginit print_PIC(void)
1143 {
1144 unsigned int v;
1145 unsigned long flags;
1146
1147 if (apic_verbosity == APIC_QUIET)
1148 return;
1149
1150 printk(KERN_DEBUG "\nprinting PIC contents\n");
1151
1152 spin_lock_irqsave(&i8259A_lock, flags);
1153
1154 v = inb(0xa1) << 8 | inb(0x21);
1155 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1156
1157 v = inb(0xa0) << 8 | inb(0x20);
1158 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1159
1160 outb(0x0b,0xa0);
1161 outb(0x0b,0x20);
1162 v = inb(0xa0) << 8 | inb(0x20);
1163 outb(0x0a,0xa0);
1164 outb(0x0a,0x20);
1165
1166 spin_unlock_irqrestore(&i8259A_lock, flags);
1167
1168 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1169
1170 v = inb(0x4d1) << 8 | inb(0x4d0);
1171 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1172 }
1173
1174 #endif /* 0 */
1175
1176 void __init enable_IO_APIC(void)
1177 {
1178 union IO_APIC_reg_01 reg_01;
1179 int i8259_apic, i8259_pin;
1180 int i, apic;
1181 unsigned long flags;
1182
1183 for (i = 0; i < PIN_MAP_SIZE; i++) {
1184 irq_2_pin[i].pin = -1;
1185 irq_2_pin[i].next = 0;
1186 }
1187
1188 /*
1189 * The number of IO-APIC IRQ registers (== #pins):
1190 */
1191 for (apic = 0; apic < nr_ioapics; apic++) {
1192 spin_lock_irqsave(&ioapic_lock, flags);
1193 reg_01.raw = io_apic_read(apic, 1);
1194 spin_unlock_irqrestore(&ioapic_lock, flags);
1195 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1196 }
1197 for(apic = 0; apic < nr_ioapics; apic++) {
1198 int pin;
1199 /* See if any of the pins is in ExtINT mode */
1200 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1201 struct IO_APIC_route_entry entry;
1202 entry = ioapic_read_entry(apic, pin);
1203
1204 /* If the interrupt line is enabled and in ExtInt mode
1205 * I have found the pin where the i8259 is connected.
1206 */
1207 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1208 ioapic_i8259.apic = apic;
1209 ioapic_i8259.pin = pin;
1210 goto found_i8259;
1211 }
1212 }
1213 }
1214 found_i8259:
1215 /* Look to see what if the MP table has reported the ExtINT */
1216 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1217 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1218 /* Trust the MP table if nothing is setup in the hardware */
1219 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1220 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1221 ioapic_i8259.pin = i8259_pin;
1222 ioapic_i8259.apic = i8259_apic;
1223 }
1224 /* Complain if the MP table and the hardware disagree */
1225 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1226 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1227 {
1228 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1229 }
1230
1231 /*
1232 * Do not trust the IO-APIC being empty at bootup
1233 */
1234 clear_IO_APIC();
1235 }
1236
1237 /*
1238 * Not an __init, needed by the reboot code
1239 */
1240 void disable_IO_APIC(void)
1241 {
1242 /*
1243 * Clear the IO-APIC before rebooting:
1244 */
1245 clear_IO_APIC();
1246
1247 /*
1248 * If the i8259 is routed through an IOAPIC
1249 * Put that IOAPIC in virtual wire mode
1250 * so legacy interrupts can be delivered.
1251 */
1252 if (ioapic_i8259.pin != -1) {
1253 struct IO_APIC_route_entry entry;
1254
1255 memset(&entry, 0, sizeof(entry));
1256 entry.mask = 0; /* Enabled */
1257 entry.trigger = 0; /* Edge */
1258 entry.irr = 0;
1259 entry.polarity = 0; /* High */
1260 entry.delivery_status = 0;
1261 entry.dest_mode = 0; /* Physical */
1262 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1263 entry.vector = 0;
1264 entry.dest = GET_APIC_ID(apic_read(APIC_ID));
1265
1266 /*
1267 * Add it to the IO-APIC irq-routing table:
1268 */
1269 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1270 }
1271
1272 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1273 }
1274
1275 /*
1276 * There is a nasty bug in some older SMP boards, their mptable lies
1277 * about the timer IRQ. We do the following to work around the situation:
1278 *
1279 * - timer IRQ defaults to IO-APIC IRQ
1280 * - if this function detects that timer IRQs are defunct, then we fall
1281 * back to ISA timer IRQs
1282 */
1283 static int __init timer_irq_works(void)
1284 {
1285 unsigned long t1 = jiffies;
1286 unsigned long flags;
1287
1288 local_save_flags(flags);
1289 local_irq_enable();
1290 /* Let ten ticks pass... */
1291 mdelay((10 * 1000) / HZ);
1292 local_irq_restore(flags);
1293
1294 /*
1295 * Expect a few ticks at least, to be sure some possible
1296 * glue logic does not lock up after one or two first
1297 * ticks in a non-ExtINT mode. Also the local APIC
1298 * might have cached one ExtINT interrupt. Finally, at
1299 * least one tick may be lost due to delays.
1300 */
1301
1302 /* jiffies wrap? */
1303 if (time_after(jiffies, t1 + 4))
1304 return 1;
1305 return 0;
1306 }
1307
1308 /*
1309 * In the SMP+IOAPIC case it might happen that there are an unspecified
1310 * number of pending IRQ events unhandled. These cases are very rare,
1311 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1312 * better to do it this way as thus we do not have to be aware of
1313 * 'pending' interrupts in the IRQ path, except at this point.
1314 */
1315 /*
1316 * Edge triggered needs to resend any interrupt
1317 * that was delayed but this is now handled in the device
1318 * independent code.
1319 */
1320
1321 /*
1322 * Starting up a edge-triggered IO-APIC interrupt is
1323 * nasty - we need to make sure that we get the edge.
1324 * If it is already asserted for some reason, we need
1325 * return 1 to indicate that is was pending.
1326 *
1327 * This is not complete - we should be able to fake
1328 * an edge even if it isn't on the 8259A...
1329 */
1330
1331 static unsigned int startup_ioapic_irq(unsigned int irq)
1332 {
1333 int was_pending = 0;
1334 unsigned long flags;
1335
1336 spin_lock_irqsave(&ioapic_lock, flags);
1337 if (irq < 16) {
1338 disable_8259A_irq(irq);
1339 if (i8259A_irq_pending(irq))
1340 was_pending = 1;
1341 }
1342 __unmask_IO_APIC_irq(irq);
1343 spin_unlock_irqrestore(&ioapic_lock, flags);
1344
1345 return was_pending;
1346 }
1347
1348 static int ioapic_retrigger_irq(unsigned int irq)
1349 {
1350 struct irq_cfg *cfg = &irq_cfg[irq];
1351 cpumask_t mask;
1352 unsigned long flags;
1353
1354 spin_lock_irqsave(&vector_lock, flags);
1355 cpus_clear(mask);
1356 cpu_set(first_cpu(cfg->domain), mask);
1357
1358 send_IPI_mask(mask, cfg->vector);
1359 spin_unlock_irqrestore(&vector_lock, flags);
1360
1361 return 1;
1362 }
1363
1364 /*
1365 * Level and edge triggered IO-APIC interrupts need different handling,
1366 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1367 * handled with the level-triggered descriptor, but that one has slightly
1368 * more overhead. Level-triggered interrupts cannot be handled with the
1369 * edge-triggered handler, without risking IRQ storms and other ugly
1370 * races.
1371 */
1372
1373 #ifdef CONFIG_SMP
1374 asmlinkage void smp_irq_move_cleanup_interrupt(void)
1375 {
1376 unsigned vector, me;
1377 ack_APIC_irq();
1378 exit_idle();
1379 irq_enter();
1380
1381 me = smp_processor_id();
1382 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
1383 unsigned int irq;
1384 struct irq_desc *desc;
1385 struct irq_cfg *cfg;
1386 irq = __get_cpu_var(vector_irq)[vector];
1387 if (irq >= NR_IRQS)
1388 continue;
1389
1390 desc = irq_desc + irq;
1391 cfg = irq_cfg + irq;
1392 spin_lock(&desc->lock);
1393 if (!cfg->move_cleanup_count)
1394 goto unlock;
1395
1396 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain))
1397 goto unlock;
1398
1399 __get_cpu_var(vector_irq)[vector] = -1;
1400 cfg->move_cleanup_count--;
1401 unlock:
1402 spin_unlock(&desc->lock);
1403 }
1404
1405 irq_exit();
1406 }
1407
1408 static void irq_complete_move(unsigned int irq)
1409 {
1410 struct irq_cfg *cfg = irq_cfg + irq;
1411 unsigned vector, me;
1412
1413 if (likely(!cfg->move_in_progress))
1414 return;
1415
1416 vector = ~get_irq_regs()->orig_ax;
1417 me = smp_processor_id();
1418 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain)) {
1419 cpumask_t cleanup_mask;
1420
1421 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
1422 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
1423 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
1424 cfg->move_in_progress = 0;
1425 }
1426 }
1427 #else
1428 static inline void irq_complete_move(unsigned int irq) {}
1429 #endif
1430
1431 static void ack_apic_edge(unsigned int irq)
1432 {
1433 irq_complete_move(irq);
1434 move_native_irq(irq);
1435 ack_APIC_irq();
1436 }
1437
1438 static void ack_apic_level(unsigned int irq)
1439 {
1440 int do_unmask_irq = 0;
1441
1442 irq_complete_move(irq);
1443 #ifdef CONFIG_GENERIC_PENDING_IRQ
1444 /* If we are moving the irq we need to mask it */
1445 if (unlikely(irq_desc[irq].status & IRQ_MOVE_PENDING)) {
1446 do_unmask_irq = 1;
1447 mask_IO_APIC_irq(irq);
1448 }
1449 #endif
1450
1451 /*
1452 * We must acknowledge the irq before we move it or the acknowledge will
1453 * not propagate properly.
1454 */
1455 ack_APIC_irq();
1456
1457 /* Now we can move and renable the irq */
1458 if (unlikely(do_unmask_irq)) {
1459 /* Only migrate the irq if the ack has been received.
1460 *
1461 * On rare occasions the broadcast level triggered ack gets
1462 * delayed going to ioapics, and if we reprogram the
1463 * vector while Remote IRR is still set the irq will never
1464 * fire again.
1465 *
1466 * To prevent this scenario we read the Remote IRR bit
1467 * of the ioapic. This has two effects.
1468 * - On any sane system the read of the ioapic will
1469 * flush writes (and acks) going to the ioapic from
1470 * this cpu.
1471 * - We get to see if the ACK has actually been delivered.
1472 *
1473 * Based on failed experiments of reprogramming the
1474 * ioapic entry from outside of irq context starting
1475 * with masking the ioapic entry and then polling until
1476 * Remote IRR was clear before reprogramming the
1477 * ioapic I don't trust the Remote IRR bit to be
1478 * completey accurate.
1479 *
1480 * However there appears to be no other way to plug
1481 * this race, so if the Remote IRR bit is not
1482 * accurate and is causing problems then it is a hardware bug
1483 * and you can go talk to the chipset vendor about it.
1484 */
1485 if (!io_apic_level_ack_pending(irq))
1486 move_masked_irq(irq);
1487 unmask_IO_APIC_irq(irq);
1488 }
1489 }
1490
1491 static struct irq_chip ioapic_chip __read_mostly = {
1492 .name = "IO-APIC",
1493 .startup = startup_ioapic_irq,
1494 .mask = mask_IO_APIC_irq,
1495 .unmask = unmask_IO_APIC_irq,
1496 .ack = ack_apic_edge,
1497 .eoi = ack_apic_level,
1498 #ifdef CONFIG_SMP
1499 .set_affinity = set_ioapic_affinity_irq,
1500 #endif
1501 .retrigger = ioapic_retrigger_irq,
1502 };
1503
1504 static inline void init_IO_APIC_traps(void)
1505 {
1506 int irq;
1507
1508 /*
1509 * NOTE! The local APIC isn't very good at handling
1510 * multiple interrupts at the same interrupt level.
1511 * As the interrupt level is determined by taking the
1512 * vector number and shifting that right by 4, we
1513 * want to spread these out a bit so that they don't
1514 * all fall in the same interrupt level.
1515 *
1516 * Also, we've got to be careful not to trash gate
1517 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1518 */
1519 for (irq = 0; irq < NR_IRQS ; irq++) {
1520 int tmp = irq;
1521 if (IO_APIC_IRQ(tmp) && !irq_cfg[tmp].vector) {
1522 /*
1523 * Hmm.. We don't have an entry for this,
1524 * so default to an old-fashioned 8259
1525 * interrupt if we can..
1526 */
1527 if (irq < 16)
1528 make_8259A_irq(irq);
1529 else
1530 /* Strange. Oh, well.. */
1531 irq_desc[irq].chip = &no_irq_chip;
1532 }
1533 }
1534 }
1535
1536 static void enable_lapic_irq (unsigned int irq)
1537 {
1538 unsigned long v;
1539
1540 v = apic_read(APIC_LVT0);
1541 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1542 }
1543
1544 static void disable_lapic_irq (unsigned int irq)
1545 {
1546 unsigned long v;
1547
1548 v = apic_read(APIC_LVT0);
1549 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1550 }
1551
1552 static void ack_lapic_irq (unsigned int irq)
1553 {
1554 ack_APIC_irq();
1555 }
1556
1557 static void end_lapic_irq (unsigned int i) { /* nothing */ }
1558
1559 static struct hw_interrupt_type lapic_irq_type __read_mostly = {
1560 .name = "local-APIC",
1561 .typename = "local-APIC-edge",
1562 .startup = NULL, /* startup_irq() not used for IRQ0 */
1563 .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1564 .enable = enable_lapic_irq,
1565 .disable = disable_lapic_irq,
1566 .ack = ack_lapic_irq,
1567 .end = end_lapic_irq,
1568 };
1569
1570 static void __init setup_nmi(void)
1571 {
1572 /*
1573 * Dirty trick to enable the NMI watchdog ...
1574 * We put the 8259A master into AEOI mode and
1575 * unmask on all local APICs LVT0 as NMI.
1576 *
1577 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1578 * is from Maciej W. Rozycki - so we do not have to EOI from
1579 * the NMI handler or the timer interrupt.
1580 */
1581 printk(KERN_INFO "activating NMI Watchdog ...");
1582
1583 enable_NMI_through_LVT0();
1584
1585 printk(" done.\n");
1586 }
1587
1588 /*
1589 * This looks a bit hackish but it's about the only one way of sending
1590 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1591 * not support the ExtINT mode, unfortunately. We need to send these
1592 * cycles as some i82489DX-based boards have glue logic that keeps the
1593 * 8259A interrupt line asserted until INTA. --macro
1594 */
1595 static inline void unlock_ExtINT_logic(void)
1596 {
1597 int apic, pin, i;
1598 struct IO_APIC_route_entry entry0, entry1;
1599 unsigned char save_control, save_freq_select;
1600 unsigned long flags;
1601
1602 pin = find_isa_irq_pin(8, mp_INT);
1603 apic = find_isa_irq_apic(8, mp_INT);
1604 if (pin == -1)
1605 return;
1606
1607 spin_lock_irqsave(&ioapic_lock, flags);
1608 *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1609 *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1610 spin_unlock_irqrestore(&ioapic_lock, flags);
1611 clear_IO_APIC_pin(apic, pin);
1612
1613 memset(&entry1, 0, sizeof(entry1));
1614
1615 entry1.dest_mode = 0; /* physical delivery */
1616 entry1.mask = 0; /* unmask IRQ now */
1617 entry1.dest = hard_smp_processor_id();
1618 entry1.delivery_mode = dest_ExtINT;
1619 entry1.polarity = entry0.polarity;
1620 entry1.trigger = 0;
1621 entry1.vector = 0;
1622
1623 spin_lock_irqsave(&ioapic_lock, flags);
1624 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1625 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1626 spin_unlock_irqrestore(&ioapic_lock, flags);
1627
1628 save_control = CMOS_READ(RTC_CONTROL);
1629 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1630 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1631 RTC_FREQ_SELECT);
1632 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1633
1634 i = 100;
1635 while (i-- > 0) {
1636 mdelay(10);
1637 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1638 i -= 10;
1639 }
1640
1641 CMOS_WRITE(save_control, RTC_CONTROL);
1642 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1643 clear_IO_APIC_pin(apic, pin);
1644
1645 spin_lock_irqsave(&ioapic_lock, flags);
1646 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1647 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1648 spin_unlock_irqrestore(&ioapic_lock, flags);
1649 }
1650
1651 /*
1652 * This code may look a bit paranoid, but it's supposed to cooperate with
1653 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1654 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1655 * fanatically on his truly buggy board.
1656 *
1657 * FIXME: really need to revamp this for modern platforms only.
1658 */
1659 static inline void __init check_timer(void)
1660 {
1661 struct irq_cfg *cfg = irq_cfg + 0;
1662 int apic1, pin1, apic2, pin2;
1663 unsigned long flags;
1664
1665 local_irq_save(flags);
1666
1667 /*
1668 * get/set the timer IRQ vector:
1669 */
1670 disable_8259A_irq(0);
1671 assign_irq_vector(0, TARGET_CPUS);
1672
1673 /*
1674 * Subtle, code in do_timer_interrupt() expects an AEOI
1675 * mode for the 8259A whenever interrupts are routed
1676 * through I/O APICs. Also IRQ0 has to be enabled in
1677 * the 8259A which implies the virtual wire has to be
1678 * disabled in the local APIC.
1679 */
1680 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1681 init_8259A(1);
1682 if (timer_over_8254 > 0)
1683 enable_8259A_irq(0);
1684
1685 pin1 = find_isa_irq_pin(0, mp_INT);
1686 apic1 = find_isa_irq_apic(0, mp_INT);
1687 pin2 = ioapic_i8259.pin;
1688 apic2 = ioapic_i8259.apic;
1689
1690 apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
1691 cfg->vector, apic1, pin1, apic2, pin2);
1692
1693 if (pin1 != -1) {
1694 /*
1695 * Ok, does IRQ0 through the IOAPIC work?
1696 */
1697 unmask_IO_APIC_irq(0);
1698 if (!no_timer_check && timer_irq_works()) {
1699 nmi_watchdog_default();
1700 if (nmi_watchdog == NMI_IO_APIC) {
1701 disable_8259A_irq(0);
1702 setup_nmi();
1703 enable_8259A_irq(0);
1704 }
1705 if (disable_timer_pin_1 > 0)
1706 clear_IO_APIC_pin(0, pin1);
1707 goto out;
1708 }
1709 clear_IO_APIC_pin(apic1, pin1);
1710 apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: 8254 timer not "
1711 "connected to IO-APIC\n");
1712 }
1713
1714 apic_printk(APIC_VERBOSE,KERN_INFO "...trying to set up timer (IRQ0) "
1715 "through the 8259A ... ");
1716 if (pin2 != -1) {
1717 apic_printk(APIC_VERBOSE,"\n..... (found apic %d pin %d) ...",
1718 apic2, pin2);
1719 /*
1720 * legacy devices should be connected to IO APIC #0
1721 */
1722 setup_ExtINT_IRQ0_pin(apic2, pin2, cfg->vector);
1723 if (timer_irq_works()) {
1724 apic_printk(APIC_VERBOSE," works.\n");
1725 nmi_watchdog_default();
1726 if (nmi_watchdog == NMI_IO_APIC) {
1727 setup_nmi();
1728 }
1729 goto out;
1730 }
1731 /*
1732 * Cleanup, just in case ...
1733 */
1734 clear_IO_APIC_pin(apic2, pin2);
1735 }
1736 apic_printk(APIC_VERBOSE," failed.\n");
1737
1738 if (nmi_watchdog == NMI_IO_APIC) {
1739 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1740 nmi_watchdog = 0;
1741 }
1742
1743 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1744
1745 disable_8259A_irq(0);
1746 irq_desc[0].chip = &lapic_irq_type;
1747 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
1748 enable_8259A_irq(0);
1749
1750 if (timer_irq_works()) {
1751 apic_printk(APIC_VERBOSE," works.\n");
1752 goto out;
1753 }
1754 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
1755 apic_printk(APIC_VERBOSE," failed.\n");
1756
1757 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1758
1759 init_8259A(0);
1760 make_8259A_irq(0);
1761 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1762
1763 unlock_ExtINT_logic();
1764
1765 if (timer_irq_works()) {
1766 apic_printk(APIC_VERBOSE," works.\n");
1767 goto out;
1768 }
1769 apic_printk(APIC_VERBOSE," failed :(.\n");
1770 panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
1771 out:
1772 local_irq_restore(flags);
1773 }
1774
1775 static int __init notimercheck(char *s)
1776 {
1777 no_timer_check = 1;
1778 return 1;
1779 }
1780 __setup("no_timer_check", notimercheck);
1781
1782 /*
1783 *
1784 * IRQs that are handled by the PIC in the MPS IOAPIC case.
1785 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1786 * Linux doesn't really care, as it's not actually used
1787 * for any interrupt handling anyway.
1788 */
1789 #define PIC_IRQS (1<<2)
1790
1791 void __init setup_IO_APIC(void)
1792 {
1793
1794 /*
1795 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
1796 */
1797
1798 if (acpi_ioapic)
1799 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
1800 else
1801 io_apic_irqs = ~PIC_IRQS;
1802
1803 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
1804
1805 sync_Arb_IDs();
1806 setup_IO_APIC_irqs();
1807 init_IO_APIC_traps();
1808 check_timer();
1809 if (!acpi_ioapic)
1810 print_IO_APIC();
1811 }
1812
1813 struct sysfs_ioapic_data {
1814 struct sys_device dev;
1815 struct IO_APIC_route_entry entry[0];
1816 };
1817 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
1818
1819 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1820 {
1821 struct IO_APIC_route_entry *entry;
1822 struct sysfs_ioapic_data *data;
1823 int i;
1824
1825 data = container_of(dev, struct sysfs_ioapic_data, dev);
1826 entry = data->entry;
1827 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
1828 *entry = ioapic_read_entry(dev->id, i);
1829
1830 return 0;
1831 }
1832
1833 static int ioapic_resume(struct sys_device *dev)
1834 {
1835 struct IO_APIC_route_entry *entry;
1836 struct sysfs_ioapic_data *data;
1837 unsigned long flags;
1838 union IO_APIC_reg_00 reg_00;
1839 int i;
1840
1841 data = container_of(dev, struct sysfs_ioapic_data, dev);
1842 entry = data->entry;
1843
1844 spin_lock_irqsave(&ioapic_lock, flags);
1845 reg_00.raw = io_apic_read(dev->id, 0);
1846 if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
1847 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
1848 io_apic_write(dev->id, 0, reg_00.raw);
1849 }
1850 spin_unlock_irqrestore(&ioapic_lock, flags);
1851 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
1852 ioapic_write_entry(dev->id, i, entry[i]);
1853
1854 return 0;
1855 }
1856
1857 static struct sysdev_class ioapic_sysdev_class = {
1858 .name = "ioapic",
1859 .suspend = ioapic_suspend,
1860 .resume = ioapic_resume,
1861 };
1862
1863 static int __init ioapic_init_sysfs(void)
1864 {
1865 struct sys_device * dev;
1866 int i, size, error;
1867
1868 error = sysdev_class_register(&ioapic_sysdev_class);
1869 if (error)
1870 return error;
1871
1872 for (i = 0; i < nr_ioapics; i++ ) {
1873 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
1874 * sizeof(struct IO_APIC_route_entry);
1875 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
1876 if (!mp_ioapic_data[i]) {
1877 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1878 continue;
1879 }
1880 dev = &mp_ioapic_data[i]->dev;
1881 dev->id = i;
1882 dev->cls = &ioapic_sysdev_class;
1883 error = sysdev_register(dev);
1884 if (error) {
1885 kfree(mp_ioapic_data[i]);
1886 mp_ioapic_data[i] = NULL;
1887 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1888 continue;
1889 }
1890 }
1891
1892 return 0;
1893 }
1894
1895 device_initcall(ioapic_init_sysfs);
1896
1897 /*
1898 * Dynamic irq allocate and deallocation
1899 */
1900 int create_irq(void)
1901 {
1902 /* Allocate an unused irq */
1903 int irq;
1904 int new;
1905 unsigned long flags;
1906
1907 irq = -ENOSPC;
1908 spin_lock_irqsave(&vector_lock, flags);
1909 for (new = (NR_IRQS - 1); new >= 0; new--) {
1910 if (platform_legacy_irq(new))
1911 continue;
1912 if (irq_cfg[new].vector != 0)
1913 continue;
1914 if (__assign_irq_vector(new, TARGET_CPUS) == 0)
1915 irq = new;
1916 break;
1917 }
1918 spin_unlock_irqrestore(&vector_lock, flags);
1919
1920 if (irq >= 0) {
1921 dynamic_irq_init(irq);
1922 }
1923 return irq;
1924 }
1925
1926 void destroy_irq(unsigned int irq)
1927 {
1928 unsigned long flags;
1929
1930 dynamic_irq_cleanup(irq);
1931
1932 spin_lock_irqsave(&vector_lock, flags);
1933 __clear_irq_vector(irq);
1934 spin_unlock_irqrestore(&vector_lock, flags);
1935 }
1936
1937 /*
1938 * MSI message composition
1939 */
1940 #ifdef CONFIG_PCI_MSI
1941 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
1942 {
1943 struct irq_cfg *cfg = irq_cfg + irq;
1944 int err;
1945 unsigned dest;
1946 cpumask_t tmp;
1947
1948 tmp = TARGET_CPUS;
1949 err = assign_irq_vector(irq, tmp);
1950 if (!err) {
1951 cpus_and(tmp, cfg->domain, tmp);
1952 dest = cpu_mask_to_apicid(tmp);
1953
1954 msg->address_hi = MSI_ADDR_BASE_HI;
1955 msg->address_lo =
1956 MSI_ADDR_BASE_LO |
1957 ((INT_DEST_MODE == 0) ?
1958 MSI_ADDR_DEST_MODE_PHYSICAL:
1959 MSI_ADDR_DEST_MODE_LOGICAL) |
1960 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1961 MSI_ADDR_REDIRECTION_CPU:
1962 MSI_ADDR_REDIRECTION_LOWPRI) |
1963 MSI_ADDR_DEST_ID(dest);
1964
1965 msg->data =
1966 MSI_DATA_TRIGGER_EDGE |
1967 MSI_DATA_LEVEL_ASSERT |
1968 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1969 MSI_DATA_DELIVERY_FIXED:
1970 MSI_DATA_DELIVERY_LOWPRI) |
1971 MSI_DATA_VECTOR(cfg->vector);
1972 }
1973 return err;
1974 }
1975
1976 #ifdef CONFIG_SMP
1977 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
1978 {
1979 struct irq_cfg *cfg = irq_cfg + irq;
1980 struct msi_msg msg;
1981 unsigned int dest;
1982 cpumask_t tmp;
1983
1984 cpus_and(tmp, mask, cpu_online_map);
1985 if (cpus_empty(tmp))
1986 return;
1987
1988 if (assign_irq_vector(irq, mask))
1989 return;
1990
1991 cpus_and(tmp, cfg->domain, mask);
1992 dest = cpu_mask_to_apicid(tmp);
1993
1994 read_msi_msg(irq, &msg);
1995
1996 msg.data &= ~MSI_DATA_VECTOR_MASK;
1997 msg.data |= MSI_DATA_VECTOR(cfg->vector);
1998 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
1999 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2000
2001 write_msi_msg(irq, &msg);
2002 irq_desc[irq].affinity = mask;
2003 }
2004 #endif /* CONFIG_SMP */
2005
2006 /*
2007 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2008 * which implement the MSI or MSI-X Capability Structure.
2009 */
2010 static struct irq_chip msi_chip = {
2011 .name = "PCI-MSI",
2012 .unmask = unmask_msi_irq,
2013 .mask = mask_msi_irq,
2014 .ack = ack_apic_edge,
2015 #ifdef CONFIG_SMP
2016 .set_affinity = set_msi_irq_affinity,
2017 #endif
2018 .retrigger = ioapic_retrigger_irq,
2019 };
2020
2021 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
2022 {
2023 struct msi_msg msg;
2024 int irq, ret;
2025 irq = create_irq();
2026 if (irq < 0)
2027 return irq;
2028
2029 ret = msi_compose_msg(dev, irq, &msg);
2030 if (ret < 0) {
2031 destroy_irq(irq);
2032 return ret;
2033 }
2034
2035 set_irq_msi(irq, desc);
2036 write_msi_msg(irq, &msg);
2037
2038 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
2039
2040 return 0;
2041 }
2042
2043 void arch_teardown_msi_irq(unsigned int irq)
2044 {
2045 destroy_irq(irq);
2046 }
2047
2048 #ifdef CONFIG_DMAR
2049 #ifdef CONFIG_SMP
2050 static void dmar_msi_set_affinity(unsigned int irq, cpumask_t mask)
2051 {
2052 struct irq_cfg *cfg = irq_cfg + irq;
2053 struct msi_msg msg;
2054 unsigned int dest;
2055 cpumask_t tmp;
2056
2057 cpus_and(tmp, mask, cpu_online_map);
2058 if (cpus_empty(tmp))
2059 return;
2060
2061 if (assign_irq_vector(irq, mask))
2062 return;
2063
2064 cpus_and(tmp, cfg->domain, mask);
2065 dest = cpu_mask_to_apicid(tmp);
2066
2067 dmar_msi_read(irq, &msg);
2068
2069 msg.data &= ~MSI_DATA_VECTOR_MASK;
2070 msg.data |= MSI_DATA_VECTOR(cfg->vector);
2071 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2072 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2073
2074 dmar_msi_write(irq, &msg);
2075 irq_desc[irq].affinity = mask;
2076 }
2077 #endif /* CONFIG_SMP */
2078
2079 struct irq_chip dmar_msi_type = {
2080 .name = "DMAR_MSI",
2081 .unmask = dmar_msi_unmask,
2082 .mask = dmar_msi_mask,
2083 .ack = ack_apic_edge,
2084 #ifdef CONFIG_SMP
2085 .set_affinity = dmar_msi_set_affinity,
2086 #endif
2087 .retrigger = ioapic_retrigger_irq,
2088 };
2089
2090 int arch_setup_dmar_msi(unsigned int irq)
2091 {
2092 int ret;
2093 struct msi_msg msg;
2094
2095 ret = msi_compose_msg(NULL, irq, &msg);
2096 if (ret < 0)
2097 return ret;
2098 dmar_msi_write(irq, &msg);
2099 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
2100 "edge");
2101 return 0;
2102 }
2103 #endif
2104
2105 #endif /* CONFIG_PCI_MSI */
2106 /*
2107 * Hypertransport interrupt support
2108 */
2109 #ifdef CONFIG_HT_IRQ
2110
2111 #ifdef CONFIG_SMP
2112
2113 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
2114 {
2115 struct ht_irq_msg msg;
2116 fetch_ht_irq_msg(irq, &msg);
2117
2118 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
2119 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
2120
2121 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
2122 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
2123
2124 write_ht_irq_msg(irq, &msg);
2125 }
2126
2127 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
2128 {
2129 struct irq_cfg *cfg = irq_cfg + irq;
2130 unsigned int dest;
2131 cpumask_t tmp;
2132
2133 cpus_and(tmp, mask, cpu_online_map);
2134 if (cpus_empty(tmp))
2135 return;
2136
2137 if (assign_irq_vector(irq, mask))
2138 return;
2139
2140 cpus_and(tmp, cfg->domain, mask);
2141 dest = cpu_mask_to_apicid(tmp);
2142
2143 target_ht_irq(irq, dest, cfg->vector);
2144 irq_desc[irq].affinity = mask;
2145 }
2146 #endif
2147
2148 static struct irq_chip ht_irq_chip = {
2149 .name = "PCI-HT",
2150 .mask = mask_ht_irq,
2151 .unmask = unmask_ht_irq,
2152 .ack = ack_apic_edge,
2153 #ifdef CONFIG_SMP
2154 .set_affinity = set_ht_irq_affinity,
2155 #endif
2156 .retrigger = ioapic_retrigger_irq,
2157 };
2158
2159 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2160 {
2161 struct irq_cfg *cfg = irq_cfg + irq;
2162 int err;
2163 cpumask_t tmp;
2164
2165 tmp = TARGET_CPUS;
2166 err = assign_irq_vector(irq, tmp);
2167 if (!err) {
2168 struct ht_irq_msg msg;
2169 unsigned dest;
2170
2171 cpus_and(tmp, cfg->domain, tmp);
2172 dest = cpu_mask_to_apicid(tmp);
2173
2174 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
2175
2176 msg.address_lo =
2177 HT_IRQ_LOW_BASE |
2178 HT_IRQ_LOW_DEST_ID(dest) |
2179 HT_IRQ_LOW_VECTOR(cfg->vector) |
2180 ((INT_DEST_MODE == 0) ?
2181 HT_IRQ_LOW_DM_PHYSICAL :
2182 HT_IRQ_LOW_DM_LOGICAL) |
2183 HT_IRQ_LOW_RQEOI_EDGE |
2184 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2185 HT_IRQ_LOW_MT_FIXED :
2186 HT_IRQ_LOW_MT_ARBITRATED) |
2187 HT_IRQ_LOW_IRQ_MASKED;
2188
2189 write_ht_irq_msg(irq, &msg);
2190
2191 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2192 handle_edge_irq, "edge");
2193 }
2194 return err;
2195 }
2196 #endif /* CONFIG_HT_IRQ */
2197
2198 /* --------------------------------------------------------------------------
2199 ACPI-based IOAPIC Configuration
2200 -------------------------------------------------------------------------- */
2201
2202 #ifdef CONFIG_ACPI
2203
2204 #define IO_APIC_MAX_ID 0xFE
2205
2206 int __init io_apic_get_redir_entries (int ioapic)
2207 {
2208 union IO_APIC_reg_01 reg_01;
2209 unsigned long flags;
2210
2211 spin_lock_irqsave(&ioapic_lock, flags);
2212 reg_01.raw = io_apic_read(ioapic, 1);
2213 spin_unlock_irqrestore(&ioapic_lock, flags);
2214
2215 return reg_01.bits.entries;
2216 }
2217
2218
2219 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
2220 {
2221 if (!IO_APIC_IRQ(irq)) {
2222 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2223 ioapic);
2224 return -EINVAL;
2225 }
2226
2227 /*
2228 * IRQs < 16 are already in the irq_2_pin[] map
2229 */
2230 if (irq >= 16)
2231 add_pin_to_irq(irq, ioapic, pin);
2232
2233 setup_IO_APIC_irq(ioapic, pin, irq, triggering, polarity);
2234
2235 return 0;
2236 }
2237
2238
2239 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
2240 {
2241 int i;
2242
2243 if (skip_ioapic_setup)
2244 return -1;
2245
2246 for (i = 0; i < mp_irq_entries; i++)
2247 if (mp_irqs[i].mpc_irqtype == mp_INT &&
2248 mp_irqs[i].mpc_srcbusirq == bus_irq)
2249 break;
2250 if (i >= mp_irq_entries)
2251 return -1;
2252
2253 *trigger = irq_trigger(i);
2254 *polarity = irq_polarity(i);
2255 return 0;
2256 }
2257
2258 #endif /* CONFIG_ACPI */
2259
2260 /*
2261 * This function currently is only a helper for the i386 smp boot process where
2262 * we need to reprogram the ioredtbls to cater for the cpus which have come online
2263 * so mask in all cases should simply be TARGET_CPUS
2264 */
2265 #ifdef CONFIG_SMP
2266 void __init setup_ioapic_dest(void)
2267 {
2268 int pin, ioapic, irq, irq_entry;
2269
2270 if (skip_ioapic_setup == 1)
2271 return;
2272
2273 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
2274 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
2275 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
2276 if (irq_entry == -1)
2277 continue;
2278 irq = pin_2_irq(irq_entry, ioapic, pin);
2279
2280 /* setup_IO_APIC_irqs could fail to get vector for some device
2281 * when you have too many devices, because at that time only boot
2282 * cpu is online.
2283 */
2284 if (!irq_cfg[irq].vector)
2285 setup_IO_APIC_irq(ioapic, pin, irq,
2286 irq_trigger(irq_entry),
2287 irq_polarity(irq_entry));
2288 else
2289 set_ioapic_affinity_irq(irq, TARGET_CPUS);
2290 }
2291
2292 }
2293 }
2294 #endif
2295
2296 #define IOAPIC_RESOURCE_NAME_SIZE 11
2297
2298 static struct resource *ioapic_resources;
2299
2300 static struct resource * __init ioapic_setup_resources(void)
2301 {
2302 unsigned long n;
2303 struct resource *res;
2304 char *mem;
2305 int i;
2306
2307 if (nr_ioapics <= 0)
2308 return NULL;
2309
2310 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
2311 n *= nr_ioapics;
2312
2313 mem = alloc_bootmem(n);
2314 res = (void *)mem;
2315
2316 if (mem != NULL) {
2317 memset(mem, 0, n);
2318 mem += sizeof(struct resource) * nr_ioapics;
2319
2320 for (i = 0; i < nr_ioapics; i++) {
2321 res[i].name = mem;
2322 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
2323 sprintf(mem, "IOAPIC %u", i);
2324 mem += IOAPIC_RESOURCE_NAME_SIZE;
2325 }
2326 }
2327
2328 ioapic_resources = res;
2329
2330 return res;
2331 }
2332
2333 void __init ioapic_init_mappings(void)
2334 {
2335 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
2336 struct resource *ioapic_res;
2337 int i;
2338
2339 ioapic_res = ioapic_setup_resources();
2340 for (i = 0; i < nr_ioapics; i++) {
2341 if (smp_found_config) {
2342 ioapic_phys = mp_ioapics[i].mpc_apicaddr;
2343 } else {
2344 ioapic_phys = (unsigned long)
2345 alloc_bootmem_pages(PAGE_SIZE);
2346 ioapic_phys = __pa(ioapic_phys);
2347 }
2348 set_fixmap_nocache(idx, ioapic_phys);
2349 apic_printk(APIC_VERBOSE,
2350 "mapped IOAPIC to %016lx (%016lx)\n",
2351 __fix_to_virt(idx), ioapic_phys);
2352 idx++;
2353
2354 if (ioapic_res != NULL) {
2355 ioapic_res->start = ioapic_phys;
2356 ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
2357 ioapic_res++;
2358 }
2359 }
2360 }
2361
2362 static int __init ioapic_insert_resources(void)
2363 {
2364 int i;
2365 struct resource *r = ioapic_resources;
2366
2367 if (!r) {
2368 printk(KERN_ERR
2369 "IO APIC resources could be not be allocated.\n");
2370 return -1;
2371 }
2372
2373 for (i = 0; i < nr_ioapics; i++) {
2374 insert_resource(&iomem_resource, r);
2375 r++;
2376 }
2377
2378 return 0;
2379 }
2380
2381 /* Insert the IO APIC resources after PCI initialization has occured to handle
2382 * IO APICS that are mapped in on a BAR in PCI space. */
2383 late_initcall(ioapic_insert_resources);
2384
WRT350N Kernel Patches