arch/xtensa/mm/cache.c

   1 /*
   2  * arch/xtensa/mm/cache.c
   3  *
   4  * This file is subject to the terms and conditions of the GNU General Public
   5  * License.  See the file "COPYING" in the main directory of this archive
   6  * for more details.
   7  *
   8  * Copyright (C) 2001-2006 Tensilica Inc.
   9  *
  10  * Chris Zankel <chris@zankel.net>
  11  * Joe Taylor
  12  * Marc Gauthier
  13  *
  14  */
  15
  16 #include <linux/init.h>
  17 #include <linux/signal.h>
  18 #include <linux/sched.h>
  19 #include <linux/kernel.h>
  20 #include <linux/errno.h>
  21 #include <linux/string.h>
  22 #include <linux/types.h>
  23 #include <linux/ptrace.h>
  24 #include <linux/bootmem.h>
  25 #include <linux/swap.h>
  26 #include <linux/pagemap.h>
  27
  28 <<<<<<< HEAD:arch/xtensa/mm/cache.c
  29 #include <asm/pgtable.h>
  30 =======
  31 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/xtensa/mm/cache.c
  32 #include <asm/bootparam.h>
  33 #include <asm/mmu_context.h>
  34 #include <asm/tlb.h>
  35 #include <asm/tlbflush.h>
  36 #include <asm/page.h>
  37 #include <asm/pgalloc.h>
  38 #include <asm/pgtable.h>
  39
  40 //#define printd(x...) printk(x)
  41 #define printd(x...) do { } while(0)
  42
  43 /*
  44  * Note:
  45  * The kernel provides one architecture bit PG_arch_1 in the page flags that
  46  * can be used for cache coherency.
  47  *
  48  * I$-D$ coherency.
  49  *
  50  * The Xtensa architecture doesn't keep the instruction cache coherent with
  51  * the data cache. We use the architecture bit to indicate if the caches
  52  * are coherent. The kernel clears this bit whenever a page is added to the
  53  * page cache. At that time, the caches might not be in sync. We, therefore,
  54  * define this flag as 'clean' if set.
  55  *
  56  * D-cache aliasing.
  57  *
  58  * With cache aliasing, we have to always flush the cache when pages are
  59  * unmapped (see tlb_start_vma(). So, we use this flag to indicate a dirty
  60  * page.
  61  *
  62  *
  63  *
  64  */
  65
  66 #if (DCACHE_WAY_SIZE > PAGE_SIZE) && XCHAL_DCACHE_IS_WRITEBACK
  67
  68 /*
  69  * Any time the kernel writes to a user page cache page, or it is about to
  70  * read from a page cache page this routine is called.
  71  *
  72  */
  73
  74 void flush_dcache_page(struct page *page)
  75 {
  76         struct address_space *mapping = page_mapping(page);
  77
  78         /*
  79          * If we have a mapping but the page is not mapped to user-space
  80          * yet, we simply mark this page dirty and defer flushing the
  81          * caches until update_mmu().
  82          */
  83
  84         if (mapping && !mapping_mapped(mapping)) {
  85                 if (!test_bit(PG_arch_1, &page->flags))
  86                         set_bit(PG_arch_1, &page->flags);
  87                 return;
  88
  89         } else {
  90
  91                 unsigned long phys = page_to_phys(page);
  92                 unsigned long temp = page->index << PAGE_SHIFT;
  93                 unsigned long alias = !(DCACHE_ALIAS_EQ(temp, phys));
  94                 unsigned long virt;
  95
  96                 /*
  97                  * Flush the page in kernel space and user space.
  98                  * Note that we can omit that step if aliasing is not
  99                  * an issue, but we do have to synchronize I$ and D$
 100                  * if we have a mapping.
 101                  */
 102
 103                 if (!alias && !mapping)
 104                         return;
 105
 106                 __flush_invalidate_dcache_page((long)page_address(page));
 107
 108                 virt = TLBTEMP_BASE_1 + (temp & DCACHE_ALIAS_MASK);
 109
 110                 if (alias)
 111                         __flush_invalidate_dcache_page_alias(virt, phys);
 112
 113                 if (mapping)
 114                         __invalidate_icache_page_alias(virt, phys);
 115         }
 116
 117         /* There shouldn't be an entry in the cache for this page anymore. */
 118 }
 119
 120
 121 /*
 122  * For now, flush the whole cache. FIXME??
 123  */
 124
 125 void flush_cache_range(struct vm_area_struct* vma,
 126                        unsigned long start, unsigned long end)
 127 {
 128         __flush_invalidate_dcache_all();
 129         __invalidate_icache_all();
 130 }
 131
 132 /*
 133  * Remove any entry in the cache for this page.
 134  *
 135  * Note that this function is only called for user pages, so use the
 136  * alias versions of the cache flush functions.
 137  */
 138
 139 void flush_cache_page(struct vm_area_struct* vma, unsigned long address,
 140                       unsigned long pfn)
 141 {
 142         /* Note that we have to use the 'alias' address to avoid multi-hit */
 143
 144         unsigned long phys = page_to_phys(pfn_to_page(pfn));
 145         unsigned long virt = TLBTEMP_BASE_1 + (address & DCACHE_ALIAS_MASK);
 146
 147         __flush_invalidate_dcache_page_alias(virt, phys);
 148         __invalidate_icache_page_alias(virt, phys);
 149 }
 150
 151 #endif
 152
 153 void
 154 update_mmu_cache(struct vm_area_struct * vma, unsigned long addr, pte_t pte)
 155 {
 156         unsigned long pfn = pte_pfn(pte);
 157         struct page *page;
 158
 159         if (!pfn_valid(pfn))
 160                 return;
 161
 162         page = pfn_to_page(pfn);
 163
 164         /* Invalidate old entry in TLBs */
 165
 166         invalidate_itlb_mapping(addr);
 167         invalidate_dtlb_mapping(addr);
 168
 169 #if (DCACHE_WAY_SIZE > PAGE_SIZE) && XCHAL_DCACHE_IS_WRITEBACK
 170
 171         if (!PageReserved(page) && test_bit(PG_arch_1, &page->flags)) {
 172
 173                 unsigned long vaddr = TLBTEMP_BASE_1 + (addr & DCACHE_ALIAS_MASK);
 174                 unsigned long paddr = (unsigned long) page_address(page);
 175                 unsigned long phys = page_to_phys(page);
 176
 177                 __flush_invalidate_dcache_page(paddr);
 178
 179                 __flush_invalidate_dcache_page_alias(vaddr, phys);
 180                 __invalidate_icache_page_alias(vaddr, phys);
 181
 182                 clear_bit(PG_arch_1, &page->flags);
 183         }
 184 #else
 185         if (!PageReserved(page) && !test_bit(PG_arch_1, &page->flags)
 186             && (vma->vm_flags & VM_EXEC) != 0) {
 187 <<<<<<< HEAD:arch/xtensa/mm/cache.c
 188                 unsigned long vaddr = addr & PAGE_MASK;
 189                 __flush_dcache_page(vaddr);
 190                 __invalidate_icache_page(vaddr);
 191 =======
 192                 unsigned long paddr = (unsigned long) page_address(page);
 193                 __flush_dcache_page(paddr);
 194                 __invalidate_icache_page(paddr);
 195 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/xtensa/mm/cache.c
 196                 set_bit(PG_arch_1, &page->flags);
 197         }
 198 #endif
 199 }
 200
 201 /*
 202  * access_process_vm() has called get_user_pages(), which has done a
 203  * flush_dcache_page() on the page.
 204  */
 205
 206 #if (DCACHE_WAY_SIZE > PAGE_SIZE) && XCHAL_DCACHE_IS_WRITEBACK
 207
 208 void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
 209                 unsigned long vaddr, void *dst, const void *src,
 210                 unsigned long len)
 211 {
 212         unsigned long phys = page_to_phys(page);
 213         unsigned long alias = !(DCACHE_ALIAS_EQ(vaddr, phys));
 214
 215         /* Flush and invalidate user page if aliased. */
 216
 217         if (alias) {
 218                 unsigned long temp = TLBTEMP_BASE_1 + (vaddr & DCACHE_ALIAS_MASK);
 219                 __flush_invalidate_dcache_page_alias(temp, phys);
 220         }
 221
 222         /* Copy data */
 223
 224         memcpy(dst, src, len);
 225
 226         /*
 227          * Flush and invalidate kernel page if aliased and synchronize
 228          * data and instruction caches for executable pages.
 229          */
 230
 231         if (alias) {
 232                 unsigned long temp = TLBTEMP_BASE_1 + (vaddr & DCACHE_ALIAS_MASK);
 233
 234                 __flush_invalidate_dcache_range((unsigned long) dst, len);
 235                 if ((vma->vm_flags & VM_EXEC) != 0) {
 236                         __invalidate_icache_page_alias(temp, phys);
 237                 }
 238
 239         } else if ((vma->vm_flags & VM_EXEC) != 0) {
 240                 __flush_dcache_range((unsigned long)dst,len);
 241                 __invalidate_icache_range((unsigned long) dst, len);
 242         }
 243 }
 244
 245 extern void copy_from_user_page(struct vm_area_struct *vma, struct page *page,
 246                 unsigned long vaddr, void *dst, const void *src,
 247                 unsigned long len)
 248 {
 249         unsigned long phys = page_to_phys(page);
 250         unsigned long alias = !(DCACHE_ALIAS_EQ(vaddr, phys));
 251
 252         /*
 253          * Flush user page if aliased.
 254          * (Note: a simply flush would be sufficient)
 255          */
 256
 257         if (alias) {
 258                 unsigned long temp = TLBTEMP_BASE_1 + (vaddr & DCACHE_ALIAS_MASK);
 259                 __flush_invalidate_dcache_page_alias(temp, phys);
 260         }
 261
 262         memcpy(dst, src, len);
 263 }
 264
 265 #endif