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Merge git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
[wrt350n-kernel.git] / drivers / ata / pata_serverworks.c
blob66b03a973df3eb44baab8ff3e953e8df28498731
1 /*
2 * pata_serverworks.c - Serverworks PATA for new ATA layer
3 * (C) 2005 Red Hat Inc
4 * Alan Cox <alan@redhat.com>
5 *
6 * based upon
7 *
8 * serverworks.c
9 *
10 * Copyright (C) 1998-2000 Michel Aubry
11 * Copyright (C) 1998-2000 Andrzej Krzysztofowicz
12 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
13 * Portions copyright (c) 2001 Sun Microsystems
14 *
15 *
16 * RCC/ServerWorks IDE driver for Linux
17 *
18 * OSB4: `Open South Bridge' IDE Interface (fn 1)
19 * supports UDMA mode 2 (33 MB/s)
20 *
21 * CSB5: `Champion South Bridge' IDE Interface (fn 1)
22 * all revisions support UDMA mode 4 (66 MB/s)
23 * revision A2.0 and up support UDMA mode 5 (100 MB/s)
24 *
25 * *** The CSB5 does not provide ANY register ***
26 * *** to detect 80-conductor cable presence. ***
27 *
28 * CSB6: `Champion South Bridge' IDE Interface (optional: third channel)
29 *
30 * Documentation:
31 * Available under NDA only. Errata info very hard to get.
32 */
33
34 #include <linux/kernel.h>
35 #include <linux/module.h>
36 #include <linux/pci.h>
37 #include <linux/init.h>
38 #include <linux/blkdev.h>
39 #include <linux/delay.h>
40 #include <scsi/scsi_host.h>
41 #include <linux/libata.h>
42
43 #define DRV_NAME "pata_serverworks"
44 #define DRV_VERSION "0.4.3"
45
46 #define SVWKS_CSB5_REVISION_NEW 0x92 /* min PCI_REVISION_ID for UDMA5 (A2.0) */
47 #define SVWKS_CSB6_REVISION 0xa0 /* min PCI_REVISION_ID for UDMA4 (A1.0) */
48
49 /* Seagate Barracuda ATA IV Family drives in UDMA mode 5
50 * can overrun their FIFOs when used with the CSB5 */
51
52 static const char *csb_bad_ata100[] = {
53 "ST320011A",
54 "ST340016A",
55 "ST360021A",
56 "ST380021A",
57 NULL
58 };
59
60 /**
61 * dell_cable - Dell serverworks cable detection
62 * @ap: ATA port to do cable detect
63 *
64 * Dell hide the 40/80 pin select for their interfaces in the top two
65 * bits of the subsystem ID.
66 */
67
68 static int dell_cable(struct ata_port *ap) {
69 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
70
71 if (pdev->subsystem_device & (1 << (ap->port_no + 14)))
72 return ATA_CBL_PATA80;
73 return ATA_CBL_PATA40;
74 }
75
76 /**
77 * sun_cable - Sun Cobalt 'Alpine' cable detection
78 * @ap: ATA port to do cable select
79 *
80 * Cobalt CSB5 IDE hides the 40/80pin in the top two bits of the
81 * subsystem ID the same as dell. We could use one function but we may
82 * need to extend the Dell one in future
83 */
84
85 static int sun_cable(struct ata_port *ap) {
86 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
87
88 if (pdev->subsystem_device & (1 << (ap->port_no + 14)))
89 return ATA_CBL_PATA80;
90 return ATA_CBL_PATA40;
91 }
92
93 /**
94 * osb4_cable - OSB4 cable detect
95 * @ap: ATA port to check
96 *
97 * The OSB4 isn't UDMA66 capable so this is easy
98 */
99
100 static int osb4_cable(struct ata_port *ap) {
101 return ATA_CBL_PATA40;
102 }
103
104 /**
105 * csb_cable - CSB5/6 cable detect
106 * @ap: ATA port to check
107 *
108 * Serverworks default arrangement is to use the drive side detection
109 * only.
110 */
111
112 static int csb_cable(struct ata_port *ap) {
113 return ATA_CBL_PATA_UNK;
114 }
115
116 struct sv_cable_table {
117 int device;
118 int subvendor;
119 int (*cable_detect)(struct ata_port *ap);
120 };
121
122 /*
123 * Note that we don't copy the old serverworks code because the old
124 * code contains obvious mistakes
125 */
126
127 static struct sv_cable_table cable_detect[] = {
128 { PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_VENDOR_ID_DELL, dell_cable },
129 { PCI_DEVICE_ID_SERVERWORKS_CSB6IDE, PCI_VENDOR_ID_DELL, dell_cable },
130 { PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_VENDOR_ID_SUN, sun_cable },
131 { PCI_DEVICE_ID_SERVERWORKS_OSB4IDE, PCI_ANY_ID, osb4_cable },
132 { PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_ANY_ID, csb_cable },
133 { PCI_DEVICE_ID_SERVERWORKS_CSB6IDE, PCI_ANY_ID, csb_cable },
134 { PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2, PCI_ANY_ID, csb_cable },
135 { PCI_DEVICE_ID_SERVERWORKS_HT1000IDE, PCI_ANY_ID, csb_cable },
136 { }
137 };
138
139 /**
140 * serverworks_cable_detect - cable detection
141 * @ap: ATA port
142 * @deadline: deadline jiffies for the operation
143 *
144 * Perform cable detection according to the device and subvendor
145 * identifications
146 */
147
148 static int serverworks_cable_detect(struct ata_port *ap)
149 {
150 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
151 struct sv_cable_table *cb = cable_detect;
152
153 while(cb->device) {
154 if (cb->device == pdev->device &&
155 (cb->subvendor == pdev->subsystem_vendor ||
156 cb->subvendor == PCI_ANY_ID)) {
157 return cb->cable_detect(ap);
158 }
159 cb++;
160 }
161
162 BUG();
163 return -1; /* kill compiler warning */
164 }
165
166 /**
167 * serverworks_is_csb - Check for CSB or OSB
168 * @pdev: PCI device to check
169 *
170 * Returns true if the device being checked is known to be a CSB
171 * series device.
172 */
173
174 static u8 serverworks_is_csb(struct pci_dev *pdev)
175 {
176 switch (pdev->device) {
177 case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE:
178 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE:
179 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2:
180 case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE:
181 return 1;
182 default:
183 break;
184 }
185 return 0;
186 }
187
188 /**
189 * serverworks_osb4_filter - mode selection filter
190 * @adev: ATA device
191 * @mask: Mask of proposed modes
192 *
193 * Filter the offered modes for the device to apply controller
194 * specific rules. OSB4 requires no UDMA for disks due to a FIFO
195 * bug we hit.
196 */
197
198 static unsigned long serverworks_osb4_filter(struct ata_device *adev, unsigned long mask)
199 {
200 if (adev->class == ATA_DEV_ATA)
201 mask &= ~ATA_MASK_UDMA;
202 return ata_pci_default_filter(adev, mask);
203 }
204
205
206 /**
207 * serverworks_csb_filter - mode selection filter
208 * @adev: ATA device
209 * @mask: Mask of proposed modes
210 *
211 * Check the blacklist and disable UDMA5 if matched
212 */
213
214 static unsigned long serverworks_csb_filter(struct ata_device *adev, unsigned long mask)
215 {
216 const char *p;
217 char model_num[ATA_ID_PROD_LEN + 1];
218 int i;
219
220 /* Disk, UDMA */
221 if (adev->class != ATA_DEV_ATA)
222 return ata_pci_default_filter(adev, mask);
223
224 /* Actually do need to check */
225 ata_id_c_string(adev->id, model_num, ATA_ID_PROD, sizeof(model_num));
226
227 for (i = 0; (p = csb_bad_ata100[i]) != NULL; i++) {
228 if (!strcmp(p, model_num))
229 <<<<<<< HEAD:drivers/ata/pata_serverworks.c
230 mask &= ~(0x1F << ATA_SHIFT_UDMA);
231 =======
232 mask &= ~(0xE0 << ATA_SHIFT_UDMA);
233 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/ata/pata_serverworks.c
234 }
235 return ata_pci_default_filter(adev, mask);
236 }
237
238 /**
239 * serverworks_set_piomode - set initial PIO mode data
240 * @ap: ATA interface
241 * @adev: ATA device
242 *
243 * Program the OSB4/CSB5 timing registers for PIO. The PIO register
244 * load is done as a simple lookup.
245 */
246 static void serverworks_set_piomode(struct ata_port *ap, struct ata_device *adev)
247 {
248 static const u8 pio_mode[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 };
249 int offset = 1 + 2 * ap->port_no - adev->devno;
250 int devbits = (2 * ap->port_no + adev->devno) * 4;
251 u16 csb5_pio;
252 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
253 int pio = adev->pio_mode - XFER_PIO_0;
254
255 pci_write_config_byte(pdev, 0x40 + offset, pio_mode[pio]);
256
257 /* The OSB4 just requires the timing but the CSB series want the
258 mode number as well */
259 if (serverworks_is_csb(pdev)) {
260 pci_read_config_word(pdev, 0x4A, &csb5_pio);
261 csb5_pio &= ~(0x0F << devbits);
262 pci_write_config_byte(pdev, 0x4A, csb5_pio | (pio << devbits));
263 }
264 }
265
266 /**
267 * serverworks_set_dmamode - set initial DMA mode data
268 * @ap: ATA interface
269 * @adev: ATA device
270 *
271 * Program the MWDMA/UDMA modes for the serverworks OSB4/CSB5
272 * chipset. The MWDMA mode values are pulled from a lookup table
273 * while the chipset uses mode number for UDMA.
274 */
275
276 static void serverworks_set_dmamode(struct ata_port *ap, struct ata_device *adev)
277 {
278 static const u8 dma_mode[] = { 0x77, 0x21, 0x20 };
279 int offset = 1 + 2 * ap->port_no - adev->devno;
280 int devbits = 2 * ap->port_no + adev->devno;
281 u8 ultra;
282 u8 ultra_cfg;
283 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
284
285 pci_read_config_byte(pdev, 0x54, &ultra_cfg);
286 pci_read_config_byte(pdev, 0x56 + ap->port_no, &ultra);
287 ultra &= ~(0x0F << (adev->devno * 4));
288
289 if (adev->dma_mode >= XFER_UDMA_0) {
290 pci_write_config_byte(pdev, 0x44 + offset, 0x20);
291
292 ultra |= (adev->dma_mode - XFER_UDMA_0)
293 << (adev->devno * 4);
294 ultra_cfg |= (1 << devbits);
295 } else {
296 pci_write_config_byte(pdev, 0x44 + offset,
297 dma_mode[adev->dma_mode - XFER_MW_DMA_0]);
298 ultra_cfg &= ~(1 << devbits);
299 }
300 pci_write_config_byte(pdev, 0x56 + ap->port_no, ultra);
301 pci_write_config_byte(pdev, 0x54, ultra_cfg);
302 }
303
304 static struct scsi_host_template serverworks_sht = {
305 .module = THIS_MODULE,
306 .name = DRV_NAME,
307 .ioctl = ata_scsi_ioctl,
308 .queuecommand = ata_scsi_queuecmd,
309 .can_queue = ATA_DEF_QUEUE,
310 .this_id = ATA_SHT_THIS_ID,
311 .sg_tablesize = LIBATA_MAX_PRD,
312 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
313 .emulated = ATA_SHT_EMULATED,
314 .use_clustering = ATA_SHT_USE_CLUSTERING,
315 .proc_name = DRV_NAME,
316 .dma_boundary = ATA_DMA_BOUNDARY,
317 .slave_configure = ata_scsi_slave_config,
318 .slave_destroy = ata_scsi_slave_destroy,
319 .bios_param = ata_std_bios_param,
320 };
321
322 static struct ata_port_operations serverworks_osb4_port_ops = {
323 .set_piomode = serverworks_set_piomode,
324 .set_dmamode = serverworks_set_dmamode,
325 .mode_filter = serverworks_osb4_filter,
326
327 .tf_load = ata_tf_load,
328 .tf_read = ata_tf_read,
329 .check_status = ata_check_status,
330 .exec_command = ata_exec_command,
331 .dev_select = ata_std_dev_select,
332
333 .freeze = ata_bmdma_freeze,
334 .thaw = ata_bmdma_thaw,
335 .error_handler = ata_bmdma_error_handler,
336 .post_internal_cmd = ata_bmdma_post_internal_cmd,
337 .cable_detect = serverworks_cable_detect,
338
339 .bmdma_setup = ata_bmdma_setup,
340 .bmdma_start = ata_bmdma_start,
341 .bmdma_stop = ata_bmdma_stop,
342 .bmdma_status = ata_bmdma_status,
343
344 .qc_prep = ata_qc_prep,
345 .qc_issue = ata_qc_issue_prot,
346
347 .data_xfer = ata_data_xfer,
348
349 .irq_handler = ata_interrupt,
350 .irq_clear = ata_bmdma_irq_clear,
351 .irq_on = ata_irq_on,
352
353 .port_start = ata_sff_port_start,
354 };
355
356 static struct ata_port_operations serverworks_csb_port_ops = {
357 .set_piomode = serverworks_set_piomode,
358 .set_dmamode = serverworks_set_dmamode,
359 .mode_filter = serverworks_csb_filter,
360
361 .tf_load = ata_tf_load,
362 .tf_read = ata_tf_read,
363 .check_status = ata_check_status,
364 .exec_command = ata_exec_command,
365 .dev_select = ata_std_dev_select,
366
367 .freeze = ata_bmdma_freeze,
368 .thaw = ata_bmdma_thaw,
369 .error_handler = ata_bmdma_error_handler,
370 .post_internal_cmd = ata_bmdma_post_internal_cmd,
371 .cable_detect = serverworks_cable_detect,
372
373 .bmdma_setup = ata_bmdma_setup,
374 .bmdma_start = ata_bmdma_start,
375 .bmdma_stop = ata_bmdma_stop,
376 .bmdma_status = ata_bmdma_status,
377
378 .qc_prep = ata_qc_prep,
379 .qc_issue = ata_qc_issue_prot,
380
381 .data_xfer = ata_data_xfer,
382
383 .irq_handler = ata_interrupt,
384 .irq_clear = ata_bmdma_irq_clear,
385 .irq_on = ata_irq_on,
386
387 .port_start = ata_sff_port_start,
388 };
389
390 static int serverworks_fixup_osb4(struct pci_dev *pdev)
391 {
392 u32 reg;
393 struct pci_dev *isa_dev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
394 PCI_DEVICE_ID_SERVERWORKS_OSB4, NULL);
395 if (isa_dev) {
396 pci_read_config_dword(isa_dev, 0x64, &reg);
397 reg &= ~0x00002000; /* disable 600ns interrupt mask */
398 if (!(reg & 0x00004000))
399 printk(KERN_DEBUG DRV_NAME ": UDMA not BIOS enabled.\n");
400 reg |= 0x00004000; /* enable UDMA/33 support */
401 pci_write_config_dword(isa_dev, 0x64, reg);
402 pci_dev_put(isa_dev);
403 return 0;
404 }
405 printk(KERN_WARNING "ata_serverworks: Unable to find bridge.\n");
406 return -ENODEV;
407 }
408
409 static int serverworks_fixup_csb(struct pci_dev *pdev)
410 {
411 u8 btr;
412
413 /* Third Channel Test */
414 if (!(PCI_FUNC(pdev->devfn) & 1)) {
415 struct pci_dev * findev = NULL;
416 u32 reg4c = 0;
417 findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
418 PCI_DEVICE_ID_SERVERWORKS_CSB5, NULL);
419 if (findev) {
420 pci_read_config_dword(findev, 0x4C, &reg4c);
421 reg4c &= ~0x000007FF;
422 reg4c |= 0x00000040;
423 reg4c |= 0x00000020;
424 pci_write_config_dword(findev, 0x4C, reg4c);
425 pci_dev_put(findev);
426 }
427 } else {
428 struct pci_dev * findev = NULL;
429 u8 reg41 = 0;
430
431 findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
432 PCI_DEVICE_ID_SERVERWORKS_CSB6, NULL);
433 if (findev) {
434 pci_read_config_byte(findev, 0x41, &reg41);
435 reg41 &= ~0x40;
436 pci_write_config_byte(findev, 0x41, reg41);
437 pci_dev_put(findev);
438 }
439 }
440 /* setup the UDMA Control register
441 *
442 * 1. clear bit 6 to enable DMA
443 * 2. enable DMA modes with bits 0-1
444 * 00 : legacy
445 * 01 : udma2
446 * 10 : udma2/udma4
447 * 11 : udma2/udma4/udma5
448 */
449 pci_read_config_byte(pdev, 0x5A, &btr);
450 btr &= ~0x40;
451 if (!(PCI_FUNC(pdev->devfn) & 1))
452 btr |= 0x2;
453 else
454 btr |= (pdev->revision >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2;
455 pci_write_config_byte(pdev, 0x5A, btr);
456
457 return btr;
458 }
459
460 static void serverworks_fixup_ht1000(struct pci_dev *pdev)
461 {
462 u8 btr;
463 /* Setup HT1000 SouthBridge Controller - Single Channel Only */
464 pci_read_config_byte(pdev, 0x5A, &btr);
465 btr &= ~0x40;
466 btr |= 0x3;
467 pci_write_config_byte(pdev, 0x5A, btr);
468 }
469
470
471 static int serverworks_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
472 {
473 static const struct ata_port_info info[4] = {
474 { /* OSB4 */
475 .sht = &serverworks_sht,
476 .flags = ATA_FLAG_SLAVE_POSS,
477 .pio_mask = 0x1f,
478 .mwdma_mask = 0x07,
479 .udma_mask = 0x07,
480 .port_ops = &serverworks_osb4_port_ops
481 }, { /* OSB4 no UDMA */
482 .sht = &serverworks_sht,
483 .flags = ATA_FLAG_SLAVE_POSS,
484 .pio_mask = 0x1f,
485 .mwdma_mask = 0x07,
486 .udma_mask = 0x00,
487 .port_ops = &serverworks_osb4_port_ops
488 }, { /* CSB5 */
489 .sht = &serverworks_sht,
490 .flags = ATA_FLAG_SLAVE_POSS,
491 .pio_mask = 0x1f,
492 .mwdma_mask = 0x07,
493 .udma_mask = ATA_UDMA4,
494 .port_ops = &serverworks_csb_port_ops
495 }, { /* CSB5 - later revisions*/
496 .sht = &serverworks_sht,
497 .flags = ATA_FLAG_SLAVE_POSS,
498 .pio_mask = 0x1f,
499 .mwdma_mask = 0x07,
500 .udma_mask = ATA_UDMA5,
501 .port_ops = &serverworks_csb_port_ops
502 }
503 };
504 const struct ata_port_info *ppi[] = { &info[id->driver_data], NULL };
505
506 /* Force master latency timer to 64 PCI clocks */
507 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x40);
508
509 /* OSB4 : South Bridge and IDE */
510 if (pdev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
511 /* Select non UDMA capable OSB4 if we can't do fixups */
512 if ( serverworks_fixup_osb4(pdev) < 0)
513 ppi[0] = &info[1];
514 }
515 /* setup CSB5/CSB6 : South Bridge and IDE option RAID */
516 else if ((pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) ||
517 (pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
518 (pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) {
519
520 /* If the returned btr is the newer revision then
521 select the right info block */
522 if (serverworks_fixup_csb(pdev) == 3)
523 ppi[0] = &info[3];
524
525 /* Is this the 3rd channel CSB6 IDE ? */
526 if (pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)
527 ppi[1] = &ata_dummy_port_info;
528 }
529 /* setup HT1000E */
530 else if (pdev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE)
531 serverworks_fixup_ht1000(pdev);
532
533 if (pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE)
534 ata_pci_clear_simplex(pdev);
535
536 return ata_pci_init_one(pdev, ppi);
537 }
538
539 #ifdef CONFIG_PM
540 static int serverworks_reinit_one(struct pci_dev *pdev)
541 {
542 /* Force master latency timer to 64 PCI clocks */
543 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x40);
544
545 switch (pdev->device)
546 {
547 case PCI_DEVICE_ID_SERVERWORKS_OSB4IDE:
548 serverworks_fixup_osb4(pdev);
549 break;
550 case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE:
551 ata_pci_clear_simplex(pdev);
552 /* fall through */
553 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE:
554 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2:
555 serverworks_fixup_csb(pdev);
556 break;
557 case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE:
558 serverworks_fixup_ht1000(pdev);
559 break;
560 }
561 return ata_pci_device_resume(pdev);
562 }
563 #endif
564
565 static const struct pci_device_id serverworks[] = {
566 { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4IDE), 0},
567 { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE), 2},
568 { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE), 2},
569 { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2), 2},
570 { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000IDE), 2},
571
572 { },
573 };
574
575 static struct pci_driver serverworks_pci_driver = {
576 .name = DRV_NAME,
577 .id_table = serverworks,
578 .probe = serverworks_init_one,
579 .remove = ata_pci_remove_one,
580 #ifdef CONFIG_PM
581 .suspend = ata_pci_device_suspend,
582 .resume = serverworks_reinit_one,
583 #endif
584 };
585
586 static int __init serverworks_init(void)
587 {
588 return pci_register_driver(&serverworks_pci_driver);
589 }
590
591 static void __exit serverworks_exit(void)
592 {
593 pci_unregister_driver(&serverworks_pci_driver);
594 }
595
596 MODULE_AUTHOR("Alan Cox");
597 MODULE_DESCRIPTION("low-level driver for Serverworks OSB4/CSB5/CSB6");
598 MODULE_LICENSE("GPL");
599 MODULE_DEVICE_TABLE(pci, serverworks);
600 MODULE_VERSION(DRV_VERSION);
601
602 module_init(serverworks_init);
603 module_exit(serverworks_exit);
WRT350N Kernel Patches