drivers/char/agp/sworks-agp.c

   1 /*
   2  * Serverworks AGPGART routines.
   3  */
   4
   5 #include <linux/module.h>
   6 #include <linux/pci.h>
   7 #include <linux/init.h>
   8 #include <linux/string.h>
   9 #include <linux/slab.h>
  10 #include <linux/jiffies.h>
  11 #include <linux/agp_backend.h>
  12 #include "agp.h"
  13
  14 #define SVWRKS_COMMAND          0x04
  15 #define SVWRKS_APSIZE           0x10
  16 #define SVWRKS_MMBASE           0x14
  17 #define SVWRKS_CACHING          0x4b
  18 #define SVWRKS_AGP_ENABLE       0x60
  19 #define SVWRKS_FEATURE          0x68
  20
  21 #define SVWRKS_SIZE_MASK        0xfe000000
  22
  23 /* Memory mapped registers */
  24 #define SVWRKS_GART_CACHE       0x02
  25 #define SVWRKS_GATTBASE         0x04
  26 #define SVWRKS_TLBFLUSH         0x10
  27 #define SVWRKS_POSTFLUSH        0x14
  28 #define SVWRKS_DIRFLUSH         0x0c
  29
  30
  31 struct serverworks_page_map {
  32         unsigned long *real;
  33         unsigned long __iomem *remapped;
  34 };
  35
  36 static struct _serverworks_private {
  37         struct pci_dev *svrwrks_dev;    /* device one */
  38         volatile u8 __iomem *registers;
  39         struct serverworks_page_map **gatt_pages;
  40         int num_tables;
  41         struct serverworks_page_map scratch_dir;
  42
  43         int gart_addr_ofs;
  44         int mm_addr_ofs;
  45 } serverworks_private;
  46
  47 static int serverworks_create_page_map(struct serverworks_page_map *page_map)
  48 {
  49         int i;
  50
  51         page_map->real = (unsigned long *) __get_free_page(GFP_KERNEL);
  52         if (page_map->real == NULL) {
  53                 return -ENOMEM;
  54         }
  55 <<<<<<< HEAD:drivers/char/agp/sworks-agp.c
  56         SetPageReserved(virt_to_page(page_map->real));
  57         global_cache_flush();
  58         page_map->remapped = ioremap_nocache(virt_to_gart(page_map->real),
  59                                             PAGE_SIZE);
  60         if (page_map->remapped == NULL) {
  61                 ClearPageReserved(virt_to_page(page_map->real));
  62                 free_page((unsigned long) page_map->real);
  63                 page_map->real = NULL;
  64                 return -ENOMEM;
  65         }
  66         global_cache_flush();
  67 =======
  68
  69         set_memory_uc((unsigned long)page_map->real, 1);
  70         page_map->remapped = page_map->real;
  71 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/char/agp/sworks-agp.c
  72
  73         for (i = 0; i < PAGE_SIZE / sizeof(unsigned long); i++)
  74                 writel(agp_bridge->scratch_page, page_map->remapped+i);
  75 <<<<<<< HEAD:drivers/char/agp/sworks-agp.c
  76 =======
  77                 /* Red Pen: Everyone else does pci posting flush here */
  78 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/char/agp/sworks-agp.c
  79
  80         return 0;
  81 }
  82
  83 static void serverworks_free_page_map(struct serverworks_page_map *page_map)
  84 {
  85 <<<<<<< HEAD:drivers/char/agp/sworks-agp.c
  86         iounmap(page_map->remapped);
  87         ClearPageReserved(virt_to_page(page_map->real));
  88 =======
  89         set_memory_wb((unsigned long)page_map->real, 1);
  90 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/char/agp/sworks-agp.c
  91         free_page((unsigned long) page_map->real);
  92 }
  93
  94 static void serverworks_free_gatt_pages(void)
  95 {
  96         int i;
  97         struct serverworks_page_map **tables;
  98         struct serverworks_page_map *entry;
  99
 100         tables = serverworks_private.gatt_pages;
 101         for (i = 0; i < serverworks_private.num_tables; i++) {
 102                 entry = tables[i];
 103                 if (entry != NULL) {
 104                         if (entry->real != NULL) {
 105                                 serverworks_free_page_map(entry);
 106                         }
 107                         kfree(entry);
 108                 }
 109         }
 110         kfree(tables);
 111 }
 112
 113 static int serverworks_create_gatt_pages(int nr_tables)
 114 {
 115         struct serverworks_page_map **tables;
 116         struct serverworks_page_map *entry;
 117         int retval = 0;
 118         int i;
 119
 120         tables = kzalloc((nr_tables + 1) * sizeof(struct serverworks_page_map *),
 121                          GFP_KERNEL);
 122         if (tables == NULL)
 123                 return -ENOMEM;
 124
 125         for (i = 0; i < nr_tables; i++) {
 126                 entry = kzalloc(sizeof(struct serverworks_page_map), GFP_KERNEL);
 127                 if (entry == NULL) {
 128                         retval = -ENOMEM;
 129                         break;
 130                 }
 131                 tables[i] = entry;
 132                 retval = serverworks_create_page_map(entry);
 133                 if (retval != 0) break;
 134         }
 135         serverworks_private.num_tables = nr_tables;
 136         serverworks_private.gatt_pages = tables;
 137
 138         if (retval != 0) serverworks_free_gatt_pages();
 139
 140         return retval;
 141 }
 142
 143 #define SVRWRKS_GET_GATT(addr) (serverworks_private.gatt_pages[\
 144         GET_PAGE_DIR_IDX(addr)]->remapped)
 145
 146 #ifndef GET_PAGE_DIR_OFF
 147 #define GET_PAGE_DIR_OFF(addr) (addr >> 22)
 148 #endif
 149
 150 #ifndef GET_PAGE_DIR_IDX
 151 #define GET_PAGE_DIR_IDX(addr) (GET_PAGE_DIR_OFF(addr) - \
 152         GET_PAGE_DIR_OFF(agp_bridge->gart_bus_addr))
 153 #endif
 154
 155 #ifndef GET_GATT_OFF
 156 #define GET_GATT_OFF(addr) ((addr & 0x003ff000) >> 12)
 157 #endif
 158
 159 static int serverworks_create_gatt_table(struct agp_bridge_data *bridge)
 160 {
 161         struct aper_size_info_lvl2 *value;
 162         struct serverworks_page_map page_dir;
 163         int retval;
 164         u32 temp;
 165         int i;
 166
 167         value = A_SIZE_LVL2(agp_bridge->current_size);
 168         retval = serverworks_create_page_map(&page_dir);
 169         if (retval != 0) {
 170                 return retval;
 171         }
 172         retval = serverworks_create_page_map(&serverworks_private.scratch_dir);
 173         if (retval != 0) {
 174                 serverworks_free_page_map(&page_dir);
 175                 return retval;
 176         }
 177         /* Create a fake scratch directory */
 178         for (i = 0; i < 1024; i++) {
 179                 writel(agp_bridge->scratch_page, serverworks_private.scratch_dir.remapped+i);
 180                 writel(virt_to_gart(serverworks_private.scratch_dir.real) | 1, page_dir.remapped+i);
 181         }
 182
 183         retval = serverworks_create_gatt_pages(value->num_entries / 1024);
 184         if (retval != 0) {
 185                 serverworks_free_page_map(&page_dir);
 186                 serverworks_free_page_map(&serverworks_private.scratch_dir);
 187                 return retval;
 188         }
 189
 190         agp_bridge->gatt_table_real = (u32 *)page_dir.real;
 191         agp_bridge->gatt_table = (u32 __iomem *)page_dir.remapped;
 192         agp_bridge->gatt_bus_addr = virt_to_gart(page_dir.real);
 193
 194         /* Get the address for the gart region.
 195          * This is a bus address even on the alpha, b/c its
 196          * used to program the agp master not the cpu
 197          */
 198
 199         pci_read_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,&temp);
 200         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
 201
 202         /* Calculate the agp offset */
 203         for (i = 0; i < value->num_entries / 1024; i++)
 204                 writel(virt_to_gart(serverworks_private.gatt_pages[i]->real)|1, page_dir.remapped+i);
 205
 206         return 0;
 207 }
 208
 209 static int serverworks_free_gatt_table(struct agp_bridge_data *bridge)
 210 {
 211         struct serverworks_page_map page_dir;
 212
 213         page_dir.real = (unsigned long *)agp_bridge->gatt_table_real;
 214         page_dir.remapped = (unsigned long __iomem *)agp_bridge->gatt_table;
 215
 216         serverworks_free_gatt_pages();
 217         serverworks_free_page_map(&page_dir);
 218         serverworks_free_page_map(&serverworks_private.scratch_dir);
 219         return 0;
 220 }
 221
 222 static int serverworks_fetch_size(void)
 223 {
 224         int i;
 225         u32 temp;
 226         u32 temp2;
 227         struct aper_size_info_lvl2 *values;
 228
 229         values = A_SIZE_LVL2(agp_bridge->driver->aperture_sizes);
 230         pci_read_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,&temp);
 231         pci_write_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,
 232                                         SVWRKS_SIZE_MASK);
 233         pci_read_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,&temp2);
 234         pci_write_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,temp);
 235         temp2 &= SVWRKS_SIZE_MASK;
 236
 237         for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
 238                 if (temp2 == values[i].size_value) {
 239                         agp_bridge->previous_size =
 240                             agp_bridge->current_size = (void *) (values + i);
 241
 242                         agp_bridge->aperture_size_idx = i;
 243                         return values[i].size;
 244                 }
 245         }
 246
 247         return 0;
 248 }
 249
 250 /*
 251  * This routine could be implemented by taking the addresses
 252  * written to the GATT, and flushing them individually.  However
 253  * currently it just flushes the whole table.  Which is probably
 254  * more efficent, since agp_memory blocks can be a large number of
 255  * entries.
 256  */
 257 static void serverworks_tlbflush(struct agp_memory *temp)
 258 {
 259         unsigned long timeout;
 260
 261         writeb(1, serverworks_private.registers+SVWRKS_POSTFLUSH);
 262         timeout = jiffies + 3*HZ;
 263         while (readb(serverworks_private.registers+SVWRKS_POSTFLUSH) == 1) {
 264                 cpu_relax();
 265                 if (time_after(jiffies, timeout)) {
 266                         printk(KERN_ERR PFX "TLB post flush took more than 3 seconds\n");
 267                         break;
 268                 }
 269         }
 270
 271         writel(1, serverworks_private.registers+SVWRKS_DIRFLUSH);
 272         timeout = jiffies + 3*HZ;
 273         while (readl(serverworks_private.registers+SVWRKS_DIRFLUSH) == 1) {
 274                 cpu_relax();
 275                 if (time_after(jiffies, timeout)) {
 276                         printk(KERN_ERR PFX "TLB Dir flush took more than 3 seconds\n");
 277                         break;
 278                 }
 279         }
 280 }
 281
 282 static int serverworks_configure(void)
 283 {
 284         struct aper_size_info_lvl2 *current_size;
 285         u32 temp;
 286         u8 enable_reg;
 287         u16 cap_reg;
 288
 289         current_size = A_SIZE_LVL2(agp_bridge->current_size);
 290
 291         /* Get the memory mapped registers */
 292         pci_read_config_dword(agp_bridge->dev, serverworks_private.mm_addr_ofs, &temp);
 293         temp = (temp & PCI_BASE_ADDRESS_MEM_MASK);
 294         serverworks_private.registers = (volatile u8 __iomem *) ioremap(temp, 4096);
 295         if (!serverworks_private.registers) {
 296                 printk (KERN_ERR PFX "Unable to ioremap() memory.\n");
 297                 return -ENOMEM;
 298         }
 299
 300         writeb(0xA, serverworks_private.registers+SVWRKS_GART_CACHE);
 301         readb(serverworks_private.registers+SVWRKS_GART_CACHE); /* PCI Posting. */
 302
 303         writel(agp_bridge->gatt_bus_addr, serverworks_private.registers+SVWRKS_GATTBASE);
 304         readl(serverworks_private.registers+SVWRKS_GATTBASE);   /* PCI Posting. */
 305
 306         cap_reg = readw(serverworks_private.registers+SVWRKS_COMMAND);
 307         cap_reg &= ~0x0007;
 308         cap_reg |= 0x4;
 309         writew(cap_reg, serverworks_private.registers+SVWRKS_COMMAND);
 310         readw(serverworks_private.registers+SVWRKS_COMMAND);
 311
 312         pci_read_config_byte(serverworks_private.svrwrks_dev,SVWRKS_AGP_ENABLE, &enable_reg);
 313         enable_reg |= 0x1; /* Agp Enable bit */
 314         pci_write_config_byte(serverworks_private.svrwrks_dev,SVWRKS_AGP_ENABLE, enable_reg);
 315         serverworks_tlbflush(NULL);
 316
 317         agp_bridge->capndx = pci_find_capability(serverworks_private.svrwrks_dev, PCI_CAP_ID_AGP);
 318
 319         /* Fill in the mode register */
 320         pci_read_config_dword(serverworks_private.svrwrks_dev,
 321                               agp_bridge->capndx+PCI_AGP_STATUS, &agp_bridge->mode);
 322
 323         pci_read_config_byte(agp_bridge->dev, SVWRKS_CACHING, &enable_reg);
 324         enable_reg &= ~0x3;
 325         pci_write_config_byte(agp_bridge->dev, SVWRKS_CACHING, enable_reg);
 326
 327         pci_read_config_byte(agp_bridge->dev, SVWRKS_FEATURE, &enable_reg);
 328         enable_reg |= (1<<6);
 329         pci_write_config_byte(agp_bridge->dev,SVWRKS_FEATURE, enable_reg);
 330
 331         return 0;
 332 }
 333
 334 static void serverworks_cleanup(void)
 335 {
 336         iounmap((void __iomem *) serverworks_private.registers);
 337 }
 338
 339 static int serverworks_insert_memory(struct agp_memory *mem,
 340                              off_t pg_start, int type)
 341 {
 342         int i, j, num_entries;
 343         unsigned long __iomem *cur_gatt;
 344         unsigned long addr;
 345
 346         num_entries = A_SIZE_LVL2(agp_bridge->current_size)->num_entries;
 347
 348         if (type != 0 || mem->type != 0) {
 349                 return -EINVAL;
 350         }
 351         if ((pg_start + mem->page_count) > num_entries) {
 352                 return -EINVAL;
 353         }
 354
 355         j = pg_start;
 356         while (j < (pg_start + mem->page_count)) {
 357                 addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr;
 358                 cur_gatt = SVRWRKS_GET_GATT(addr);
 359                 if (!PGE_EMPTY(agp_bridge, readl(cur_gatt+GET_GATT_OFF(addr))))
 360                         return -EBUSY;
 361                 j++;
 362         }
 363
 364         if (mem->is_flushed == FALSE) {
 365                 global_cache_flush();
 366                 mem->is_flushed = TRUE;
 367         }
 368
 369         for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
 370                 addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr;
 371                 cur_gatt = SVRWRKS_GET_GATT(addr);
 372                 writel(agp_bridge->driver->mask_memory(agp_bridge, mem->memory[i], mem->type), cur_gatt+GET_GATT_OFF(addr));
 373         }
 374         serverworks_tlbflush(mem);
 375         return 0;
 376 }
 377
 378 static int serverworks_remove_memory(struct agp_memory *mem, off_t pg_start,
 379                              int type)
 380 {
 381         int i;
 382         unsigned long __iomem *cur_gatt;
 383         unsigned long addr;
 384
 385         if (type != 0 || mem->type != 0) {
 386                 return -EINVAL;
 387         }
 388
 389         global_cache_flush();
 390         serverworks_tlbflush(mem);
 391
 392         for (i = pg_start; i < (mem->page_count + pg_start); i++) {
 393                 addr = (i * PAGE_SIZE) + agp_bridge->gart_bus_addr;
 394                 cur_gatt = SVRWRKS_GET_GATT(addr);
 395                 writel(agp_bridge->scratch_page, cur_gatt+GET_GATT_OFF(addr));
 396         }
 397
 398         serverworks_tlbflush(mem);
 399         return 0;
 400 }
 401
 402 static const struct gatt_mask serverworks_masks[] =
 403 {
 404         {.mask = 1, .type = 0}
 405 };
 406
 407 static const struct aper_size_info_lvl2 serverworks_sizes[7] =
 408 {
 409         {2048, 524288, 0x80000000},
 410         {1024, 262144, 0xc0000000},
 411         {512, 131072, 0xe0000000},
 412         {256, 65536, 0xf0000000},
 413         {128, 32768, 0xf8000000},
 414         {64, 16384, 0xfc000000},
 415         {32, 8192, 0xfe000000}
 416 };
 417
 418 static void serverworks_agp_enable(struct agp_bridge_data *bridge, u32 mode)
 419 {
 420         u32 command;
 421
 422         pci_read_config_dword(serverworks_private.svrwrks_dev,
 423                               bridge->capndx + PCI_AGP_STATUS,
 424                               &command);
 425
 426         command = agp_collect_device_status(bridge, mode, command);
 427
 428         command &= ~0x10;       /* disable FW */
 429         command &= ~0x08;
 430
 431         command |= 0x100;
 432
 433         pci_write_config_dword(serverworks_private.svrwrks_dev,
 434                                bridge->capndx + PCI_AGP_COMMAND,
 435                                command);
 436
 437         agp_device_command(command, 0);
 438 }
 439
 440 static const struct agp_bridge_driver sworks_driver = {
 441         .owner                  = THIS_MODULE,
 442         .aperture_sizes         = serverworks_sizes,
 443         .size_type              = LVL2_APER_SIZE,
 444         .num_aperture_sizes     = 7,
 445         .configure              = serverworks_configure,
 446         .fetch_size             = serverworks_fetch_size,
 447         .cleanup                = serverworks_cleanup,
 448         .tlb_flush              = serverworks_tlbflush,
 449         .mask_memory            = agp_generic_mask_memory,
 450         .masks                  = serverworks_masks,
 451         .agp_enable             = serverworks_agp_enable,
 452         .cache_flush            = global_cache_flush,
 453         .create_gatt_table      = serverworks_create_gatt_table,
 454         .free_gatt_table        = serverworks_free_gatt_table,
 455         .insert_memory          = serverworks_insert_memory,
 456         .remove_memory          = serverworks_remove_memory,
 457         .alloc_by_type          = agp_generic_alloc_by_type,
 458         .free_by_type           = agp_generic_free_by_type,
 459         .agp_alloc_page         = agp_generic_alloc_page,
 460         .agp_destroy_page       = agp_generic_destroy_page,
 461         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
 462 };
 463
 464 static int __devinit agp_serverworks_probe(struct pci_dev *pdev,
 465                                            const struct pci_device_id *ent)
 466 {
 467         struct agp_bridge_data *bridge;
 468         struct pci_dev *bridge_dev;
 469         u32 temp, temp2;
 470         u8 cap_ptr = 0;
 471
 472         cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
 473
 474         switch (pdev->device) {
 475         case 0x0006:
 476                 printk (KERN_ERR PFX "ServerWorks CNB20HE is unsupported due to lack of documentation.\n");
 477                 return -ENODEV;
 478
 479         case PCI_DEVICE_ID_SERVERWORKS_HE:
 480         case PCI_DEVICE_ID_SERVERWORKS_LE:
 481         case 0x0007:
 482                 break;
 483
 484         default:
 485                 if (cap_ptr)
 486                         printk(KERN_ERR PFX "Unsupported Serverworks chipset "
 487                                         "(device id: %04x)\n", pdev->device);
 488                 return -ENODEV;
 489         }
 490
 491         /* Everything is on func 1 here so we are hardcoding function one */
 492         bridge_dev = pci_get_bus_and_slot((unsigned int)pdev->bus->number,
 493                         PCI_DEVFN(0, 1));
 494         if (!bridge_dev) {
 495                 printk(KERN_INFO PFX "Detected a Serverworks chipset "
 496                        "but could not find the secondary device.\n");
 497                 return -ENODEV;
 498         }
 499
 500         serverworks_private.svrwrks_dev = bridge_dev;
 501         serverworks_private.gart_addr_ofs = 0x10;
 502
 503         pci_read_config_dword(pdev, SVWRKS_APSIZE, &temp);
 504         if (temp & PCI_BASE_ADDRESS_MEM_TYPE_64) {
 505                 pci_read_config_dword(pdev, SVWRKS_APSIZE + 4, &temp2);
 506                 if (temp2 != 0) {
 507                         printk(KERN_INFO PFX "Detected 64 bit aperture address, "
 508                                "but top bits are not zero.  Disabling agp\n");
 509                         return -ENODEV;
 510                 }
 511                 serverworks_private.mm_addr_ofs = 0x18;
 512         } else
 513                 serverworks_private.mm_addr_ofs = 0x14;
 514
 515         pci_read_config_dword(pdev, serverworks_private.mm_addr_ofs, &temp);
 516         if (temp & PCI_BASE_ADDRESS_MEM_TYPE_64) {
 517                 pci_read_config_dword(pdev,
 518                                 serverworks_private.mm_addr_ofs + 4, &temp2);
 519                 if (temp2 != 0) {
 520                         printk(KERN_INFO PFX "Detected 64 bit MMIO address, "
 521                                "but top bits are not zero.  Disabling agp\n");
 522                         return -ENODEV;
 523                 }
 524         }
 525
 526         bridge = agp_alloc_bridge();
 527         if (!bridge)
 528                 return -ENOMEM;
 529
 530         bridge->driver = &sworks_driver;
 531         bridge->dev_private_data = &serverworks_private,
 532         bridge->dev = pci_dev_get(pdev);
 533
 534         pci_set_drvdata(pdev, bridge);
 535         return agp_add_bridge(bridge);
 536 }
 537
 538 static void __devexit agp_serverworks_remove(struct pci_dev *pdev)
 539 {
 540         struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
 541
 542         pci_dev_put(bridge->dev);
 543         agp_remove_bridge(bridge);
 544         agp_put_bridge(bridge);
 545         pci_dev_put(serverworks_private.svrwrks_dev);
 546         serverworks_private.svrwrks_dev = NULL;
 547 }
 548
 549 static struct pci_device_id agp_serverworks_pci_table[] = {
 550         {
 551         .class          = (PCI_CLASS_BRIDGE_HOST << 8),
 552         .class_mask     = ~0,
 553         .vendor         = PCI_VENDOR_ID_SERVERWORKS,
 554         .device         = PCI_ANY_ID,
 555         .subvendor      = PCI_ANY_ID,
 556         .subdevice      = PCI_ANY_ID,
 557         },
 558         { }
 559 };
 560
 561 MODULE_DEVICE_TABLE(pci, agp_serverworks_pci_table);
 562
 563 static struct pci_driver agp_serverworks_pci_driver = {
 564         .name           = "agpgart-serverworks",
 565         .id_table       = agp_serverworks_pci_table,
 566         .probe          = agp_serverworks_probe,
 567         .remove         = agp_serverworks_remove,
 568 };
 569
 570 static int __init agp_serverworks_init(void)
 571 {
 572         if (agp_off)
 573                 return -EINVAL;
 574         return pci_register_driver(&agp_serverworks_pci_driver);
 575 }
 576
 577 static void __exit agp_serverworks_cleanup(void)
 578 {
 579         pci_unregister_driver(&agp_serverworks_pci_driver);
 580 }
 581
 582 module_init(agp_serverworks_init);
 583 module_exit(agp_serverworks_cleanup);
 584
 585 MODULE_LICENSE("GPL and additional rights");
 586