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Merge git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
[wrt350n-kernel.git] / drivers / char / drm / radeon_cp.c
blob19b659791f8f3d9209da6b57d249d5811c557fac
1 /* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */
2 /*
3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
25 *
26 * Authors:
27 * Kevin E. Martin <martin@valinux.com>
28 * Gareth Hughes <gareth@valinux.com>
29 */
30
31 #include "drmP.h"
32 #include "drm.h"
33 #include "radeon_drm.h"
34 #include "radeon_drv.h"
35 #include "r300_reg.h"
36
37 #define RADEON_FIFO_DEBUG 0
38
39 static int radeon_do_cleanup_cp(struct drm_device * dev);
40
41 /* CP microcode (from ATI) */
42 static const u32 R200_cp_microcode[][2] = {
43 {0x21007000, 0000000000},
44 {0x20007000, 0000000000},
45 {0x000000ab, 0x00000004},
46 {0x000000af, 0x00000004},
47 {0x66544a49, 0000000000},
48 {0x49494174, 0000000000},
49 {0x54517d83, 0000000000},
50 {0x498d8b64, 0000000000},
51 {0x49494949, 0000000000},
52 {0x49da493c, 0000000000},
53 {0x49989898, 0000000000},
54 {0xd34949d5, 0000000000},
55 {0x9dc90e11, 0000000000},
56 {0xce9b9b9b, 0000000000},
57 {0x000f0000, 0x00000016},
58 {0x352e232c, 0000000000},
59 {0x00000013, 0x00000004},
60 {0x000f0000, 0x00000016},
61 {0x352e272c, 0000000000},
62 {0x000f0001, 0x00000016},
63 {0x3239362f, 0000000000},
64 {0x000077ef, 0x00000002},
65 {0x00061000, 0x00000002},
66 {0x00000020, 0x0000001a},
67 {0x00004000, 0x0000001e},
68 {0x00061000, 0x00000002},
69 {0x00000020, 0x0000001a},
70 {0x00004000, 0x0000001e},
71 {0x00061000, 0x00000002},
72 {0x00000020, 0x0000001a},
73 {0x00004000, 0x0000001e},
74 {0x00000016, 0x00000004},
75 {0x0003802a, 0x00000002},
76 {0x040067e0, 0x00000002},
77 {0x00000016, 0x00000004},
78 {0x000077e0, 0x00000002},
79 {0x00065000, 0x00000002},
80 {0x000037e1, 0x00000002},
81 {0x040067e1, 0x00000006},
82 {0x000077e0, 0x00000002},
83 {0x000077e1, 0x00000002},
84 {0x000077e1, 0x00000006},
85 {0xffffffff, 0000000000},
86 {0x10000000, 0000000000},
87 {0x0003802a, 0x00000002},
88 {0x040067e0, 0x00000006},
89 {0x00007675, 0x00000002},
90 {0x00007676, 0x00000002},
91 {0x00007677, 0x00000002},
92 {0x00007678, 0x00000006},
93 {0x0003802b, 0x00000002},
94 {0x04002676, 0x00000002},
95 {0x00007677, 0x00000002},
96 {0x00007678, 0x00000006},
97 {0x0000002e, 0x00000018},
98 {0x0000002e, 0x00000018},
99 {0000000000, 0x00000006},
100 {0x0000002f, 0x00000018},
101 {0x0000002f, 0x00000018},
102 {0000000000, 0x00000006},
103 {0x01605000, 0x00000002},
104 {0x00065000, 0x00000002},
105 {0x00098000, 0x00000002},
106 {0x00061000, 0x00000002},
107 {0x64c0603d, 0x00000004},
108 {0x00080000, 0x00000016},
109 {0000000000, 0000000000},
110 {0x0400251d, 0x00000002},
111 {0x00007580, 0x00000002},
112 {0x00067581, 0x00000002},
113 {0x04002580, 0x00000002},
114 {0x00067581, 0x00000002},
115 {0x00000046, 0x00000004},
116 {0x00005000, 0000000000},
117 {0x00061000, 0x00000002},
118 {0x0000750e, 0x00000002},
119 {0x00019000, 0x00000002},
120 {0x00011055, 0x00000014},
121 {0x00000055, 0x00000012},
122 {0x0400250f, 0x00000002},
123 {0x0000504a, 0x00000004},
124 {0x00007565, 0x00000002},
125 {0x00007566, 0x00000002},
126 {0x00000051, 0x00000004},
127 {0x01e655b4, 0x00000002},
128 {0x4401b0dc, 0x00000002},
129 {0x01c110dc, 0x00000002},
130 {0x2666705d, 0x00000018},
131 {0x040c2565, 0x00000002},
132 {0x0000005d, 0x00000018},
133 {0x04002564, 0x00000002},
134 {0x00007566, 0x00000002},
135 {0x00000054, 0x00000004},
136 {0x00401060, 0x00000008},
137 {0x00101000, 0x00000002},
138 {0x000d80ff, 0x00000002},
139 {0x00800063, 0x00000008},
140 {0x000f9000, 0x00000002},
141 {0x000e00ff, 0x00000002},
142 {0000000000, 0x00000006},
143 {0x00000080, 0x00000018},
144 {0x00000054, 0x00000004},
145 {0x00007576, 0x00000002},
146 {0x00065000, 0x00000002},
147 {0x00009000, 0x00000002},
148 {0x00041000, 0x00000002},
149 {0x0c00350e, 0x00000002},
150 {0x00049000, 0x00000002},
151 {0x00051000, 0x00000002},
152 {0x01e785f8, 0x00000002},
153 {0x00200000, 0x00000002},
154 {0x00600073, 0x0000000c},
155 {0x00007563, 0x00000002},
156 {0x006075f0, 0x00000021},
157 {0x20007068, 0x00000004},
158 {0x00005068, 0x00000004},
159 {0x00007576, 0x00000002},
160 {0x00007577, 0x00000002},
161 {0x0000750e, 0x00000002},
162 {0x0000750f, 0x00000002},
163 {0x00a05000, 0x00000002},
164 {0x00600076, 0x0000000c},
165 {0x006075f0, 0x00000021},
166 {0x000075f8, 0x00000002},
167 {0x00000076, 0x00000004},
168 {0x000a750e, 0x00000002},
169 {0x0020750f, 0x00000002},
170 {0x00600079, 0x00000004},
171 {0x00007570, 0x00000002},
172 {0x00007571, 0x00000002},
173 {0x00007572, 0x00000006},
174 {0x00005000, 0x00000002},
175 {0x00a05000, 0x00000002},
176 {0x00007568, 0x00000002},
177 {0x00061000, 0x00000002},
178 {0x00000084, 0x0000000c},
179 {0x00058000, 0x00000002},
180 {0x0c607562, 0x00000002},
181 {0x00000086, 0x00000004},
182 {0x00600085, 0x00000004},
183 {0x400070dd, 0000000000},
184 {0x000380dd, 0x00000002},
185 {0x00000093, 0x0000001c},
186 {0x00065095, 0x00000018},
187 {0x040025bb, 0x00000002},
188 {0x00061096, 0x00000018},
189 {0x040075bc, 0000000000},
190 {0x000075bb, 0x00000002},
191 {0x000075bc, 0000000000},
192 {0x00090000, 0x00000006},
193 {0x00090000, 0x00000002},
194 {0x000d8002, 0x00000006},
195 {0x00005000, 0x00000002},
196 {0x00007821, 0x00000002},
197 {0x00007800, 0000000000},
198 {0x00007821, 0x00000002},
199 {0x00007800, 0000000000},
200 {0x01665000, 0x00000002},
201 {0x000a0000, 0x00000002},
202 {0x000671cc, 0x00000002},
203 {0x0286f1cd, 0x00000002},
204 {0x000000a3, 0x00000010},
205 {0x21007000, 0000000000},
206 {0x000000aa, 0x0000001c},
207 {0x00065000, 0x00000002},
208 {0x000a0000, 0x00000002},
209 {0x00061000, 0x00000002},
210 {0x000b0000, 0x00000002},
211 {0x38067000, 0x00000002},
212 {0x000a00a6, 0x00000004},
213 {0x20007000, 0000000000},
214 {0x01200000, 0x00000002},
215 {0x20077000, 0x00000002},
216 {0x01200000, 0x00000002},
217 {0x20007000, 0000000000},
218 {0x00061000, 0x00000002},
219 {0x0120751b, 0x00000002},
220 {0x8040750a, 0x00000002},
221 {0x8040750b, 0x00000002},
222 {0x00110000, 0x00000002},
223 {0x000380dd, 0x00000002},
224 {0x000000bd, 0x0000001c},
225 {0x00061096, 0x00000018},
226 {0x844075bd, 0x00000002},
227 {0x00061095, 0x00000018},
228 {0x840075bb, 0x00000002},
229 {0x00061096, 0x00000018},
230 {0x844075bc, 0x00000002},
231 {0x000000c0, 0x00000004},
232 {0x804075bd, 0x00000002},
233 {0x800075bb, 0x00000002},
234 {0x804075bc, 0x00000002},
235 {0x00108000, 0x00000002},
236 {0x01400000, 0x00000002},
237 {0x006000c4, 0x0000000c},
238 {0x20c07000, 0x00000020},
239 {0x000000c6, 0x00000012},
240 {0x00800000, 0x00000006},
241 {0x0080751d, 0x00000006},
242 {0x000025bb, 0x00000002},
243 {0x000040c0, 0x00000004},
244 {0x0000775c, 0x00000002},
245 {0x00a05000, 0x00000002},
246 {0x00661000, 0x00000002},
247 {0x0460275d, 0x00000020},
248 {0x00004000, 0000000000},
249 {0x00007999, 0x00000002},
250 {0x00a05000, 0x00000002},
251 {0x00661000, 0x00000002},
252 {0x0460299b, 0x00000020},
253 {0x00004000, 0000000000},
254 {0x01e00830, 0x00000002},
255 {0x21007000, 0000000000},
256 {0x00005000, 0x00000002},
257 {0x00038042, 0x00000002},
258 {0x040025e0, 0x00000002},
259 {0x000075e1, 0000000000},
260 {0x00000001, 0000000000},
261 {0x000380d9, 0x00000002},
262 {0x04007394, 0000000000},
263 {0000000000, 0000000000},
264 {0000000000, 0000000000},
265 {0000000000, 0000000000},
266 {0000000000, 0000000000},
267 {0000000000, 0000000000},
268 {0000000000, 0000000000},
269 {0000000000, 0000000000},
270 {0000000000, 0000000000},
271 {0000000000, 0000000000},
272 {0000000000, 0000000000},
273 {0000000000, 0000000000},
274 {0000000000, 0000000000},
275 {0000000000, 0000000000},
276 {0000000000, 0000000000},
277 {0000000000, 0000000000},
278 {0000000000, 0000000000},
279 {0000000000, 0000000000},
280 {0000000000, 0000000000},
281 {0000000000, 0000000000},
282 {0000000000, 0000000000},
283 {0000000000, 0000000000},
284 {0000000000, 0000000000},
285 {0000000000, 0000000000},
286 {0000000000, 0000000000},
287 {0000000000, 0000000000},
288 {0000000000, 0000000000},
289 {0000000000, 0000000000},
290 {0000000000, 0000000000},
291 {0000000000, 0000000000},
292 {0000000000, 0000000000},
293 {0000000000, 0000000000},
294 {0000000000, 0000000000},
295 {0000000000, 0000000000},
296 {0000000000, 0000000000},
297 {0000000000, 0000000000},
298 {0000000000, 0000000000},
299 };
300
301 static const u32 radeon_cp_microcode[][2] = {
302 {0x21007000, 0000000000},
303 {0x20007000, 0000000000},
304 {0x000000b4, 0x00000004},
305 {0x000000b8, 0x00000004},
306 {0x6f5b4d4c, 0000000000},
307 {0x4c4c427f, 0000000000},
308 {0x5b568a92, 0000000000},
309 {0x4ca09c6d, 0000000000},
310 {0xad4c4c4c, 0000000000},
311 {0x4ce1af3d, 0000000000},
312 {0xd8afafaf, 0000000000},
313 {0xd64c4cdc, 0000000000},
314 {0x4cd10d10, 0000000000},
315 {0x000f0000, 0x00000016},
316 {0x362f242d, 0000000000},
317 {0x00000012, 0x00000004},
318 {0x000f0000, 0x00000016},
319 {0x362f282d, 0000000000},
320 {0x000380e7, 0x00000002},
321 {0x04002c97, 0x00000002},
322 {0x000f0001, 0x00000016},
323 {0x333a3730, 0000000000},
324 {0x000077ef, 0x00000002},
325 {0x00061000, 0x00000002},
326 {0x00000021, 0x0000001a},
327 {0x00004000, 0x0000001e},
328 {0x00061000, 0x00000002},
329 {0x00000021, 0x0000001a},
330 {0x00004000, 0x0000001e},
331 {0x00061000, 0x00000002},
332 {0x00000021, 0x0000001a},
333 {0x00004000, 0x0000001e},
334 {0x00000017, 0x00000004},
335 {0x0003802b, 0x00000002},
336 {0x040067e0, 0x00000002},
337 {0x00000017, 0x00000004},
338 {0x000077e0, 0x00000002},
339 {0x00065000, 0x00000002},
340 {0x000037e1, 0x00000002},
341 {0x040067e1, 0x00000006},
342 {0x000077e0, 0x00000002},
343 {0x000077e1, 0x00000002},
344 {0x000077e1, 0x00000006},
345 {0xffffffff, 0000000000},
346 {0x10000000, 0000000000},
347 {0x0003802b, 0x00000002},
348 {0x040067e0, 0x00000006},
349 {0x00007675, 0x00000002},
350 {0x00007676, 0x00000002},
351 {0x00007677, 0x00000002},
352 {0x00007678, 0x00000006},
353 {0x0003802c, 0x00000002},
354 {0x04002676, 0x00000002},
355 {0x00007677, 0x00000002},
356 {0x00007678, 0x00000006},
357 {0x0000002f, 0x00000018},
358 {0x0000002f, 0x00000018},
359 {0000000000, 0x00000006},
360 {0x00000030, 0x00000018},
361 {0x00000030, 0x00000018},
362 {0000000000, 0x00000006},
363 {0x01605000, 0x00000002},
364 {0x00065000, 0x00000002},
365 {0x00098000, 0x00000002},
366 {0x00061000, 0x00000002},
367 {0x64c0603e, 0x00000004},
368 {0x000380e6, 0x00000002},
369 {0x040025c5, 0x00000002},
370 {0x00080000, 0x00000016},
371 {0000000000, 0000000000},
372 {0x0400251d, 0x00000002},
373 {0x00007580, 0x00000002},
374 {0x00067581, 0x00000002},
375 {0x04002580, 0x00000002},
376 {0x00067581, 0x00000002},
377 {0x00000049, 0x00000004},
378 {0x00005000, 0000000000},
379 {0x000380e6, 0x00000002},
380 {0x040025c5, 0x00000002},
381 {0x00061000, 0x00000002},
382 {0x0000750e, 0x00000002},
383 {0x00019000, 0x00000002},
384 {0x00011055, 0x00000014},
385 {0x00000055, 0x00000012},
386 {0x0400250f, 0x00000002},
387 {0x0000504f, 0x00000004},
388 {0x000380e6, 0x00000002},
389 {0x040025c5, 0x00000002},
390 {0x00007565, 0x00000002},
391 {0x00007566, 0x00000002},
392 {0x00000058, 0x00000004},
393 {0x000380e6, 0x00000002},
394 {0x040025c5, 0x00000002},
395 {0x01e655b4, 0x00000002},
396 {0x4401b0e4, 0x00000002},
397 {0x01c110e4, 0x00000002},
398 {0x26667066, 0x00000018},
399 {0x040c2565, 0x00000002},
400 {0x00000066, 0x00000018},
401 {0x04002564, 0x00000002},
402 {0x00007566, 0x00000002},
403 {0x0000005d, 0x00000004},
404 {0x00401069, 0x00000008},
405 {0x00101000, 0x00000002},
406 {0x000d80ff, 0x00000002},
407 {0x0080006c, 0x00000008},
408 {0x000f9000, 0x00000002},
409 {0x000e00ff, 0x00000002},
410 {0000000000, 0x00000006},
411 {0x0000008f, 0x00000018},
412 {0x0000005b, 0x00000004},
413 {0x000380e6, 0x00000002},
414 {0x040025c5, 0x00000002},
415 {0x00007576, 0x00000002},
416 {0x00065000, 0x00000002},
417 {0x00009000, 0x00000002},
418 {0x00041000, 0x00000002},
419 {0x0c00350e, 0x00000002},
420 {0x00049000, 0x00000002},
421 {0x00051000, 0x00000002},
422 {0x01e785f8, 0x00000002},
423 {0x00200000, 0x00000002},
424 {0x0060007e, 0x0000000c},
425 {0x00007563, 0x00000002},
426 {0x006075f0, 0x00000021},
427 {0x20007073, 0x00000004},
428 {0x00005073, 0x00000004},
429 {0x000380e6, 0x00000002},
430 {0x040025c5, 0x00000002},
431 {0x00007576, 0x00000002},
432 {0x00007577, 0x00000002},
433 {0x0000750e, 0x00000002},
434 {0x0000750f, 0x00000002},
435 {0x00a05000, 0x00000002},
436 {0x00600083, 0x0000000c},
437 {0x006075f0, 0x00000021},
438 {0x000075f8, 0x00000002},
439 {0x00000083, 0x00000004},
440 {0x000a750e, 0x00000002},
441 {0x000380e6, 0x00000002},
442 {0x040025c5, 0x00000002},
443 {0x0020750f, 0x00000002},
444 {0x00600086, 0x00000004},
445 {0x00007570, 0x00000002},
446 {0x00007571, 0x00000002},
447 {0x00007572, 0x00000006},
448 {0x000380e6, 0x00000002},
449 {0x040025c5, 0x00000002},
450 {0x00005000, 0x00000002},
451 {0x00a05000, 0x00000002},
452 {0x00007568, 0x00000002},
453 {0x00061000, 0x00000002},
454 {0x00000095, 0x0000000c},
455 {0x00058000, 0x00000002},
456 {0x0c607562, 0x00000002},
457 {0x00000097, 0x00000004},
458 {0x000380e6, 0x00000002},
459 {0x040025c5, 0x00000002},
460 {0x00600096, 0x00000004},
461 {0x400070e5, 0000000000},
462 {0x000380e6, 0x00000002},
463 {0x040025c5, 0x00000002},
464 {0x000380e5, 0x00000002},
465 {0x000000a8, 0x0000001c},
466 {0x000650aa, 0x00000018},
467 {0x040025bb, 0x00000002},
468 {0x000610ab, 0x00000018},
469 {0x040075bc, 0000000000},
470 {0x000075bb, 0x00000002},
471 {0x000075bc, 0000000000},
472 {0x00090000, 0x00000006},
473 {0x00090000, 0x00000002},
474 {0x000d8002, 0x00000006},
475 {0x00007832, 0x00000002},
476 {0x00005000, 0x00000002},
477 {0x000380e7, 0x00000002},
478 {0x04002c97, 0x00000002},
479 {0x00007820, 0x00000002},
480 {0x00007821, 0x00000002},
481 {0x00007800, 0000000000},
482 {0x01200000, 0x00000002},
483 {0x20077000, 0x00000002},
484 {0x01200000, 0x00000002},
485 {0x20007000, 0x00000002},
486 {0x00061000, 0x00000002},
487 {0x0120751b, 0x00000002},
488 {0x8040750a, 0x00000002},
489 {0x8040750b, 0x00000002},
490 {0x00110000, 0x00000002},
491 {0x000380e5, 0x00000002},
492 {0x000000c6, 0x0000001c},
493 {0x000610ab, 0x00000018},
494 {0x844075bd, 0x00000002},
495 {0x000610aa, 0x00000018},
496 {0x840075bb, 0x00000002},
497 {0x000610ab, 0x00000018},
498 {0x844075bc, 0x00000002},
499 {0x000000c9, 0x00000004},
500 {0x804075bd, 0x00000002},
501 {0x800075bb, 0x00000002},
502 {0x804075bc, 0x00000002},
503 {0x00108000, 0x00000002},
504 {0x01400000, 0x00000002},
505 {0x006000cd, 0x0000000c},
506 {0x20c07000, 0x00000020},
507 {0x000000cf, 0x00000012},
508 {0x00800000, 0x00000006},
509 {0x0080751d, 0x00000006},
510 {0000000000, 0000000000},
511 {0x0000775c, 0x00000002},
512 {0x00a05000, 0x00000002},
513 {0x00661000, 0x00000002},
514 {0x0460275d, 0x00000020},
515 {0x00004000, 0000000000},
516 {0x01e00830, 0x00000002},
517 {0x21007000, 0000000000},
518 {0x6464614d, 0000000000},
519 {0x69687420, 0000000000},
520 {0x00000073, 0000000000},
521 {0000000000, 0000000000},
522 {0x00005000, 0x00000002},
523 {0x000380d0, 0x00000002},
524 {0x040025e0, 0x00000002},
525 {0x000075e1, 0000000000},
526 {0x00000001, 0000000000},
527 {0x000380e0, 0x00000002},
528 {0x04002394, 0x00000002},
529 {0x00005000, 0000000000},
530 {0000000000, 0000000000},
531 {0000000000, 0000000000},
532 {0x00000008, 0000000000},
533 {0x00000004, 0000000000},
534 {0000000000, 0000000000},
535 {0000000000, 0000000000},
536 {0000000000, 0000000000},
537 {0000000000, 0000000000},
538 {0000000000, 0000000000},
539 {0000000000, 0000000000},
540 {0000000000, 0000000000},
541 {0000000000, 0000000000},
542 {0000000000, 0000000000},
543 {0000000000, 0000000000},
544 {0000000000, 0000000000},
545 {0000000000, 0000000000},
546 {0000000000, 0000000000},
547 {0000000000, 0000000000},
548 {0000000000, 0000000000},
549 {0000000000, 0000000000},
550 {0000000000, 0000000000},
551 {0000000000, 0000000000},
552 {0000000000, 0000000000},
553 {0000000000, 0000000000},
554 {0000000000, 0000000000},
555 {0000000000, 0000000000},
556 {0000000000, 0000000000},
557 {0000000000, 0000000000},
558 };
559
560 static const u32 R300_cp_microcode[][2] = {
561 {0x4200e000, 0000000000},
562 {0x4000e000, 0000000000},
563 {0x000000af, 0x00000008},
564 {0x000000b3, 0x00000008},
565 {0x6c5a504f, 0000000000},
566 {0x4f4f497a, 0000000000},
567 {0x5a578288, 0000000000},
568 {0x4f91906a, 0000000000},
569 {0x4f4f4f4f, 0000000000},
570 {0x4fe24f44, 0000000000},
571 {0x4f9c9c9c, 0000000000},
572 {0xdc4f4fde, 0000000000},
573 {0xa1cd4f4f, 0000000000},
574 {0xd29d9d9d, 0000000000},
575 {0x4f0f9fd7, 0000000000},
576 {0x000ca000, 0x00000004},
577 {0x000d0012, 0x00000038},
578 {0x0000e8b4, 0x00000004},
579 {0x000d0014, 0x00000038},
580 {0x0000e8b6, 0x00000004},
581 {0x000d0016, 0x00000038},
582 {0x0000e854, 0x00000004},
583 {0x000d0018, 0x00000038},
584 {0x0000e855, 0x00000004},
585 {0x000d001a, 0x00000038},
586 {0x0000e856, 0x00000004},
587 {0x000d001c, 0x00000038},
588 {0x0000e857, 0x00000004},
589 {0x000d001e, 0x00000038},
590 {0x0000e824, 0x00000004},
591 {0x000d0020, 0x00000038},
592 {0x0000e825, 0x00000004},
593 {0x000d0022, 0x00000038},
594 {0x0000e830, 0x00000004},
595 {0x000d0024, 0x00000038},
596 {0x0000f0c0, 0x00000004},
597 {0x000d0026, 0x00000038},
598 {0x0000f0c1, 0x00000004},
599 {0x000d0028, 0x00000038},
600 {0x0000f041, 0x00000004},
601 {0x000d002a, 0x00000038},
602 {0x0000f184, 0x00000004},
603 {0x000d002c, 0x00000038},
604 {0x0000f185, 0x00000004},
605 {0x000d002e, 0x00000038},
606 {0x0000f186, 0x00000004},
607 {0x000d0030, 0x00000038},
608 {0x0000f187, 0x00000004},
609 {0x000d0032, 0x00000038},
610 {0x0000f180, 0x00000004},
611 {0x000d0034, 0x00000038},
612 {0x0000f393, 0x00000004},
613 {0x000d0036, 0x00000038},
614 {0x0000f38a, 0x00000004},
615 {0x000d0038, 0x00000038},
616 {0x0000f38e, 0x00000004},
617 {0x0000e821, 0x00000004},
618 {0x0140a000, 0x00000004},
619 {0x00000043, 0x00000018},
620 {0x00cce800, 0x00000004},
621 {0x001b0001, 0x00000004},
622 {0x08004800, 0x00000004},
623 {0x001b0001, 0x00000004},
624 {0x08004800, 0x00000004},
625 {0x001b0001, 0x00000004},
626 {0x08004800, 0x00000004},
627 {0x0000003a, 0x00000008},
628 {0x0000a000, 0000000000},
629 {0x02c0a000, 0x00000004},
630 {0x000ca000, 0x00000004},
631 {0x00130000, 0x00000004},
632 {0x000c2000, 0x00000004},
633 {0xc980c045, 0x00000008},
634 {0x2000451d, 0x00000004},
635 {0x0000e580, 0x00000004},
636 {0x000ce581, 0x00000004},
637 {0x08004580, 0x00000004},
638 {0x000ce581, 0x00000004},
639 {0x0000004c, 0x00000008},
640 {0x0000a000, 0000000000},
641 {0x000c2000, 0x00000004},
642 {0x0000e50e, 0x00000004},
643 {0x00032000, 0x00000004},
644 {0x00022056, 0x00000028},
645 {0x00000056, 0x00000024},
646 {0x0800450f, 0x00000004},
647 {0x0000a050, 0x00000008},
648 {0x0000e565, 0x00000004},
649 {0x0000e566, 0x00000004},
650 {0x00000057, 0x00000008},
651 {0x03cca5b4, 0x00000004},
652 {0x05432000, 0x00000004},
653 {0x00022000, 0x00000004},
654 {0x4ccce063, 0x00000030},
655 {0x08274565, 0x00000004},
656 {0x00000063, 0x00000030},
657 {0x08004564, 0x00000004},
658 {0x0000e566, 0x00000004},
659 {0x0000005a, 0x00000008},
660 {0x00802066, 0x00000010},
661 {0x00202000, 0x00000004},
662 {0x001b00ff, 0x00000004},
663 {0x01000069, 0x00000010},
664 {0x001f2000, 0x00000004},
665 {0x001c00ff, 0x00000004},
666 {0000000000, 0x0000000c},
667 {0x00000085, 0x00000030},
668 {0x0000005a, 0x00000008},
669 {0x0000e576, 0x00000004},
670 {0x000ca000, 0x00000004},
671 {0x00012000, 0x00000004},
672 {0x00082000, 0x00000004},
673 {0x1800650e, 0x00000004},
674 {0x00092000, 0x00000004},
675 {0x000a2000, 0x00000004},
676 {0x000f0000, 0x00000004},
677 {0x00400000, 0x00000004},
678 {0x00000079, 0x00000018},
679 {0x0000e563, 0x00000004},
680 {0x00c0e5f9, 0x000000c2},
681 {0x0000006e, 0x00000008},
682 {0x0000a06e, 0x00000008},
683 {0x0000e576, 0x00000004},
684 {0x0000e577, 0x00000004},
685 {0x0000e50e, 0x00000004},
686 {0x0000e50f, 0x00000004},
687 {0x0140a000, 0x00000004},
688 {0x0000007c, 0x00000018},
689 {0x00c0e5f9, 0x000000c2},
690 {0x0000007c, 0x00000008},
691 {0x0014e50e, 0x00000004},
692 {0x0040e50f, 0x00000004},
693 {0x00c0007f, 0x00000008},
694 {0x0000e570, 0x00000004},
695 {0x0000e571, 0x00000004},
696 {0x0000e572, 0x0000000c},
697 {0x0000a000, 0x00000004},
698 {0x0140a000, 0x00000004},
699 {0x0000e568, 0x00000004},
700 {0x000c2000, 0x00000004},
701 {0x00000089, 0x00000018},
702 {0x000b0000, 0x00000004},
703 {0x18c0e562, 0x00000004},
704 {0x0000008b, 0x00000008},
705 {0x00c0008a, 0x00000008},
706 {0x000700e4, 0x00000004},
707 {0x00000097, 0x00000038},
708 {0x000ca099, 0x00000030},
709 {0x080045bb, 0x00000004},
710 {0x000c209a, 0x00000030},
711 {0x0800e5bc, 0000000000},
712 {0x0000e5bb, 0x00000004},
713 {0x0000e5bc, 0000000000},
714 {0x00120000, 0x0000000c},
715 {0x00120000, 0x00000004},
716 {0x001b0002, 0x0000000c},
717 {0x0000a000, 0x00000004},
718 {0x0000e821, 0x00000004},
719 {0x0000e800, 0000000000},
720 {0x0000e821, 0x00000004},
721 {0x0000e82e, 0000000000},
722 {0x02cca000, 0x00000004},
723 {0x00140000, 0x00000004},
724 {0x000ce1cc, 0x00000004},
725 {0x050de1cd, 0x00000004},
726 {0x000000a7, 0x00000020},
727 {0x4200e000, 0000000000},
728 {0x000000ae, 0x00000038},
729 {0x000ca000, 0x00000004},
730 {0x00140000, 0x00000004},
731 {0x000c2000, 0x00000004},
732 {0x00160000, 0x00000004},
733 {0x700ce000, 0x00000004},
734 {0x001400aa, 0x00000008},
735 {0x4000e000, 0000000000},
736 {0x02400000, 0x00000004},
737 {0x400ee000, 0x00000004},
738 {0x02400000, 0x00000004},
739 {0x4000e000, 0000000000},
740 {0x000c2000, 0x00000004},
741 {0x0240e51b, 0x00000004},
742 {0x0080e50a, 0x00000005},
743 {0x0080e50b, 0x00000005},
744 {0x00220000, 0x00000004},
745 {0x000700e4, 0x00000004},
746 {0x000000c1, 0x00000038},
747 {0x000c209a, 0x00000030},
748 {0x0880e5bd, 0x00000005},
749 {0x000c2099, 0x00000030},
750 {0x0800e5bb, 0x00000005},
751 {0x000c209a, 0x00000030},
752 {0x0880e5bc, 0x00000005},
753 {0x000000c4, 0x00000008},
754 {0x0080e5bd, 0x00000005},
755 {0x0000e5bb, 0x00000005},
756 {0x0080e5bc, 0x00000005},
757 {0x00210000, 0x00000004},
758 {0x02800000, 0x00000004},
759 {0x00c000c8, 0x00000018},
760 {0x4180e000, 0x00000040},
761 {0x000000ca, 0x00000024},
762 {0x01000000, 0x0000000c},
763 {0x0100e51d, 0x0000000c},
764 {0x000045bb, 0x00000004},
765 {0x000080c4, 0x00000008},
766 {0x0000f3ce, 0x00000004},
767 {0x0140a000, 0x00000004},
768 {0x00cc2000, 0x00000004},
769 {0x08c053cf, 0x00000040},
770 {0x00008000, 0000000000},
771 {0x0000f3d2, 0x00000004},
772 {0x0140a000, 0x00000004},
773 {0x00cc2000, 0x00000004},
774 {0x08c053d3, 0x00000040},
775 {0x00008000, 0000000000},
776 {0x0000f39d, 0x00000004},
777 {0x0140a000, 0x00000004},
778 {0x00cc2000, 0x00000004},
779 {0x08c0539e, 0x00000040},
780 {0x00008000, 0000000000},
781 {0x03c00830, 0x00000004},
782 {0x4200e000, 0000000000},
783 {0x0000a000, 0x00000004},
784 {0x200045e0, 0x00000004},
785 {0x0000e5e1, 0000000000},
786 {0x00000001, 0000000000},
787 {0x000700e1, 0x00000004},
788 {0x0800e394, 0000000000},
789 {0000000000, 0000000000},
790 {0000000000, 0000000000},
791 {0000000000, 0000000000},
792 {0000000000, 0000000000},
793 {0000000000, 0000000000},
794 {0000000000, 0000000000},
795 {0000000000, 0000000000},
796 {0000000000, 0000000000},
797 {0000000000, 0000000000},
798 {0000000000, 0000000000},
799 {0000000000, 0000000000},
800 {0000000000, 0000000000},
801 {0000000000, 0000000000},
802 {0000000000, 0000000000},
803 {0000000000, 0000000000},
804 {0000000000, 0000000000},
805 {0000000000, 0000000000},
806 {0000000000, 0000000000},
807 {0000000000, 0000000000},
808 {0000000000, 0000000000},
809 {0000000000, 0000000000},
810 {0000000000, 0000000000},
811 {0000000000, 0000000000},
812 {0000000000, 0000000000},
813 {0000000000, 0000000000},
814 {0000000000, 0000000000},
815 {0000000000, 0000000000},
816 {0000000000, 0000000000},
817 };
818
819 static u32 RADEON_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
820 {
821 u32 ret;
822 RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff));
823 ret = RADEON_READ(R520_MC_IND_DATA);
824 RADEON_WRITE(R520_MC_IND_INDEX, 0);
825 return ret;
826 }
827
828 <<<<<<< HEAD:drivers/char/drm/radeon_cp.c
829 =======
830 static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
831 {
832 RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
833 return RADEON_READ(RS690_MC_DATA);
834 }
835
836 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/char/drm/radeon_cp.c
837 u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
838 {
839
840 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
841 return RADEON_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
842 <<<<<<< HEAD:drivers/char/drm/radeon_cp.c
843 =======
844 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
845 return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION);
846 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/char/drm/radeon_cp.c
847 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
848 return RADEON_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
849 else
850 return RADEON_READ(RADEON_MC_FB_LOCATION);
851 }
852
853 static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
854 {
855 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
856 RADEON_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
857 <<<<<<< HEAD:drivers/char/drm/radeon_cp.c
858 =======
859 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
860 RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc);
861 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/char/drm/radeon_cp.c
862 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
863 RADEON_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
864 else
865 RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc);
866 }
867
868 static void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
869 {
870 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
871 RADEON_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
872 <<<<<<< HEAD:drivers/char/drm/radeon_cp.c
873 =======
874 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
875 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc);
876 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/char/drm/radeon_cp.c
877 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
878 RADEON_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
879 else
880 RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
881 }
882
883 static int RADEON_READ_PLL(struct drm_device * dev, int addr)
884 {
885 drm_radeon_private_t *dev_priv = dev->dev_private;
886
887 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
888 return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
889 }
890
891 static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
892 {
893 RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
894 return RADEON_READ(RADEON_PCIE_DATA);
895 }
896
897 static u32 RADEON_READ_IGPGART(drm_radeon_private_t *dev_priv, int addr)
898 {
899 u32 ret;
900 RADEON_WRITE(RADEON_IGPGART_INDEX, addr & 0x7f);
901 ret = RADEON_READ(RADEON_IGPGART_DATA);
902 RADEON_WRITE(RADEON_IGPGART_INDEX, 0x7f);
903 return ret;
904 }
905
906 #if RADEON_FIFO_DEBUG
907 static void radeon_status(drm_radeon_private_t * dev_priv)
908 {
909 printk("%s:\n", __FUNCTION__);
910 printk("RBBM_STATUS = 0x%08x\n",
911 (unsigned int)RADEON_READ(RADEON_RBBM_STATUS));
912 printk("CP_RB_RTPR = 0x%08x\n",
913 (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR));
914 printk("CP_RB_WTPR = 0x%08x\n",
915 (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR));
916 printk("AIC_CNTL = 0x%08x\n",
917 (unsigned int)RADEON_READ(RADEON_AIC_CNTL));
918 printk("AIC_STAT = 0x%08x\n",
919 (unsigned int)RADEON_READ(RADEON_AIC_STAT));
920 printk("AIC_PT_BASE = 0x%08x\n",
921 (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE));
922 printk("TLB_ADDR = 0x%08x\n",
923 (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR));
924 printk("TLB_DATA = 0x%08x\n",
925 (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA));
926 }
927 #endif
928
929 /* ================================================================
930 * Engine, FIFO control
931 */
932
933 static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
934 {
935 u32 tmp;
936 int i;
937
938 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
939
940 tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
941 tmp |= RADEON_RB3D_DC_FLUSH_ALL;
942 RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
943
944 for (i = 0; i < dev_priv->usec_timeout; i++) {
945 if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT)
946 & RADEON_RB3D_DC_BUSY)) {
947 return 0;
948 }
949 DRM_UDELAY(1);
950 }
951
952 #if RADEON_FIFO_DEBUG
953 DRM_ERROR("failed!\n");
954 radeon_status(dev_priv);
955 #endif
956 return -EBUSY;
957 }
958
959 static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
960 {
961 int i;
962
963 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
964
965 for (i = 0; i < dev_priv->usec_timeout; i++) {
966 int slots = (RADEON_READ(RADEON_RBBM_STATUS)
967 & RADEON_RBBM_FIFOCNT_MASK);
968 if (slots >= entries)
969 return 0;
970 DRM_UDELAY(1);
971 }
972
973 #if RADEON_FIFO_DEBUG
974 DRM_ERROR("failed!\n");
975 radeon_status(dev_priv);
976 #endif
977 return -EBUSY;
978 }
979
980 static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
981 {
982 int i, ret;
983
984 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
985
986 ret = radeon_do_wait_for_fifo(dev_priv, 64);
987 if (ret)
988 return ret;
989
990 for (i = 0; i < dev_priv->usec_timeout; i++) {
991 if (!(RADEON_READ(RADEON_RBBM_STATUS)
992 & RADEON_RBBM_ACTIVE)) {
993 radeon_do_pixcache_flush(dev_priv);
994 return 0;
995 }
996 DRM_UDELAY(1);
997 }
998
999 #if RADEON_FIFO_DEBUG
1000 DRM_ERROR("failed!\n");
1001 radeon_status(dev_priv);
1002 #endif
1003 return -EBUSY;
1004 }
1005
1006 /* ================================================================
1007 * CP control, initialization
1008 */
1009
1010 /* Load the microcode for the CP */
1011 static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
1012 {
1013 int i;
1014 DRM_DEBUG("\n");
1015
1016 radeon_do_wait_for_idle(dev_priv);
1017
1018 RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
1019
1020 if (dev_priv->microcode_version == UCODE_R200) {
1021 DRM_INFO("Loading R200 Microcode\n");
1022 for (i = 0; i < 256; i++) {
1023 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
1024 R200_cp_microcode[i][1]);
1025 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
1026 R200_cp_microcode[i][0]);
1027 }
1028 } else if (dev_priv->microcode_version == UCODE_R300) {
1029 DRM_INFO("Loading R300 Microcode\n");
1030 for (i = 0; i < 256; i++) {
1031 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
1032 R300_cp_microcode[i][1]);
1033 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
1034 R300_cp_microcode[i][0]);
1035 }
1036 } else {
1037 for (i = 0; i < 256; i++) {
1038 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
1039 radeon_cp_microcode[i][1]);
1040 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
1041 radeon_cp_microcode[i][0]);
1042 }
1043 }
1044 }
1045
1046 /* Flush any pending commands to the CP. This should only be used just
1047 * prior to a wait for idle, as it informs the engine that the command
1048 * stream is ending.
1049 */
1050 static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
1051 {
1052 DRM_DEBUG("\n");
1053 #if 0
1054 u32 tmp;
1055
1056 tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);
1057 RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
1058 #endif
1059 }
1060
1061 /* Wait for the CP to go idle.
1062 */
1063 int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
1064 {
1065 RING_LOCALS;
1066 DRM_DEBUG("\n");
1067
1068 BEGIN_RING(6);
1069
1070 RADEON_PURGE_CACHE();
1071 RADEON_PURGE_ZCACHE();
1072 RADEON_WAIT_UNTIL_IDLE();
1073
1074 ADVANCE_RING();
1075 COMMIT_RING();
1076
1077 return radeon_do_wait_for_idle(dev_priv);
1078 }
1079
1080 /* Start the Command Processor.
1081 */
1082 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
1083 {
1084 RING_LOCALS;
1085 DRM_DEBUG("\n");
1086
1087 radeon_do_wait_for_idle(dev_priv);
1088
1089 RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);
1090
1091 dev_priv->cp_running = 1;
1092
1093 BEGIN_RING(6);
1094
1095 RADEON_PURGE_CACHE();
1096 RADEON_PURGE_ZCACHE();
1097 RADEON_WAIT_UNTIL_IDLE();
1098
1099 ADVANCE_RING();
1100 COMMIT_RING();
1101 }
1102
1103 /* Reset the Command Processor. This will not flush any pending
1104 * commands, so you must wait for the CP command stream to complete
1105 * before calling this routine.
1106 */
1107 static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
1108 {
1109 u32 cur_read_ptr;
1110 DRM_DEBUG("\n");
1111
1112 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
1113 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
1114 SET_RING_HEAD(dev_priv, cur_read_ptr);
1115 dev_priv->ring.tail = cur_read_ptr;
1116 }
1117
1118 /* Stop the Command Processor. This will not flush any pending
1119 * commands, so you must flush the command stream and wait for the CP
1120 * to go idle before calling this routine.
1121 */
1122 static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
1123 {
1124 DRM_DEBUG("\n");
1125
1126 RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);
1127
1128 dev_priv->cp_running = 0;
1129 }
1130
1131 /* Reset the engine. This will stop the CP if it is running.
1132 */
1133 static int radeon_do_engine_reset(struct drm_device * dev)
1134 {
1135 drm_radeon_private_t *dev_priv = dev->dev_private;
1136 u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset;
1137 DRM_DEBUG("\n");
1138
1139 radeon_do_pixcache_flush(dev_priv);
1140
1141 if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV515) {
1142 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
1143 mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
1144
1145 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl |
1146 RADEON_FORCEON_MCLKA |
1147 RADEON_FORCEON_MCLKB |
1148 RADEON_FORCEON_YCLKA |
1149 RADEON_FORCEON_YCLKB |
1150 RADEON_FORCEON_MC |
1151 RADEON_FORCEON_AIC));
1152
1153 rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
1154
1155 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
1156 RADEON_SOFT_RESET_CP |
1157 RADEON_SOFT_RESET_HI |
1158 RADEON_SOFT_RESET_SE |
1159 RADEON_SOFT_RESET_RE |
1160 RADEON_SOFT_RESET_PP |
1161 RADEON_SOFT_RESET_E2 |
1162 RADEON_SOFT_RESET_RB));
1163 RADEON_READ(RADEON_RBBM_SOFT_RESET);
1164 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
1165 ~(RADEON_SOFT_RESET_CP |
1166 RADEON_SOFT_RESET_HI |
1167 RADEON_SOFT_RESET_SE |
1168 RADEON_SOFT_RESET_RE |
1169 RADEON_SOFT_RESET_PP |
1170 RADEON_SOFT_RESET_E2 |
1171 RADEON_SOFT_RESET_RB)));
1172 RADEON_READ(RADEON_RBBM_SOFT_RESET);
1173
1174 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
1175 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
1176 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
1177 }
1178
1179 /* Reset the CP ring */
1180 radeon_do_cp_reset(dev_priv);
1181
1182 /* The CP is no longer running after an engine reset */
1183 dev_priv->cp_running = 0;
1184
1185 /* Reset any pending vertex, indirect buffers */
1186 radeon_freelist_reset(dev);
1187
1188 return 0;
1189 }
1190
1191 static void radeon_cp_init_ring_buffer(struct drm_device * dev,
1192 drm_radeon_private_t * dev_priv)
1193 {
1194 u32 ring_start, cur_read_ptr;
1195 u32 tmp;
1196
1197 /* Initialize the memory controller. With new memory map, the fb location
1198 * is not changed, it should have been properly initialized already. Part
1199 * of the problem is that the code below is bogus, assuming the GART is
1200 * always appended to the fb which is not necessarily the case
1201 */
1202 if (!dev_priv->new_memmap)
1203 radeon_write_fb_location(dev_priv,
1204 ((dev_priv->gart_vm_start - 1) & 0xffff0000)
1205 | (dev_priv->fb_location >> 16));
1206
1207 #if __OS_HAS_AGP
1208 if (dev_priv->flags & RADEON_IS_AGP) {
1209 RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev->agp->base);
1210 radeon_write_agp_location(dev_priv,
1211 (((dev_priv->gart_vm_start - 1 +
1212 dev_priv->gart_size) & 0xffff0000) |
1213 (dev_priv->gart_vm_start >> 16)));
1214
1215 ring_start = (dev_priv->cp_ring->offset
1216 - dev->agp->base
1217 + dev_priv->gart_vm_start);
1218 } else
1219 #endif
1220 ring_start = (dev_priv->cp_ring->offset
1221 - (unsigned long)dev->sg->virtual
1222 + dev_priv->gart_vm_start);
1223
1224 RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);
1225
1226 /* Set the write pointer delay */
1227 RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0);
1228
1229 /* Initialize the ring buffer's read and write pointers */
1230 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
1231 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
1232 SET_RING_HEAD(dev_priv, cur_read_ptr);
1233 dev_priv->ring.tail = cur_read_ptr;
1234
1235 #if __OS_HAS_AGP
1236 if (dev_priv->flags & RADEON_IS_AGP) {
1237 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
1238 dev_priv->ring_rptr->offset
1239 - dev->agp->base + dev_priv->gart_vm_start);
1240 } else
1241 #endif
1242 {
1243 struct drm_sg_mem *entry = dev->sg;
1244 unsigned long tmp_ofs, page_ofs;
1245
1246 tmp_ofs = dev_priv->ring_rptr->offset -
1247 (unsigned long)dev->sg->virtual;
1248 page_ofs = tmp_ofs >> PAGE_SHIFT;
1249
1250 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, entry->busaddr[page_ofs]);
1251 DRM_DEBUG("ring rptr: offset=0x%08lx handle=0x%08lx\n",
1252 (unsigned long)entry->busaddr[page_ofs],
1253 entry->handle + tmp_ofs);
1254 }
1255
1256 /* Set ring buffer size */
1257 #ifdef __BIG_ENDIAN
1258 RADEON_WRITE(RADEON_CP_RB_CNTL,
1259 RADEON_BUF_SWAP_32BIT |
1260 (dev_priv->ring.fetch_size_l2ow << 18) |
1261 (dev_priv->ring.rptr_update_l2qw << 8) |
1262 dev_priv->ring.size_l2qw);
1263 #else
1264 RADEON_WRITE(RADEON_CP_RB_CNTL,
1265 (dev_priv->ring.fetch_size_l2ow << 18) |
1266 (dev_priv->ring.rptr_update_l2qw << 8) |
1267 dev_priv->ring.size_l2qw);
1268 #endif
1269
1270 /* Start with assuming that writeback doesn't work */
1271 dev_priv->writeback_works = 0;
1272
1273 /* Initialize the scratch register pointer. This will cause
1274 * the scratch register values to be written out to memory
1275 * whenever they are updated.
1276 *
1277 * We simply put this behind the ring read pointer, this works
1278 * with PCI GART as well as (whatever kind of) AGP GART
1279 */
1280 RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
1281 + RADEON_SCRATCH_REG_OFFSET);
1282
1283 dev_priv->scratch = ((__volatile__ u32 *)
1284 dev_priv->ring_rptr->handle +
1285 (RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));
1286
1287 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
1288
1289 /* Turn on bus mastering */
1290 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
1291 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
1292
1293 dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0;
1294 RADEON_WRITE(RADEON_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame);
1295
1296 dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0;
1297 RADEON_WRITE(RADEON_LAST_DISPATCH_REG,
1298 dev_priv->sarea_priv->last_dispatch);
1299
1300 dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0;
1301 RADEON_WRITE(RADEON_LAST_CLEAR_REG, dev_priv->sarea_priv->last_clear);
1302
1303 radeon_do_wait_for_idle(dev_priv);
1304
1305 /* Sync everything up */
1306 RADEON_WRITE(RADEON_ISYNC_CNTL,
1307 (RADEON_ISYNC_ANY2D_IDLE3D |
1308 RADEON_ISYNC_ANY3D_IDLE2D |
1309 RADEON_ISYNC_WAIT_IDLEGUI |
1310 RADEON_ISYNC_CPSCRATCH_IDLEGUI));
1311
1312 }
1313
1314 static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
1315 {
1316 u32 tmp;
1317
1318 /* Writeback doesn't seem to work everywhere, test it here and possibly
1319 * enable it if it appears to work
1320 */
1321 DRM_WRITE32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0);
1322 RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);
1323
1324 for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
1325 if (DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)) ==
1326 0xdeadbeef)
1327 break;
1328 DRM_UDELAY(1);
1329 }
1330
1331 if (tmp < dev_priv->usec_timeout) {
1332 dev_priv->writeback_works = 1;
1333 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
1334 } else {
1335 dev_priv->writeback_works = 0;
1336 DRM_INFO("writeback test failed\n");
1337 }
1338 if (radeon_no_wb == 1) {
1339 dev_priv->writeback_works = 0;
1340 DRM_INFO("writeback forced off\n");
1341 }
1342
1343 if (!dev_priv->writeback_works) {
1344 /* Disable writeback to avoid unnecessary bus master transfer */
1345 RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) |
1346 RADEON_RB_NO_UPDATE);
1347 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0);
1348 }
1349 }
1350
1351 /* Enable or disable IGP GART on the chip */
1352 static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
1353 {
1354 u32 temp, tmp;
1355
1356 tmp = RADEON_READ(RADEON_AIC_CNTL);
1357 if (on) {
1358 DRM_DEBUG("programming igpgart %08X %08lX %08X\n",
1359 dev_priv->gart_vm_start,
1360 (long)dev_priv->gart_info.bus_addr,
1361 dev_priv->gart_size);
1362
1363 RADEON_WRITE_IGPGART(RADEON_IGPGART_UNK_18, 0x1000);
1364 RADEON_WRITE_IGPGART(RADEON_IGPGART_ENABLE, 0x1);
1365 RADEON_WRITE_IGPGART(RADEON_IGPGART_CTRL, 0x42040800);
1366 RADEON_WRITE_IGPGART(RADEON_IGPGART_BASE_ADDR,
1367 dev_priv->gart_info.bus_addr);
1368
1369 temp = RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_UNK_39);
1370 RADEON_WRITE_IGPGART(RADEON_IGPGART_UNK_39, temp);
1371
1372 RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev_priv->gart_vm_start);
1373 dev_priv->gart_size = 32*1024*1024;
1374 radeon_write_agp_location(dev_priv,
1375 (((dev_priv->gart_vm_start - 1 +
1376 dev_priv->gart_size) & 0xffff0000) |
1377 (dev_priv->gart_vm_start >> 16)));
1378
1379 temp = RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_ENABLE);
1380 RADEON_WRITE_IGPGART(RADEON_IGPGART_ENABLE, temp);
1381
1382 RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_FLUSH);
1383 RADEON_WRITE_IGPGART(RADEON_IGPGART_FLUSH, 0x1);
1384 RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_FLUSH);
1385 RADEON_WRITE_IGPGART(RADEON_IGPGART_FLUSH, 0x0);
1386 }
1387 }
1388
1389 <<<<<<< HEAD:drivers/char/drm/radeon_cp.c
1390 =======
1391 /* Enable or disable RS690 GART on the chip */
1392 static void radeon_set_rs690gart(drm_radeon_private_t *dev_priv, int on)
1393 {
1394 u32 temp;
1395
1396 if (on) {
1397 DRM_DEBUG("programming rs690 gart %08X %08lX %08X\n",
1398 dev_priv->gart_vm_start,
1399 (long)dev_priv->gart_info.bus_addr,
1400 dev_priv->gart_size);
1401
1402 temp = RS690_READ_MCIND(dev_priv, RS690_MC_MISC_CNTL);
1403 RS690_WRITE_MCIND(RS690_MC_MISC_CNTL, 0x5000);
1404
1405 RS690_WRITE_MCIND(RS690_MC_AGP_SIZE,
1406 RS690_MC_GART_EN | RS690_MC_AGP_SIZE_32MB);
1407
1408 temp = RS690_READ_MCIND(dev_priv, RS690_MC_GART_FEATURE_ID);
1409 RS690_WRITE_MCIND(RS690_MC_GART_FEATURE_ID, 0x42040800);
1410
1411 RS690_WRITE_MCIND(RS690_MC_GART_BASE,
1412 dev_priv->gart_info.bus_addr);
1413
1414 temp = RS690_READ_MCIND(dev_priv, RS690_MC_AGP_MODE_CONTROL);
1415 RS690_WRITE_MCIND(RS690_MC_AGP_MODE_CONTROL, 0x01400000);
1416
1417 RS690_WRITE_MCIND(RS690_MC_AGP_BASE,
1418 (unsigned int)dev_priv->gart_vm_start);
1419
1420 dev_priv->gart_size = 32*1024*1024;
1421 temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) &
1422 0xffff0000) | (dev_priv->gart_vm_start >> 16));
1423
1424 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, temp);
1425
1426 temp = RS690_READ_MCIND(dev_priv, RS690_MC_AGP_SIZE);
1427 RS690_WRITE_MCIND(RS690_MC_AGP_SIZE,
1428 RS690_MC_GART_EN | RS690_MC_AGP_SIZE_32MB);
1429
1430 do {
1431 temp = RS690_READ_MCIND(dev_priv, RS690_MC_GART_CACHE_CNTL);
1432 if ((temp & RS690_MC_GART_CLEAR_STATUS) ==
1433 RS690_MC_GART_CLEAR_DONE)
1434 break;
1435 DRM_UDELAY(1);
1436 } while (1);
1437
1438 RS690_WRITE_MCIND(RS690_MC_GART_CACHE_CNTL,
1439 RS690_MC_GART_CC_CLEAR);
1440 do {
1441 temp = RS690_READ_MCIND(dev_priv, RS690_MC_GART_CACHE_CNTL);
1442 if ((temp & RS690_MC_GART_CLEAR_STATUS) ==
1443 RS690_MC_GART_CLEAR_DONE)
1444 break;
1445 DRM_UDELAY(1);
1446 } while (1);
1447
1448 RS690_WRITE_MCIND(RS690_MC_GART_CACHE_CNTL,
1449 RS690_MC_GART_CC_NO_CHANGE);
1450 } else {
1451 RS690_WRITE_MCIND(RS690_MC_AGP_SIZE, RS690_MC_GART_DIS);
1452 }
1453 }
1454
1455 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/char/drm/radeon_cp.c
1456 static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
1457 {
1458 u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
1459 if (on) {
1460
1461 DRM_DEBUG("programming pcie %08X %08lX %08X\n",
1462 dev_priv->gart_vm_start,
1463 (long)dev_priv->gart_info.bus_addr,
1464 dev_priv->gart_size);
1465 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO,
1466 dev_priv->gart_vm_start);
1467 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE,
1468 dev_priv->gart_info.bus_addr);
1469 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO,
1470 dev_priv->gart_vm_start);
1471 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO,
1472 dev_priv->gart_vm_start +
1473 dev_priv->gart_size - 1);
1474
1475 radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */
1476
1477 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
1478 RADEON_PCIE_TX_GART_EN);
1479 } else {
1480 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
1481 tmp & ~RADEON_PCIE_TX_GART_EN);
1482 }
1483 }
1484
1485 /* Enable or disable PCI GART on the chip */
1486 static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
1487 {
1488 u32 tmp;
1489
1490 <<<<<<< HEAD:drivers/char/drm/radeon_cp.c
1491 =======
1492 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) {
1493 radeon_set_rs690gart(dev_priv, on);
1494 return;
1495 }
1496
1497 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/char/drm/radeon_cp.c
1498 if (dev_priv->flags & RADEON_IS_IGPGART) {
1499 radeon_set_igpgart(dev_priv, on);
1500 return;
1501 }
1502
1503 if (dev_priv->flags & RADEON_IS_PCIE) {
1504 radeon_set_pciegart(dev_priv, on);
1505 return;
1506 }
1507
1508 tmp = RADEON_READ(RADEON_AIC_CNTL);
1509
1510 if (on) {
1511 RADEON_WRITE(RADEON_AIC_CNTL,
1512 tmp | RADEON_PCIGART_TRANSLATE_EN);
1513
1514 /* set PCI GART page-table base address
1515 */
1516 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr);
1517
1518 /* set address range for PCI address translate
1519 */
1520 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);
1521 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
1522 + dev_priv->gart_size - 1);
1523
1524 /* Turn off AGP aperture -- is this required for PCI GART?
1525 */
1526 radeon_write_agp_location(dev_priv, 0xffffffc0);
1527 RADEON_WRITE(RADEON_AGP_COMMAND, 0); /* clear AGP_COMMAND */
1528 } else {
1529 RADEON_WRITE(RADEON_AIC_CNTL,
1530 tmp & ~RADEON_PCIGART_TRANSLATE_EN);
1531 }
1532 }
1533
1534 static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
1535 {
1536 drm_radeon_private_t *dev_priv = dev->dev_private;
1537
1538 DRM_DEBUG("\n");
1539
1540 /* if we require new memory map but we don't have it fail */
1541 if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
1542 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
1543 radeon_do_cleanup_cp(dev);
1544 return -EINVAL;
1545 }
1546
1547 if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) {
1548 DRM_DEBUG("Forcing AGP card to PCI mode\n");
1549 dev_priv->flags &= ~RADEON_IS_AGP;
1550 } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
1551 && !init->is_pci) {
1552 DRM_DEBUG("Restoring AGP flag\n");
1553 dev_priv->flags |= RADEON_IS_AGP;
1554 }
1555
1556 if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) {
1557 DRM_ERROR("PCI GART memory not allocated!\n");
1558 radeon_do_cleanup_cp(dev);
1559 return -EINVAL;
1560 }
1561
1562 dev_priv->usec_timeout = init->usec_timeout;
1563 if (dev_priv->usec_timeout < 1 ||
1564 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
1565 DRM_DEBUG("TIMEOUT problem!\n");
1566 radeon_do_cleanup_cp(dev);
1567 return -EINVAL;
1568 }
1569
1570 /* Enable vblank on CRTC1 for older X servers
1571 */
1572 dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
1573
1574 switch(init->func) {
1575 case RADEON_INIT_R200_CP:
1576 dev_priv->microcode_version = UCODE_R200;
1577 break;
1578 case RADEON_INIT_R300_CP:
1579 dev_priv->microcode_version = UCODE_R300;
1580 break;
1581 default:
1582 dev_priv->microcode_version = UCODE_R100;
1583 }
1584
1585 dev_priv->do_boxes = 0;
1586 dev_priv->cp_mode = init->cp_mode;
1587
1588 /* We don't support anything other than bus-mastering ring mode,
1589 * but the ring can be in either AGP or PCI space for the ring
1590 * read pointer.
1591 */
1592 if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
1593 (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
1594 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
1595 radeon_do_cleanup_cp(dev);
1596 return -EINVAL;
1597 }
1598
1599 switch (init->fb_bpp) {
1600 case 16:
1601 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1602 break;
1603 case 32:
1604 default:
1605 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1606 break;
1607 }
1608 dev_priv->front_offset = init->front_offset;
1609 dev_priv->front_pitch = init->front_pitch;
1610 dev_priv->back_offset = init->back_offset;
1611 dev_priv->back_pitch = init->back_pitch;
1612
1613 switch (init->depth_bpp) {
1614 case 16:
1615 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
1616 break;
1617 case 32:
1618 default:
1619 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
1620 break;
1621 }
1622 dev_priv->depth_offset = init->depth_offset;
1623 dev_priv->depth_pitch = init->depth_pitch;
1624
1625 /* Hardware state for depth clears. Remove this if/when we no
1626 * longer clear the depth buffer with a 3D rectangle. Hard-code
1627 * all values to prevent unwanted 3D state from slipping through
1628 * and screwing with the clear operation.
1629 */
1630 dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
1631 (dev_priv->color_fmt << 10) |
1632 (dev_priv->microcode_version ==
1633 UCODE_R100 ? RADEON_ZBLOCK16 : 0));
1634
1635 dev_priv->depth_clear.rb3d_zstencilcntl =
1636 (dev_priv->depth_fmt |
1637 RADEON_Z_TEST_ALWAYS |
1638 RADEON_STENCIL_TEST_ALWAYS |
1639 RADEON_STENCIL_S_FAIL_REPLACE |
1640 RADEON_STENCIL_ZPASS_REPLACE |
1641 RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE);
1642
1643 dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
1644 RADEON_BFACE_SOLID |
1645 RADEON_FFACE_SOLID |
1646 RADEON_FLAT_SHADE_VTX_LAST |
1647 RADEON_DIFFUSE_SHADE_FLAT |
1648 RADEON_ALPHA_SHADE_FLAT |
1649 RADEON_SPECULAR_SHADE_FLAT |
1650 RADEON_FOG_SHADE_FLAT |
1651 RADEON_VTX_PIX_CENTER_OGL |
1652 RADEON_ROUND_MODE_TRUNC |
1653 RADEON_ROUND_PREC_8TH_PIX);
1654
1655
1656 dev_priv->ring_offset = init->ring_offset;
1657 dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1658 dev_priv->buffers_offset = init->buffers_offset;
1659 dev_priv->gart_textures_offset = init->gart_textures_offset;
1660
1661 dev_priv->sarea = drm_getsarea(dev);
1662 if (!dev_priv->sarea) {
1663 DRM_ERROR("could not find sarea!\n");
1664 radeon_do_cleanup_cp(dev);
1665 return -EINVAL;
1666 }
1667
1668 dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
1669 if (!dev_priv->cp_ring) {
1670 DRM_ERROR("could not find cp ring region!\n");
1671 radeon_do_cleanup_cp(dev);
1672 return -EINVAL;
1673 }
1674 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
1675 if (!dev_priv->ring_rptr) {
1676 DRM_ERROR("could not find ring read pointer!\n");
1677 radeon_do_cleanup_cp(dev);
1678 return -EINVAL;
1679 }
1680 dev->agp_buffer_token = init->buffers_offset;
1681 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
1682 if (!dev->agp_buffer_map) {
1683 DRM_ERROR("could not find dma buffer region!\n");
1684 radeon_do_cleanup_cp(dev);
1685 return -EINVAL;
1686 }
1687
1688 if (init->gart_textures_offset) {
1689 dev_priv->gart_textures =
1690 drm_core_findmap(dev, init->gart_textures_offset);
1691 if (!dev_priv->gart_textures) {
1692 DRM_ERROR("could not find GART texture region!\n");
1693 radeon_do_cleanup_cp(dev);
1694 return -EINVAL;
1695 }
1696 }
1697
1698 dev_priv->sarea_priv =
1699 (drm_radeon_sarea_t *) ((u8 *) dev_priv->sarea->handle +
1700 init->sarea_priv_offset);
1701
1702 #if __OS_HAS_AGP
1703 if (dev_priv->flags & RADEON_IS_AGP) {
1704 drm_core_ioremap(dev_priv->cp_ring, dev);
1705 drm_core_ioremap(dev_priv->ring_rptr, dev);
1706 drm_core_ioremap(dev->agp_buffer_map, dev);
1707 if (!dev_priv->cp_ring->handle ||
1708 !dev_priv->ring_rptr->handle ||
1709 !dev->agp_buffer_map->handle) {
1710 DRM_ERROR("could not find ioremap agp regions!\n");
1711 radeon_do_cleanup_cp(dev);
1712 return -EINVAL;
1713 }
1714 } else
1715 #endif
1716 {
1717 dev_priv->cp_ring->handle = (void *)dev_priv->cp_ring->offset;
1718 dev_priv->ring_rptr->handle =
1719 (void *)dev_priv->ring_rptr->offset;
1720 dev->agp_buffer_map->handle =
1721 (void *)dev->agp_buffer_map->offset;
1722
1723 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
1724 dev_priv->cp_ring->handle);
1725 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1726 dev_priv->ring_rptr->handle);
1727 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
1728 dev->agp_buffer_map->handle);
1729 }
1730
1731 dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16;
1732 dev_priv->fb_size =
1733 ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000)
1734 - dev_priv->fb_location;
1735
1736 dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1737 ((dev_priv->front_offset
1738 + dev_priv->fb_location) >> 10));
1739
1740 dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1741 ((dev_priv->back_offset
1742 + dev_priv->fb_location) >> 10));
1743
1744 dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1745 ((dev_priv->depth_offset
1746 + dev_priv->fb_location) >> 10));
1747
1748 dev_priv->gart_size = init->gart_size;
1749
1750 /* New let's set the memory map ... */
1751 if (dev_priv->new_memmap) {
1752 u32 base = 0;
1753
1754 DRM_INFO("Setting GART location based on new memory map\n");
1755
1756 /* If using AGP, try to locate the AGP aperture at the same
1757 * location in the card and on the bus, though we have to
1758 * align it down.
1759 */
1760 #if __OS_HAS_AGP
1761 if (dev_priv->flags & RADEON_IS_AGP) {
1762 base = dev->agp->base;
1763 /* Check if valid */
1764 if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
1765 base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
1766 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
1767 dev->agp->base);
1768 base = 0;
1769 }
1770 }
1771 #endif
1772 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
1773 if (base == 0) {
1774 base = dev_priv->fb_location + dev_priv->fb_size;
1775 if (base < dev_priv->fb_location ||
1776 ((base + dev_priv->gart_size) & 0xfffffffful) < base)
1777 base = dev_priv->fb_location
1778 - dev_priv->gart_size;
1779 }
1780 dev_priv->gart_vm_start = base & 0xffc00000u;
1781 if (dev_priv->gart_vm_start != base)
1782 DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
1783 base, dev_priv->gart_vm_start);
1784 } else {
1785 DRM_INFO("Setting GART location based on old memory map\n");
1786 dev_priv->gart_vm_start = dev_priv->fb_location +
1787 RADEON_READ(RADEON_CONFIG_APER_SIZE);
1788 }
1789
1790 #if __OS_HAS_AGP
1791 if (dev_priv->flags & RADEON_IS_AGP)
1792 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1793 - dev->agp->base
1794 + dev_priv->gart_vm_start);
1795 else
1796 #endif
1797 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1798 - (unsigned long)dev->sg->virtual
1799 + dev_priv->gart_vm_start);
1800
1801 DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1802 DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
1803 DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1804 dev_priv->gart_buffers_offset);
1805
1806 dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1807 dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
1808 + init->ring_size / sizeof(u32));
1809 dev_priv->ring.size = init->ring_size;
1810 dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
1811
1812 dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
1813 dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ 4096 / 8);
1814
1815 dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
1816 dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ 32 / 16);
1817 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
1818
1819 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1820
1821 #if __OS_HAS_AGP
1822 if (dev_priv->flags & RADEON_IS_AGP) {
1823 /* Turn off PCI GART */
1824 radeon_set_pcigart(dev_priv, 0);
1825 } else
1826 #endif
1827 {
1828 <<<<<<< HEAD:drivers/char/drm/radeon_cp.c
1829 =======
1830 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
1831 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/char/drm/radeon_cp.c
1832 /* if we have an offset set from userspace */
1833 if (dev_priv->pcigart_offset_set) {
1834 dev_priv->gart_info.bus_addr =
1835 dev_priv->pcigart_offset + dev_priv->fb_location;
1836 dev_priv->gart_info.mapping.offset =
1837 dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
1838 dev_priv->gart_info.mapping.size =
1839 dev_priv->gart_info.table_size;
1840
1841 drm_core_ioremap(&dev_priv->gart_info.mapping, dev);
1842 dev_priv->gart_info.addr =
1843 dev_priv->gart_info.mapping.handle;
1844
1845 if (dev_priv->flags & RADEON_IS_PCIE)
1846 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE;
1847 else
1848 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1849 dev_priv->gart_info.gart_table_location =
1850 DRM_ATI_GART_FB;
1851
1852 DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
1853 dev_priv->gart_info.addr,
1854 dev_priv->pcigart_offset);
1855 } else {
1856 if (dev_priv->flags & RADEON_IS_IGPGART)
1857 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP;
1858 else
1859 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1860 dev_priv->gart_info.gart_table_location =
1861 DRM_ATI_GART_MAIN;
1862 dev_priv->gart_info.addr = NULL;
1863 dev_priv->gart_info.bus_addr = 0;
1864 if (dev_priv->flags & RADEON_IS_PCIE) {
1865 DRM_ERROR
1866 ("Cannot use PCI Express without GART in FB memory\n");
1867 radeon_do_cleanup_cp(dev);
1868 return -EINVAL;
1869 }
1870 }
1871
1872 if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) {
1873 DRM_ERROR("failed to init PCI GART!\n");
1874 radeon_do_cleanup_cp(dev);
1875 return -ENOMEM;
1876 }
1877
1878 /* Turn on PCI GART */
1879 radeon_set_pcigart(dev_priv, 1);
1880 }
1881
1882 radeon_cp_load_microcode(dev_priv);
1883 radeon_cp_init_ring_buffer(dev, dev_priv);
1884
1885 dev_priv->last_buf = 0;
1886
1887 radeon_do_engine_reset(dev);
1888 radeon_test_writeback(dev_priv);
1889
1890 return 0;
1891 }
1892
1893 static int radeon_do_cleanup_cp(struct drm_device * dev)
1894 {
1895 drm_radeon_private_t *dev_priv = dev->dev_private;
1896 DRM_DEBUG("\n");
1897
1898 /* Make sure interrupts are disabled here because the uninstall ioctl
1899 * may not have been called from userspace and after dev_private
1900 * is freed, it's too late.
1901 */
1902 if (dev->irq_enabled)
1903 drm_irq_uninstall(dev);
1904
1905 #if __OS_HAS_AGP
1906 if (dev_priv->flags & RADEON_IS_AGP) {
1907 if (dev_priv->cp_ring != NULL) {
1908 drm_core_ioremapfree(dev_priv->cp_ring, dev);
1909 dev_priv->cp_ring = NULL;
1910 }
1911 if (dev_priv->ring_rptr != NULL) {
1912 drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1913 dev_priv->ring_rptr = NULL;
1914 }
1915 if (dev->agp_buffer_map != NULL) {
1916 drm_core_ioremapfree(dev->agp_buffer_map, dev);
1917 dev->agp_buffer_map = NULL;
1918 }
1919 } else
1920 #endif
1921 {
1922
1923 if (dev_priv->gart_info.bus_addr) {
1924 /* Turn off PCI GART */
1925 radeon_set_pcigart(dev_priv, 0);
1926 if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
1927 DRM_ERROR("failed to cleanup PCI GART!\n");
1928 }
1929
1930 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB)
1931 {
1932 drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
1933 dev_priv->gart_info.addr = 0;
1934 }
1935 }
1936 /* only clear to the start of flags */
1937 memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1938
1939 return 0;
1940 }
1941
1942 /* This code will reinit the Radeon CP hardware after a resume from disc.
1943 * AFAIK, it would be very difficult to pickle the state at suspend time, so
1944 * here we make sure that all Radeon hardware initialisation is re-done without
1945 * affecting running applications.
1946 *
1947 * Charl P. Botha <http://cpbotha.net>
1948 */
1949 static int radeon_do_resume_cp(struct drm_device * dev)
1950 {
1951 drm_radeon_private_t *dev_priv = dev->dev_private;
1952
1953 if (!dev_priv) {
1954 DRM_ERROR("Called with no initialization\n");
1955 return -EINVAL;
1956 }
1957
1958 DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1959
1960 #if __OS_HAS_AGP
1961 if (dev_priv->flags & RADEON_IS_AGP) {
1962 /* Turn off PCI GART */
1963 radeon_set_pcigart(dev_priv, 0);
1964 } else
1965 #endif
1966 {
1967 /* Turn on PCI GART */
1968 radeon_set_pcigart(dev_priv, 1);
1969 }
1970
1971 radeon_cp_load_microcode(dev_priv);
1972 radeon_cp_init_ring_buffer(dev, dev_priv);
1973
1974 radeon_do_engine_reset(dev);
1975
1976 DRM_DEBUG("radeon_do_resume_cp() complete\n");
1977
1978 return 0;
1979 }
1980
1981 int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
1982 {
1983 drm_radeon_init_t *init = data;
1984
1985 LOCK_TEST_WITH_RETURN(dev, file_priv);
1986
1987 if (init->func == RADEON_INIT_R300_CP)
1988 r300_init_reg_flags(dev);
1989
1990 switch (init->func) {
1991 case RADEON_INIT_CP:
1992 case RADEON_INIT_R200_CP:
1993 case RADEON_INIT_R300_CP:
1994 return radeon_do_init_cp(dev, init);
1995 case RADEON_CLEANUP_CP:
1996 return radeon_do_cleanup_cp(dev);
1997 }
1998
1999 return -EINVAL;
2000 }
2001
2002 int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv)
2003 {
2004 drm_radeon_private_t *dev_priv = dev->dev_private;
2005 DRM_DEBUG("\n");
2006
2007 LOCK_TEST_WITH_RETURN(dev, file_priv);
2008
2009 if (dev_priv->cp_running) {
2010 DRM_DEBUG("while CP running\n");
2011 return 0;
2012 }
2013 if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) {
2014 DRM_DEBUG("called with bogus CP mode (%d)\n",
2015 dev_priv->cp_mode);
2016 return 0;
2017 }
2018
2019 radeon_do_cp_start(dev_priv);
2020
2021 return 0;
2022 }
2023
2024 /* Stop the CP. The engine must have been idled before calling this
2025 * routine.
2026 */
2027 int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv)
2028 {
2029 drm_radeon_private_t *dev_priv = dev->dev_private;
2030 drm_radeon_cp_stop_t *stop = data;
2031 int ret;
2032 DRM_DEBUG("\n");
2033
2034 LOCK_TEST_WITH_RETURN(dev, file_priv);
2035
2036 if (!dev_priv->cp_running)
2037 return 0;
2038
2039 /* Flush any pending CP commands. This ensures any outstanding
2040 * commands are exectuted by the engine before we turn it off.
2041 */
2042 if (stop->flush) {
2043 radeon_do_cp_flush(dev_priv);
2044 }
2045
2046 /* If we fail to make the engine go idle, we return an error
2047 * code so that the DRM ioctl wrapper can try again.
2048 */
2049 if (stop->idle) {
2050 ret = radeon_do_cp_idle(dev_priv);
2051 if (ret)
2052 return ret;
2053 }
2054
2055 /* Finally, we can turn off the CP. If the engine isn't idle,
2056 * we will get some dropped triangles as they won't be fully
2057 * rendered before the CP is shut down.
2058 */
2059 radeon_do_cp_stop(dev_priv);
2060
2061 /* Reset the engine */
2062 radeon_do_engine_reset(dev);
2063
2064 return 0;
2065 }
2066
2067 void radeon_do_release(struct drm_device * dev)
2068 {
2069 drm_radeon_private_t *dev_priv = dev->dev_private;
2070 int i, ret;
2071
2072 if (dev_priv) {
2073 if (dev_priv->cp_running) {
2074 /* Stop the cp */
2075 while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
2076 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
2077 #ifdef __linux__
2078 schedule();
2079 #else
2080 tsleep(&ret, PZERO, "rdnrel", 1);
2081 #endif
2082 }
2083 radeon_do_cp_stop(dev_priv);
2084 radeon_do_engine_reset(dev);
2085 }
2086
2087 /* Disable *all* interrupts */
2088 if (dev_priv->mmio) /* remove this after permanent addmaps */
2089 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
2090
2091 if (dev_priv->mmio) { /* remove all surfaces */
2092 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
2093 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0);
2094 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND +
2095 16 * i, 0);
2096 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND +
2097 16 * i, 0);
2098 }
2099 }
2100
2101 /* Free memory heap structures */
2102 radeon_mem_takedown(&(dev_priv->gart_heap));
2103 radeon_mem_takedown(&(dev_priv->fb_heap));
2104
2105 /* deallocate kernel resources */
2106 radeon_do_cleanup_cp(dev);
2107 }
2108 }
2109
2110 /* Just reset the CP ring. Called as part of an X Server engine reset.
2111 */
2112 int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
2113 {
2114 drm_radeon_private_t *dev_priv = dev->dev_private;
2115 DRM_DEBUG("\n");
2116
2117 LOCK_TEST_WITH_RETURN(dev, file_priv);
2118
2119 if (!dev_priv) {
2120 DRM_DEBUG("called before init done\n");
2121 return -EINVAL;
2122 }
2123
2124 radeon_do_cp_reset(dev_priv);
2125
2126 /* The CP is no longer running after an engine reset */
2127 dev_priv->cp_running = 0;
2128
2129 return 0;
2130 }
2131
2132 int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv)
2133 {
2134 drm_radeon_private_t *dev_priv = dev->dev_private;
2135 DRM_DEBUG("\n");
2136
2137 LOCK_TEST_WITH_RETURN(dev, file_priv);
2138
2139 return radeon_do_cp_idle(dev_priv);
2140 }
2141
2142 /* Added by Charl P. Botha to call radeon_do_resume_cp().
2143 */
2144 int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv)
2145 {
2146
2147 return radeon_do_resume_cp(dev);
2148 }
2149
2150 int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
2151 {
2152 DRM_DEBUG("\n");
2153
2154 LOCK_TEST_WITH_RETURN(dev, file_priv);
2155
2156 return radeon_do_engine_reset(dev);
2157 }
2158
2159 /* ================================================================
2160 * Fullscreen mode
2161 */
2162
2163 /* KW: Deprecated to say the least:
2164 */
2165 int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv)
2166 {
2167 return 0;
2168 }
2169
2170 /* ================================================================
2171 * Freelist management
2172 */
2173
2174 /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
2175 * bufs until freelist code is used. Note this hides a problem with
2176 * the scratch register * (used to keep track of last buffer
2177 * completed) being written to before * the last buffer has actually
2178 * completed rendering.
2179 *
2180 * KW: It's also a good way to find free buffers quickly.
2181 *
2182 * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
2183 * sleep. However, bugs in older versions of radeon_accel.c mean that
2184 * we essentially have to do this, else old clients will break.
2185 *
2186 * However, it does leave open a potential deadlock where all the
2187 * buffers are held by other clients, which can't release them because
2188 * they can't get the lock.
2189 */
2190
2191 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
2192 {
2193 struct drm_device_dma *dma = dev->dma;
2194 drm_radeon_private_t *dev_priv = dev->dev_private;
2195 drm_radeon_buf_priv_t *buf_priv;
2196 struct drm_buf *buf;
2197 int i, t;
2198 int start;
2199
2200 if (++dev_priv->last_buf >= dma->buf_count)
2201 dev_priv->last_buf = 0;
2202
2203 start = dev_priv->last_buf;
2204
2205 for (t = 0; t < dev_priv->usec_timeout; t++) {
2206 u32 done_age = GET_SCRATCH(1);
2207 DRM_DEBUG("done_age = %d\n", done_age);
2208 for (i = start; i < dma->buf_count; i++) {
2209 buf = dma->buflist[i];
2210 buf_priv = buf->dev_private;
2211 if (buf->file_priv == NULL || (buf->pending &&
2212 buf_priv->age <=
2213 done_age)) {
2214 dev_priv->stats.requested_bufs++;
2215 buf->pending = 0;
2216 return buf;
2217 }
2218 start = 0;
2219 }
2220
2221 if (t) {
2222 DRM_UDELAY(1);
2223 dev_priv->stats.freelist_loops++;
2224 }
2225 }
2226
2227 DRM_DEBUG("returning NULL!\n");
2228 return NULL;
2229 }
2230
2231 #if 0
2232 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
2233 {
2234 struct drm_device_dma *dma = dev->dma;
2235 drm_radeon_private_t *dev_priv = dev->dev_private;
2236 drm_radeon_buf_priv_t *buf_priv;
2237 struct drm_buf *buf;
2238 int i, t;
2239 int start;
2240 u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1));
2241
2242 if (++dev_priv->last_buf >= dma->buf_count)
2243 dev_priv->last_buf = 0;
2244
2245 start = dev_priv->last_buf;
2246 dev_priv->stats.freelist_loops++;
2247
2248 for (t = 0; t < 2; t++) {
2249 for (i = start; i < dma->buf_count; i++) {
2250 buf = dma->buflist[i];
2251 buf_priv = buf->dev_private;
2252 if (buf->file_priv == 0 || (buf->pending &&
2253 buf_priv->age <=
2254 done_age)) {
2255 dev_priv->stats.requested_bufs++;
2256 buf->pending = 0;
2257 return buf;
2258 }
2259 }
2260 start = 0;
2261 }
2262
2263 return NULL;
2264 }
2265 #endif
2266
2267 void radeon_freelist_reset(struct drm_device * dev)
2268 {
2269 struct drm_device_dma *dma = dev->dma;
2270 drm_radeon_private_t *dev_priv = dev->dev_private;
2271 int i;
2272
2273 dev_priv->last_buf = 0;
2274 for (i = 0; i < dma->buf_count; i++) {
2275 struct drm_buf *buf = dma->buflist[i];
2276 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
2277 buf_priv->age = 0;
2278 }
2279 }
2280
2281 /* ================================================================
2282 * CP command submission
2283 */
2284
2285 int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n)
2286 {
2287 drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
2288 int i;
2289 u32 last_head = GET_RING_HEAD(dev_priv);
2290
2291 for (i = 0; i < dev_priv->usec_timeout; i++) {
2292 u32 head = GET_RING_HEAD(dev_priv);
2293
2294 ring->space = (head - ring->tail) * sizeof(u32);
2295 if (ring->space <= 0)
2296 ring->space += ring->size;
2297 if (ring->space > n)
2298 return 0;
2299
2300 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
2301
2302 if (head != last_head)
2303 i = 0;
2304 last_head = head;
2305
2306 DRM_UDELAY(1);
2307 }
2308
2309 /* FIXME: This return value is ignored in the BEGIN_RING macro! */
2310 #if RADEON_FIFO_DEBUG
2311 radeon_status(dev_priv);
2312 DRM_ERROR("failed!\n");
2313 #endif
2314 return -EBUSY;
2315 }
2316
2317 static int radeon_cp_get_buffers(struct drm_device *dev,
2318 struct drm_file *file_priv,
2319 struct drm_dma * d)
2320 {
2321 int i;
2322 struct drm_buf *buf;
2323
2324 for (i = d->granted_count; i < d->request_count; i++) {
2325 buf = radeon_freelist_get(dev);
2326 if (!buf)
2327 return -EBUSY; /* NOTE: broken client */
2328
2329 buf->file_priv = file_priv;
2330
2331 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
2332 sizeof(buf->idx)))
2333 return -EFAULT;
2334 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
2335 sizeof(buf->total)))
2336 return -EFAULT;
2337
2338 d->granted_count++;
2339 }
2340 return 0;
2341 }
2342
2343 int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv)
2344 {
2345 struct drm_device_dma *dma = dev->dma;
2346 int ret = 0;
2347 struct drm_dma *d = data;
2348
2349 LOCK_TEST_WITH_RETURN(dev, file_priv);
2350
2351 /* Please don't send us buffers.
2352 */
2353 if (d->send_count != 0) {
2354 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
2355 DRM_CURRENTPID, d->send_count);
2356 return -EINVAL;
2357 }
2358
2359 /* We'll send you buffers.
2360 */
2361 if (d->request_count < 0 || d->request_count > dma->buf_count) {
2362 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
2363 DRM_CURRENTPID, d->request_count, dma->buf_count);
2364 return -EINVAL;
2365 }
2366
2367 d->granted_count = 0;
2368
2369 if (d->request_count) {
2370 ret = radeon_cp_get_buffers(dev, file_priv, d);
2371 }
2372
2373 return ret;
2374 }
2375
2376 int radeon_driver_load(struct drm_device *dev, unsigned long flags)
2377 {
2378 drm_radeon_private_t *dev_priv;
2379 int ret = 0;
2380
2381 dev_priv = drm_alloc(sizeof(drm_radeon_private_t), DRM_MEM_DRIVER);
2382 if (dev_priv == NULL)
2383 return -ENOMEM;
2384
2385 memset(dev_priv, 0, sizeof(drm_radeon_private_t));
2386 dev->dev_private = (void *)dev_priv;
2387 dev_priv->flags = flags;
2388
2389 switch (flags & RADEON_FAMILY_MASK) {
2390 case CHIP_R100:
2391 case CHIP_RV200:
2392 case CHIP_R200:
2393 case CHIP_R300:
2394 case CHIP_R350:
2395 case CHIP_R420:
2396 case CHIP_RV410:
2397 case CHIP_RV515:
2398 case CHIP_R520:
2399 case CHIP_RV570:
2400 case CHIP_R580:
2401 dev_priv->flags |= RADEON_HAS_HIERZ;
2402 break;
2403 default:
2404 /* all other chips have no hierarchical z buffer */
2405 break;
2406 }
2407
2408 if (drm_device_is_agp(dev))
2409 dev_priv->flags |= RADEON_IS_AGP;
2410 else if (drm_device_is_pcie(dev))
2411 dev_priv->flags |= RADEON_IS_PCIE;
2412 else
2413 dev_priv->flags |= RADEON_IS_PCI;
2414
2415 DRM_DEBUG("%s card detected\n",
2416 ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
2417 return ret;
2418 }
2419
2420 /* Create mappings for registers and framebuffer so userland doesn't necessarily
2421 * have to find them.
2422 */
2423 int radeon_driver_firstopen(struct drm_device *dev)
2424 {
2425 int ret;
2426 drm_local_map_t *map;
2427 drm_radeon_private_t *dev_priv = dev->dev_private;
2428
2429 dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
2430
2431 ret = drm_addmap(dev, drm_get_resource_start(dev, 2),
2432 drm_get_resource_len(dev, 2), _DRM_REGISTERS,
2433 _DRM_READ_ONLY, &dev_priv->mmio);
2434 if (ret != 0)
2435 return ret;
2436
2437 dev_priv->fb_aper_offset = drm_get_resource_start(dev, 0);
2438 ret = drm_addmap(dev, dev_priv->fb_aper_offset,
2439 drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER,
2440 _DRM_WRITE_COMBINING, &map);
2441 if (ret != 0)
2442 return ret;
2443
2444 return 0;
2445 }
2446
2447 int radeon_driver_unload(struct drm_device *dev)
2448 {
2449 drm_radeon_private_t *dev_priv = dev->dev_private;
2450
2451 DRM_DEBUG("\n");
2452 drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
2453
2454 dev->dev_private = NULL;
2455 return 0;
2456 }
WRT350N Kernel Patches