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Merge git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
[wrt350n-kernel.git] / drivers / char / drm / radeon_drv.h
blob6a6433b431c05804fd6bba3f7f3397378c90f16a
1 /* radeon_drv.h -- Private header for radeon driver -*- linux-c -*-
2 *
3 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * All rights reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
25 *
26 * Authors:
27 * Kevin E. Martin <martin@valinux.com>
28 * Gareth Hughes <gareth@valinux.com>
29 */
30
31 #ifndef __RADEON_DRV_H__
32 #define __RADEON_DRV_H__
33
34 /* General customization:
35 */
36
37 #define DRIVER_AUTHOR "Gareth Hughes, Keith Whitwell, others."
38
39 #define DRIVER_NAME "radeon"
40 #define DRIVER_DESC "ATI Radeon"
41 #define DRIVER_DATE "20060524"
42
43 /* Interface history:
44 *
45 * 1.1 - ??
46 * 1.2 - Add vertex2 ioctl (keith)
47 * - Add stencil capability to clear ioctl (gareth, keith)
48 * - Increase MAX_TEXTURE_LEVELS (brian)
49 * 1.3 - Add cmdbuf ioctl (keith)
50 * - Add support for new radeon packets (keith)
51 * - Add getparam ioctl (keith)
52 * - Add flip-buffers ioctl, deprecate fullscreen foo (keith).
53 * 1.4 - Add scratch registers to get_param ioctl.
54 * 1.5 - Add r200 packets to cmdbuf ioctl
55 * - Add r200 function to init ioctl
56 * - Add 'scalar2' instruction to cmdbuf
57 * 1.6 - Add static GART memory manager
58 * Add irq handler (won't be turned on unless X server knows to)
59 * Add irq ioctls and irq_active getparam.
60 * Add wait command for cmdbuf ioctl
61 * Add GART offset query for getparam
62 * 1.7 - Add support for cube map registers: R200_PP_CUBIC_FACES_[0..5]
63 * and R200_PP_CUBIC_OFFSET_F1_[0..5].
64 * Added packets R200_EMIT_PP_CUBIC_FACES_[0..5] and
65 * R200_EMIT_PP_CUBIC_OFFSETS_[0..5]. (brian)
66 * 1.8 - Remove need to call cleanup ioctls on last client exit (keith)
67 * Add 'GET' queries for starting additional clients on different VT's.
68 * 1.9 - Add DRM_IOCTL_RADEON_CP_RESUME ioctl.
69 * Add texture rectangle support for r100.
70 * 1.10- Add SETPARAM ioctl; first parameter to set is FB_LOCATION, which
71 * clients use to tell the DRM where they think the framebuffer is
72 * located in the card's address space
73 * 1.11- Add packet R200_EMIT_RB3D_BLENDCOLOR to support GL_EXT_blend_color
74 * and GL_EXT_blend_[func|equation]_separate on r200
75 * 1.12- Add R300 CP microcode support - this just loads the CP on r300
76 * (No 3D support yet - just microcode loading).
77 * 1.13- Add packet R200_EMIT_TCL_POINT_SPRITE_CNTL for ARB_point_parameters
78 * - Add hyperz support, add hyperz flags to clear ioctl.
79 * 1.14- Add support for color tiling
80 * - Add R100/R200 surface allocation/free support
81 * 1.15- Add support for texture micro tiling
82 * - Add support for r100 cube maps
83 * 1.16- Add R200_EMIT_PP_TRI_PERF_CNTL packet to support brilinear
84 * texture filtering on r200
85 * 1.17- Add initial support for R300 (3D).
86 * 1.18- Add support for GL_ATI_fragment_shader, new packets
87 * R200_EMIT_PP_AFS_0/1, R200_EMIT_PP_TXCTLALL_0-5 (replaces
88 * R200_EMIT_PP_TXFILTER_0-5, 2 more regs) and R200_EMIT_ATF_TFACTOR
89 * (replaces R200_EMIT_TFACTOR_0 (8 consts instead of 6)
90 * 1.19- Add support for gart table in FB memory and PCIE r300
91 * 1.20- Add support for r300 texrect
92 * 1.21- Add support for card type getparam
93 * 1.22- Add support for texture cache flushes (R300_TX_CNTL)
94 * 1.23- Add new radeon memory map work from benh
95 * 1.24- Add general-purpose packet for manipulating scratch registers (r300)
96 * 1.25- Add support for r200 vertex programs (R200_EMIT_VAP_PVS_CNTL,
97 * new packet type)
98 * 1.26- Add support for variable size PCI(E) gart aperture
99 * 1.27- Add support for IGP GART
100 * 1.28- Add support for VBL on CRTC2
101 */
102 #define DRIVER_MAJOR 1
103 #define DRIVER_MINOR 28
104 #define DRIVER_PATCHLEVEL 0
105
106 /*
107 * Radeon chip families
108 */
109 enum radeon_family {
110 CHIP_R100,
111 CHIP_RV100,
112 CHIP_RS100,
113 CHIP_RV200,
114 CHIP_RS200,
115 CHIP_R200,
116 CHIP_RV250,
117 CHIP_RS300,
118 CHIP_RV280,
119 CHIP_R300,
120 CHIP_R350,
121 CHIP_RV350,
122 CHIP_RV380,
123 CHIP_R420,
124 CHIP_RV410,
125 CHIP_RS400,
126 <<<<<<< HEAD:drivers/char/drm/radeon_drv.h
127 =======
128 CHIP_RS690,
129 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/char/drm/radeon_drv.h
130 CHIP_RV515,
131 CHIP_R520,
132 CHIP_RV530,
133 CHIP_RV560,
134 CHIP_RV570,
135 CHIP_R580,
136 CHIP_LAST,
137 };
138
139 enum radeon_cp_microcode_version {
140 UCODE_R100,
141 UCODE_R200,
142 UCODE_R300,
143 };
144
145 /*
146 * Chip flags
147 */
148 enum radeon_chip_flags {
149 RADEON_FAMILY_MASK = 0x0000ffffUL,
150 RADEON_FLAGS_MASK = 0xffff0000UL,
151 RADEON_IS_MOBILITY = 0x00010000UL,
152 RADEON_IS_IGP = 0x00020000UL,
153 RADEON_SINGLE_CRTC = 0x00040000UL,
154 RADEON_IS_AGP = 0x00080000UL,
155 RADEON_HAS_HIERZ = 0x00100000UL,
156 RADEON_IS_PCIE = 0x00200000UL,
157 RADEON_NEW_MEMMAP = 0x00400000UL,
158 RADEON_IS_PCI = 0x00800000UL,
159 RADEON_IS_IGPGART = 0x01000000UL,
160 };
161
162 #define GET_RING_HEAD(dev_priv) (dev_priv->writeback_works ? \
163 DRM_READ32( (dev_priv)->ring_rptr, 0 ) : RADEON_READ(RADEON_CP_RB_RPTR))
164 #define SET_RING_HEAD(dev_priv,val) DRM_WRITE32( (dev_priv)->ring_rptr, 0, (val) )
165
166 typedef struct drm_radeon_freelist {
167 unsigned int age;
168 struct drm_buf *buf;
169 struct drm_radeon_freelist *next;
170 struct drm_radeon_freelist *prev;
171 } drm_radeon_freelist_t;
172
173 typedef struct drm_radeon_ring_buffer {
174 u32 *start;
175 u32 *end;
176 int size;
177 int size_l2qw;
178
179 int rptr_update; /* Double Words */
180 int rptr_update_l2qw; /* log2 Quad Words */
181
182 int fetch_size; /* Double Words */
183 int fetch_size_l2ow; /* log2 Oct Words */
184
185 u32 tail;
186 u32 tail_mask;
187 int space;
188
189 int high_mark;
190 } drm_radeon_ring_buffer_t;
191
192 typedef struct drm_radeon_depth_clear_t {
193 u32 rb3d_cntl;
194 u32 rb3d_zstencilcntl;
195 u32 se_cntl;
196 } drm_radeon_depth_clear_t;
197
198 struct drm_radeon_driver_file_fields {
199 int64_t radeon_fb_delta;
200 };
201
202 struct mem_block {
203 struct mem_block *next;
204 struct mem_block *prev;
205 int start;
206 int size;
207 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
208 };
209
210 struct radeon_surface {
211 int refcount;
212 u32 lower;
213 u32 upper;
214 u32 flags;
215 };
216
217 struct radeon_virt_surface {
218 int surface_index;
219 u32 lower;
220 u32 upper;
221 u32 flags;
222 struct drm_file *file_priv;
223 };
224
225 typedef struct drm_radeon_private {
226 drm_radeon_ring_buffer_t ring;
227 drm_radeon_sarea_t *sarea_priv;
228
229 u32 fb_location;
230 u32 fb_size;
231 int new_memmap;
232
233 int gart_size;
234 u32 gart_vm_start;
235 unsigned long gart_buffers_offset;
236
237 int cp_mode;
238 int cp_running;
239
240 drm_radeon_freelist_t *head;
241 drm_radeon_freelist_t *tail;
242 int last_buf;
243 volatile u32 *scratch;
244 int writeback_works;
245
246 int usec_timeout;
247
248 int microcode_version;
249
250 struct {
251 u32 boxes;
252 int freelist_timeouts;
253 int freelist_loops;
254 int requested_bufs;
255 int last_frame_reads;
256 int last_clear_reads;
257 int clears;
258 int texture_uploads;
259 } stats;
260
261 int do_boxes;
262 int page_flipping;
263
264 u32 color_fmt;
265 unsigned int front_offset;
266 unsigned int front_pitch;
267 unsigned int back_offset;
268 unsigned int back_pitch;
269
270 u32 depth_fmt;
271 unsigned int depth_offset;
272 unsigned int depth_pitch;
273
274 u32 front_pitch_offset;
275 u32 back_pitch_offset;
276 u32 depth_pitch_offset;
277
278 drm_radeon_depth_clear_t depth_clear;
279
280 unsigned long ring_offset;
281 unsigned long ring_rptr_offset;
282 unsigned long buffers_offset;
283 unsigned long gart_textures_offset;
284
285 drm_local_map_t *sarea;
286 drm_local_map_t *mmio;
287 drm_local_map_t *cp_ring;
288 drm_local_map_t *ring_rptr;
289 drm_local_map_t *gart_textures;
290
291 struct mem_block *gart_heap;
292 struct mem_block *fb_heap;
293
294 /* SW interrupt */
295 wait_queue_head_t swi_queue;
296 atomic_t swi_emitted;
297 int vblank_crtc;
298 uint32_t irq_enable_reg;
299 int irq_enabled;
300
301 struct radeon_surface surfaces[RADEON_MAX_SURFACES];
302 struct radeon_virt_surface virt_surfaces[2 * RADEON_MAX_SURFACES];
303
304 unsigned long pcigart_offset;
305 unsigned int pcigart_offset_set;
306 struct drm_ati_pcigart_info gart_info;
307
308 u32 scratch_ages[5];
309
310 /* starting from here on, data is preserved accross an open */
311 uint32_t flags; /* see radeon_chip_flags */
312 unsigned long fb_aper_offset;
313 } drm_radeon_private_t;
314
315 typedef struct drm_radeon_buf_priv {
316 u32 age;
317 } drm_radeon_buf_priv_t;
318
319 typedef struct drm_radeon_kcmd_buffer {
320 int bufsz;
321 char *buf;
322 int nbox;
323 struct drm_clip_rect __user *boxes;
324 } drm_radeon_kcmd_buffer_t;
325
326 extern int radeon_no_wb;
327 extern struct drm_ioctl_desc radeon_ioctls[];
328 extern int radeon_max_ioctl;
329
330 /* Check whether the given hardware address is inside the framebuffer or the
331 * GART area.
332 */
333 static __inline__ int radeon_check_offset(drm_radeon_private_t *dev_priv,
334 u64 off)
335 {
336 u32 fb_start = dev_priv->fb_location;
337 u32 fb_end = fb_start + dev_priv->fb_size - 1;
338 u32 gart_start = dev_priv->gart_vm_start;
339 u32 gart_end = gart_start + dev_priv->gart_size - 1;
340
341 return ((off >= fb_start && off <= fb_end) ||
342 (off >= gart_start && off <= gart_end));
343 }
344
345 /* radeon_cp.c */
346 extern int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv);
347 extern int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv);
348 extern int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv);
349 extern int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv);
350 extern int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv);
351 extern int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv);
352 extern int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv);
353 extern int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv);
354 extern int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv);
355 extern u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv);
356
357 extern void radeon_freelist_reset(struct drm_device * dev);
358 extern struct drm_buf *radeon_freelist_get(struct drm_device * dev);
359
360 extern int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n);
361
362 extern int radeon_do_cp_idle(drm_radeon_private_t * dev_priv);
363
364 extern int radeon_driver_preinit(struct drm_device *dev, unsigned long flags);
365 extern int radeon_presetup(struct drm_device *dev);
366 extern int radeon_driver_postcleanup(struct drm_device *dev);
367
368 extern int radeon_mem_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv);
369 extern int radeon_mem_free(struct drm_device *dev, void *data, struct drm_file *file_priv);
370 extern int radeon_mem_init_heap(struct drm_device *dev, void *data, struct drm_file *file_priv);
371 extern void radeon_mem_takedown(struct mem_block **heap);
372 extern void radeon_mem_release(struct drm_file *file_priv,
373 struct mem_block *heap);
374
375 /* radeon_irq.c */
376 extern int radeon_irq_emit(struct drm_device *dev, void *data, struct drm_file *file_priv);
377 extern int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_priv);
378
379 extern void radeon_do_release(struct drm_device * dev);
380 extern int radeon_driver_vblank_wait(struct drm_device * dev,
381 unsigned int *sequence);
382 extern int radeon_driver_vblank_wait2(struct drm_device * dev,
383 unsigned int *sequence);
384 extern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS);
385 extern void radeon_driver_irq_preinstall(struct drm_device * dev);
386 extern void radeon_driver_irq_postinstall(struct drm_device * dev);
387 extern void radeon_driver_irq_uninstall(struct drm_device * dev);
388 extern int radeon_vblank_crtc_get(struct drm_device *dev);
389 extern int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value);
390
391 extern int radeon_driver_load(struct drm_device *dev, unsigned long flags);
392 extern int radeon_driver_unload(struct drm_device *dev);
393 extern int radeon_driver_firstopen(struct drm_device *dev);
394 extern void radeon_driver_preclose(struct drm_device * dev, struct drm_file *file_priv);
395 extern void radeon_driver_postclose(struct drm_device * dev, struct drm_file * filp);
396 extern void radeon_driver_lastclose(struct drm_device * dev);
397 extern int radeon_driver_open(struct drm_device * dev, struct drm_file * filp_priv);
398 extern long radeon_compat_ioctl(struct file *filp, unsigned int cmd,
399 unsigned long arg);
400
401 /* r300_cmdbuf.c */
402 extern void r300_init_reg_flags(struct drm_device *dev);
403
404 extern int r300_do_cp_cmdbuf(struct drm_device * dev,
405 struct drm_file *file_priv,
406 drm_radeon_kcmd_buffer_t * cmdbuf);
407
408 /* Flags for stats.boxes
409 */
410 #define RADEON_BOX_DMA_IDLE 0x1
411 #define RADEON_BOX_RING_FULL 0x2
412 #define RADEON_BOX_FLIP 0x4
413 #define RADEON_BOX_WAIT_IDLE 0x8
414 #define RADEON_BOX_TEXTURE_LOAD 0x10
415
416 /* Register definitions, register access macros and drmAddMap constants
417 * for Radeon kernel driver.
418 */
419
420 #define RADEON_AGP_COMMAND 0x0f60
421 #define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config */
422 # define RADEON_AGP_ENABLE (1<<8)
423 #define RADEON_AUX_SCISSOR_CNTL 0x26f0
424 # define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24)
425 # define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25)
426 # define RADEON_EXCLUSIVE_SCISSOR_2 (1 << 26)
427 # define RADEON_SCISSOR_0_ENABLE (1 << 28)
428 # define RADEON_SCISSOR_1_ENABLE (1 << 29)
429 # define RADEON_SCISSOR_2_ENABLE (1 << 30)
430
431 #define RADEON_BUS_CNTL 0x0030
432 # define RADEON_BUS_MASTER_DIS (1 << 6)
433
434 #define RADEON_CLOCK_CNTL_DATA 0x000c
435 # define RADEON_PLL_WR_EN (1 << 7)
436 #define RADEON_CLOCK_CNTL_INDEX 0x0008
437 #define RADEON_CONFIG_APER_SIZE 0x0108
438 #define RADEON_CONFIG_MEMSIZE 0x00f8
439 #define RADEON_CRTC_OFFSET 0x0224
440 #define RADEON_CRTC_OFFSET_CNTL 0x0228
441 # define RADEON_CRTC_TILE_EN (1 << 15)
442 # define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16)
443 #define RADEON_CRTC2_OFFSET 0x0324
444 #define RADEON_CRTC2_OFFSET_CNTL 0x0328
445
446 #define RADEON_PCIE_INDEX 0x0030
447 #define RADEON_PCIE_DATA 0x0034
448 #define RADEON_PCIE_TX_GART_CNTL 0x10
449 # define RADEON_PCIE_TX_GART_EN (1 << 0)
450 # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0<<1)
451 # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1<<1)
452 # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3<<1)
453 # define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0<<3)
454 # define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1<<3)
455 # define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1<<5)
456 # define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1<<8)
457 #define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11
458 #define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12
459 #define RADEON_PCIE_TX_GART_BASE 0x13
460 #define RADEON_PCIE_TX_GART_START_LO 0x14
461 #define RADEON_PCIE_TX_GART_START_HI 0x15
462 #define RADEON_PCIE_TX_GART_END_LO 0x16
463 #define RADEON_PCIE_TX_GART_END_HI 0x17
464
465 #define RADEON_IGPGART_INDEX 0x168
466 #define RADEON_IGPGART_DATA 0x16c
467 #define RADEON_IGPGART_UNK_18 0x18
468 #define RADEON_IGPGART_CTRL 0x2b
469 #define RADEON_IGPGART_BASE_ADDR 0x2c
470 #define RADEON_IGPGART_FLUSH 0x2e
471 #define RADEON_IGPGART_ENABLE 0x38
472 #define RADEON_IGPGART_UNK_39 0x39
473
474 <<<<<<< HEAD:drivers/char/drm/radeon_drv.h
475 =======
476 #define RS690_MC_INDEX 0x78
477 # define RS690_MC_INDEX_MASK 0x1ff
478 # define RS690_MC_INDEX_WR_EN (1 << 9)
479 # define RS690_MC_INDEX_WR_ACK 0x7f
480 #define RS690_MC_DATA 0x7c
481
482 #define RS690_MC_MISC_CNTL 0x18
483 #define RS690_MC_GART_FEATURE_ID 0x2b
484 #define RS690_MC_GART_BASE 0x2c
485 #define RS690_MC_GART_CACHE_CNTL 0x2e
486 # define RS690_MC_GART_CC_NO_CHANGE 0x0
487 # define RS690_MC_GART_CC_CLEAR 0x1
488 # define RS690_MC_GART_CLEAR_STATUS (1 << 1)
489 # define RS690_MC_GART_CLEAR_DONE (0 << 1)
490 # define RS690_MC_GART_CLEAR_PENDING (1 << 1)
491 #define RS690_MC_AGP_SIZE 0x38
492 # define RS690_MC_GART_DIS 0x0
493 # define RS690_MC_GART_EN 0x1
494 # define RS690_MC_AGP_SIZE_32MB (0 << 1)
495 # define RS690_MC_AGP_SIZE_64MB (1 << 1)
496 # define RS690_MC_AGP_SIZE_128MB (2 << 1)
497 # define RS690_MC_AGP_SIZE_256MB (3 << 1)
498 # define RS690_MC_AGP_SIZE_512MB (4 << 1)
499 # define RS690_MC_AGP_SIZE_1GB (5 << 1)
500 # define RS690_MC_AGP_SIZE_2GB (6 << 1)
501 #define RS690_MC_AGP_MODE_CONTROL 0x39
502 #define RS690_MC_FB_LOCATION 0x100
503 #define RS690_MC_AGP_LOCATION 0x101
504 #define RS690_MC_AGP_BASE 0x102
505
506 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/char/drm/radeon_drv.h
507 #define R520_MC_IND_INDEX 0x70
508 #define R520_MC_IND_WR_EN (1<<24)
509 #define R520_MC_IND_DATA 0x74
510
511 #define RV515_MC_FB_LOCATION 0x01
512 #define RV515_MC_AGP_LOCATION 0x02
513
514 #define R520_MC_FB_LOCATION 0x04
515 #define R520_MC_AGP_LOCATION 0x05
516
517 #define RADEON_MPP_TB_CONFIG 0x01c0
518 #define RADEON_MEM_CNTL 0x0140
519 #define RADEON_MEM_SDRAM_MODE_REG 0x0158
520 #define RADEON_AGP_BASE 0x0170
521
522 #define RADEON_RB3D_COLOROFFSET 0x1c40
523 #define RADEON_RB3D_COLORPITCH 0x1c48
524
525 #define RADEON_SRC_X_Y 0x1590
526
527 #define RADEON_DP_GUI_MASTER_CNTL 0x146c
528 # define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
529 # define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
530 # define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4)
531 # define RADEON_GMC_BRUSH_NONE (15 << 4)
532 # define RADEON_GMC_DST_16BPP (4 << 8)
533 # define RADEON_GMC_DST_24BPP (5 << 8)
534 # define RADEON_GMC_DST_32BPP (6 << 8)
535 # define RADEON_GMC_DST_DATATYPE_SHIFT 8
536 # define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12)
537 # define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24)
538 # define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24)
539 # define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28)
540 # define RADEON_GMC_WR_MSK_DIS (1 << 30)
541 # define RADEON_ROP3_S 0x00cc0000
542 # define RADEON_ROP3_P 0x00f00000
543 #define RADEON_DP_WRITE_MASK 0x16cc
544 #define RADEON_SRC_PITCH_OFFSET 0x1428
545 #define RADEON_DST_PITCH_OFFSET 0x142c
546 #define RADEON_DST_PITCH_OFFSET_C 0x1c80
547 # define RADEON_DST_TILE_LINEAR (0 << 30)
548 # define RADEON_DST_TILE_MACRO (1 << 30)
549 # define RADEON_DST_TILE_MICRO (2 << 30)
550 # define RADEON_DST_TILE_BOTH (3 << 30)
551
552 #define RADEON_SCRATCH_REG0 0x15e0
553 #define RADEON_SCRATCH_REG1 0x15e4
554 #define RADEON_SCRATCH_REG2 0x15e8
555 #define RADEON_SCRATCH_REG3 0x15ec
556 #define RADEON_SCRATCH_REG4 0x15f0
557 #define RADEON_SCRATCH_REG5 0x15f4
558 #define RADEON_SCRATCH_UMSK 0x0770
559 #define RADEON_SCRATCH_ADDR 0x0774
560
561 #define RADEON_SCRATCHOFF( x ) (RADEON_SCRATCH_REG_OFFSET + 4*(x))
562
563 #define GET_SCRATCH( x ) (dev_priv->writeback_works \
564 ? DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(x) ) \
565 : RADEON_READ( RADEON_SCRATCH_REG0 + 4*(x) ) )
566
567 #define RADEON_GEN_INT_CNTL 0x0040
568 # define RADEON_CRTC_VBLANK_MASK (1 << 0)
569 # define RADEON_CRTC2_VBLANK_MASK (1 << 9)
570 # define RADEON_GUI_IDLE_INT_ENABLE (1 << 19)
571 # define RADEON_SW_INT_ENABLE (1 << 25)
572
573 #define RADEON_GEN_INT_STATUS 0x0044
574 # define RADEON_CRTC_VBLANK_STAT (1 << 0)
575 # define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0)
576 # define RADEON_CRTC2_VBLANK_STAT (1 << 9)
577 # define RADEON_CRTC2_VBLANK_STAT_ACK (1 << 9)
578 # define RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19)
579 # define RADEON_SW_INT_TEST (1 << 25)
580 # define RADEON_SW_INT_TEST_ACK (1 << 25)
581 # define RADEON_SW_INT_FIRE (1 << 26)
582
583 #define RADEON_HOST_PATH_CNTL 0x0130
584 # define RADEON_HDP_SOFT_RESET (1 << 26)
585 # define RADEON_HDP_WC_TIMEOUT_MASK (7 << 28)
586 # define RADEON_HDP_WC_TIMEOUT_28BCLK (7 << 28)
587
588 #define RADEON_ISYNC_CNTL 0x1724
589 # define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0)
590 # define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1)
591 # define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2)
592 # define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3)
593 # define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4)
594 # define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5)
595
596 #define RADEON_RBBM_GUICNTL 0x172c
597 # define RADEON_HOST_DATA_SWAP_NONE (0 << 0)
598 # define RADEON_HOST_DATA_SWAP_16BIT (1 << 0)
599 # define RADEON_HOST_DATA_SWAP_32BIT (2 << 0)
600 # define RADEON_HOST_DATA_SWAP_HDW (3 << 0)
601
602 #define RADEON_MC_AGP_LOCATION 0x014c
603 #define RADEON_MC_FB_LOCATION 0x0148
604 #define RADEON_MCLK_CNTL 0x0012
605 # define RADEON_FORCEON_MCLKA (1 << 16)
606 # define RADEON_FORCEON_MCLKB (1 << 17)
607 # define RADEON_FORCEON_YCLKA (1 << 18)
608 # define RADEON_FORCEON_YCLKB (1 << 19)
609 # define RADEON_FORCEON_MC (1 << 20)
610 # define RADEON_FORCEON_AIC (1 << 21)
611
612 #define RADEON_PP_BORDER_COLOR_0 0x1d40
613 #define RADEON_PP_BORDER_COLOR_1 0x1d44
614 #define RADEON_PP_BORDER_COLOR_2 0x1d48
615 #define RADEON_PP_CNTL 0x1c38
616 # define RADEON_SCISSOR_ENABLE (1 << 1)
617 #define RADEON_PP_LUM_MATRIX 0x1d00
618 #define RADEON_PP_MISC 0x1c14
619 #define RADEON_PP_ROT_MATRIX_0 0x1d58
620 #define RADEON_PP_TXFILTER_0 0x1c54
621 #define RADEON_PP_TXOFFSET_0 0x1c5c
622 #define RADEON_PP_TXFILTER_1 0x1c6c
623 #define RADEON_PP_TXFILTER_2 0x1c84
624
625 #define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c
626 # define RADEON_RB2D_DC_FLUSH (3 << 0)
627 # define RADEON_RB2D_DC_FREE (3 << 2)
628 # define RADEON_RB2D_DC_FLUSH_ALL 0xf
629 # define RADEON_RB2D_DC_BUSY (1 << 31)
630 #define RADEON_RB3D_CNTL 0x1c3c
631 # define RADEON_ALPHA_BLEND_ENABLE (1 << 0)
632 # define RADEON_PLANE_MASK_ENABLE (1 << 1)
633 # define RADEON_DITHER_ENABLE (1 << 2)
634 # define RADEON_ROUND_ENABLE (1 << 3)
635 # define RADEON_SCALE_DITHER_ENABLE (1 << 4)
636 # define RADEON_DITHER_INIT (1 << 5)
637 # define RADEON_ROP_ENABLE (1 << 6)
638 # define RADEON_STENCIL_ENABLE (1 << 7)
639 # define RADEON_Z_ENABLE (1 << 8)
640 # define RADEON_ZBLOCK16 (1 << 15)
641 #define RADEON_RB3D_DEPTHOFFSET 0x1c24
642 #define RADEON_RB3D_DEPTHCLEARVALUE 0x3230
643 #define RADEON_RB3D_DEPTHPITCH 0x1c28
644 #define RADEON_RB3D_PLANEMASK 0x1d84
645 #define RADEON_RB3D_STENCILREFMASK 0x1d7c
646 #define RADEON_RB3D_ZCACHE_MODE 0x3250
647 #define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254
648 # define RADEON_RB3D_ZC_FLUSH (1 << 0)
649 # define RADEON_RB3D_ZC_FREE (1 << 2)
650 # define RADEON_RB3D_ZC_FLUSH_ALL 0x5
651 # define RADEON_RB3D_ZC_BUSY (1 << 31)
652 #define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325c
653 # define RADEON_RB3D_DC_FLUSH (3 << 0)
654 # define RADEON_RB3D_DC_FREE (3 << 2)
655 # define RADEON_RB3D_DC_FLUSH_ALL 0xf
656 # define RADEON_RB3D_DC_BUSY (1 << 31)
657 #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
658 # define RADEON_Z_TEST_MASK (7 << 4)
659 # define RADEON_Z_TEST_ALWAYS (7 << 4)
660 # define RADEON_Z_HIERARCHY_ENABLE (1 << 8)
661 # define RADEON_STENCIL_TEST_ALWAYS (7 << 12)
662 # define RADEON_STENCIL_S_FAIL_REPLACE (2 << 16)
663 # define RADEON_STENCIL_ZPASS_REPLACE (2 << 20)
664 # define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24)
665 # define RADEON_Z_COMPRESSION_ENABLE (1 << 28)
666 # define RADEON_FORCE_Z_DIRTY (1 << 29)
667 # define RADEON_Z_WRITE_ENABLE (1 << 30)
668 # define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31)
669 #define RADEON_RBBM_SOFT_RESET 0x00f0
670 # define RADEON_SOFT_RESET_CP (1 << 0)
671 # define RADEON_SOFT_RESET_HI (1 << 1)
672 # define RADEON_SOFT_RESET_SE (1 << 2)
673 # define RADEON_SOFT_RESET_RE (1 << 3)
674 # define RADEON_SOFT_RESET_PP (1 << 4)
675 # define RADEON_SOFT_RESET_E2 (1 << 5)
676 # define RADEON_SOFT_RESET_RB (1 << 6)
677 # define RADEON_SOFT_RESET_HDP (1 << 7)
678 /*
679 * 6:0 Available slots in the FIFO
680 * 8 Host Interface active
681 * 9 CP request active
682 * 10 FIFO request active
683 * 11 Host Interface retry active
684 * 12 CP retry active
685 * 13 FIFO retry active
686 * 14 FIFO pipeline busy
687 * 15 Event engine busy
688 * 16 CP command stream busy
689 * 17 2D engine busy
690 * 18 2D portion of render backend busy
691 * 20 3D setup engine busy
692 * 26 GA engine busy
693 * 27 CBA 2D engine busy
694 * 31 2D engine busy or 3D engine busy or FIFO not empty or CP busy or
695 * command stream queue not empty or Ring Buffer not empty
696 */
697 #define RADEON_RBBM_STATUS 0x0e40
698 /* Same as the previous RADEON_RBBM_STATUS; this is a mirror of that register. */
699 /* #define RADEON_RBBM_STATUS 0x1740 */
700 /* bits 6:0 are dword slots available in the cmd fifo */
701 # define RADEON_RBBM_FIFOCNT_MASK 0x007f
702 # define RADEON_HIRQ_ON_RBB (1 << 8)
703 # define RADEON_CPRQ_ON_RBB (1 << 9)
704 # define RADEON_CFRQ_ON_RBB (1 << 10)
705 # define RADEON_HIRQ_IN_RTBUF (1 << 11)
706 # define RADEON_CPRQ_IN_RTBUF (1 << 12)
707 # define RADEON_CFRQ_IN_RTBUF (1 << 13)
708 # define RADEON_PIPE_BUSY (1 << 14)
709 # define RADEON_ENG_EV_BUSY (1 << 15)
710 # define RADEON_CP_CMDSTRM_BUSY (1 << 16)
711 # define RADEON_E2_BUSY (1 << 17)
712 # define RADEON_RB2D_BUSY (1 << 18)
713 # define RADEON_RB3D_BUSY (1 << 19) /* not used on r300 */
714 # define RADEON_VAP_BUSY (1 << 20)
715 # define RADEON_RE_BUSY (1 << 21) /* not used on r300 */
716 # define RADEON_TAM_BUSY (1 << 22) /* not used on r300 */
717 # define RADEON_TDM_BUSY (1 << 23) /* not used on r300 */
718 # define RADEON_PB_BUSY (1 << 24) /* not used on r300 */
719 # define RADEON_TIM_BUSY (1 << 25) /* not used on r300 */
720 # define RADEON_GA_BUSY (1 << 26)
721 # define RADEON_CBA2D_BUSY (1 << 27)
722 # define RADEON_RBBM_ACTIVE (1 << 31)
723 #define RADEON_RE_LINE_PATTERN 0x1cd0
724 #define RADEON_RE_MISC 0x26c4
725 #define RADEON_RE_TOP_LEFT 0x26c0
726 #define RADEON_RE_WIDTH_HEIGHT 0x1c44
727 #define RADEON_RE_STIPPLE_ADDR 0x1cc8
728 #define RADEON_RE_STIPPLE_DATA 0x1ccc
729
730 #define RADEON_SCISSOR_TL_0 0x1cd8
731 #define RADEON_SCISSOR_BR_0 0x1cdc
732 #define RADEON_SCISSOR_TL_1 0x1ce0
733 #define RADEON_SCISSOR_BR_1 0x1ce4
734 #define RADEON_SCISSOR_TL_2 0x1ce8
735 #define RADEON_SCISSOR_BR_2 0x1cec
736 #define RADEON_SE_COORD_FMT 0x1c50
737 #define RADEON_SE_CNTL 0x1c4c
738 # define RADEON_FFACE_CULL_CW (0 << 0)
739 # define RADEON_BFACE_SOLID (3 << 1)
740 # define RADEON_FFACE_SOLID (3 << 3)
741 # define RADEON_FLAT_SHADE_VTX_LAST (3 << 6)
742 # define RADEON_DIFFUSE_SHADE_FLAT (1 << 8)
743 # define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8)
744 # define RADEON_ALPHA_SHADE_FLAT (1 << 10)
745 # define RADEON_ALPHA_SHADE_GOURAUD (2 << 10)
746 # define RADEON_SPECULAR_SHADE_FLAT (1 << 12)
747 # define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12)
748 # define RADEON_FOG_SHADE_FLAT (1 << 14)
749 # define RADEON_FOG_SHADE_GOURAUD (2 << 14)
750 # define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24)
751 # define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25)
752 # define RADEON_VTX_PIX_CENTER_OGL (1 << 27)
753 # define RADEON_ROUND_MODE_TRUNC (0 << 28)
754 # define RADEON_ROUND_PREC_8TH_PIX (1 << 30)
755 #define RADEON_SE_CNTL_STATUS 0x2140
756 #define RADEON_SE_LINE_WIDTH 0x1db8
757 #define RADEON_SE_VPORT_XSCALE 0x1d98
758 #define RADEON_SE_ZBIAS_FACTOR 0x1db0
759 #define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210
760 #define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254
761 #define RADEON_SE_TCL_VECTOR_INDX_REG 0x2200
762 # define RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT 16
763 # define RADEON_VEC_INDX_DWORD_COUNT_SHIFT 28
764 #define RADEON_SE_TCL_VECTOR_DATA_REG 0x2204
765 #define RADEON_SE_TCL_SCALAR_INDX_REG 0x2208
766 # define RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT 16
767 #define RADEON_SE_TCL_SCALAR_DATA_REG 0x220C
768 #define RADEON_SURFACE_ACCESS_FLAGS 0x0bf8
769 #define RADEON_SURFACE_ACCESS_CLR 0x0bfc
770 #define RADEON_SURFACE_CNTL 0x0b00
771 # define RADEON_SURF_TRANSLATION_DIS (1 << 8)
772 # define RADEON_NONSURF_AP0_SWP_MASK (3 << 20)
773 # define RADEON_NONSURF_AP0_SWP_LITTLE (0 << 20)
774 # define RADEON_NONSURF_AP0_SWP_BIG16 (1 << 20)
775 # define RADEON_NONSURF_AP0_SWP_BIG32 (2 << 20)
776 # define RADEON_NONSURF_AP1_SWP_MASK (3 << 22)
777 # define RADEON_NONSURF_AP1_SWP_LITTLE (0 << 22)
778 # define RADEON_NONSURF_AP1_SWP_BIG16 (1 << 22)
779 # define RADEON_NONSURF_AP1_SWP_BIG32 (2 << 22)
780 #define RADEON_SURFACE0_INFO 0x0b0c
781 # define RADEON_SURF_PITCHSEL_MASK (0x1ff << 0)
782 # define RADEON_SURF_TILE_MODE_MASK (3 << 16)
783 # define RADEON_SURF_TILE_MODE_MACRO (0 << 16)
784 # define RADEON_SURF_TILE_MODE_MICRO (1 << 16)
785 # define RADEON_SURF_TILE_MODE_32BIT_Z (2 << 16)
786 # define RADEON_SURF_TILE_MODE_16BIT_Z (3 << 16)
787 #define RADEON_SURFACE0_LOWER_BOUND 0x0b04
788 #define RADEON_SURFACE0_UPPER_BOUND 0x0b08
789 # define RADEON_SURF_ADDRESS_FIXED_MASK (0x3ff << 0)
790 #define RADEON_SURFACE1_INFO 0x0b1c
791 #define RADEON_SURFACE1_LOWER_BOUND 0x0b14
792 #define RADEON_SURFACE1_UPPER_BOUND 0x0b18
793 #define RADEON_SURFACE2_INFO 0x0b2c
794 #define RADEON_SURFACE2_LOWER_BOUND 0x0b24
795 #define RADEON_SURFACE2_UPPER_BOUND 0x0b28
796 #define RADEON_SURFACE3_INFO 0x0b3c
797 #define RADEON_SURFACE3_LOWER_BOUND 0x0b34
798 #define RADEON_SURFACE3_UPPER_BOUND 0x0b38
799 #define RADEON_SURFACE4_INFO 0x0b4c
800 #define RADEON_SURFACE4_LOWER_BOUND 0x0b44
801 #define RADEON_SURFACE4_UPPER_BOUND 0x0b48
802 #define RADEON_SURFACE5_INFO 0x0b5c
803 #define RADEON_SURFACE5_LOWER_BOUND 0x0b54
804 #define RADEON_SURFACE5_UPPER_BOUND 0x0b58
805 #define RADEON_SURFACE6_INFO 0x0b6c
806 #define RADEON_SURFACE6_LOWER_BOUND 0x0b64
807 #define RADEON_SURFACE6_UPPER_BOUND 0x0b68
808 #define RADEON_SURFACE7_INFO 0x0b7c
809 #define RADEON_SURFACE7_LOWER_BOUND 0x0b74
810 #define RADEON_SURFACE7_UPPER_BOUND 0x0b78
811 #define RADEON_SW_SEMAPHORE 0x013c
812
813 #define RADEON_WAIT_UNTIL 0x1720
814 # define RADEON_WAIT_CRTC_PFLIP (1 << 0)
815 # define RADEON_WAIT_2D_IDLE (1 << 14)
816 # define RADEON_WAIT_3D_IDLE (1 << 15)
817 # define RADEON_WAIT_2D_IDLECLEAN (1 << 16)
818 # define RADEON_WAIT_3D_IDLECLEAN (1 << 17)
819 # define RADEON_WAIT_HOST_IDLECLEAN (1 << 18)
820
821 #define RADEON_RB3D_ZMASKOFFSET 0x3234
822 #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
823 # define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0)
824 # define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0)
825
826 /* CP registers */
827 #define RADEON_CP_ME_RAM_ADDR 0x07d4
828 #define RADEON_CP_ME_RAM_RADDR 0x07d8
829 #define RADEON_CP_ME_RAM_DATAH 0x07dc
830 #define RADEON_CP_ME_RAM_DATAL 0x07e0
831
832 #define RADEON_CP_RB_BASE 0x0700
833 #define RADEON_CP_RB_CNTL 0x0704
834 # define RADEON_BUF_SWAP_32BIT (2 << 16)
835 # define RADEON_RB_NO_UPDATE (1 << 27)
836 #define RADEON_CP_RB_RPTR_ADDR 0x070c
837 #define RADEON_CP_RB_RPTR 0x0710
838 #define RADEON_CP_RB_WPTR 0x0714
839
840 #define RADEON_CP_RB_WPTR_DELAY 0x0718
841 # define RADEON_PRE_WRITE_TIMER_SHIFT 0
842 # define RADEON_PRE_WRITE_LIMIT_SHIFT 23
843
844 #define RADEON_CP_IB_BASE 0x0738
845
846 #define RADEON_CP_CSQ_CNTL 0x0740
847 # define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0)
848 # define RADEON_CSQ_PRIDIS_INDDIS (0 << 28)
849 # define RADEON_CSQ_PRIPIO_INDDIS (1 << 28)
850 # define RADEON_CSQ_PRIBM_INDDIS (2 << 28)
851 # define RADEON_CSQ_PRIPIO_INDBM (3 << 28)
852 # define RADEON_CSQ_PRIBM_INDBM (4 << 28)
853 # define RADEON_CSQ_PRIPIO_INDPIO (15 << 28)
854
855 #define RADEON_AIC_CNTL 0x01d0
856 # define RADEON_PCIGART_TRANSLATE_EN (1 << 0)
857 #define RADEON_AIC_STAT 0x01d4
858 #define RADEON_AIC_PT_BASE 0x01d8
859 #define RADEON_AIC_LO_ADDR 0x01dc
860 #define RADEON_AIC_HI_ADDR 0x01e0
861 #define RADEON_AIC_TLB_ADDR 0x01e4
862 #define RADEON_AIC_TLB_DATA 0x01e8
863
864 /* CP command packets */
865 #define RADEON_CP_PACKET0 0x00000000
866 # define RADEON_ONE_REG_WR (1 << 15)
867 #define RADEON_CP_PACKET1 0x40000000
868 #define RADEON_CP_PACKET2 0x80000000
869 #define RADEON_CP_PACKET3 0xC0000000
870 # define RADEON_CP_NOP 0x00001000
871 # define RADEON_CP_NEXT_CHAR 0x00001900
872 # define RADEON_CP_PLY_NEXTSCAN 0x00001D00
873 # define RADEON_CP_SET_SCISSORS 0x00001E00
874 /* GEN_INDX_PRIM is unsupported starting with R300 */
875 # define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300
876 # define RADEON_WAIT_FOR_IDLE 0x00002600
877 # define RADEON_3D_DRAW_VBUF 0x00002800
878 # define RADEON_3D_DRAW_IMMD 0x00002900
879 # define RADEON_3D_DRAW_INDX 0x00002A00
880 # define RADEON_CP_LOAD_PALETTE 0x00002C00
881 # define RADEON_3D_LOAD_VBPNTR 0x00002F00
882 # define RADEON_MPEG_IDCT_MACROBLOCK 0x00003000
883 # define RADEON_MPEG_IDCT_MACROBLOCK_REV 0x00003100
884 # define RADEON_3D_CLEAR_ZMASK 0x00003200
885 # define RADEON_CP_INDX_BUFFER 0x00003300
886 # define RADEON_CP_3D_DRAW_VBUF_2 0x00003400
887 # define RADEON_CP_3D_DRAW_IMMD_2 0x00003500
888 # define RADEON_CP_3D_DRAW_INDX_2 0x00003600
889 # define RADEON_3D_CLEAR_HIZ 0x00003700
890 # define RADEON_CP_3D_CLEAR_CMASK 0x00003802
891 # define RADEON_CNTL_HOSTDATA_BLT 0x00009400
892 # define RADEON_CNTL_PAINT_MULTI 0x00009A00
893 # define RADEON_CNTL_BITBLT_MULTI 0x00009B00
894 # define RADEON_CNTL_SET_SCISSORS 0xC0001E00
895
896 #define RADEON_CP_PACKET_MASK 0xC0000000
897 #define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000
898 #define RADEON_CP_PACKET0_REG_MASK 0x000007ff
899 #define RADEON_CP_PACKET1_REG0_MASK 0x000007ff
900 #define RADEON_CP_PACKET1_REG1_MASK 0x003ff800
901
902 #define RADEON_VTX_Z_PRESENT (1 << 31)
903 #define RADEON_VTX_PKCOLOR_PRESENT (1 << 3)
904
905 #define RADEON_PRIM_TYPE_NONE (0 << 0)
906 #define RADEON_PRIM_TYPE_POINT (1 << 0)
907 #define RADEON_PRIM_TYPE_LINE (2 << 0)
908 #define RADEON_PRIM_TYPE_LINE_STRIP (3 << 0)
909 #define RADEON_PRIM_TYPE_TRI_LIST (4 << 0)
910 #define RADEON_PRIM_TYPE_TRI_FAN (5 << 0)
911 #define RADEON_PRIM_TYPE_TRI_STRIP (6 << 0)
912 #define RADEON_PRIM_TYPE_TRI_TYPE2 (7 << 0)
913 #define RADEON_PRIM_TYPE_RECT_LIST (8 << 0)
914 #define RADEON_PRIM_TYPE_3VRT_POINT_LIST (9 << 0)
915 #define RADEON_PRIM_TYPE_3VRT_LINE_LIST (10 << 0)
916 #define RADEON_PRIM_TYPE_MASK 0xf
917 #define RADEON_PRIM_WALK_IND (1 << 4)
918 #define RADEON_PRIM_WALK_LIST (2 << 4)
919 #define RADEON_PRIM_WALK_RING (3 << 4)
920 #define RADEON_COLOR_ORDER_BGRA (0 << 6)
921 #define RADEON_COLOR_ORDER_RGBA (1 << 6)
922 #define RADEON_MAOS_ENABLE (1 << 7)
923 #define RADEON_VTX_FMT_R128_MODE (0 << 8)
924 #define RADEON_VTX_FMT_RADEON_MODE (1 << 8)
925 #define RADEON_NUM_VERTICES_SHIFT 16
926
927 #define RADEON_COLOR_FORMAT_CI8 2
928 #define RADEON_COLOR_FORMAT_ARGB1555 3
929 #define RADEON_COLOR_FORMAT_RGB565 4
930 #define RADEON_COLOR_FORMAT_ARGB8888 6
931 #define RADEON_COLOR_FORMAT_RGB332 7
932 #define RADEON_COLOR_FORMAT_RGB8 9
933 #define RADEON_COLOR_FORMAT_ARGB4444 15
934
935 #define RADEON_TXFORMAT_I8 0
936 #define RADEON_TXFORMAT_AI88 1
937 #define RADEON_TXFORMAT_RGB332 2
938 #define RADEON_TXFORMAT_ARGB1555 3
939 #define RADEON_TXFORMAT_RGB565 4
940 #define RADEON_TXFORMAT_ARGB4444 5
941 #define RADEON_TXFORMAT_ARGB8888 6
942 #define RADEON_TXFORMAT_RGBA8888 7
943 #define RADEON_TXFORMAT_Y8 8
944 #define RADEON_TXFORMAT_VYUY422 10
945 #define RADEON_TXFORMAT_YVYU422 11
946 #define RADEON_TXFORMAT_DXT1 12
947 #define RADEON_TXFORMAT_DXT23 14
948 #define RADEON_TXFORMAT_DXT45 15
949
950 #define R200_PP_TXCBLEND_0 0x2f00
951 #define R200_PP_TXCBLEND_1 0x2f10
952 #define R200_PP_TXCBLEND_2 0x2f20
953 #define R200_PP_TXCBLEND_3 0x2f30
954 #define R200_PP_TXCBLEND_4 0x2f40
955 #define R200_PP_TXCBLEND_5 0x2f50
956 #define R200_PP_TXCBLEND_6 0x2f60
957 #define R200_PP_TXCBLEND_7 0x2f70
958 #define R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268
959 #define R200_PP_TFACTOR_0 0x2ee0
960 #define R200_SE_VTX_FMT_0 0x2088
961 #define R200_SE_VAP_CNTL 0x2080
962 #define R200_SE_TCL_MATRIX_SEL_0 0x2230
963 #define R200_SE_TCL_TEX_PROC_CTL_2 0x22a8
964 #define R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0
965 #define R200_PP_TXFILTER_5 0x2ca0
966 #define R200_PP_TXFILTER_4 0x2c80
967 #define R200_PP_TXFILTER_3 0x2c60
968 #define R200_PP_TXFILTER_2 0x2c40
969 #define R200_PP_TXFILTER_1 0x2c20
970 #define R200_PP_TXFILTER_0 0x2c00
971 #define R200_PP_TXOFFSET_5 0x2d78
972 #define R200_PP_TXOFFSET_4 0x2d60
973 #define R200_PP_TXOFFSET_3 0x2d48
974 #define R200_PP_TXOFFSET_2 0x2d30
975 #define R200_PP_TXOFFSET_1 0x2d18
976 #define R200_PP_TXOFFSET_0 0x2d00
977
978 #define R200_PP_CUBIC_FACES_0 0x2c18
979 #define R200_PP_CUBIC_FACES_1 0x2c38
980 #define R200_PP_CUBIC_FACES_2 0x2c58
981 #define R200_PP_CUBIC_FACES_3 0x2c78
982 #define R200_PP_CUBIC_FACES_4 0x2c98
983 #define R200_PP_CUBIC_FACES_5 0x2cb8
984 #define R200_PP_CUBIC_OFFSET_F1_0 0x2d04
985 #define R200_PP_CUBIC_OFFSET_F2_0 0x2d08
986 #define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c
987 #define R200_PP_CUBIC_OFFSET_F4_0 0x2d10
988 #define R200_PP_CUBIC_OFFSET_F5_0 0x2d14
989 #define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c
990 #define R200_PP_CUBIC_OFFSET_F2_1 0x2d20
991 #define R200_PP_CUBIC_OFFSET_F3_1 0x2d24
992 #define R200_PP_CUBIC_OFFSET_F4_1 0x2d28
993 #define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c
994 #define R200_PP_CUBIC_OFFSET_F1_2 0x2d34
995 #define R200_PP_CUBIC_OFFSET_F2_2 0x2d38
996 #define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c
997 #define R200_PP_CUBIC_OFFSET_F4_2 0x2d40
998 #define R200_PP_CUBIC_OFFSET_F5_2 0x2d44
999 #define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c
1000 #define R200_PP_CUBIC_OFFSET_F2_3 0x2d50
1001 #define R200_PP_CUBIC_OFFSET_F3_3 0x2d54
1002 #define R200_PP_CUBIC_OFFSET_F4_3 0x2d58
1003 #define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c
1004 #define R200_PP_CUBIC_OFFSET_F1_4 0x2d64
1005 #define R200_PP_CUBIC_OFFSET_F2_4 0x2d68
1006 #define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c
1007 #define R200_PP_CUBIC_OFFSET_F4_4 0x2d70
1008 #define R200_PP_CUBIC_OFFSET_F5_4 0x2d74
1009 #define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c
1010 #define R200_PP_CUBIC_OFFSET_F2_5 0x2d80
1011 #define R200_PP_CUBIC_OFFSET_F3_5 0x2d84
1012 #define R200_PP_CUBIC_OFFSET_F4_5 0x2d88
1013 #define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c
1014
1015 #define R200_RE_AUX_SCISSOR_CNTL 0x26f0
1016 #define R200_SE_VTE_CNTL 0x20b0
1017 #define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250
1018 #define R200_PP_TAM_DEBUG3 0x2d9c
1019 #define R200_PP_CNTL_X 0x2cc4
1020 #define R200_SE_VAP_CNTL_STATUS 0x2140
1021 #define R200_RE_SCISSOR_TL_0 0x1cd8
1022 #define R200_RE_SCISSOR_TL_1 0x1ce0
1023 #define R200_RE_SCISSOR_TL_2 0x1ce8
1024 #define R200_RB3D_DEPTHXY_OFFSET 0x1d60
1025 #define R200_RE_AUX_SCISSOR_CNTL 0x26f0
1026 #define R200_SE_VTX_STATE_CNTL 0x2180
1027 #define R200_RE_POINTSIZE 0x2648
1028 #define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254
1029
1030 #define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */
1031 #define RADEON_PP_TEX_SIZE_1 0x1d0c
1032 #define RADEON_PP_TEX_SIZE_2 0x1d14
1033
1034 #define RADEON_PP_CUBIC_FACES_0 0x1d24
1035 #define RADEON_PP_CUBIC_FACES_1 0x1d28
1036 #define RADEON_PP_CUBIC_FACES_2 0x1d2c
1037 #define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */
1038 #define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00
1039 #define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14
1040
1041 #define RADEON_SE_TCL_STATE_FLUSH 0x2284
1042
1043 #define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001
1044 #define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000
1045 #define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012
1046 #define SE_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100
1047 #define SE_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200
1048 #define SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK 0x00000001
1049 #define SE_VTX_FMT_0__VTX_W0_PRESENT_MASK 0x00000002
1050 #define SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT 0x0000000b
1051 #define R200_3D_DRAW_IMMD_2 0xC0003500
1052 #define R200_SE_VTX_FMT_1 0x208c
1053 #define R200_RE_CNTL 0x1c50
1054
1055 #define R200_RB3D_BLENDCOLOR 0x3218
1056
1057 #define R200_SE_TCL_POINT_SPRITE_CNTL 0x22c4
1058
1059 #define R200_PP_TRI_PERF 0x2cf8
1060
1061 #define R200_PP_AFS_0 0x2f80
1062 #define R200_PP_AFS_1 0x2f00 /* same as txcblend_0 */
1063
1064 #define R200_VAP_PVS_CNTL_1 0x22D0
1065
1066 /* Constants */
1067 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
1068
1069 #define RADEON_LAST_FRAME_REG RADEON_SCRATCH_REG0
1070 #define RADEON_LAST_DISPATCH_REG RADEON_SCRATCH_REG1
1071 #define RADEON_LAST_CLEAR_REG RADEON_SCRATCH_REG2
1072 #define RADEON_LAST_SWI_REG RADEON_SCRATCH_REG3
1073 #define RADEON_LAST_DISPATCH 1
1074
1075 #define RADEON_MAX_VB_AGE 0x7fffffff
1076 #define RADEON_MAX_VB_VERTS (0xffff)
1077
1078 #define RADEON_RING_HIGH_MARK 128
1079
1080 #define RADEON_PCIGART_TABLE_SIZE (32*1024)
1081
1082 #define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
1083 #define RADEON_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) )
1084 #define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) )
1085 #define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) )
1086
1087 #define RADEON_WRITE_PLL( addr, val ) \
1088 do { \
1089 RADEON_WRITE8( RADEON_CLOCK_CNTL_INDEX, \
1090 ((addr) & 0x1f) | RADEON_PLL_WR_EN ); \
1091 RADEON_WRITE( RADEON_CLOCK_CNTL_DATA, (val) ); \
1092 } while (0)
1093
1094 #define RADEON_WRITE_IGPGART( addr, val ) \
1095 do { \
1096 RADEON_WRITE( RADEON_IGPGART_INDEX, \
1097 ((addr) & 0x7f) | (1 << 8)); \
1098 RADEON_WRITE( RADEON_IGPGART_DATA, (val) ); \
1099 RADEON_WRITE( RADEON_IGPGART_INDEX, 0x7f ); \
1100 } while (0)
1101
1102 #define RADEON_WRITE_PCIE( addr, val ) \
1103 do { \
1104 RADEON_WRITE8( RADEON_PCIE_INDEX, \
1105 ((addr) & 0xff)); \
1106 RADEON_WRITE( RADEON_PCIE_DATA, (val) ); \
1107 } while (0)
1108
1109 #define RADEON_WRITE_MCIND( addr, val ) \
1110 do { \
1111 RADEON_WRITE(R520_MC_IND_INDEX, 0xff0000 | ((addr) & 0xff)); \
1112 RADEON_WRITE(R520_MC_IND_DATA, (val)); \
1113 RADEON_WRITE(R520_MC_IND_INDEX, 0); \
1114 } while (0)
1115
1116 <<<<<<< HEAD:drivers/char/drm/radeon_drv.h
1117 =======
1118 #define RS690_WRITE_MCIND( addr, val ) \
1119 do { \
1120 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_EN | ((addr) & RS690_MC_INDEX_MASK)); \
1121 RADEON_WRITE(RS690_MC_DATA, val); \
1122 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK); \
1123 } while (0)
1124
1125 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/char/drm/radeon_drv.h
1126 #define CP_PACKET0( reg, n ) \
1127 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
1128 #define CP_PACKET0_TABLE( reg, n ) \
1129 (RADEON_CP_PACKET0 | RADEON_ONE_REG_WR | ((n) << 16) | ((reg) >> 2))
1130 #define CP_PACKET1( reg0, reg1 ) \
1131 (RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2))
1132 #define CP_PACKET2() \
1133 (RADEON_CP_PACKET2)
1134 #define CP_PACKET3( pkt, n ) \
1135 (RADEON_CP_PACKET3 | (pkt) | ((n) << 16))
1136
1137 /* ================================================================
1138 * Engine control helper macros
1139 */
1140
1141 #define RADEON_WAIT_UNTIL_2D_IDLE() do { \
1142 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1143 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
1144 RADEON_WAIT_HOST_IDLECLEAN) ); \
1145 } while (0)
1146
1147 #define RADEON_WAIT_UNTIL_3D_IDLE() do { \
1148 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1149 OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \
1150 RADEON_WAIT_HOST_IDLECLEAN) ); \
1151 } while (0)
1152
1153 #define RADEON_WAIT_UNTIL_IDLE() do { \
1154 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1155 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
1156 RADEON_WAIT_3D_IDLECLEAN | \
1157 RADEON_WAIT_HOST_IDLECLEAN) ); \
1158 } while (0)
1159
1160 #define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do { \
1161 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1162 OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \
1163 } while (0)
1164
1165 #define RADEON_FLUSH_CACHE() do { \
1166 OUT_RING( CP_PACKET0( RADEON_RB3D_DSTCACHE_CTLSTAT, 0 ) ); \
1167 OUT_RING( RADEON_RB3D_DC_FLUSH ); \
1168 } while (0)
1169
1170 #define RADEON_PURGE_CACHE() do { \
1171 OUT_RING( CP_PACKET0( RADEON_RB3D_DSTCACHE_CTLSTAT, 0 ) ); \
1172 OUT_RING( RADEON_RB3D_DC_FLUSH_ALL ); \
1173 } while (0)
1174
1175 #define RADEON_FLUSH_ZCACHE() do { \
1176 OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \
1177 OUT_RING( RADEON_RB3D_ZC_FLUSH ); \
1178 } while (0)
1179
1180 #define RADEON_PURGE_ZCACHE() do { \
1181 OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \
1182 OUT_RING( RADEON_RB3D_ZC_FLUSH_ALL ); \
1183 } while (0)
1184
1185 /* ================================================================
1186 * Misc helper macros
1187 */
1188
1189 /* Perfbox functionality only.
1190 */
1191 #define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \
1192 do { \
1193 if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) { \
1194 u32 head = GET_RING_HEAD( dev_priv ); \
1195 if (head == dev_priv->ring.tail) \
1196 dev_priv->stats.boxes |= RADEON_BOX_DMA_IDLE; \
1197 } \
1198 } while (0)
1199
1200 #define VB_AGE_TEST_WITH_RETURN( dev_priv ) \
1201 do { \
1202 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; \
1203 if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \
1204 int __ret = radeon_do_cp_idle( dev_priv ); \
1205 if ( __ret ) return __ret; \
1206 sarea_priv->last_dispatch = 0; \
1207 radeon_freelist_reset( dev ); \
1208 } \
1209 } while (0)
1210
1211 #define RADEON_DISPATCH_AGE( age ) do { \
1212 OUT_RING( CP_PACKET0( RADEON_LAST_DISPATCH_REG, 0 ) ); \
1213 OUT_RING( age ); \
1214 } while (0)
1215
1216 #define RADEON_FRAME_AGE( age ) do { \
1217 OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) ); \
1218 OUT_RING( age ); \
1219 } while (0)
1220
1221 #define RADEON_CLEAR_AGE( age ) do { \
1222 OUT_RING( CP_PACKET0( RADEON_LAST_CLEAR_REG, 0 ) ); \
1223 OUT_RING( age ); \
1224 } while (0)
1225
1226 /* ================================================================
1227 * Ring control
1228 */
1229
1230 #define RADEON_VERBOSE 0
1231
1232 #define RING_LOCALS int write, _nr; unsigned int mask; u32 *ring;
1233
1234 #define BEGIN_RING( n ) do { \
1235 if ( RADEON_VERBOSE ) { \
1236 DRM_INFO( "BEGIN_RING( %d )\n", (n)); \
1237 } \
1238 if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \
1239 COMMIT_RING(); \
1240 radeon_wait_ring( dev_priv, (n) * sizeof(u32) ); \
1241 } \
1242 _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \
1243 ring = dev_priv->ring.start; \
1244 write = dev_priv->ring.tail; \
1245 mask = dev_priv->ring.tail_mask; \
1246 } while (0)
1247
1248 #define ADVANCE_RING() do { \
1249 if ( RADEON_VERBOSE ) { \
1250 DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \
1251 write, dev_priv->ring.tail ); \
1252 } \
1253 if (((dev_priv->ring.tail + _nr) & mask) != write) { \
1254 DRM_ERROR( \
1255 "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \
1256 ((dev_priv->ring.tail + _nr) & mask), \
1257 write, __LINE__); \
1258 } else \
1259 dev_priv->ring.tail = write; \
1260 } while (0)
1261
1262 #define COMMIT_RING() do { \
1263 /* Flush writes to ring */ \
1264 DRM_MEMORYBARRIER(); \
1265 GET_RING_HEAD( dev_priv ); \
1266 RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \
1267 /* read from PCI bus to ensure correct posting */ \
1268 RADEON_READ( RADEON_CP_RB_RPTR ); \
1269 } while (0)
1270
1271 #define OUT_RING( x ) do { \
1272 if ( RADEON_VERBOSE ) { \
1273 DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \
1274 (unsigned int)(x), write ); \
1275 } \
1276 ring[write++] = (x); \
1277 write &= mask; \
1278 } while (0)
1279
1280 #define OUT_RING_REG( reg, val ) do { \
1281 OUT_RING( CP_PACKET0( reg, 0 ) ); \
1282 OUT_RING( val ); \
1283 } while (0)
1284
1285 #define OUT_RING_TABLE( tab, sz ) do { \
1286 int _size = (sz); \
1287 int *_tab = (int *)(tab); \
1288 \
1289 if (write + _size > mask) { \
1290 int _i = (mask+1) - write; \
1291 _size -= _i; \
1292 while (_i > 0 ) { \
1293 *(int *)(ring + write) = *_tab++; \
1294 write++; \
1295 _i--; \
1296 } \
1297 write = 0; \
1298 _tab += _i; \
1299 } \
1300 while (_size > 0) { \
1301 *(ring + write) = *_tab++; \
1302 write++; \
1303 _size--; \
1304 } \
1305 write &= mask; \
1306 } while (0)
1307
1308 #endif /* __RADEON_DRV_H__ */
WRT350N Kernel Patches