1 /*****************************************************************************
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
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8 * option) any later version.
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13 * OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
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22 * FOR A PARTICULAR PURPOSE.
24 * Xilinx products are not intended for use in life support appliances,
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27 * (c) Copyright 2007-2008 Xilinx Inc.
28 * All rights reserved.
30 * You should have received a copy of the GNU General Public License along
31 * with this program; if not, write to the Free Software Foundation, Inc.,
32 * 675 Mass Ave, Cambridge, MA 02139, USA.
34 *****************************************************************************/
36 #include "fifo_icap.h"
38 /* Register offsets for the XHwIcap device. */
39 #define XHI_GIER_OFFSET 0x1C /* Device Global Interrupt Enable Reg */
40 #define XHI_IPISR_OFFSET 0x20 /* Interrupt Status Register */
41 #define XHI_IPIER_OFFSET 0x28 /* Interrupt Enable Register */
42 #define XHI_WF_OFFSET 0x100 /* Write FIFO */
43 #define XHI_RF_OFFSET 0x104 /* Read FIFO */
44 #define XHI_SZ_OFFSET 0x108 /* Size Register */
45 #define XHI_CR_OFFSET 0x10C /* Control Register */
46 #define XHI_SR_OFFSET 0x110 /* Status Register */
47 #define XHI_WFV_OFFSET 0x114 /* Write FIFO Vacancy Register */
48 #define XHI_RFO_OFFSET 0x118 /* Read FIFO Occupancy Register */
50 /* Device Global Interrupt Enable Register (GIER) bit definitions */
52 #define XHI_GIER_GIE_MASK 0x80000000 /* Global Interrupt enable Mask */
55 * HwIcap Device Interrupt Status/Enable Registers
57 * Interrupt Status Register (IPISR) : This register holds the
58 * interrupt status flags for the device. These bits are toggle on
61 * Interrupt Enable Register (IPIER) : This register is used to enable
62 * interrupt sources for the device.
63 * Writing a '1' to a bit enables the corresponding interrupt.
64 * Writing a '0' to a bit disables the corresponding interrupt.
66 * IPISR/IPIER registers have the same bit definitions and are only defined
69 #define XHI_IPIXR_RFULL_MASK 0x00000008 /* Read FIFO Full */
70 #define XHI_IPIXR_WEMPTY_MASK 0x00000004 /* Write FIFO Empty */
71 #define XHI_IPIXR_RDP_MASK 0x00000002 /* Read FIFO half full */
72 #define XHI_IPIXR_WRP_MASK 0x00000001 /* Write FIFO half full */
73 #define XHI_IPIXR_ALL_MASK 0x0000000F /* Mask of all interrupts */
75 /* Control Register (CR) */
76 #define XHI_CR_SW_RESET_MASK 0x00000008 /* SW Reset Mask */
77 #define XHI_CR_FIFO_CLR_MASK 0x00000004 /* FIFO Clear Mask */
78 #define XHI_CR_READ_MASK 0x00000002 /* Read from ICAP to FIFO */
79 #define XHI_CR_WRITE_MASK 0x00000001 /* Write from FIFO to ICAP */
81 /* Status Register (SR) */
82 #define XHI_SR_CFGERR_N_MASK 0x00000100 /* Config Error Mask */
83 #define XHI_SR_DALIGN_MASK 0x00000080 /* Data Alignment Mask */
84 #define XHI_SR_RIP_MASK 0x00000040 /* Read back Mask */
85 #define XHI_SR_IN_ABORT_N_MASK 0x00000020 /* Select Map Abort Mask */
86 #define XHI_SR_DONE_MASK 0x00000001 /* Done bit Mask */
89 #define XHI_WFO_MAX_VACANCY 1024 /* Max Write FIFO Vacancy, in words */
90 #define XHI_RFO_MAX_OCCUPANCY 256 /* Max Read FIFO Occupancy, in words */
91 /* The maximum amount we can request from fifo_icap_get_configuration
93 #define XHI_MAX_READ_TRANSACTION_WORDS 0xFFF
97 <<<<<<< HEAD:drivers/char/xilinx_hwicap/fifo_icap.c
98 * fifo_icap_fifo_write: Write data to the write FIFO.
99 * @parameter drvdata: a pointer to the drvdata.
100 * @parameter data: the 32-bit value to be written to the FIFO.
102 * fifo_icap_fifo_write - Write data to the write FIFO.
103 * @drvdata: a pointer to the drvdata.
104 * @data: the 32-bit value to be written to the FIFO.
105 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/char/xilinx_hwicap/fifo_icap.c
107 * This function will silently fail if the fifo is full.
109 static inline void fifo_icap_fifo_write(struct hwicap_drvdata
*drvdata
,
112 dev_dbg(drvdata
->dev
, "fifo_write: %x\n", data
);
113 out_be32(drvdata
->base_address
+ XHI_WF_OFFSET
, data
);
117 <<<<<<< HEAD:drivers/char/xilinx_hwicap/fifo_icap.c
118 * fifo_icap_fifo_read: Read data from the Read FIFO.
119 * @parameter drvdata: a pointer to the drvdata.
121 * fifo_icap_fifo_read - Read data from the Read FIFO.
122 * @drvdata: a pointer to the drvdata.
123 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/char/xilinx_hwicap/fifo_icap.c
125 * This function will silently fail if the fifo is empty.
127 static inline u32
fifo_icap_fifo_read(struct hwicap_drvdata
*drvdata
)
129 u32 data
= in_be32(drvdata
->base_address
+ XHI_RF_OFFSET
);
130 dev_dbg(drvdata
->dev
, "fifo_read: %x\n", data
);
135 <<<<<<< HEAD:drivers/char/xilinx_hwicap/fifo_icap.c
136 * fifo_icap_set_read_size: Set the the size register.
137 * @parameter drvdata: a pointer to the drvdata.
138 * @parameter data: the size of the following read transaction, in words.
140 * fifo_icap_set_read_size - Set the the size register.
141 * @drvdata: a pointer to the drvdata.
142 * @data: the size of the following read transaction, in words.
143 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/char/xilinx_hwicap/fifo_icap.c
145 static inline void fifo_icap_set_read_size(struct hwicap_drvdata
*drvdata
,
148 out_be32(drvdata
->base_address
+ XHI_SZ_OFFSET
, data
);
152 <<<<<<< HEAD:drivers/char/xilinx_hwicap/fifo_icap.c
153 * fifo_icap_start_config: Initiate a configuration (write) to the device.
154 * @parameter drvdata: a pointer to the drvdata.
156 * fifo_icap_start_config - Initiate a configuration (write) to the device.
157 * @drvdata: a pointer to the drvdata.
158 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/char/xilinx_hwicap/fifo_icap.c
160 static inline void fifo_icap_start_config(struct hwicap_drvdata
*drvdata
)
162 out_be32(drvdata
->base_address
+ XHI_CR_OFFSET
, XHI_CR_WRITE_MASK
);
163 dev_dbg(drvdata
->dev
, "configuration started\n");
167 <<<<<<< HEAD:drivers/char/xilinx_hwicap/fifo_icap.c
168 * fifo_icap_start_readback: Initiate a readback from the device.
169 * @parameter drvdata: a pointer to the drvdata.
171 * fifo_icap_start_readback - Initiate a readback from the device.
172 * @drvdata: a pointer to the drvdata.
173 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/char/xilinx_hwicap/fifo_icap.c
175 static inline void fifo_icap_start_readback(struct hwicap_drvdata
*drvdata
)
177 out_be32(drvdata
->base_address
+ XHI_CR_OFFSET
, XHI_CR_READ_MASK
);
178 dev_dbg(drvdata
->dev
, "readback started\n");
182 <<<<<<< HEAD:drivers/char/xilinx_hwicap/fifo_icap.c
183 * fifo_icap_busy: Return true if the ICAP is still processing a transaction.
184 * @parameter drvdata: a pointer to the drvdata.
186 * fifo_icap_busy - Return true if the ICAP is still processing a transaction.
187 * @drvdata: a pointer to the drvdata.
188 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/char/xilinx_hwicap/fifo_icap.c
190 static inline u32
fifo_icap_busy(struct hwicap_drvdata
*drvdata
)
192 u32 status
= in_be32(drvdata
->base_address
+ XHI_SR_OFFSET
);
193 dev_dbg(drvdata
->dev
, "Getting status = %x\n", status
);
194 return (status
& XHI_SR_DONE_MASK
) ? 0 : 1;
198 <<<<<<< HEAD:drivers/char/xilinx_hwicap/fifo_icap.c
199 * fifo_icap_write_fifo_vacancy: Query the write fifo available space.
200 * @parameter drvdata: a pointer to the drvdata.
202 * fifo_icap_write_fifo_vacancy - Query the write fifo available space.
203 * @drvdata: a pointer to the drvdata.
204 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/char/xilinx_hwicap/fifo_icap.c
206 * Return the number of words that can be safely pushed into the write fifo.
208 static inline u32
fifo_icap_write_fifo_vacancy(
209 struct hwicap_drvdata
*drvdata
)
211 return in_be32(drvdata
->base_address
+ XHI_WFV_OFFSET
);
215 <<<<<<< HEAD:drivers/char/xilinx_hwicap/fifo_icap.c
216 * fifo_icap_read_fifo_occupancy: Query the read fifo available data.
217 * @parameter drvdata: a pointer to the drvdata.
219 * fifo_icap_read_fifo_occupancy - Query the read fifo available data.
220 * @drvdata: a pointer to the drvdata.
221 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/char/xilinx_hwicap/fifo_icap.c
223 * Return the number of words that can be safely read from the read fifo.
225 static inline u32
fifo_icap_read_fifo_occupancy(
226 struct hwicap_drvdata
*drvdata
)
228 return in_be32(drvdata
->base_address
+ XHI_RFO_OFFSET
);
232 <<<<<<< HEAD:drivers/char/xilinx_hwicap/fifo_icap.c
233 * fifo_icap_set_configuration: Send configuration data to the ICAP.
234 * @parameter drvdata: a pointer to the drvdata.
235 * @parameter frame_buffer: a pointer to the data to be written to the
237 * fifo_icap_set_configuration - Send configuration data to the ICAP.
238 * @drvdata: a pointer to the drvdata.
239 * @frame_buffer: a pointer to the data to be written to the
240 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/char/xilinx_hwicap/fifo_icap.c
242 <<<<<<< HEAD:drivers/char/xilinx_hwicap/fifo_icap.c
243 * @parameter num_words: the number of words (32 bit) to write to the ICAP
245 * @num_words: the number of words (32 bit) to write to the ICAP
246 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/char/xilinx_hwicap/fifo_icap.c
249 * This function writes the given user data to the Write FIFO in
250 * polled mode and starts the transfer of the data to
253 int fifo_icap_set_configuration(struct hwicap_drvdata
*drvdata
,
254 u32
*frame_buffer
, u32 num_words
)
257 u32 write_fifo_vacancy
= 0;
261 dev_dbg(drvdata
->dev
, "fifo_set_configuration\n");
264 * Check if the ICAP device is Busy with the last Read/Write
266 if (fifo_icap_busy(drvdata
))
270 * Set up the buffer pointer and the words to be transferred.
272 remaining_words
= num_words
;
274 while (remaining_words
> 0) {
276 * Wait until we have some data in the fifo.
278 while (write_fifo_vacancy
== 0) {
280 fifo_icap_write_fifo_vacancy(drvdata
);
282 if (retries
> XHI_MAX_RETRIES
)
287 * Write data into the Write FIFO.
289 while ((write_fifo_vacancy
!= 0) &&
290 (remaining_words
> 0)) {
291 fifo_icap_fifo_write(drvdata
, *frame_buffer
);
294 write_fifo_vacancy
--;
297 /* Start pushing whatever is in the FIFO into the ICAP. */
298 fifo_icap_start_config(drvdata
);
301 /* Wait until the write has finished. */
302 while (fifo_icap_busy(drvdata
)) {
304 if (retries
> XHI_MAX_RETRIES
)
308 dev_dbg(drvdata
->dev
, "done fifo_set_configuration\n");
311 * If the requested number of words have not been read from
312 * the device then indicate failure.
314 if (remaining_words
!= 0)
321 <<<<<<< HEAD:drivers/char/xilinx_hwicap/fifo_icap.c
322 * fifo_icap_get_configuration: Read configuration data from the device.
323 * @parameter drvdata: a pointer to the drvdata.
324 * @parameter data: Address of the data representing the partial bitstream
325 * @parameter size: the size of the partial bitstream in 32 bit words.
327 * fifo_icap_get_configuration - Read configuration data from the device.
328 * @drvdata: a pointer to the drvdata.
329 * @data: Address of the data representing the partial bitstream
330 * @size: the size of the partial bitstream in 32 bit words.
331 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/char/xilinx_hwicap/fifo_icap.c
333 * This function reads the specified number of words from the ICAP device in
336 int fifo_icap_get_configuration(struct hwicap_drvdata
*drvdata
,
337 u32
*frame_buffer
, u32 num_words
)
340 u32 read_fifo_occupancy
= 0;
342 u32
*data
= frame_buffer
;
346 dev_dbg(drvdata
->dev
, "fifo_get_configuration\n");
349 * Check if the ICAP device is Busy with the last Write/Read
351 if (fifo_icap_busy(drvdata
))
354 remaining_words
= num_words
;
356 while (remaining_words
> 0) {
357 words_to_read
= remaining_words
;
358 /* The hardware has a limit on the number of words
359 that can be read at one time. */
360 if (words_to_read
> XHI_MAX_READ_TRANSACTION_WORDS
)
361 words_to_read
= XHI_MAX_READ_TRANSACTION_WORDS
;
363 remaining_words
-= words_to_read
;
365 fifo_icap_set_read_size(drvdata
, words_to_read
);
366 fifo_icap_start_readback(drvdata
);
368 while (words_to_read
> 0) {
369 /* Wait until we have some data in the fifo. */
370 while (read_fifo_occupancy
== 0) {
371 read_fifo_occupancy
=
372 fifo_icap_read_fifo_occupancy(drvdata
);
374 if (retries
> XHI_MAX_RETRIES
)
378 if (read_fifo_occupancy
> words_to_read
)
379 read_fifo_occupancy
= words_to_read
;
381 words_to_read
-= read_fifo_occupancy
;
383 /* Read the data from the Read FIFO. */
384 while (read_fifo_occupancy
!= 0) {
385 *data
++ = fifo_icap_fifo_read(drvdata
);
386 read_fifo_occupancy
--;
391 dev_dbg(drvdata
->dev
, "done fifo_get_configuration\n");
397 <<<<<<< HEAD:drivers/char/xilinx_hwicap/fifo_icap.c
398 * buffer_icap_reset: Reset the logic of the icap device.
399 * @parameter drvdata: a pointer to the drvdata.
401 * buffer_icap_reset - Reset the logic of the icap device.
402 * @drvdata: a pointer to the drvdata.
403 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/char/xilinx_hwicap/fifo_icap.c
405 * This function forces the software reset of the complete HWICAP device.
406 * All the registers will return to the default value and the FIFO is also
407 * flushed as a part of this software reset.
409 void fifo_icap_reset(struct hwicap_drvdata
*drvdata
)
413 * Reset the device by setting/clearing the RESET bit in the
416 reg_data
= in_be32(drvdata
->base_address
+ XHI_CR_OFFSET
);
418 out_be32(drvdata
->base_address
+ XHI_CR_OFFSET
,
419 reg_data
| XHI_CR_SW_RESET_MASK
);
421 out_be32(drvdata
->base_address
+ XHI_CR_OFFSET
,
422 reg_data
& (~XHI_CR_SW_RESET_MASK
));
427 <<<<<<< HEAD:drivers/char/xilinx_hwicap/fifo_icap.c
428 * fifo_icap_flush_fifo: This function flushes the FIFOs in the device.
429 * @parameter drvdata: a pointer to the drvdata.
431 * fifo_icap_flush_fifo - This function flushes the FIFOs in the device.
432 * @drvdata: a pointer to the drvdata.
433 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/char/xilinx_hwicap/fifo_icap.c
435 void fifo_icap_flush_fifo(struct hwicap_drvdata
*drvdata
)
439 * Flush the FIFO by setting/clearing the FIFO Clear bit in the
442 reg_data
= in_be32(drvdata
->base_address
+ XHI_CR_OFFSET
);
444 out_be32(drvdata
->base_address
+ XHI_CR_OFFSET
,
445 reg_data
| XHI_CR_FIFO_CLR_MASK
);
447 out_be32(drvdata
->base_address
+ XHI_CR_OFFSET
,
448 reg_data
& (~XHI_CR_FIFO_CLR_MASK
));