2 * drivers/i2c/busses/i2c-bfin-twi.c
4 * Description: Driver for Blackfin Two Wire Interface
6 * Author: sonicz <sonic.zhang@analog.com>
8 * Copyright (c) 2005-2007 Analog Devices, Inc.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 #include <linux/module.h>
26 #include <linux/kernel.h>
27 #include <linux/init.h>
28 #include <linux/i2c.h>
30 #include <linux/timer.h>
31 #include <linux/spinlock.h>
32 #include <linux/completion.h>
33 #include <linux/interrupt.h>
34 #include <linux/platform_device.h>
36 #include <asm/blackfin.h>
39 #define POLL_TIMEOUT (2 * HZ)
42 #define TWI_I2C_MODE_STANDARD 0x01
43 #define TWI_I2C_MODE_STANDARDSUB 0x02
44 #define TWI_I2C_MODE_COMBINED 0x04
46 struct bfin_twi_iface
{
58 struct timer_list timeout_timer
;
59 struct i2c_adapter adap
;
60 struct completion complete
;
63 static struct bfin_twi_iface twi_iface
;
65 static void bfin_twi_handle_interrupt(struct bfin_twi_iface
*iface
)
67 unsigned short twi_int_status
= bfin_read_TWI_INT_STAT();
68 unsigned short mast_stat
= bfin_read_TWI_MASTER_STAT();
70 if (twi_int_status
& XMTSERV
) {
71 /* Transmit next data */
72 if (iface
->writeNum
> 0) {
73 bfin_write_TWI_XMT_DATA8(*(iface
->transPtr
++));
76 /* start receive immediately after complete sending in
79 else if (iface
->cur_mode
== TWI_I2C_MODE_COMBINED
) {
80 bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL()
82 } else if (iface
->manual_stop
)
83 bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL()
87 bfin_write_TWI_INT_STAT(XMTSERV
);
90 if (twi_int_status
& RCVSERV
) {
91 if (iface
->readNum
> 0) {
92 /* Receive next data */
93 *(iface
->transPtr
) = bfin_read_TWI_RCV_DATA8();
94 if (iface
->cur_mode
== TWI_I2C_MODE_COMBINED
) {
95 /* Change combine mode into sub mode after
98 iface
->cur_mode
= TWI_I2C_MODE_STANDARDSUB
;
99 /* Get read number from first byte in block
102 if (iface
->readNum
== 1 && iface
->manual_stop
)
103 iface
->readNum
= *iface
->transPtr
+ 1;
107 } else if (iface
->manual_stop
) {
108 bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL()
112 /* Clear interrupt source */
113 bfin_write_TWI_INT_STAT(RCVSERV
);
116 if (twi_int_status
& MERR
) {
117 bfin_write_TWI_INT_STAT(MERR
);
118 bfin_write_TWI_INT_MASK(0);
119 bfin_write_TWI_MASTER_STAT(0x3e);
120 bfin_write_TWI_MASTER_CTL(0);
123 /* if both err and complete int stats are set, return proper
126 if (twi_int_status
& MCOMP
) {
127 bfin_write_TWI_INT_STAT(MCOMP
);
128 bfin_write_TWI_INT_MASK(0);
129 bfin_write_TWI_MASTER_CTL(0);
131 /* If it is a quick transfer, only address bug no data,
132 * not an err, return 1.
134 if (iface
->writeNum
== 0 && (mast_stat
& BUFRDERR
))
136 /* If address not acknowledged return -1,
139 else if (!(mast_stat
& ANAK
))
142 complete(&iface
->complete
);
145 if (twi_int_status
& MCOMP
) {
146 bfin_write_TWI_INT_STAT(MCOMP
);
148 if (iface
->cur_mode
== TWI_I2C_MODE_COMBINED
) {
149 if (iface
->readNum
== 0) {
150 /* set the read number to 1 and ask for manual
151 * stop in block combine mode
154 iface
->manual_stop
= 1;
155 bfin_write_TWI_MASTER_CTL(
156 bfin_read_TWI_MASTER_CTL()
159 /* set the readd number in other
162 bfin_write_TWI_MASTER_CTL(
163 (bfin_read_TWI_MASTER_CTL() &
165 ( iface
->readNum
<< 6));
167 /* remove restart bit and enable master receive */
168 bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() &
170 bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() |
175 bfin_write_TWI_INT_MASK(0);
176 bfin_write_TWI_MASTER_CTL(0);
178 complete(&iface
->complete
);
183 /* Interrupt handler */
184 static irqreturn_t
bfin_twi_interrupt_entry(int irq
, void *dev_id
)
186 struct bfin_twi_iface
*iface
= dev_id
;
189 spin_lock_irqsave(&iface
->lock
, flags
);
190 del_timer(&iface
->timeout_timer
);
191 bfin_twi_handle_interrupt(iface
);
192 spin_unlock_irqrestore(&iface
->lock
, flags
);
196 static void bfin_twi_timeout(unsigned long data
)
198 struct bfin_twi_iface
*iface
= (struct bfin_twi_iface
*)data
;
201 spin_lock_irqsave(&iface
->lock
, flags
);
202 bfin_twi_handle_interrupt(iface
);
203 if (iface
->result
== 0) {
204 iface
->timeout_count
--;
205 if (iface
->timeout_count
> 0) {
206 iface
->timeout_timer
.expires
= jiffies
+ POLL_TIMEOUT
;
207 add_timer(&iface
->timeout_timer
);
210 complete(&iface
->complete
);
213 spin_unlock_irqrestore(&iface
->lock
, flags
);
217 * Generic i2c master transfer entrypoint
219 static int bfin_twi_master_xfer(struct i2c_adapter
*adap
,
220 struct i2c_msg
*msgs
, int num
)
222 struct bfin_twi_iface
*iface
= adap
->algo_data
;
223 struct i2c_msg
*pmsg
;
227 if (!(bfin_read_TWI_CONTROL() & TWI_ENA
))
230 while (bfin_read_TWI_MASTER_STAT() & BUSBUSY
) {
235 for (i
= 0; rc
>= 0 && i
< num
; i
++) {
237 if (pmsg
->flags
& I2C_M_TEN
) {
238 dev_err(&(adap
->dev
), "i2c-bfin-twi: 10 bits addr "
239 "not supported !\n");
244 iface
->cur_mode
= TWI_I2C_MODE_STANDARD
;
245 iface
->manual_stop
= 0;
246 iface
->transPtr
= pmsg
->buf
;
247 iface
->writeNum
= iface
->readNum
= pmsg
->len
;
249 iface
->timeout_count
= 10;
250 /* Set Transmit device address */
251 bfin_write_TWI_MASTER_ADDR(pmsg
->addr
);
253 /* FIFO Initiation. Data in FIFO should be
254 * discarded before start a new operation.
256 bfin_write_TWI_FIFO_CTL(0x3);
258 bfin_write_TWI_FIFO_CTL(0);
261 if (pmsg
->flags
& I2C_M_RD
)
262 iface
->read_write
= I2C_SMBUS_READ
;
264 iface
->read_write
= I2C_SMBUS_WRITE
;
265 /* Transmit first data */
266 if (iface
->writeNum
> 0) {
267 bfin_write_TWI_XMT_DATA8(*(iface
->transPtr
++));
274 bfin_write_TWI_INT_STAT(MERR
|MCOMP
|XMTSERV
|RCVSERV
);
276 /* Interrupt mask . Enable XMT, RCV interrupt */
277 bfin_write_TWI_INT_MASK(MCOMP
| MERR
|
278 ((iface
->read_write
== I2C_SMBUS_READ
)?
282 if (pmsg
->len
> 0 && pmsg
->len
<= 255)
283 bfin_write_TWI_MASTER_CTL(pmsg
->len
<< 6);
284 else if (pmsg
->len
> 255) {
285 bfin_write_TWI_MASTER_CTL(0xff << 6);
286 iface
->manual_stop
= 1;
290 iface
->timeout_timer
.expires
= jiffies
+ POLL_TIMEOUT
;
291 add_timer(&iface
->timeout_timer
);
294 bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() | MEN
|
295 ((iface
->read_write
== I2C_SMBUS_READ
) ? MDIR
: 0) |
296 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ
>100) ? FAST
: 0));
299 wait_for_completion(&iface
->complete
);
312 * SMBus type transfer entrypoint
315 int bfin_twi_smbus_xfer(struct i2c_adapter
*adap
, u16 addr
,
316 unsigned short flags
, char read_write
,
317 u8 command
, int size
, union i2c_smbus_data
*data
)
319 struct bfin_twi_iface
*iface
= adap
->algo_data
;
322 if (!(bfin_read_TWI_CONTROL() & TWI_ENA
))
325 while (bfin_read_TWI_MASTER_STAT() & BUSBUSY
) {
332 /* Prepare datas & select mode */
334 case I2C_SMBUS_QUICK
:
335 iface
->transPtr
= NULL
;
336 iface
->cur_mode
= TWI_I2C_MODE_STANDARD
;
340 iface
->transPtr
= NULL
;
342 if (read_write
== I2C_SMBUS_READ
)
346 iface
->transPtr
= &data
->byte
;
348 iface
->cur_mode
= TWI_I2C_MODE_STANDARD
;
350 case I2C_SMBUS_BYTE_DATA
:
351 if (read_write
== I2C_SMBUS_READ
) {
353 iface
->cur_mode
= TWI_I2C_MODE_COMBINED
;
356 iface
->cur_mode
= TWI_I2C_MODE_STANDARDSUB
;
358 iface
->transPtr
= &data
->byte
;
360 case I2C_SMBUS_WORD_DATA
:
361 if (read_write
== I2C_SMBUS_READ
) {
363 iface
->cur_mode
= TWI_I2C_MODE_COMBINED
;
366 iface
->cur_mode
= TWI_I2C_MODE_STANDARDSUB
;
368 iface
->transPtr
= (u8
*)&data
->word
;
370 case I2C_SMBUS_PROC_CALL
:
373 iface
->cur_mode
= TWI_I2C_MODE_COMBINED
;
374 iface
->transPtr
= (u8
*)&data
->word
;
376 case I2C_SMBUS_BLOCK_DATA
:
377 if (read_write
== I2C_SMBUS_READ
) {
379 iface
->cur_mode
= TWI_I2C_MODE_COMBINED
;
381 iface
->writeNum
= data
->block
[0] + 1;
382 iface
->cur_mode
= TWI_I2C_MODE_STANDARDSUB
;
384 iface
->transPtr
= data
->block
;
391 iface
->manual_stop
= 0;
392 iface
->read_write
= read_write
;
393 iface
->command
= command
;
394 iface
->timeout_count
= 10;
396 /* FIFO Initiation. Data in FIFO should be discarded before
397 * start a new operation.
399 bfin_write_TWI_FIFO_CTL(0x3);
401 bfin_write_TWI_FIFO_CTL(0);
404 bfin_write_TWI_INT_STAT(MERR
|MCOMP
|XMTSERV
|RCVSERV
);
406 /* Set Transmit device address */
407 bfin_write_TWI_MASTER_ADDR(addr
);
410 iface
->timeout_timer
.expires
= jiffies
+ POLL_TIMEOUT
;
411 add_timer(&iface
->timeout_timer
);
413 switch (iface
->cur_mode
) {
414 case TWI_I2C_MODE_STANDARDSUB
:
415 bfin_write_TWI_XMT_DATA8(iface
->command
);
416 bfin_write_TWI_INT_MASK(MCOMP
| MERR
|
417 ((iface
->read_write
== I2C_SMBUS_READ
) ?
421 if (iface
->writeNum
+ 1 <= 255)
422 bfin_write_TWI_MASTER_CTL((iface
->writeNum
+ 1) << 6);
424 bfin_write_TWI_MASTER_CTL(0xff << 6);
425 iface
->manual_stop
= 1;
428 bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() | MEN
|
429 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ
>100) ? FAST
: 0));
431 case TWI_I2C_MODE_COMBINED
:
432 bfin_write_TWI_XMT_DATA8(iface
->command
);
433 bfin_write_TWI_INT_MASK(MCOMP
| MERR
| RCVSERV
| XMTSERV
);
436 if (iface
->writeNum
> 0)
437 bfin_write_TWI_MASTER_CTL((iface
->writeNum
+ 1) << 6);
439 bfin_write_TWI_MASTER_CTL(0x1 << 6);
441 bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() | MEN
|
442 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ
>100) ? FAST
: 0));
445 bfin_write_TWI_MASTER_CTL(0);
446 if (size
!= I2C_SMBUS_QUICK
) {
447 /* Don't access xmit data register when this is a
450 if (iface
->read_write
!= I2C_SMBUS_READ
) {
451 if (iface
->writeNum
> 0) {
452 bfin_write_TWI_XMT_DATA8(*(iface
->transPtr
++));
453 if (iface
->writeNum
<= 255)
454 bfin_write_TWI_MASTER_CTL(iface
->writeNum
<< 6);
456 bfin_write_TWI_MASTER_CTL(0xff << 6);
457 iface
->manual_stop
= 1;
461 bfin_write_TWI_XMT_DATA8(iface
->command
);
462 bfin_write_TWI_MASTER_CTL(1 << 6);
465 if (iface
->readNum
> 0 && iface
->readNum
<= 255)
466 bfin_write_TWI_MASTER_CTL(iface
->readNum
<< 6);
467 else if (iface
->readNum
> 255) {
468 bfin_write_TWI_MASTER_CTL(0xff << 6);
469 iface
->manual_stop
= 1;
471 del_timer(&iface
->timeout_timer
);
476 bfin_write_TWI_INT_MASK(MCOMP
| MERR
|
477 ((iface
->read_write
== I2C_SMBUS_READ
) ?
482 bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() | MEN
|
483 ((iface
->read_write
== I2C_SMBUS_READ
) ? MDIR
: 0) |
484 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ
> 100) ? FAST
: 0));
489 wait_for_completion(&iface
->complete
);
491 rc
= (iface
->result
>= 0) ? 0 : -1;
497 * Return what the adapter supports
499 static u32
bfin_twi_functionality(struct i2c_adapter
*adap
)
501 return I2C_FUNC_SMBUS_QUICK
| I2C_FUNC_SMBUS_BYTE
|
502 I2C_FUNC_SMBUS_BYTE_DATA
| I2C_FUNC_SMBUS_WORD_DATA
|
503 I2C_FUNC_SMBUS_BLOCK_DATA
| I2C_FUNC_SMBUS_PROC_CALL
|
508 static struct i2c_algorithm bfin_twi_algorithm
= {
509 .master_xfer
= bfin_twi_master_xfer
,
510 .smbus_xfer
= bfin_twi_smbus_xfer
,
511 .functionality
= bfin_twi_functionality
,
515 static int i2c_bfin_twi_suspend(struct platform_device
*dev
, pm_message_t state
)
517 /* struct bfin_twi_iface *iface = platform_get_drvdata(dev);*/
520 bfin_write_TWI_CONTROL(bfin_read_TWI_CONTROL() & ~TWI_ENA
);
526 static int i2c_bfin_twi_resume(struct platform_device
*dev
)
528 /* struct bfin_twi_iface *iface = platform_get_drvdata(dev);*/
531 bfin_write_TWI_CONTROL(bfin_read_TWI_CONTROL() | TWI_ENA
);
537 static int i2c_bfin_twi_probe(struct platform_device
*dev
)
539 struct bfin_twi_iface
*iface
= &twi_iface
;
540 struct i2c_adapter
*p_adap
;
543 spin_lock_init(&(iface
->lock
));
544 init_completion(&(iface
->complete
));
545 iface
->irq
= IRQ_TWI
;
547 init_timer(&(iface
->timeout_timer
));
548 iface
->timeout_timer
.function
= bfin_twi_timeout
;
549 iface
->timeout_timer
.data
= (unsigned long)iface
;
551 p_adap
= &iface
->adap
;
552 p_adap
->id
= I2C_HW_BLACKFIN
;
553 p_adap
->nr
= dev
->id
;
554 strlcpy(p_adap
->name
, dev
->name
, sizeof(p_adap
->name
));
555 p_adap
->algo
= &bfin_twi_algorithm
;
556 p_adap
->algo_data
= iface
;
557 p_adap
->class = I2C_CLASS_ALL
;
558 p_adap
->dev
.parent
= &dev
->dev
;
560 rc
= request_irq(iface
->irq
, bfin_twi_interrupt_entry
,
561 IRQF_DISABLED
, dev
->name
, iface
);
563 dev_err(&(p_adap
->dev
), "i2c-bfin-twi: can't get IRQ %d !\n",
568 /* Set TWI internal clock as 10MHz */
569 bfin_write_TWI_CONTROL(((get_sclk() / 1024 / 1024 + 5) / 10) & 0x7F);
571 /* Set Twi interface clock as specified */
572 bfin_write_TWI_CLKDIV((( 5*1024 / CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ
)
573 << 8) | (( 5*1024 / CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ
)
577 bfin_write_TWI_CONTROL(bfin_read_TWI_CONTROL() | TWI_ENA
);
580 rc
= i2c_add_numbered_adapter(p_adap
);
582 free_irq(iface
->irq
, iface
);
584 platform_set_drvdata(dev
, iface
);
589 static int i2c_bfin_twi_remove(struct platform_device
*pdev
)
591 struct bfin_twi_iface
*iface
= platform_get_drvdata(pdev
);
593 platform_set_drvdata(pdev
, NULL
);
595 i2c_del_adapter(&(iface
->adap
));
596 free_irq(iface
->irq
, iface
);
601 static struct platform_driver i2c_bfin_twi_driver
= {
602 .probe
= i2c_bfin_twi_probe
,
603 .remove
= i2c_bfin_twi_remove
,
604 .suspend
= i2c_bfin_twi_suspend
,
605 .resume
= i2c_bfin_twi_resume
,
607 .name
= "i2c-bfin-twi",
608 .owner
= THIS_MODULE
,
612 static int __init
i2c_bfin_twi_init(void)
614 pr_info("I2C: Blackfin I2C TWI driver\n");
616 return platform_driver_register(&i2c_bfin_twi_driver
);
619 static void __exit
i2c_bfin_twi_exit(void)
621 platform_driver_unregister(&i2c_bfin_twi_driver
);
624 MODULE_AUTHOR("Sonic Zhang <sonic.zhang@analog.com>");
625 MODULE_DESCRIPTION("I2C-Bus adapter routines for Blackfin TWI");
626 MODULE_LICENSE("GPL");
628 module_init(i2c_bfin_twi_init
);
629 module_exit(i2c_bfin_twi_exit
);