drivers/ide/pci/atiixp.c

   1 /*
   2  *  Copyright (C) 2003 ATI Inc. <hyu@ati.com>
   3  *  Copyright (C) 2004,2007 Bartlomiej Zolnierkiewicz
   4  */
   5
   6 #include <linux/types.h>
   7 #include <linux/module.h>
   8 #include <linux/kernel.h>
   9 #include <linux/pci.h>
  10 #include <linux/hdreg.h>
  11 #include <linux/ide.h>
  12 #include <linux/init.h>
  13
  14 #define ATIIXP_IDE_PIO_TIMING           0x40
  15 #define ATIIXP_IDE_MDMA_TIMING          0x44
  16 #define ATIIXP_IDE_PIO_CONTROL          0x48
  17 #define ATIIXP_IDE_PIO_MODE             0x4a
  18 #define ATIIXP_IDE_UDMA_CONTROL         0x54
  19 #define ATIIXP_IDE_UDMA_MODE            0x56
  20
  21 typedef struct {
  22         u8 command_width;
  23         u8 recover_width;
  24 } atiixp_ide_timing;
  25
  26 static atiixp_ide_timing pio_timing[] = {
  27         { 0x05, 0x0d },
  28         { 0x04, 0x07 },
  29         { 0x03, 0x04 },
  30         { 0x02, 0x02 },
  31         { 0x02, 0x00 },
  32 };
  33
  34 static atiixp_ide_timing mdma_timing[] = {
  35         { 0x07, 0x07 },
  36         { 0x02, 0x01 },
  37         { 0x02, 0x00 },
  38 };
  39
  40 static DEFINE_SPINLOCK(atiixp_lock);
  41
  42 /**
  43  *      atiixp_set_pio_mode     -       set host controller for PIO mode
  44  *      @drive: drive
  45  *      @pio: PIO mode number
  46  *
  47  *      Set the interface PIO mode.
  48  */
  49
  50 static void atiixp_set_pio_mode(ide_drive_t *drive, const u8 pio)
  51 {
  52         struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
  53         unsigned long flags;
  54         int timing_shift = (drive->dn & 2) ? 16 : 0 + (drive->dn & 1) ? 0 : 8;
  55         u32 pio_timing_data;
  56         u16 pio_mode_data;
  57
  58         spin_lock_irqsave(&atiixp_lock, flags);
  59
  60         pci_read_config_word(dev, ATIIXP_IDE_PIO_MODE, &pio_mode_data);
  61         pio_mode_data &= ~(0x07 << (drive->dn * 4));
  62         pio_mode_data |= (pio << (drive->dn * 4));
  63         pci_write_config_word(dev, ATIIXP_IDE_PIO_MODE, pio_mode_data);
  64
  65         pci_read_config_dword(dev, ATIIXP_IDE_PIO_TIMING, &pio_timing_data);
  66         pio_timing_data &= ~(0xff << timing_shift);
  67         pio_timing_data |= (pio_timing[pio].recover_width << timing_shift) |
  68                  (pio_timing[pio].command_width << (timing_shift + 4));
  69         pci_write_config_dword(dev, ATIIXP_IDE_PIO_TIMING, pio_timing_data);
  70
  71         spin_unlock_irqrestore(&atiixp_lock, flags);
  72 }
  73
  74 /**
  75  *      atiixp_set_dma_mode     -       set host controller for DMA mode
  76  *      @drive: drive
  77  *      @speed: DMA mode
  78  *
  79  *      Set a ATIIXP host controller to the desired DMA mode.  This involves
  80  *      programming the right timing data into the PCI configuration space.
  81  */
  82
  83 static void atiixp_set_dma_mode(ide_drive_t *drive, const u8 speed)
  84 {
  85         struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
  86         unsigned long flags;
  87         int timing_shift = (drive->dn & 2) ? 16 : 0 + (drive->dn & 1) ? 0 : 8;
  88         u32 tmp32;
  89         u16 tmp16;
  90         u16 udma_ctl = 0;
  91
  92         spin_lock_irqsave(&atiixp_lock, flags);
  93
  94         pci_read_config_word(dev, ATIIXP_IDE_UDMA_CONTROL, &udma_ctl);
  95
  96         if (speed >= XFER_UDMA_0) {
  97                 pci_read_config_word(dev, ATIIXP_IDE_UDMA_MODE, &tmp16);
  98                 tmp16 &= ~(0x07 << (drive->dn * 4));
  99                 tmp16 |= ((speed & 0x07) << (drive->dn * 4));
 100                 pci_write_config_word(dev, ATIIXP_IDE_UDMA_MODE, tmp16);
 101
 102                 udma_ctl |= (1 << drive->dn);
 103         } else if (speed >= XFER_MW_DMA_0) {
 104                 u8 i = speed & 0x03;
 105
 106                 pci_read_config_dword(dev, ATIIXP_IDE_MDMA_TIMING, &tmp32);
 107                 tmp32 &= ~(0xff << timing_shift);
 108                 tmp32 |= (mdma_timing[i].recover_width << timing_shift) |
 109                          (mdma_timing[i].command_width << (timing_shift + 4));
 110                 pci_write_config_dword(dev, ATIIXP_IDE_MDMA_TIMING, tmp32);
 111
 112                 udma_ctl &= ~(1 << drive->dn);
 113         }
 114
 115         pci_write_config_word(dev, ATIIXP_IDE_UDMA_CONTROL, udma_ctl);
 116
 117         spin_unlock_irqrestore(&atiixp_lock, flags);
 118 }
 119
 120 static u8 __devinit atiixp_cable_detect(ide_hwif_t *hwif)
 121 {
 122         struct pci_dev *pdev = to_pci_dev(hwif->dev);
 123         u8 udma_mode = 0, ch = hwif->channel;
 124
 125         pci_read_config_byte(pdev, ATIIXP_IDE_UDMA_MODE + ch, &udma_mode);
 126
 127         if ((udma_mode & 0x07) >= 0x04 || (udma_mode & 0x70) >= 0x40)
 128                 return ATA_CBL_PATA80;
 129         else
 130                 return ATA_CBL_PATA40;
 131 }
 132
 133 /**
 134  *      init_hwif_atiixp                -       fill in the hwif for the ATIIXP
 135  *      @hwif: IDE interface
 136  *
 137  *      Set up the ide_hwif_t for the ATIIXP interface according to the
 138  *      capabilities of the hardware.
 139  */
 140
 141 static void __devinit init_hwif_atiixp(ide_hwif_t *hwif)
 142 {
 143         hwif->set_pio_mode = &atiixp_set_pio_mode;
 144         hwif->set_dma_mode = &atiixp_set_dma_mode;
 145
 146         hwif->cable_detect = atiixp_cable_detect;
 147 }
 148
 149 static const struct ide_port_info atiixp_pci_info[] __devinitdata = {
 150         {       /* 0 */
 151                 .name           = "ATIIXP",
 152                 .init_hwif      = init_hwif_atiixp,
 153                 .enablebits     = {{0x48,0x01,0x00}, {0x48,0x08,0x00}},
 154                 .host_flags     = IDE_HFLAG_LEGACY_IRQS | IDE_HFLAG_BOOTABLE,
 155                 .pio_mask       = ATA_PIO4,
 156                 .mwdma_mask     = ATA_MWDMA2,
 157                 .udma_mask      = ATA_UDMA5,
 158         },{     /* 1 */
 159                 .name           = "SB600_PATA",
 160                 .init_hwif      = init_hwif_atiixp,
 161                 .enablebits     = {{0x48,0x01,0x00}, {0x00,0x00,0x00}},
 162                 .host_flags     = IDE_HFLAG_SINGLE | IDE_HFLAG_LEGACY_IRQS |
 163                                   IDE_HFLAG_BOOTABLE,
 164                 .pio_mask       = ATA_PIO4,
 165                 .mwdma_mask     = ATA_MWDMA2,
 166                 .udma_mask      = ATA_UDMA5,
 167         },
 168 };
 169
 170 /**
 171  *      atiixp_init_one -       called when a ATIIXP is found
 172  *      @dev: the atiixp device
 173  *      @id: the matching pci id
 174  *
 175  *      Called when the PCI registration layer (or the IDE initialization)
 176  *      finds a device matching our IDE device tables.
 177  */
 178
 179 static int __devinit atiixp_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 180 {
 181         return ide_setup_pci_device(dev, &atiixp_pci_info[id->driver_data]);
 182 }
 183
 184 static const struct pci_device_id atiixp_pci_tbl[] = {
 185         { PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP200_IDE), 0 },
 186         { PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP300_IDE), 0 },
 187         { PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP400_IDE), 0 },
 188         { PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP600_IDE), 1 },
 189         { PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP700_IDE), 0 },
 190         { 0, },
 191 };
 192 MODULE_DEVICE_TABLE(pci, atiixp_pci_tbl);
 193
 194 static struct pci_driver driver = {
 195         .name           = "ATIIXP_IDE",
 196         .id_table       = atiixp_pci_tbl,
 197         .probe          = atiixp_init_one,
 198 };
 199
 200 static int __init atiixp_ide_init(void)
 201 {
 202         return ide_pci_register_driver(&driver);
 203 }
 204
 205 module_init(atiixp_ide_init);
 206
 207 MODULE_AUTHOR("HUI YU");
 208 MODULE_DESCRIPTION("PCI driver module for ATI IXP IDE");
 209 MODULE_LICENSE("GPL");