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Merge git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
[wrt350n-kernel.git] / drivers / infiniband / hw / ehca / ehca_qp.c
blob1012f15a7140e11cf579548069a80f890389ce6a
1 /*
2 * IBM eServer eHCA Infiniband device driver for Linux on POWER
3 *
4 * QP functions
5 *
6 * Authors: Joachim Fenkes <fenkes@de.ibm.com>
7 * Stefan Roscher <stefan.roscher@de.ibm.com>
8 * Waleri Fomin <fomin@de.ibm.com>
9 * Hoang-Nam Nguyen <hnguyen@de.ibm.com>
10 * Reinhard Ernst <rernst@de.ibm.com>
11 * Heiko J Schick <schickhj@de.ibm.com>
12 *
13 * Copyright (c) 2005 IBM Corporation
14 *
15 * All rights reserved.
16 *
17 * This source code is distributed under a dual license of GPL v2.0 and OpenIB
18 * BSD.
19 *
20 * OpenIB BSD License
21 *
22 * Redistribution and use in source and binary forms, with or without
23 * modification, are permitted provided that the following conditions are met:
24 *
25 * Redistributions of source code must retain the above copyright notice, this
26 * list of conditions and the following disclaimer.
27 *
28 * Redistributions in binary form must reproduce the above copyright notice,
29 * this list of conditions and the following disclaimer in the documentation
30 * and/or other materials
31 * provided with the distribution.
32 *
33 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
34 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
35 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
36 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
37 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
38 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
39 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
40 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
41 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
42 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
43 * POSSIBILITY OF SUCH DAMAGE.
44 */
45
46
47 #include <asm/current.h>
48
49 #include "ehca_classes.h"
50 #include "ehca_tools.h"
51 #include "ehca_qes.h"
52 #include "ehca_iverbs.h"
53 #include "hcp_if.h"
54 #include "hipz_fns.h"
55
56 static struct kmem_cache *qp_cache;
57
58 /*
59 * attributes not supported by query qp
60 */
61 #define QP_ATTR_QUERY_NOT_SUPPORTED (IB_QP_MAX_DEST_RD_ATOMIC | \
62 IB_QP_MAX_QP_RD_ATOMIC | \
63 IB_QP_ACCESS_FLAGS | \
64 IB_QP_EN_SQD_ASYNC_NOTIFY)
65
66 /*
67 * ehca (internal) qp state values
68 */
69 enum ehca_qp_state {
70 EHCA_QPS_RESET = 1,
71 EHCA_QPS_INIT = 2,
72 EHCA_QPS_RTR = 3,
73 EHCA_QPS_RTS = 5,
74 EHCA_QPS_SQD = 6,
75 EHCA_QPS_SQE = 8,
76 EHCA_QPS_ERR = 128
77 };
78
79 /*
80 * qp state transitions as defined by IB Arch Rel 1.1 page 431
81 */
82 enum ib_qp_statetrans {
83 IB_QPST_ANY2RESET,
84 IB_QPST_ANY2ERR,
85 IB_QPST_RESET2INIT,
86 IB_QPST_INIT2RTR,
87 IB_QPST_INIT2INIT,
88 IB_QPST_RTR2RTS,
89 IB_QPST_RTS2SQD,
90 IB_QPST_RTS2RTS,
91 IB_QPST_SQD2RTS,
92 IB_QPST_SQE2RTS,
93 IB_QPST_SQD2SQD,
94 IB_QPST_MAX /* nr of transitions, this must be last!!! */
95 };
96
97 /*
98 * ib2ehca_qp_state maps IB to ehca qp_state
99 * returns ehca qp state corresponding to given ib qp state
100 */
101 static inline enum ehca_qp_state ib2ehca_qp_state(enum ib_qp_state ib_qp_state)
102 {
103 switch (ib_qp_state) {
104 case IB_QPS_RESET:
105 return EHCA_QPS_RESET;
106 case IB_QPS_INIT:
107 return EHCA_QPS_INIT;
108 case IB_QPS_RTR:
109 return EHCA_QPS_RTR;
110 case IB_QPS_RTS:
111 return EHCA_QPS_RTS;
112 case IB_QPS_SQD:
113 return EHCA_QPS_SQD;
114 case IB_QPS_SQE:
115 return EHCA_QPS_SQE;
116 case IB_QPS_ERR:
117 return EHCA_QPS_ERR;
118 default:
119 ehca_gen_err("invalid ib_qp_state=%x", ib_qp_state);
120 return -EINVAL;
121 }
122 }
123
124 /*
125 * ehca2ib_qp_state maps ehca to IB qp_state
126 * returns ib qp state corresponding to given ehca qp state
127 */
128 static inline enum ib_qp_state ehca2ib_qp_state(enum ehca_qp_state
129 ehca_qp_state)
130 {
131 switch (ehca_qp_state) {
132 case EHCA_QPS_RESET:
133 return IB_QPS_RESET;
134 case EHCA_QPS_INIT:
135 return IB_QPS_INIT;
136 case EHCA_QPS_RTR:
137 return IB_QPS_RTR;
138 case EHCA_QPS_RTS:
139 return IB_QPS_RTS;
140 case EHCA_QPS_SQD:
141 return IB_QPS_SQD;
142 case EHCA_QPS_SQE:
143 return IB_QPS_SQE;
144 case EHCA_QPS_ERR:
145 return IB_QPS_ERR;
146 default:
147 ehca_gen_err("invalid ehca_qp_state=%x", ehca_qp_state);
148 return -EINVAL;
149 }
150 }
151
152 /*
153 * ehca_qp_type used as index for req_attr and opt_attr of
154 * struct ehca_modqp_statetrans
155 */
156 enum ehca_qp_type {
157 QPT_RC = 0,
158 QPT_UC = 1,
159 QPT_UD = 2,
160 QPT_SQP = 3,
161 QPT_MAX
162 };
163
164 /*
165 * ib2ehcaqptype maps Ib to ehca qp_type
166 * returns ehca qp type corresponding to ib qp type
167 */
168 static inline enum ehca_qp_type ib2ehcaqptype(enum ib_qp_type ibqptype)
169 {
170 switch (ibqptype) {
171 case IB_QPT_SMI:
172 case IB_QPT_GSI:
173 return QPT_SQP;
174 case IB_QPT_RC:
175 return QPT_RC;
176 case IB_QPT_UC:
177 return QPT_UC;
178 case IB_QPT_UD:
179 return QPT_UD;
180 default:
181 ehca_gen_err("Invalid ibqptype=%x", ibqptype);
182 return -EINVAL;
183 }
184 }
185
186 static inline enum ib_qp_statetrans get_modqp_statetrans(int ib_fromstate,
187 int ib_tostate)
188 {
189 int index = -EINVAL;
190 switch (ib_tostate) {
191 case IB_QPS_RESET:
192 index = IB_QPST_ANY2RESET;
193 break;
194 case IB_QPS_INIT:
195 switch (ib_fromstate) {
196 case IB_QPS_RESET:
197 index = IB_QPST_RESET2INIT;
198 break;
199 case IB_QPS_INIT:
200 index = IB_QPST_INIT2INIT;
201 break;
202 }
203 break;
204 case IB_QPS_RTR:
205 if (ib_fromstate == IB_QPS_INIT)
206 index = IB_QPST_INIT2RTR;
207 break;
208 case IB_QPS_RTS:
209 switch (ib_fromstate) {
210 case IB_QPS_RTR:
211 index = IB_QPST_RTR2RTS;
212 break;
213 case IB_QPS_RTS:
214 index = IB_QPST_RTS2RTS;
215 break;
216 case IB_QPS_SQD:
217 index = IB_QPST_SQD2RTS;
218 break;
219 case IB_QPS_SQE:
220 index = IB_QPST_SQE2RTS;
221 break;
222 }
223 break;
224 case IB_QPS_SQD:
225 if (ib_fromstate == IB_QPS_RTS)
226 index = IB_QPST_RTS2SQD;
227 break;
228 case IB_QPS_SQE:
229 break;
230 case IB_QPS_ERR:
231 index = IB_QPST_ANY2ERR;
232 break;
233 default:
234 break;
235 }
236 return index;
237 }
238
239 /*
240 * ibqptype2servicetype returns hcp service type corresponding to given
241 * ib qp type used by create_qp()
242 */
243 static inline int ibqptype2servicetype(enum ib_qp_type ibqptype)
244 {
245 switch (ibqptype) {
246 case IB_QPT_SMI:
247 case IB_QPT_GSI:
248 return ST_UD;
249 case IB_QPT_RC:
250 return ST_RC;
251 case IB_QPT_UC:
252 return ST_UC;
253 case IB_QPT_UD:
254 return ST_UD;
255 case IB_QPT_RAW_IPV6:
256 return -EINVAL;
257 case IB_QPT_RAW_ETY:
258 return -EINVAL;
259 default:
260 ehca_gen_err("Invalid ibqptype=%x", ibqptype);
261 return -EINVAL;
262 }
263 }
264
265 /*
266 * init userspace queue info from ipz_queue data
267 */
268 static inline void queue2resp(struct ipzu_queue_resp *resp,
269 struct ipz_queue *queue)
270 {
271 resp->qe_size = queue->qe_size;
272 resp->act_nr_of_sg = queue->act_nr_of_sg;
273 resp->queue_length = queue->queue_length;
274 resp->pagesize = queue->pagesize;
275 resp->toggle_state = queue->toggle_state;
276 resp->offset = queue->offset;
277 }
278
279 /*
280 * init_qp_queue initializes/constructs r/squeue and registers queue pages.
281 */
282 static inline int init_qp_queue(struct ehca_shca *shca,
283 struct ehca_pd *pd,
284 struct ehca_qp *my_qp,
285 struct ipz_queue *queue,
286 int q_type,
287 u64 expected_hret,
288 struct ehca_alloc_queue_parms *parms,
289 int wqe_size)
290 {
291 int ret, cnt, ipz_rc, nr_q_pages;
292 void *vpage;
293 u64 rpage, h_ret;
294 struct ib_device *ib_dev = &shca->ib_device;
295 struct ipz_adapter_handle ipz_hca_handle = shca->ipz_hca_handle;
296
297 if (!parms->queue_size)
298 return 0;
299
300 if (parms->is_small) {
301 nr_q_pages = 1;
302 ipz_rc = ipz_queue_ctor(pd, queue, nr_q_pages,
303 128 << parms->page_size,
304 wqe_size, parms->act_nr_sges, 1);
305 } else {
306 nr_q_pages = parms->queue_size;
307 ipz_rc = ipz_queue_ctor(pd, queue, nr_q_pages,
308 EHCA_PAGESIZE, wqe_size,
309 parms->act_nr_sges, 0);
310 }
311
312 if (!ipz_rc) {
313 ehca_err(ib_dev, "Cannot allocate page for queue. ipz_rc=%i",
314 ipz_rc);
315 return -EBUSY;
316 }
317
318 /* register queue pages */
319 for (cnt = 0; cnt < nr_q_pages; cnt++) {
320 vpage = ipz_qpageit_get_inc(queue);
321 if (!vpage) {
322 ehca_err(ib_dev, "ipz_qpageit_get_inc() "
323 "failed p_vpage= %p", vpage);
324 ret = -EINVAL;
325 goto init_qp_queue1;
326 }
327 rpage = virt_to_abs(vpage);
328
329 h_ret = hipz_h_register_rpage_qp(ipz_hca_handle,
330 my_qp->ipz_qp_handle,
331 NULL, 0, q_type,
332 rpage, parms->is_small ? 0 : 1,
333 my_qp->galpas.kernel);
334 if (cnt == (nr_q_pages - 1)) { /* last page! */
335 if (h_ret != expected_hret) {
336 ehca_err(ib_dev, "hipz_qp_register_rpage() "
337 "h_ret=%li", h_ret);
338 ret = ehca2ib_return_code(h_ret);
339 goto init_qp_queue1;
340 }
341 vpage = ipz_qpageit_get_inc(&my_qp->ipz_rqueue);
342 if (vpage) {
343 ehca_err(ib_dev, "ipz_qpageit_get_inc() "
344 "should not succeed vpage=%p", vpage);
345 ret = -EINVAL;
346 goto init_qp_queue1;
347 }
348 } else {
349 if (h_ret != H_PAGE_REGISTERED) {
350 ehca_err(ib_dev, "hipz_qp_register_rpage() "
351 "h_ret=%li", h_ret);
352 ret = ehca2ib_return_code(h_ret);
353 goto init_qp_queue1;
354 }
355 }
356 }
357
358 ipz_qeit_reset(queue);
359
360 return 0;
361
362 init_qp_queue1:
363 ipz_queue_dtor(pd, queue);
364 return ret;
365 }
366
367 static inline int ehca_calc_wqe_size(int act_nr_sge, int is_llqp)
368 {
369 if (is_llqp)
370 return 128 << act_nr_sge;
371 else
372 return offsetof(struct ehca_wqe,
373 u.nud.sg_list[act_nr_sge]);
374 }
375
376 static void ehca_determine_small_queue(struct ehca_alloc_queue_parms *queue,
377 int req_nr_sge, int is_llqp)
378 {
379 u32 wqe_size, q_size;
380 int act_nr_sge = req_nr_sge;
381
382 if (!is_llqp)
383 /* round up #SGEs so WQE size is a power of 2 */
384 for (act_nr_sge = 4; act_nr_sge <= 252;
385 act_nr_sge = 4 + 2 * act_nr_sge)
386 if (act_nr_sge >= req_nr_sge)
387 break;
388
389 wqe_size = ehca_calc_wqe_size(act_nr_sge, is_llqp);
390 q_size = wqe_size * (queue->max_wr + 1);
391
392 if (q_size <= 512)
393 queue->page_size = 2;
394 else if (q_size <= 1024)
395 queue->page_size = 3;
396 else
397 queue->page_size = 0;
398
399 queue->is_small = (queue->page_size != 0);
400 }
401
402 /*
403 * Create an ib_qp struct that is either a QP or an SRQ, depending on
404 * the value of the is_srq parameter. If init_attr and srq_init_attr share
405 * fields, the field out of init_attr is used.
406 */
407 static struct ehca_qp *internal_create_qp(
408 struct ib_pd *pd,
409 struct ib_qp_init_attr *init_attr,
410 struct ib_srq_init_attr *srq_init_attr,
411 struct ib_udata *udata, int is_srq)
412 {
413 struct ehca_qp *my_qp;
414 struct ehca_pd *my_pd = container_of(pd, struct ehca_pd, ib_pd);
415 struct ehca_shca *shca = container_of(pd->device, struct ehca_shca,
416 ib_device);
417 struct ib_ucontext *context = NULL;
418 u64 h_ret;
419 int is_llqp = 0, has_srq = 0;
420 int qp_type, max_send_sge, max_recv_sge, ret;
421
422 /* h_call's out parameters */
423 struct ehca_alloc_qp_parms parms;
424 u32 swqe_size = 0, rwqe_size = 0, ib_qp_num;
425 unsigned long flags;
426
427 memset(&parms, 0, sizeof(parms));
428 qp_type = init_attr->qp_type;
429
430 if (init_attr->sq_sig_type != IB_SIGNAL_REQ_WR &&
431 init_attr->sq_sig_type != IB_SIGNAL_ALL_WR) {
432 ehca_err(pd->device, "init_attr->sg_sig_type=%x not allowed",
433 init_attr->sq_sig_type);
434 return ERR_PTR(-EINVAL);
435 }
436
437 /* save LLQP info */
438 if (qp_type & 0x80) {
439 is_llqp = 1;
440 parms.ext_type = EQPT_LLQP;
441 parms.ll_comp_flags = qp_type & LLQP_COMP_MASK;
442 }
443 qp_type &= 0x1F;
444 init_attr->qp_type &= 0x1F;
445
446 /* handle SRQ base QPs */
447 if (init_attr->srq) {
448 struct ehca_qp *my_srq =
449 container_of(init_attr->srq, struct ehca_qp, ib_srq);
450
451 has_srq = 1;
452 parms.ext_type = EQPT_SRQBASE;
453 parms.srq_qpn = my_srq->real_qp_num;
454 }
455
456 if (is_llqp && has_srq) {
457 ehca_err(pd->device, "LLQPs can't have an SRQ");
458 return ERR_PTR(-EINVAL);
459 }
460
461 /* handle SRQs */
462 if (is_srq) {
463 parms.ext_type = EQPT_SRQ;
464 parms.srq_limit = srq_init_attr->attr.srq_limit;
465 if (init_attr->cap.max_recv_sge > 3) {
466 ehca_err(pd->device, "no more than three SGEs "
467 "supported for SRQ pd=%p max_sge=%x",
468 pd, init_attr->cap.max_recv_sge);
469 return ERR_PTR(-EINVAL);
470 }
471 }
472
473 /* check QP type */
474 if (qp_type != IB_QPT_UD &&
475 qp_type != IB_QPT_UC &&
476 qp_type != IB_QPT_RC &&
477 qp_type != IB_QPT_SMI &&
478 qp_type != IB_QPT_GSI) {
479 ehca_err(pd->device, "wrong QP Type=%x", qp_type);
480 return ERR_PTR(-EINVAL);
481 }
482
483 if (is_llqp) {
484 switch (qp_type) {
485 case IB_QPT_RC:
486 if ((init_attr->cap.max_send_wr > 255) ||
487 (init_attr->cap.max_recv_wr > 255)) {
488 ehca_err(pd->device,
489 "Invalid Number of max_sq_wr=%x "
490 "or max_rq_wr=%x for RC LLQP",
491 init_attr->cap.max_send_wr,
492 init_attr->cap.max_recv_wr);
493 return ERR_PTR(-EINVAL);
494 }
495 break;
496 case IB_QPT_UD:
497 if (!EHCA_BMASK_GET(HCA_CAP_UD_LL_QP, shca->hca_cap)) {
498 ehca_err(pd->device, "UD LLQP not supported "
499 "by this adapter");
500 return ERR_PTR(-ENOSYS);
501 }
502 if (!(init_attr->cap.max_send_sge <= 5
503 && init_attr->cap.max_send_sge >= 1
504 && init_attr->cap.max_recv_sge <= 5
505 && init_attr->cap.max_recv_sge >= 1)) {
506 ehca_err(pd->device,
507 "Invalid Number of max_send_sge=%x "
508 "or max_recv_sge=%x for UD LLQP",
509 init_attr->cap.max_send_sge,
510 init_attr->cap.max_recv_sge);
511 return ERR_PTR(-EINVAL);
512 } else if (init_attr->cap.max_send_wr > 255) {
513 ehca_err(pd->device,
514 "Invalid Number of "
515 "max_send_wr=%x for UD QP_TYPE=%x",
516 init_attr->cap.max_send_wr, qp_type);
517 return ERR_PTR(-EINVAL);
518 }
519 break;
520 default:
521 ehca_err(pd->device, "unsupported LL QP Type=%x",
522 qp_type);
523 return ERR_PTR(-EINVAL);
524 break;
525 }
526 } else {
527 int max_sge = (qp_type == IB_QPT_UD || qp_type == IB_QPT_SMI
528 || qp_type == IB_QPT_GSI) ? 250 : 252;
529
530 if (init_attr->cap.max_send_sge > max_sge
531 || init_attr->cap.max_recv_sge > max_sge) {
532 ehca_err(pd->device, "Invalid number of SGEs requested "
533 "send_sge=%x recv_sge=%x max_sge=%x",
534 init_attr->cap.max_send_sge,
535 init_attr->cap.max_recv_sge, max_sge);
536 return ERR_PTR(-EINVAL);
537 }
538 }
539
540 if (pd->uobject && udata)
541 context = pd->uobject->context;
542
543 my_qp = kmem_cache_zalloc(qp_cache, GFP_KERNEL);
544 if (!my_qp) {
545 ehca_err(pd->device, "pd=%p not enough memory to alloc qp", pd);
546 return ERR_PTR(-ENOMEM);
547 }
548
549 spin_lock_init(&my_qp->spinlock_s);
550 spin_lock_init(&my_qp->spinlock_r);
551 my_qp->qp_type = qp_type;
552 my_qp->ext_type = parms.ext_type;
553
554 if (init_attr->recv_cq)
555 my_qp->recv_cq =
556 container_of(init_attr->recv_cq, struct ehca_cq, ib_cq);
557 if (init_attr->send_cq)
558 my_qp->send_cq =
559 container_of(init_attr->send_cq, struct ehca_cq, ib_cq);
560
561 do {
562 if (!idr_pre_get(&ehca_qp_idr, GFP_KERNEL)) {
563 ret = -ENOMEM;
564 ehca_err(pd->device, "Can't reserve idr resources.");
565 goto create_qp_exit0;
566 }
567
568 write_lock_irqsave(&ehca_qp_idr_lock, flags);
569 ret = idr_get_new(&ehca_qp_idr, my_qp, &my_qp->token);
570 write_unlock_irqrestore(&ehca_qp_idr_lock, flags);
571 } while (ret == -EAGAIN);
572
573 if (ret) {
574 ret = -ENOMEM;
575 ehca_err(pd->device, "Can't allocate new idr entry.");
576 goto create_qp_exit0;
577 }
578
579 if (my_qp->token > 0x1FFFFFF) {
580 ret = -EINVAL;
581 ehca_err(pd->device, "Invalid number of qp");
582 goto create_qp_exit1;
583 }
584
585 if (has_srq)
586 parms.srq_token = my_qp->token;
587
588 parms.servicetype = ibqptype2servicetype(qp_type);
589 if (parms.servicetype < 0) {
590 ret = -EINVAL;
591 ehca_err(pd->device, "Invalid qp_type=%x", qp_type);
592 goto create_qp_exit1;
593 }
594
595 /* Always signal by WQE so we can hide circ. WQEs */
596 parms.sigtype = HCALL_SIGT_BY_WQE;
597
598 /* UD_AV CIRCUMVENTION */
599 max_send_sge = init_attr->cap.max_send_sge;
600 max_recv_sge = init_attr->cap.max_recv_sge;
601 if (parms.servicetype == ST_UD && !is_llqp) {
602 max_send_sge += 2;
603 max_recv_sge += 2;
604 }
605
606 parms.token = my_qp->token;
607 parms.eq_handle = shca->eq.ipz_eq_handle;
608 parms.pd = my_pd->fw_pd;
609 if (my_qp->send_cq)
610 parms.send_cq_handle = my_qp->send_cq->ipz_cq_handle;
611 if (my_qp->recv_cq)
612 parms.recv_cq_handle = my_qp->recv_cq->ipz_cq_handle;
613
614 parms.squeue.max_wr = init_attr->cap.max_send_wr;
615 parms.rqueue.max_wr = init_attr->cap.max_recv_wr;
616 parms.squeue.max_sge = max_send_sge;
617 parms.rqueue.max_sge = max_recv_sge;
618
619 /* RC QPs need one more SWQE for unsolicited ack circumvention */
620 if (qp_type == IB_QPT_RC)
621 parms.squeue.max_wr++;
622
623 if (EHCA_BMASK_GET(HCA_CAP_MINI_QP, shca->hca_cap)) {
624 if (HAS_SQ(my_qp))
625 ehca_determine_small_queue(
626 &parms.squeue, max_send_sge, is_llqp);
627 if (HAS_RQ(my_qp))
628 ehca_determine_small_queue(
629 &parms.rqueue, max_recv_sge, is_llqp);
630 parms.qp_storage =
631 (parms.squeue.is_small || parms.rqueue.is_small);
632 }
633
634 h_ret = hipz_h_alloc_resource_qp(shca->ipz_hca_handle, &parms);
635 if (h_ret != H_SUCCESS) {
636 ehca_err(pd->device, "h_alloc_resource_qp() failed h_ret=%li",
637 h_ret);
638 ret = ehca2ib_return_code(h_ret);
639 goto create_qp_exit1;
640 }
641
642 ib_qp_num = my_qp->real_qp_num = parms.real_qp_num;
643 my_qp->ipz_qp_handle = parms.qp_handle;
644 my_qp->galpas = parms.galpas;
645
646 swqe_size = ehca_calc_wqe_size(parms.squeue.act_nr_sges, is_llqp);
647 rwqe_size = ehca_calc_wqe_size(parms.rqueue.act_nr_sges, is_llqp);
648
649 switch (qp_type) {
650 case IB_QPT_RC:
651 if (is_llqp) {
652 parms.squeue.act_nr_sges = 1;
653 parms.rqueue.act_nr_sges = 1;
654 }
655 /* hide the extra WQE */
656 parms.squeue.act_nr_wqes--;
657 break;
658 case IB_QPT_UD:
659 case IB_QPT_GSI:
660 case IB_QPT_SMI:
661 /* UD circumvention */
662 if (is_llqp) {
663 parms.squeue.act_nr_sges = 1;
664 parms.rqueue.act_nr_sges = 1;
665 } else {
666 parms.squeue.act_nr_sges -= 2;
667 parms.rqueue.act_nr_sges -= 2;
668 }
669
670 if (IB_QPT_GSI == qp_type || IB_QPT_SMI == qp_type) {
671 parms.squeue.act_nr_wqes = init_attr->cap.max_send_wr;
672 parms.rqueue.act_nr_wqes = init_attr->cap.max_recv_wr;
673 parms.squeue.act_nr_sges = init_attr->cap.max_send_sge;
674 parms.rqueue.act_nr_sges = init_attr->cap.max_recv_sge;
675 ib_qp_num = (qp_type == IB_QPT_SMI) ? 0 : 1;
676 }
677
678 break;
679
680 default:
681 break;
682 }
683
684 /* initialize r/squeue and register queue pages */
685 if (HAS_SQ(my_qp)) {
686 ret = init_qp_queue(
687 shca, my_pd, my_qp, &my_qp->ipz_squeue, 0,
688 HAS_RQ(my_qp) ? H_PAGE_REGISTERED : H_SUCCESS,
689 &parms.squeue, swqe_size);
690 if (ret) {
691 ehca_err(pd->device, "Couldn't initialize squeue "
692 "and pages ret=%i", ret);
693 goto create_qp_exit2;
694 }
695 }
696
697 if (HAS_RQ(my_qp)) {
698 ret = init_qp_queue(
699 shca, my_pd, my_qp, &my_qp->ipz_rqueue, 1,
700 H_SUCCESS, &parms.rqueue, rwqe_size);
701 if (ret) {
702 ehca_err(pd->device, "Couldn't initialize rqueue "
703 "and pages ret=%i", ret);
704 goto create_qp_exit3;
705 }
706 }
707
708 if (is_srq) {
709 my_qp->ib_srq.pd = &my_pd->ib_pd;
710 my_qp->ib_srq.device = my_pd->ib_pd.device;
711
712 my_qp->ib_srq.srq_context = init_attr->qp_context;
713 my_qp->ib_srq.event_handler = init_attr->event_handler;
714 } else {
715 my_qp->ib_qp.qp_num = ib_qp_num;
716 my_qp->ib_qp.pd = &my_pd->ib_pd;
717 my_qp->ib_qp.device = my_pd->ib_pd.device;
718
719 my_qp->ib_qp.recv_cq = init_attr->recv_cq;
720 my_qp->ib_qp.send_cq = init_attr->send_cq;
721
722 my_qp->ib_qp.qp_type = qp_type;
723 my_qp->ib_qp.srq = init_attr->srq;
724
725 my_qp->ib_qp.qp_context = init_attr->qp_context;
726 my_qp->ib_qp.event_handler = init_attr->event_handler;
727 }
728
729 init_attr->cap.max_inline_data = 0; /* not supported yet */
730 init_attr->cap.max_recv_sge = parms.rqueue.act_nr_sges;
731 init_attr->cap.max_recv_wr = parms.rqueue.act_nr_wqes;
732 init_attr->cap.max_send_sge = parms.squeue.act_nr_sges;
733 init_attr->cap.max_send_wr = parms.squeue.act_nr_wqes;
734 my_qp->init_attr = *init_attr;
735
736 if (qp_type == IB_QPT_SMI || qp_type == IB_QPT_GSI) {
737 shca->sport[init_attr->port_num - 1].ibqp_sqp[qp_type] =
738 &my_qp->ib_qp;
739 if (ehca_nr_ports < 0) {
740 /* alloc array to cache subsequent modify qp parms
741 * for autodetect mode
742 */
743 my_qp->mod_qp_parm =
744 kzalloc(EHCA_MOD_QP_PARM_MAX *
745 sizeof(*my_qp->mod_qp_parm),
746 GFP_KERNEL);
747 if (!my_qp->mod_qp_parm) {
748 ehca_err(pd->device,
749 "Could not alloc mod_qp_parm");
750 goto create_qp_exit4;
751 }
752 }
753 }
754
755 /* NOTE: define_apq0() not supported yet */
756 if (qp_type == IB_QPT_GSI) {
757 h_ret = ehca_define_sqp(shca, my_qp, init_attr);
758 if (h_ret != H_SUCCESS) {
759 ret = ehca2ib_return_code(h_ret);
760 goto create_qp_exit5;
761 }
762 }
763
764 if (my_qp->send_cq) {
765 ret = ehca_cq_assign_qp(my_qp->send_cq, my_qp);
766 if (ret) {
767 ehca_err(pd->device,
768 "Couldn't assign qp to send_cq ret=%i", ret);
769 goto create_qp_exit5;
770 }
771 }
772
773 /* copy queues, galpa data to user space */
774 if (context && udata) {
775 struct ehca_create_qp_resp resp;
776 memset(&resp, 0, sizeof(resp));
777
778 resp.qp_num = my_qp->real_qp_num;
779 resp.token = my_qp->token;
780 resp.qp_type = my_qp->qp_type;
781 resp.ext_type = my_qp->ext_type;
782 resp.qkey = my_qp->qkey;
783 resp.real_qp_num = my_qp->real_qp_num;
784
785 if (HAS_SQ(my_qp))
786 queue2resp(&resp.ipz_squeue, &my_qp->ipz_squeue);
787 if (HAS_RQ(my_qp))
788 queue2resp(&resp.ipz_rqueue, &my_qp->ipz_rqueue);
789 resp.fw_handle_ofs = (u32)
790 (my_qp->galpas.user.fw_handle & (PAGE_SIZE - 1));
791
792 if (ib_copy_to_udata(udata, &resp, sizeof resp)) {
793 ehca_err(pd->device, "Copy to udata failed");
794 ret = -EINVAL;
795 goto create_qp_exit6;
796 }
797 }
798
799 return my_qp;
800
801 create_qp_exit6:
802 ehca_cq_unassign_qp(my_qp->send_cq, my_qp->real_qp_num);
803
804 create_qp_exit5:
805 kfree(my_qp->mod_qp_parm);
806
807 create_qp_exit4:
808 if (HAS_RQ(my_qp))
809 ipz_queue_dtor(my_pd, &my_qp->ipz_rqueue);
810
811 create_qp_exit3:
812 if (HAS_SQ(my_qp))
813 ipz_queue_dtor(my_pd, &my_qp->ipz_squeue);
814
815 create_qp_exit2:
816 hipz_h_destroy_qp(shca->ipz_hca_handle, my_qp);
817
818 create_qp_exit1:
819 write_lock_irqsave(&ehca_qp_idr_lock, flags);
820 idr_remove(&ehca_qp_idr, my_qp->token);
821 write_unlock_irqrestore(&ehca_qp_idr_lock, flags);
822
823 create_qp_exit0:
824 kmem_cache_free(qp_cache, my_qp);
825 return ERR_PTR(ret);
826 }
827
828 struct ib_qp *ehca_create_qp(struct ib_pd *pd,
829 struct ib_qp_init_attr *qp_init_attr,
830 struct ib_udata *udata)
831 {
832 struct ehca_qp *ret;
833
834 ret = internal_create_qp(pd, qp_init_attr, NULL, udata, 0);
835 return IS_ERR(ret) ? (struct ib_qp *)ret : &ret->ib_qp;
836 }
837
838 static int internal_destroy_qp(struct ib_device *dev, struct ehca_qp *my_qp,
839 struct ib_uobject *uobject);
840
841 struct ib_srq *ehca_create_srq(struct ib_pd *pd,
842 struct ib_srq_init_attr *srq_init_attr,
843 struct ib_udata *udata)
844 {
845 struct ib_qp_init_attr qp_init_attr;
846 struct ehca_qp *my_qp;
847 struct ib_srq *ret;
848 struct ehca_shca *shca = container_of(pd->device, struct ehca_shca,
849 ib_device);
850 struct hcp_modify_qp_control_block *mqpcb;
851 u64 hret, update_mask;
852
853 /* For common attributes, internal_create_qp() takes its info
854 * out of qp_init_attr, so copy all common attrs there.
855 */
856 memset(&qp_init_attr, 0, sizeof(qp_init_attr));
857 qp_init_attr.event_handler = srq_init_attr->event_handler;
858 qp_init_attr.qp_context = srq_init_attr->srq_context;
859 qp_init_attr.sq_sig_type = IB_SIGNAL_ALL_WR;
860 qp_init_attr.qp_type = IB_QPT_RC;
861 qp_init_attr.cap.max_recv_wr = srq_init_attr->attr.max_wr;
862 qp_init_attr.cap.max_recv_sge = srq_init_attr->attr.max_sge;
863
864 my_qp = internal_create_qp(pd, &qp_init_attr, srq_init_attr, udata, 1);
865 if (IS_ERR(my_qp))
866 return (struct ib_srq *)my_qp;
867
868 /* copy back return values */
869 srq_init_attr->attr.max_wr = qp_init_attr.cap.max_recv_wr;
870 srq_init_attr->attr.max_sge = 3;
871
872 /* drive SRQ into RTR state */
873 mqpcb = ehca_alloc_fw_ctrlblock(GFP_KERNEL);
874 if (!mqpcb) {
875 ehca_err(pd->device, "Could not get zeroed page for mqpcb "
876 "ehca_qp=%p qp_num=%x ", my_qp, my_qp->real_qp_num);
877 ret = ERR_PTR(-ENOMEM);
878 goto create_srq1;
879 }
880
881 mqpcb->qp_state = EHCA_QPS_INIT;
882 mqpcb->prim_phys_port = 1;
883 update_mask = EHCA_BMASK_SET(MQPCB_MASK_QP_STATE, 1);
884 hret = hipz_h_modify_qp(shca->ipz_hca_handle,
885 my_qp->ipz_qp_handle,
886 &my_qp->pf,
887 update_mask,
888 mqpcb, my_qp->galpas.kernel);
889 if (hret != H_SUCCESS) {
890 ehca_err(pd->device, "Could not modify SRQ to INIT "
891 "ehca_qp=%p qp_num=%x h_ret=%li",
892 my_qp, my_qp->real_qp_num, hret);
893 goto create_srq2;
894 }
895
896 mqpcb->qp_enable = 1;
897 update_mask = EHCA_BMASK_SET(MQPCB_MASK_QP_ENABLE, 1);
898 hret = hipz_h_modify_qp(shca->ipz_hca_handle,
899 my_qp->ipz_qp_handle,
900 &my_qp->pf,
901 update_mask,
902 mqpcb, my_qp->galpas.kernel);
903 if (hret != H_SUCCESS) {
904 ehca_err(pd->device, "Could not enable SRQ "
905 "ehca_qp=%p qp_num=%x h_ret=%li",
906 my_qp, my_qp->real_qp_num, hret);
907 goto create_srq2;
908 }
909
910 mqpcb->qp_state = EHCA_QPS_RTR;
911 update_mask = EHCA_BMASK_SET(MQPCB_MASK_QP_STATE, 1);
912 hret = hipz_h_modify_qp(shca->ipz_hca_handle,
913 my_qp->ipz_qp_handle,
914 &my_qp->pf,
915 update_mask,
916 mqpcb, my_qp->galpas.kernel);
917 if (hret != H_SUCCESS) {
918 ehca_err(pd->device, "Could not modify SRQ to RTR "
919 "ehca_qp=%p qp_num=%x h_ret=%li",
920 my_qp, my_qp->real_qp_num, hret);
921 goto create_srq2;
922 }
923
924 ehca_free_fw_ctrlblock(mqpcb);
925
926 return &my_qp->ib_srq;
927
928 create_srq2:
929 ret = ERR_PTR(ehca2ib_return_code(hret));
930 ehca_free_fw_ctrlblock(mqpcb);
931
932 create_srq1:
933 internal_destroy_qp(pd->device, my_qp, my_qp->ib_srq.uobject);
934
935 return ret;
936 }
937
938 /*
939 * prepare_sqe_rts called by internal_modify_qp() at trans sqe -> rts
940 * set purge bit of bad wqe and subsequent wqes to avoid reentering sqe
941 * returns total number of bad wqes in bad_wqe_cnt
942 */
943 static int prepare_sqe_rts(struct ehca_qp *my_qp, struct ehca_shca *shca,
944 int *bad_wqe_cnt)
945 {
946 u64 h_ret;
947 struct ipz_queue *squeue;
948 void *bad_send_wqe_p, *bad_send_wqe_v;
949 u64 q_ofs;
950 struct ehca_wqe *wqe;
951 int qp_num = my_qp->ib_qp.qp_num;
952
953 /* get send wqe pointer */
954 h_ret = hipz_h_disable_and_get_wqe(shca->ipz_hca_handle,
955 my_qp->ipz_qp_handle, &my_qp->pf,
956 &bad_send_wqe_p, NULL, 2);
957 if (h_ret != H_SUCCESS) {
958 ehca_err(&shca->ib_device, "hipz_h_disable_and_get_wqe() failed"
959 " ehca_qp=%p qp_num=%x h_ret=%li",
960 my_qp, qp_num, h_ret);
961 return ehca2ib_return_code(h_ret);
962 }
963 bad_send_wqe_p = (void *)((u64)bad_send_wqe_p & (~(1L << 63)));
964 ehca_dbg(&shca->ib_device, "qp_num=%x bad_send_wqe_p=%p",
965 qp_num, bad_send_wqe_p);
966 /* convert wqe pointer to vadr */
967 bad_send_wqe_v = abs_to_virt((u64)bad_send_wqe_p);
968 if (ehca_debug_level)
969 ehca_dmp(bad_send_wqe_v, 32, "qp_num=%x bad_wqe", qp_num);
970 squeue = &my_qp->ipz_squeue;
971 if (ipz_queue_abs_to_offset(squeue, (u64)bad_send_wqe_p, &q_ofs)) {
972 ehca_err(&shca->ib_device, "failed to get wqe offset qp_num=%x"
973 " bad_send_wqe_p=%p", qp_num, bad_send_wqe_p);
974 return -EFAULT;
975 }
976
977 /* loop sets wqe's purge bit */
978 wqe = (struct ehca_wqe *)ipz_qeit_calc(squeue, q_ofs);
979 *bad_wqe_cnt = 0;
980 while (wqe->optype != 0xff && wqe->wqef != 0xff) {
981 if (ehca_debug_level)
982 ehca_dmp(wqe, 32, "qp_num=%x wqe", qp_num);
983 wqe->nr_of_data_seg = 0; /* suppress data access */
984 wqe->wqef = WQEF_PURGE; /* WQE to be purged */
985 q_ofs = ipz_queue_advance_offset(squeue, q_ofs);
986 wqe = (struct ehca_wqe *)ipz_qeit_calc(squeue, q_ofs);
987 *bad_wqe_cnt = (*bad_wqe_cnt)+1;
988 }
989 /*
990 * bad wqe will be reprocessed and ignored when pol_cq() is called,
991 * i.e. nr of wqes with flush error status is one less
992 */
993 ehca_dbg(&shca->ib_device, "qp_num=%x flusherr_wqe_cnt=%x",
994 qp_num, (*bad_wqe_cnt)-1);
995 wqe->wqef = 0;
996
997 return 0;
998 }
999
1000 /*
1001 * internal_modify_qp with circumvention to handle aqp0 properly
1002 * smi_reset2init indicates if this is an internal reset-to-init-call for
1003 * smi. This flag must always be zero if called from ehca_modify_qp()!
1004 * This internal func was intorduced to avoid recursion of ehca_modify_qp()!
1005 */
1006 static int internal_modify_qp(struct ib_qp *ibqp,
1007 struct ib_qp_attr *attr,
1008 int attr_mask, int smi_reset2init)
1009 {
1010 enum ib_qp_state qp_cur_state, qp_new_state;
1011 int cnt, qp_attr_idx, ret = 0;
1012 enum ib_qp_statetrans statetrans;
1013 struct hcp_modify_qp_control_block *mqpcb;
1014 struct ehca_qp *my_qp = container_of(ibqp, struct ehca_qp, ib_qp);
1015 struct ehca_shca *shca =
1016 container_of(ibqp->pd->device, struct ehca_shca, ib_device);
1017 u64 update_mask;
1018 u64 h_ret;
1019 int bad_wqe_cnt = 0;
1020 int squeue_locked = 0;
1021 unsigned long flags = 0;
1022
1023 /* do query_qp to obtain current attr values */
1024 mqpcb = ehca_alloc_fw_ctrlblock(GFP_ATOMIC);
1025 if (!mqpcb) {
1026 ehca_err(ibqp->device, "Could not get zeroed page for mqpcb "
1027 "ehca_qp=%p qp_num=%x ", my_qp, ibqp->qp_num);
1028 return -ENOMEM;
1029 }
1030
1031 h_ret = hipz_h_query_qp(shca->ipz_hca_handle,
1032 my_qp->ipz_qp_handle,
1033 &my_qp->pf,
1034 mqpcb, my_qp->galpas.kernel);
1035 if (h_ret != H_SUCCESS) {
1036 ehca_err(ibqp->device, "hipz_h_query_qp() failed "
1037 "ehca_qp=%p qp_num=%x h_ret=%li",
1038 my_qp, ibqp->qp_num, h_ret);
1039 ret = ehca2ib_return_code(h_ret);
1040 goto modify_qp_exit1;
1041 }
1042
1043 qp_cur_state = ehca2ib_qp_state(mqpcb->qp_state);
1044
1045 if (qp_cur_state == -EINVAL) { /* invalid qp state */
1046 ret = -EINVAL;
1047 ehca_err(ibqp->device, "Invalid current ehca_qp_state=%x "
1048 "ehca_qp=%p qp_num=%x",
1049 mqpcb->qp_state, my_qp, ibqp->qp_num);
1050 goto modify_qp_exit1;
1051 }
1052 /*
1053 * circumvention to set aqp0 initial state to init
1054 * as expected by IB spec
1055 */
1056 if (smi_reset2init == 0 &&
1057 ibqp->qp_type == IB_QPT_SMI &&
1058 qp_cur_state == IB_QPS_RESET &&
1059 (attr_mask & IB_QP_STATE) &&
1060 attr->qp_state == IB_QPS_INIT) { /* RESET -> INIT */
1061 struct ib_qp_attr smiqp_attr = {
1062 .qp_state = IB_QPS_INIT,
1063 .port_num = my_qp->init_attr.port_num,
1064 .pkey_index = 0,
1065 .qkey = 0
1066 };
1067 int smiqp_attr_mask = IB_QP_STATE | IB_QP_PORT |
1068 IB_QP_PKEY_INDEX | IB_QP_QKEY;
1069 int smirc = internal_modify_qp(
1070 ibqp, &smiqp_attr, smiqp_attr_mask, 1);
1071 if (smirc) {
1072 ehca_err(ibqp->device, "SMI RESET -> INIT failed. "
1073 "ehca_modify_qp() rc=%i", smirc);
1074 ret = H_PARAMETER;
1075 goto modify_qp_exit1;
1076 }
1077 qp_cur_state = IB_QPS_INIT;
1078 ehca_dbg(ibqp->device, "SMI RESET -> INIT succeeded");
1079 }
1080 /* is transmitted current state equal to "real" current state */
1081 if ((attr_mask & IB_QP_CUR_STATE) &&
1082 qp_cur_state != attr->cur_qp_state) {
1083 ret = -EINVAL;
1084 ehca_err(ibqp->device,
1085 "Invalid IB_QP_CUR_STATE attr->curr_qp_state=%x <>"
1086 " actual cur_qp_state=%x. ehca_qp=%p qp_num=%x",
1087 attr->cur_qp_state, qp_cur_state, my_qp, ibqp->qp_num);
1088 goto modify_qp_exit1;
1089 }
1090
1091 ehca_dbg(ibqp->device, "ehca_qp=%p qp_num=%x current qp_state=%x "
1092 "new qp_state=%x attribute_mask=%x",
1093 my_qp, ibqp->qp_num, qp_cur_state, attr->qp_state, attr_mask);
1094
1095 qp_new_state = attr_mask & IB_QP_STATE ? attr->qp_state : qp_cur_state;
1096 if (!smi_reset2init &&
1097 !ib_modify_qp_is_ok(qp_cur_state, qp_new_state, ibqp->qp_type,
1098 attr_mask)) {
1099 ret = -EINVAL;
1100 ehca_err(ibqp->device,
1101 "Invalid qp transition new_state=%x cur_state=%x "
1102 "ehca_qp=%p qp_num=%x attr_mask=%x", qp_new_state,
1103 qp_cur_state, my_qp, ibqp->qp_num, attr_mask);
1104 goto modify_qp_exit1;
1105 }
1106
1107 mqpcb->qp_state = ib2ehca_qp_state(qp_new_state);
1108 if (mqpcb->qp_state)
1109 update_mask = EHCA_BMASK_SET(MQPCB_MASK_QP_STATE, 1);
1110 else {
1111 ret = -EINVAL;
1112 ehca_err(ibqp->device, "Invalid new qp state=%x "
1113 "ehca_qp=%p qp_num=%x",
1114 qp_new_state, my_qp, ibqp->qp_num);
1115 goto modify_qp_exit1;
1116 }
1117
1118 /* retrieve state transition struct to get req and opt attrs */
1119 statetrans = get_modqp_statetrans(qp_cur_state, qp_new_state);
1120 if (statetrans < 0) {
1121 ret = -EINVAL;
1122 ehca_err(ibqp->device, "<INVALID STATE CHANGE> qp_cur_state=%x "
1123 "new_qp_state=%x State_xsition=%x ehca_qp=%p "
1124 "qp_num=%x", qp_cur_state, qp_new_state,
1125 statetrans, my_qp, ibqp->qp_num);
1126 goto modify_qp_exit1;
1127 }
1128
1129 qp_attr_idx = ib2ehcaqptype(ibqp->qp_type);
1130
1131 if (qp_attr_idx < 0) {
1132 ret = qp_attr_idx;
1133 ehca_err(ibqp->device,
1134 "Invalid QP type=%x ehca_qp=%p qp_num=%x",
1135 ibqp->qp_type, my_qp, ibqp->qp_num);
1136 goto modify_qp_exit1;
1137 }
1138
1139 ehca_dbg(ibqp->device,
1140 "ehca_qp=%p qp_num=%x <VALID STATE CHANGE> qp_state_xsit=%x",
1141 my_qp, ibqp->qp_num, statetrans);
1142
1143 /* eHCA2 rev2 and higher require the SEND_GRH_FLAG to be set
1144 * in non-LL UD QPs.
1145 */
1146 if ((my_qp->qp_type == IB_QPT_UD) &&
1147 (my_qp->ext_type != EQPT_LLQP) &&
1148 (statetrans == IB_QPST_INIT2RTR) &&
1149 (shca->hw_level >= 0x22)) {
1150 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_SEND_GRH_FLAG, 1);
1151 mqpcb->send_grh_flag = 1;
1152 }
1153
1154 /* sqe -> rts: set purge bit of bad wqe before actual trans */
1155 if ((my_qp->qp_type == IB_QPT_UD ||
1156 my_qp->qp_type == IB_QPT_GSI ||
1157 my_qp->qp_type == IB_QPT_SMI) &&
1158 statetrans == IB_QPST_SQE2RTS) {
1159 /* mark next free wqe if kernel */
1160 if (!ibqp->uobject) {
1161 struct ehca_wqe *wqe;
1162 /* lock send queue */
1163 spin_lock_irqsave(&my_qp->spinlock_s, flags);
1164 squeue_locked = 1;
1165 /* mark next free wqe */
1166 wqe = (struct ehca_wqe *)
1167 ipz_qeit_get(&my_qp->ipz_squeue);
1168 wqe->optype = wqe->wqef = 0xff;
1169 ehca_dbg(ibqp->device, "qp_num=%x next_free_wqe=%p",
1170 ibqp->qp_num, wqe);
1171 }
1172 ret = prepare_sqe_rts(my_qp, shca, &bad_wqe_cnt);
1173 if (ret) {
1174 ehca_err(ibqp->device, "prepare_sqe_rts() failed "
1175 "ehca_qp=%p qp_num=%x ret=%i",
1176 my_qp, ibqp->qp_num, ret);
1177 goto modify_qp_exit2;
1178 }
1179 }
1180
1181 /*
1182 * enable RDMA_Atomic_Control if reset->init und reliable con
1183 * this is necessary since gen2 does not provide that flag,
1184 * but pHyp requires it
1185 */
1186 if (statetrans == IB_QPST_RESET2INIT &&
1187 (ibqp->qp_type == IB_QPT_RC || ibqp->qp_type == IB_QPT_UC)) {
1188 mqpcb->rdma_atomic_ctrl = 3;
1189 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_RDMA_ATOMIC_CTRL, 1);
1190 }
1191 /* circ. pHyp requires #RDMA/Atomic Resp Res for UC INIT -> RTR */
1192 if (statetrans == IB_QPST_INIT2RTR &&
1193 (ibqp->qp_type == IB_QPT_UC) &&
1194 !(attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)) {
1195 mqpcb->rdma_nr_atomic_resp_res = 1; /* default to 1 */
1196 update_mask |=
1197 EHCA_BMASK_SET(MQPCB_MASK_RDMA_NR_ATOMIC_RESP_RES, 1);
1198 }
1199
1200 if (attr_mask & IB_QP_PKEY_INDEX) {
1201 if (attr->pkey_index >= 16) {
1202 ret = -EINVAL;
1203 ehca_err(ibqp->device, "Invalid pkey_index=%x. "
1204 "ehca_qp=%p qp_num=%x max_pkey_index=f",
1205 attr->pkey_index, my_qp, ibqp->qp_num);
1206 goto modify_qp_exit2;
1207 }
1208 mqpcb->prim_p_key_idx = attr->pkey_index;
1209 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_PRIM_P_KEY_IDX, 1);
1210 }
1211 if (attr_mask & IB_QP_PORT) {
1212 struct ehca_sport *sport;
1213 struct ehca_qp *aqp1;
1214 if (attr->port_num < 1 || attr->port_num > shca->num_ports) {
1215 ret = -EINVAL;
1216 ehca_err(ibqp->device, "Invalid port=%x. "
1217 "ehca_qp=%p qp_num=%x num_ports=%x",
1218 attr->port_num, my_qp, ibqp->qp_num,
1219 shca->num_ports);
1220 goto modify_qp_exit2;
1221 }
1222 sport = &shca->sport[attr->port_num - 1];
1223 if (!sport->ibqp_sqp[IB_QPT_GSI]) {
1224 /* should not occur */
1225 ret = -EFAULT;
1226 ehca_err(ibqp->device, "AQP1 was not created for "
1227 "port=%x", attr->port_num);
1228 goto modify_qp_exit2;
1229 }
1230 aqp1 = container_of(sport->ibqp_sqp[IB_QPT_GSI],
1231 struct ehca_qp, ib_qp);
1232 if (ibqp->qp_type != IB_QPT_GSI &&
1233 ibqp->qp_type != IB_QPT_SMI &&
1234 aqp1->mod_qp_parm) {
1235 /*
1236 * firmware will reject this modify_qp() because
1237 * port is not activated/initialized fully
1238 */
1239 ret = -EFAULT;
1240 ehca_warn(ibqp->device, "Couldn't modify qp port=%x: "
1241 "either port is being activated (try again) "
1242 "or cabling issue", attr->port_num);
1243 goto modify_qp_exit2;
1244 }
1245 mqpcb->prim_phys_port = attr->port_num;
1246 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_PRIM_PHYS_PORT, 1);
1247 }
1248 if (attr_mask & IB_QP_QKEY) {
1249 mqpcb->qkey = attr->qkey;
1250 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_QKEY, 1);
1251 }
1252 if (attr_mask & IB_QP_AV) {
1253 mqpcb->dlid = attr->ah_attr.dlid;
1254 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_DLID, 1);
1255 mqpcb->source_path_bits = attr->ah_attr.src_path_bits;
1256 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_SOURCE_PATH_BITS, 1);
1257 mqpcb->service_level = attr->ah_attr.sl;
1258 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_SERVICE_LEVEL, 1);
1259
1260 if (ehca_calc_ipd(shca, mqpcb->prim_phys_port,
1261 attr->ah_attr.static_rate,
1262 &mqpcb->max_static_rate)) {
1263 ret = -EINVAL;
1264 goto modify_qp_exit2;
1265 }
1266 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_MAX_STATIC_RATE, 1);
1267
1268 /*
1269 * Always supply the GRH flag, even if it's zero, to give the
1270 * hypervisor a clear "yes" or "no" instead of a "perhaps"
1271 */
1272 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_SEND_GRH_FLAG, 1);
1273
1274 /*
1275 * only if GRH is TRUE we might consider SOURCE_GID_IDX
1276 * and DEST_GID otherwise phype will return H_ATTR_PARM!!!
1277 */
1278 if (attr->ah_attr.ah_flags == IB_AH_GRH) {
1279 mqpcb->send_grh_flag = 1;
1280
1281 mqpcb->source_gid_idx = attr->ah_attr.grh.sgid_index;
1282 update_mask |=
1283 EHCA_BMASK_SET(MQPCB_MASK_SOURCE_GID_IDX, 1);
1284
1285 for (cnt = 0; cnt < 16; cnt++)
1286 mqpcb->dest_gid.byte[cnt] =
1287 attr->ah_attr.grh.dgid.raw[cnt];
1288
1289 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_DEST_GID, 1);
1290 mqpcb->flow_label = attr->ah_attr.grh.flow_label;
1291 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_FLOW_LABEL, 1);
1292 mqpcb->hop_limit = attr->ah_attr.grh.hop_limit;
1293 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_HOP_LIMIT, 1);
1294 mqpcb->traffic_class = attr->ah_attr.grh.traffic_class;
1295 update_mask |=
1296 EHCA_BMASK_SET(MQPCB_MASK_TRAFFIC_CLASS, 1);
1297 }
1298 }
1299
1300 if (attr_mask & IB_QP_PATH_MTU) {
1301 /* store ld(MTU) */
1302 my_qp->mtu_shift = attr->path_mtu + 7;
1303 mqpcb->path_mtu = attr->path_mtu;
1304 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_PATH_MTU, 1);
1305 }
1306 if (attr_mask & IB_QP_TIMEOUT) {
1307 mqpcb->timeout = attr->timeout;
1308 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_TIMEOUT, 1);
1309 }
1310 if (attr_mask & IB_QP_RETRY_CNT) {
1311 mqpcb->retry_count = attr->retry_cnt;
1312 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_RETRY_COUNT, 1);
1313 }
1314 if (attr_mask & IB_QP_RNR_RETRY) {
1315 mqpcb->rnr_retry_count = attr->rnr_retry;
1316 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_RNR_RETRY_COUNT, 1);
1317 }
1318 if (attr_mask & IB_QP_RQ_PSN) {
1319 mqpcb->receive_psn = attr->rq_psn;
1320 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_RECEIVE_PSN, 1);
1321 }
1322 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
1323 mqpcb->rdma_nr_atomic_resp_res = attr->max_dest_rd_atomic < 3 ?
1324 attr->max_dest_rd_atomic : 2;
1325 update_mask |=
1326 EHCA_BMASK_SET(MQPCB_MASK_RDMA_NR_ATOMIC_RESP_RES, 1);
1327 }
1328 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
1329 mqpcb->rdma_atomic_outst_dest_qp = attr->max_rd_atomic < 3 ?
1330 attr->max_rd_atomic : 2;
1331 update_mask |=
1332 EHCA_BMASK_SET
1333 (MQPCB_MASK_RDMA_ATOMIC_OUTST_DEST_QP, 1);
1334 }
1335 if (attr_mask & IB_QP_ALT_PATH) {
1336 if (attr->alt_port_num < 1
1337 || attr->alt_port_num > shca->num_ports) {
1338 ret = -EINVAL;
1339 ehca_err(ibqp->device, "Invalid alt_port=%x. "
1340 "ehca_qp=%p qp_num=%x num_ports=%x",
1341 attr->alt_port_num, my_qp, ibqp->qp_num,
1342 shca->num_ports);
1343 goto modify_qp_exit2;
1344 }
1345 mqpcb->alt_phys_port = attr->alt_port_num;
1346
1347 if (attr->alt_pkey_index >= 16) {
1348 ret = -EINVAL;
1349 ehca_err(ibqp->device, "Invalid alt_pkey_index=%x. "
1350 "ehca_qp=%p qp_num=%x max_pkey_index=f",
1351 attr->pkey_index, my_qp, ibqp->qp_num);
1352 goto modify_qp_exit2;
1353 }
1354 mqpcb->alt_p_key_idx = attr->alt_pkey_index;
1355
1356 mqpcb->timeout_al = attr->alt_timeout;
1357 mqpcb->dlid_al = attr->alt_ah_attr.dlid;
1358 mqpcb->source_path_bits_al = attr->alt_ah_attr.src_path_bits;
1359 mqpcb->service_level_al = attr->alt_ah_attr.sl;
1360
1361 if (ehca_calc_ipd(shca, mqpcb->alt_phys_port,
1362 attr->alt_ah_attr.static_rate,
1363 &mqpcb->max_static_rate_al)) {
1364 ret = -EINVAL;
1365 goto modify_qp_exit2;
1366 }
1367
1368 /* OpenIB doesn't support alternate retry counts - copy them */
1369 mqpcb->retry_count_al = mqpcb->retry_count;
1370 mqpcb->rnr_retry_count_al = mqpcb->rnr_retry_count;
1371
1372 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_ALT_PHYS_PORT, 1)
1373 | EHCA_BMASK_SET(MQPCB_MASK_ALT_P_KEY_IDX, 1)
1374 | EHCA_BMASK_SET(MQPCB_MASK_TIMEOUT_AL, 1)
1375 | EHCA_BMASK_SET(MQPCB_MASK_DLID_AL, 1)
1376 | EHCA_BMASK_SET(MQPCB_MASK_SOURCE_PATH_BITS_AL, 1)
1377 | EHCA_BMASK_SET(MQPCB_MASK_SERVICE_LEVEL_AL, 1)
1378 | EHCA_BMASK_SET(MQPCB_MASK_MAX_STATIC_RATE_AL, 1)
1379 | EHCA_BMASK_SET(MQPCB_MASK_RETRY_COUNT_AL, 1)
1380 | EHCA_BMASK_SET(MQPCB_MASK_RNR_RETRY_COUNT_AL, 1);
1381
1382 /*
1383 * Always supply the GRH flag, even if it's zero, to give the
1384 * hypervisor a clear "yes" or "no" instead of a "perhaps"
1385 */
1386 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_SEND_GRH_FLAG_AL, 1);
1387
1388 /*
1389 * only if GRH is TRUE we might consider SOURCE_GID_IDX
1390 * and DEST_GID otherwise phype will return H_ATTR_PARM!!!
1391 */
1392 if (attr->alt_ah_attr.ah_flags == IB_AH_GRH) {
1393 mqpcb->send_grh_flag_al = 1;
1394
1395 for (cnt = 0; cnt < 16; cnt++)
1396 mqpcb->dest_gid_al.byte[cnt] =
1397 attr->alt_ah_attr.grh.dgid.raw[cnt];
1398 mqpcb->source_gid_idx_al =
1399 attr->alt_ah_attr.grh.sgid_index;
1400 mqpcb->flow_label_al = attr->alt_ah_attr.grh.flow_label;
1401 mqpcb->hop_limit_al = attr->alt_ah_attr.grh.hop_limit;
1402 mqpcb->traffic_class_al =
1403 attr->alt_ah_attr.grh.traffic_class;
1404
1405 update_mask |=
1406 EHCA_BMASK_SET(MQPCB_MASK_SOURCE_GID_IDX_AL, 1)
1407 | EHCA_BMASK_SET(MQPCB_MASK_DEST_GID_AL, 1)
1408 | EHCA_BMASK_SET(MQPCB_MASK_FLOW_LABEL_AL, 1)
1409 | EHCA_BMASK_SET(MQPCB_MASK_HOP_LIMIT_AL, 1) |
1410 EHCA_BMASK_SET(MQPCB_MASK_TRAFFIC_CLASS_AL, 1);
1411 }
1412 }
1413
1414 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
1415 mqpcb->min_rnr_nak_timer_field = attr->min_rnr_timer;
1416 update_mask |=
1417 EHCA_BMASK_SET(MQPCB_MASK_MIN_RNR_NAK_TIMER_FIELD, 1);
1418 }
1419
1420 if (attr_mask & IB_QP_SQ_PSN) {
1421 mqpcb->send_psn = attr->sq_psn;
1422 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_SEND_PSN, 1);
1423 }
1424
1425 if (attr_mask & IB_QP_DEST_QPN) {
1426 mqpcb->dest_qp_nr = attr->dest_qp_num;
1427 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_DEST_QP_NR, 1);
1428 }
1429
1430 if (attr_mask & IB_QP_PATH_MIG_STATE) {
1431 if (attr->path_mig_state != IB_MIG_REARM
1432 && attr->path_mig_state != IB_MIG_MIGRATED) {
1433 ret = -EINVAL;
1434 ehca_err(ibqp->device, "Invalid mig_state=%x",
1435 attr->path_mig_state);
1436 goto modify_qp_exit2;
1437 }
1438 mqpcb->path_migration_state = attr->path_mig_state + 1;
1439 update_mask |=
1440 EHCA_BMASK_SET(MQPCB_MASK_PATH_MIGRATION_STATE, 1);
1441 }
1442
1443 if (attr_mask & IB_QP_CAP) {
1444 mqpcb->max_nr_outst_send_wr = attr->cap.max_send_wr+1;
1445 update_mask |=
1446 EHCA_BMASK_SET(MQPCB_MASK_MAX_NR_OUTST_SEND_WR, 1);
1447 mqpcb->max_nr_outst_recv_wr = attr->cap.max_recv_wr+1;
1448 update_mask |=
1449 EHCA_BMASK_SET(MQPCB_MASK_MAX_NR_OUTST_RECV_WR, 1);
1450 /* no support for max_send/recv_sge yet */
1451 }
1452
1453 if (ehca_debug_level)
1454 ehca_dmp(mqpcb, 4*70, "qp_num=%x", ibqp->qp_num);
1455
1456 h_ret = hipz_h_modify_qp(shca->ipz_hca_handle,
1457 my_qp->ipz_qp_handle,
1458 &my_qp->pf,
1459 update_mask,
1460 mqpcb, my_qp->galpas.kernel);
1461
1462 if (h_ret != H_SUCCESS) {
1463 ret = ehca2ib_return_code(h_ret);
1464 ehca_err(ibqp->device, "hipz_h_modify_qp() failed h_ret=%li "
1465 "ehca_qp=%p qp_num=%x", h_ret, my_qp, ibqp->qp_num);
1466 goto modify_qp_exit2;
1467 }
1468
1469 if ((my_qp->qp_type == IB_QPT_UD ||
1470 my_qp->qp_type == IB_QPT_GSI ||
1471 my_qp->qp_type == IB_QPT_SMI) &&
1472 statetrans == IB_QPST_SQE2RTS) {
1473 /* doorbell to reprocessing wqes */
1474 iosync(); /* serialize GAL register access */
1475 hipz_update_sqa(my_qp, bad_wqe_cnt-1);
1476 ehca_gen_dbg("doorbell for %x wqes", bad_wqe_cnt);
1477 }
1478
1479 if (statetrans == IB_QPST_RESET2INIT ||
1480 statetrans == IB_QPST_INIT2INIT) {
1481 mqpcb->qp_enable = 1;
1482 mqpcb->qp_state = EHCA_QPS_INIT;
1483 update_mask = 0;
1484 update_mask = EHCA_BMASK_SET(MQPCB_MASK_QP_ENABLE, 1);
1485
1486 h_ret = hipz_h_modify_qp(shca->ipz_hca_handle,
1487 my_qp->ipz_qp_handle,
1488 &my_qp->pf,
1489 update_mask,
1490 mqpcb,
1491 my_qp->galpas.kernel);
1492
1493 if (h_ret != H_SUCCESS) {
1494 ret = ehca2ib_return_code(h_ret);
1495 ehca_err(ibqp->device, "ENABLE in context of "
1496 "RESET_2_INIT failed! Maybe you didn't get "
1497 "a LID h_ret=%li ehca_qp=%p qp_num=%x",
1498 h_ret, my_qp, ibqp->qp_num);
1499 goto modify_qp_exit2;
1500 }
1501 }
1502
1503 if (statetrans == IB_QPST_ANY2RESET) {
1504 ipz_qeit_reset(&my_qp->ipz_rqueue);
1505 ipz_qeit_reset(&my_qp->ipz_squeue);
1506 }
1507
1508 if (attr_mask & IB_QP_QKEY)
1509 my_qp->qkey = attr->qkey;
1510
1511 modify_qp_exit2:
1512 if (squeue_locked) { /* this means: sqe -> rts */
1513 spin_unlock_irqrestore(&my_qp->spinlock_s, flags);
1514 my_qp->sqerr_purgeflag = 1;
1515 }
1516
1517 modify_qp_exit1:
1518 ehca_free_fw_ctrlblock(mqpcb);
1519
1520 return ret;
1521 }
1522
1523 int ehca_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask,
1524 struct ib_udata *udata)
1525 {
1526 struct ehca_shca *shca = container_of(ibqp->device, struct ehca_shca,
1527 ib_device);
1528 struct ehca_qp *my_qp = container_of(ibqp, struct ehca_qp, ib_qp);
1529 struct ehca_pd *my_pd = container_of(my_qp->ib_qp.pd, struct ehca_pd,
1530 ib_pd);
1531 u32 cur_pid = current->tgid;
1532
1533 if (my_pd->ib_pd.uobject && my_pd->ib_pd.uobject->context &&
1534 my_pd->ownpid != cur_pid) {
1535 ehca_err(ibqp->pd->device, "Invalid caller pid=%x ownpid=%x",
1536 cur_pid, my_pd->ownpid);
1537 return -EINVAL;
1538 }
1539
1540 /* The if-block below caches qp_attr to be modified for GSI and SMI
1541 * qps during the initialization by ib_mad. When the respective port
1542 * is activated, ie we got an event PORT_ACTIVE, we'll replay the
1543 * cached modify calls sequence, see ehca_recover_sqs() below.
1544 * Why that is required:
1545 * 1) If one port is connected, older code requires that port one
1546 * to be connected and module option nr_ports=1 to be given by
1547 * user, which is very inconvenient for end user.
1548 * 2) Firmware accepts modify_qp() only if respective port has become
1549 * active. Older code had a wait loop of 30sec create_qp()/
1550 * define_aqp1(), which is not appropriate in practice. This
1551 * code now removes that wait loop, see define_aqp1(), and always
1552 * reports all ports to ib_mad resp. users. Only activated ports
1553 * will then usable for the users.
1554 */
1555 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI) {
1556 int port = my_qp->init_attr.port_num;
1557 struct ehca_sport *sport = &shca->sport[port - 1];
1558 unsigned long flags;
1559 spin_lock_irqsave(&sport->mod_sqp_lock, flags);
1560 /* cache qp_attr only during init */
1561 if (my_qp->mod_qp_parm) {
1562 struct ehca_mod_qp_parm *p;
1563 if (my_qp->mod_qp_parm_idx >= EHCA_MOD_QP_PARM_MAX) {
1564 ehca_err(&shca->ib_device,
1565 "mod_qp_parm overflow state=%x port=%x"
1566 " type=%x", attr->qp_state,
1567 my_qp->init_attr.port_num,
1568 ibqp->qp_type);
1569 spin_unlock_irqrestore(&sport->mod_sqp_lock,
1570 flags);
1571 return -EINVAL;
1572 }
1573 p = &my_qp->mod_qp_parm[my_qp->mod_qp_parm_idx];
1574 p->mask = attr_mask;
1575 p->attr = *attr;
1576 my_qp->mod_qp_parm_idx++;
1577 ehca_dbg(&shca->ib_device,
1578 "Saved qp_attr for state=%x port=%x type=%x",
1579 attr->qp_state, my_qp->init_attr.port_num,
1580 ibqp->qp_type);
1581 spin_unlock_irqrestore(&sport->mod_sqp_lock, flags);
1582 return 0;
1583 }
1584 spin_unlock_irqrestore(&sport->mod_sqp_lock, flags);
1585 }
1586
1587 return internal_modify_qp(ibqp, attr, attr_mask, 0);
1588 }
1589
1590 void ehca_recover_sqp(struct ib_qp *sqp)
1591 {
1592 struct ehca_qp *my_sqp = container_of(sqp, struct ehca_qp, ib_qp);
1593 int port = my_sqp->init_attr.port_num;
1594 struct ib_qp_attr attr;
1595 struct ehca_mod_qp_parm *qp_parm;
1596 int i, qp_parm_idx, ret;
1597 unsigned long flags, wr_cnt;
1598
1599 if (!my_sqp->mod_qp_parm)
1600 return;
1601 ehca_dbg(sqp->device, "SQP port=%x qp_num=%x", port, sqp->qp_num);
1602
1603 qp_parm = my_sqp->mod_qp_parm;
1604 qp_parm_idx = my_sqp->mod_qp_parm_idx;
1605 for (i = 0; i < qp_parm_idx; i++) {
1606 attr = qp_parm[i].attr;
1607 ret = internal_modify_qp(sqp, &attr, qp_parm[i].mask, 0);
1608 if (ret) {
1609 ehca_err(sqp->device, "Could not modify SQP port=%x "
1610 "qp_num=%x ret=%x", port, sqp->qp_num, ret);
1611 goto free_qp_parm;
1612 }
1613 ehca_dbg(sqp->device, "SQP port=%x qp_num=%x in state=%x",
1614 port, sqp->qp_num, attr.qp_state);
1615 }
1616
1617 /* re-trigger posted recv wrs */
1618 wr_cnt = my_sqp->ipz_rqueue.current_q_offset /
1619 my_sqp->ipz_rqueue.qe_size;
1620 if (wr_cnt) {
1621 spin_lock_irqsave(&my_sqp->spinlock_r, flags);
1622 hipz_update_rqa(my_sqp, wr_cnt);
1623 spin_unlock_irqrestore(&my_sqp->spinlock_r, flags);
1624 ehca_dbg(sqp->device, "doorbell port=%x qp_num=%x wr_cnt=%lx",
1625 port, sqp->qp_num, wr_cnt);
1626 }
1627
1628 free_qp_parm:
1629 kfree(qp_parm);
1630 /* this prevents subsequent calls to modify_qp() to cache qp_attr */
1631 my_sqp->mod_qp_parm = NULL;
1632 }
1633
1634 int ehca_query_qp(struct ib_qp *qp,
1635 struct ib_qp_attr *qp_attr,
1636 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
1637 {
1638 struct ehca_qp *my_qp = container_of(qp, struct ehca_qp, ib_qp);
1639 struct ehca_pd *my_pd = container_of(my_qp->ib_qp.pd, struct ehca_pd,
1640 ib_pd);
1641 struct ehca_shca *shca = container_of(qp->device, struct ehca_shca,
1642 ib_device);
1643 struct ipz_adapter_handle adapter_handle = shca->ipz_hca_handle;
1644 struct hcp_modify_qp_control_block *qpcb;
1645 u32 cur_pid = current->tgid;
1646 int cnt, ret = 0;
1647 u64 h_ret;
1648
1649 if (my_pd->ib_pd.uobject && my_pd->ib_pd.uobject->context &&
1650 my_pd->ownpid != cur_pid) {
1651 ehca_err(qp->device, "Invalid caller pid=%x ownpid=%x",
1652 cur_pid, my_pd->ownpid);
1653 return -EINVAL;
1654 }
1655
1656 if (qp_attr_mask & QP_ATTR_QUERY_NOT_SUPPORTED) {
1657 ehca_err(qp->device, "Invalid attribute mask "
1658 "ehca_qp=%p qp_num=%x qp_attr_mask=%x ",
1659 my_qp, qp->qp_num, qp_attr_mask);
1660 return -EINVAL;
1661 }
1662
1663 qpcb = ehca_alloc_fw_ctrlblock(GFP_KERNEL);
1664 if (!qpcb) {
1665 ehca_err(qp->device, "Out of memory for qpcb "
1666 "ehca_qp=%p qp_num=%x", my_qp, qp->qp_num);
1667 return -ENOMEM;
1668 }
1669
1670 h_ret = hipz_h_query_qp(adapter_handle,
1671 my_qp->ipz_qp_handle,
1672 &my_qp->pf,
1673 qpcb, my_qp->galpas.kernel);
1674
1675 if (h_ret != H_SUCCESS) {
1676 ret = ehca2ib_return_code(h_ret);
1677 ehca_err(qp->device, "hipz_h_query_qp() failed "
1678 "ehca_qp=%p qp_num=%x h_ret=%li",
1679 my_qp, qp->qp_num, h_ret);
1680 goto query_qp_exit1;
1681 }
1682
1683 qp_attr->cur_qp_state = ehca2ib_qp_state(qpcb->qp_state);
1684 qp_attr->qp_state = qp_attr->cur_qp_state;
1685
1686 if (qp_attr->cur_qp_state == -EINVAL) {
1687 ret = -EINVAL;
1688 ehca_err(qp->device, "Got invalid ehca_qp_state=%x "
1689 "ehca_qp=%p qp_num=%x",
1690 qpcb->qp_state, my_qp, qp->qp_num);
1691 goto query_qp_exit1;
1692 }
1693
1694 if (qp_attr->qp_state == IB_QPS_SQD)
1695 qp_attr->sq_draining = 1;
1696
1697 qp_attr->qkey = qpcb->qkey;
1698 qp_attr->path_mtu = qpcb->path_mtu;
1699 qp_attr->path_mig_state = qpcb->path_migration_state - 1;
1700 qp_attr->rq_psn = qpcb->receive_psn;
1701 qp_attr->sq_psn = qpcb->send_psn;
1702 qp_attr->min_rnr_timer = qpcb->min_rnr_nak_timer_field;
1703 qp_attr->cap.max_send_wr = qpcb->max_nr_outst_send_wr-1;
1704 qp_attr->cap.max_recv_wr = qpcb->max_nr_outst_recv_wr-1;
1705 /* UD_AV CIRCUMVENTION */
1706 if (my_qp->qp_type == IB_QPT_UD) {
1707 qp_attr->cap.max_send_sge =
1708 qpcb->actual_nr_sges_in_sq_wqe - 2;
1709 qp_attr->cap.max_recv_sge =
1710 qpcb->actual_nr_sges_in_rq_wqe - 2;
1711 } else {
1712 qp_attr->cap.max_send_sge =
1713 qpcb->actual_nr_sges_in_sq_wqe;
1714 qp_attr->cap.max_recv_sge =
1715 qpcb->actual_nr_sges_in_rq_wqe;
1716 }
1717
1718 qp_attr->cap.max_inline_data = my_qp->sq_max_inline_data_size;
1719 qp_attr->dest_qp_num = qpcb->dest_qp_nr;
1720
1721 qp_attr->pkey_index =
1722 EHCA_BMASK_GET(MQPCB_PRIM_P_KEY_IDX, qpcb->prim_p_key_idx);
1723
1724 qp_attr->port_num =
1725 EHCA_BMASK_GET(MQPCB_PRIM_PHYS_PORT, qpcb->prim_phys_port);
1726
1727 qp_attr->timeout = qpcb->timeout;
1728 qp_attr->retry_cnt = qpcb->retry_count;
1729 qp_attr->rnr_retry = qpcb->rnr_retry_count;
1730
1731 qp_attr->alt_pkey_index =
1732 EHCA_BMASK_GET(MQPCB_PRIM_P_KEY_IDX, qpcb->alt_p_key_idx);
1733
1734 qp_attr->alt_port_num = qpcb->alt_phys_port;
1735 qp_attr->alt_timeout = qpcb->timeout_al;
1736
1737 qp_attr->max_dest_rd_atomic = qpcb->rdma_nr_atomic_resp_res;
1738 qp_attr->max_rd_atomic = qpcb->rdma_atomic_outst_dest_qp;
1739
1740 /* primary av */
1741 qp_attr->ah_attr.sl = qpcb->service_level;
1742
1743 if (qpcb->send_grh_flag) {
1744 qp_attr->ah_attr.ah_flags = IB_AH_GRH;
1745 }
1746
1747 qp_attr->ah_attr.static_rate = qpcb->max_static_rate;
1748 qp_attr->ah_attr.dlid = qpcb->dlid;
1749 qp_attr->ah_attr.src_path_bits = qpcb->source_path_bits;
1750 qp_attr->ah_attr.port_num = qp_attr->port_num;
1751
1752 /* primary GRH */
1753 qp_attr->ah_attr.grh.traffic_class = qpcb->traffic_class;
1754 qp_attr->ah_attr.grh.hop_limit = qpcb->hop_limit;
1755 qp_attr->ah_attr.grh.sgid_index = qpcb->source_gid_idx;
1756 qp_attr->ah_attr.grh.flow_label = qpcb->flow_label;
1757
1758 for (cnt = 0; cnt < 16; cnt++)
1759 qp_attr->ah_attr.grh.dgid.raw[cnt] =
1760 qpcb->dest_gid.byte[cnt];
1761
1762 /* alternate AV */
1763 qp_attr->alt_ah_attr.sl = qpcb->service_level_al;
1764 if (qpcb->send_grh_flag_al) {
1765 qp_attr->alt_ah_attr.ah_flags = IB_AH_GRH;
1766 }
1767
1768 qp_attr->alt_ah_attr.static_rate = qpcb->max_static_rate_al;
1769 qp_attr->alt_ah_attr.dlid = qpcb->dlid_al;
1770 qp_attr->alt_ah_attr.src_path_bits = qpcb->source_path_bits_al;
1771
1772 /* alternate GRH */
1773 qp_attr->alt_ah_attr.grh.traffic_class = qpcb->traffic_class_al;
1774 qp_attr->alt_ah_attr.grh.hop_limit = qpcb->hop_limit_al;
1775 qp_attr->alt_ah_attr.grh.sgid_index = qpcb->source_gid_idx_al;
1776 qp_attr->alt_ah_attr.grh.flow_label = qpcb->flow_label_al;
1777
1778 for (cnt = 0; cnt < 16; cnt++)
1779 qp_attr->alt_ah_attr.grh.dgid.raw[cnt] =
1780 qpcb->dest_gid_al.byte[cnt];
1781
1782 /* return init attributes given in ehca_create_qp */
1783 if (qp_init_attr)
1784 *qp_init_attr = my_qp->init_attr;
1785
1786 if (ehca_debug_level)
1787 ehca_dmp(qpcb, 4*70, "qp_num=%x", qp->qp_num);
1788
1789 query_qp_exit1:
1790 ehca_free_fw_ctrlblock(qpcb);
1791
1792 return ret;
1793 }
1794
1795 int ehca_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr,
1796 enum ib_srq_attr_mask attr_mask, struct ib_udata *udata)
1797 {
1798 struct ehca_qp *my_qp =
1799 container_of(ibsrq, struct ehca_qp, ib_srq);
1800 struct ehca_pd *my_pd =
1801 container_of(ibsrq->pd, struct ehca_pd, ib_pd);
1802 struct ehca_shca *shca =
1803 container_of(ibsrq->pd->device, struct ehca_shca, ib_device);
1804 struct hcp_modify_qp_control_block *mqpcb;
1805 u64 update_mask;
1806 u64 h_ret;
1807 int ret = 0;
1808
1809 u32 cur_pid = current->tgid;
1810 if (my_pd->ib_pd.uobject && my_pd->ib_pd.uobject->context &&
1811 my_pd->ownpid != cur_pid) {
1812 ehca_err(ibsrq->pd->device, "Invalid caller pid=%x ownpid=%x",
1813 cur_pid, my_pd->ownpid);
1814 return -EINVAL;
1815 }
1816
1817 mqpcb = ehca_alloc_fw_ctrlblock(GFP_KERNEL);
1818 if (!mqpcb) {
1819 ehca_err(ibsrq->device, "Could not get zeroed page for mqpcb "
1820 "ehca_qp=%p qp_num=%x ", my_qp, my_qp->real_qp_num);
1821 return -ENOMEM;
1822 }
1823
1824 update_mask = 0;
1825 if (attr_mask & IB_SRQ_LIMIT) {
1826 attr_mask &= ~IB_SRQ_LIMIT;
1827 update_mask |=
1828 EHCA_BMASK_SET(MQPCB_MASK_CURR_SRQ_LIMIT, 1)
1829 | EHCA_BMASK_SET(MQPCB_MASK_QP_AFF_ASYN_EV_LOG_REG, 1);
1830 mqpcb->curr_srq_limit =
1831 EHCA_BMASK_SET(MQPCB_CURR_SRQ_LIMIT, attr->srq_limit);
1832 mqpcb->qp_aff_asyn_ev_log_reg =
1833 EHCA_BMASK_SET(QPX_AAELOG_RESET_SRQ_LIMIT, 1);
1834 }
1835
1836 /* by now, all bits in attr_mask should have been cleared */
1837 if (attr_mask) {
1838 ehca_err(ibsrq->device, "invalid attribute mask bits set "
1839 "attr_mask=%x", attr_mask);
1840 ret = -EINVAL;
1841 goto modify_srq_exit0;
1842 }
1843
1844 if (ehca_debug_level)
1845 ehca_dmp(mqpcb, 4*70, "qp_num=%x", my_qp->real_qp_num);
1846
1847 h_ret = hipz_h_modify_qp(shca->ipz_hca_handle, my_qp->ipz_qp_handle,
1848 NULL, update_mask, mqpcb,
1849 my_qp->galpas.kernel);
1850
1851 if (h_ret != H_SUCCESS) {
1852 ret = ehca2ib_return_code(h_ret);
1853 ehca_err(ibsrq->device, "hipz_h_modify_qp() failed h_ret=%li "
1854 "ehca_qp=%p qp_num=%x",
1855 h_ret, my_qp, my_qp->real_qp_num);
1856 }
1857
1858 modify_srq_exit0:
1859 ehca_free_fw_ctrlblock(mqpcb);
1860
1861 return ret;
1862 }
1863
1864 int ehca_query_srq(struct ib_srq *srq, struct ib_srq_attr *srq_attr)
1865 {
1866 struct ehca_qp *my_qp = container_of(srq, struct ehca_qp, ib_srq);
1867 struct ehca_pd *my_pd = container_of(srq->pd, struct ehca_pd, ib_pd);
1868 struct ehca_shca *shca = container_of(srq->device, struct ehca_shca,
1869 ib_device);
1870 struct ipz_adapter_handle adapter_handle = shca->ipz_hca_handle;
1871 struct hcp_modify_qp_control_block *qpcb;
1872 u32 cur_pid = current->tgid;
1873 int ret = 0;
1874 u64 h_ret;
1875
1876 if (my_pd->ib_pd.uobject && my_pd->ib_pd.uobject->context &&
1877 my_pd->ownpid != cur_pid) {
1878 ehca_err(srq->device, "Invalid caller pid=%x ownpid=%x",
1879 cur_pid, my_pd->ownpid);
1880 return -EINVAL;
1881 }
1882
1883 qpcb = ehca_alloc_fw_ctrlblock(GFP_KERNEL);
1884 if (!qpcb) {
1885 ehca_err(srq->device, "Out of memory for qpcb "
1886 "ehca_qp=%p qp_num=%x", my_qp, my_qp->real_qp_num);
1887 return -ENOMEM;
1888 }
1889
1890 h_ret = hipz_h_query_qp(adapter_handle, my_qp->ipz_qp_handle,
1891 NULL, qpcb, my_qp->galpas.kernel);
1892
1893 if (h_ret != H_SUCCESS) {
1894 ret = ehca2ib_return_code(h_ret);
1895 ehca_err(srq->device, "hipz_h_query_qp() failed "
1896 "ehca_qp=%p qp_num=%x h_ret=%li",
1897 my_qp, my_qp->real_qp_num, h_ret);
1898 goto query_srq_exit1;
1899 }
1900
1901 srq_attr->max_wr = qpcb->max_nr_outst_recv_wr - 1;
1902 srq_attr->max_sge = 3;
1903 srq_attr->srq_limit = EHCA_BMASK_GET(
1904 MQPCB_CURR_SRQ_LIMIT, qpcb->curr_srq_limit);
1905
1906 if (ehca_debug_level)
1907 ehca_dmp(qpcb, 4*70, "qp_num=%x", my_qp->real_qp_num);
1908
1909 query_srq_exit1:
1910 ehca_free_fw_ctrlblock(qpcb);
1911
1912 return ret;
1913 }
1914
1915 static int internal_destroy_qp(struct ib_device *dev, struct ehca_qp *my_qp,
1916 struct ib_uobject *uobject)
1917 {
1918 struct ehca_shca *shca = container_of(dev, struct ehca_shca, ib_device);
1919 struct ehca_pd *my_pd = container_of(my_qp->ib_qp.pd, struct ehca_pd,
1920 ib_pd);
1921 struct ehca_sport *sport = &shca->sport[my_qp->init_attr.port_num - 1];
1922 u32 cur_pid = current->tgid;
1923 u32 qp_num = my_qp->real_qp_num;
1924 int ret;
1925 u64 h_ret;
1926 u8 port_num;
1927 enum ib_qp_type qp_type;
1928 unsigned long flags;
1929
1930 if (uobject) {
1931 if (my_qp->mm_count_galpa ||
1932 my_qp->mm_count_rqueue || my_qp->mm_count_squeue) {
1933 ehca_err(dev, "Resources still referenced in "
1934 "user space qp_num=%x", qp_num);
1935 return -EINVAL;
1936 }
1937 if (my_pd->ownpid != cur_pid) {
1938 ehca_err(dev, "Invalid caller pid=%x ownpid=%x",
1939 cur_pid, my_pd->ownpid);
1940 return -EINVAL;
1941 }
1942 }
1943
1944 if (my_qp->send_cq) {
1945 ret = ehca_cq_unassign_qp(my_qp->send_cq, qp_num);
1946 if (ret) {
1947 ehca_err(dev, "Couldn't unassign qp from "
1948 "send_cq ret=%i qp_num=%x cq_num=%x", ret,
1949 qp_num, my_qp->send_cq->cq_number);
1950 return ret;
1951 }
1952 }
1953
1954 write_lock_irqsave(&ehca_qp_idr_lock, flags);
1955 idr_remove(&ehca_qp_idr, my_qp->token);
1956 write_unlock_irqrestore(&ehca_qp_idr_lock, flags);
1957
1958 h_ret = hipz_h_destroy_qp(shca->ipz_hca_handle, my_qp);
1959 if (h_ret != H_SUCCESS) {
1960 ehca_err(dev, "hipz_h_destroy_qp() failed h_ret=%li "
1961 "ehca_qp=%p qp_num=%x", h_ret, my_qp, qp_num);
1962 return ehca2ib_return_code(h_ret);
1963 }
1964
1965 port_num = my_qp->init_attr.port_num;
1966 qp_type = my_qp->init_attr.qp_type;
1967
1968 if (qp_type == IB_QPT_SMI || qp_type == IB_QPT_GSI) {
1969 spin_lock_irqsave(&sport->mod_sqp_lock, flags);
1970 kfree(my_qp->mod_qp_parm);
1971 my_qp->mod_qp_parm = NULL;
1972 shca->sport[port_num - 1].ibqp_sqp[qp_type] = NULL;
1973 spin_unlock_irqrestore(&sport->mod_sqp_lock, flags);
1974 }
1975
1976 /* no support for IB_QPT_SMI yet */
1977 if (qp_type == IB_QPT_GSI) {
1978 struct ib_event event;
1979 ehca_info(dev, "device %s: port %x is inactive.",
1980 shca->ib_device.name, port_num);
1981 event.device = &shca->ib_device;
1982 event.event = IB_EVENT_PORT_ERR;
1983 event.element.port_num = port_num;
1984 shca->sport[port_num - 1].port_state = IB_PORT_DOWN;
1985 ib_dispatch_event(&event);
1986 }
1987
1988 if (HAS_RQ(my_qp))
1989 ipz_queue_dtor(my_pd, &my_qp->ipz_rqueue);
1990 if (HAS_SQ(my_qp))
1991 ipz_queue_dtor(my_pd, &my_qp->ipz_squeue);
1992 kmem_cache_free(qp_cache, my_qp);
1993 return 0;
1994 }
1995
1996 int ehca_destroy_qp(struct ib_qp *qp)
1997 {
1998 return internal_destroy_qp(qp->device,
1999 container_of(qp, struct ehca_qp, ib_qp),
2000 qp->uobject);
2001 }
2002
2003 int ehca_destroy_srq(struct ib_srq *srq)
2004 {
2005 return internal_destroy_qp(srq->device,
2006 container_of(srq, struct ehca_qp, ib_srq),
2007 srq->uobject);
2008 }
2009
2010 int ehca_init_qp_cache(void)
2011 {
2012 qp_cache = kmem_cache_create("ehca_cache_qp",
2013 sizeof(struct ehca_qp), 0,
2014 SLAB_HWCACHE_ALIGN,
2015 NULL);
2016 if (!qp_cache)
2017 return -ENOMEM;
2018 return 0;
2019 }
2020
2021 void ehca_cleanup_qp_cache(void)
2022 {
2023 if (qp_cache)
2024 kmem_cache_destroy(qp_cache);
2025 }
WRT350N Kernel Patches