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Merge git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
[wrt350n-kernel.git] / drivers / infiniband / hw / mthca / mthca_mr.c
blob85d63a9e04cad6af95733cecc5c1648781bbd4ce
1 /*
2 * Copyright (c) 2004 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 *
33 * $Id: mthca_mr.c 1349 2004-12-16 21:09:43Z roland $
34 */
35
36 #include <linux/slab.h>
37 #include <linux/errno.h>
38
39 #include "mthca_dev.h"
40 #include "mthca_cmd.h"
41 #include "mthca_memfree.h"
42
43 struct mthca_mtt {
44 struct mthca_buddy *buddy;
45 int order;
46 u32 first_seg;
47 };
48
49 /*
50 * Must be packed because mtt_seg is 64 bits but only aligned to 32 bits.
51 */
52 struct mthca_mpt_entry {
53 __be32 flags;
54 __be32 page_size;
55 __be32 key;
56 __be32 pd;
57 __be64 start;
58 __be64 length;
59 __be32 lkey;
60 __be32 window_count;
61 __be32 window_count_limit;
62 __be64 mtt_seg;
63 __be32 mtt_sz; /* Arbel only */
64 u32 reserved[2];
65 } __attribute__((packed));
66
67 #define MTHCA_MPT_FLAG_SW_OWNS (0xfUL << 28)
68 #define MTHCA_MPT_FLAG_MIO (1 << 17)
69 #define MTHCA_MPT_FLAG_BIND_ENABLE (1 << 15)
70 #define MTHCA_MPT_FLAG_PHYSICAL (1 << 9)
71 #define MTHCA_MPT_FLAG_REGION (1 << 8)
72
73 #define MTHCA_MTT_FLAG_PRESENT 1
74
75 #define MTHCA_MPT_STATUS_SW 0xF0
76 #define MTHCA_MPT_STATUS_HW 0x00
77
78 #define SINAI_FMR_KEY_INC 0x1000000
79
80 /*
81 * Buddy allocator for MTT segments (currently not very efficient
82 * since it doesn't keep a free list and just searches linearly
83 * through the bitmaps)
84 */
85
86 static u32 mthca_buddy_alloc(struct mthca_buddy *buddy, int order)
87 {
88 int o;
89 int m;
90 u32 seg;
91
92 spin_lock(&buddy->lock);
93
94 for (o = order; o <= buddy->max_order; ++o) {
95 m = 1 << (buddy->max_order - o);
96 seg = find_first_bit(buddy->bits[o], m);
97 if (seg < m)
98 goto found;
99 }
100
101 spin_unlock(&buddy->lock);
102 return -1;
103
104 found:
105 clear_bit(seg, buddy->bits[o]);
106
107 while (o > order) {
108 --o;
109 seg <<= 1;
110 set_bit(seg ^ 1, buddy->bits[o]);
111 }
112
113 spin_unlock(&buddy->lock);
114
115 seg <<= order;
116
117 return seg;
118 }
119
120 static void mthca_buddy_free(struct mthca_buddy *buddy, u32 seg, int order)
121 {
122 seg >>= order;
123
124 spin_lock(&buddy->lock);
125
126 while (test_bit(seg ^ 1, buddy->bits[order])) {
127 clear_bit(seg ^ 1, buddy->bits[order]);
128 seg >>= 1;
129 ++order;
130 }
131
132 set_bit(seg, buddy->bits[order]);
133
134 spin_unlock(&buddy->lock);
135 }
136
137 static int mthca_buddy_init(struct mthca_buddy *buddy, int max_order)
138 {
139 int i, s;
140
141 buddy->max_order = max_order;
142 spin_lock_init(&buddy->lock);
143
144 buddy->bits = kzalloc((buddy->max_order + 1) * sizeof (long *),
145 GFP_KERNEL);
146 if (!buddy->bits)
147 goto err_out;
148
149 for (i = 0; i <= buddy->max_order; ++i) {
150 s = BITS_TO_LONGS(1 << (buddy->max_order - i));
151 buddy->bits[i] = kmalloc(s * sizeof (long), GFP_KERNEL);
152 if (!buddy->bits[i])
153 goto err_out_free;
154 bitmap_zero(buddy->bits[i],
155 1 << (buddy->max_order - i));
156 }
157
158 set_bit(0, buddy->bits[buddy->max_order]);
159
160 return 0;
161
162 err_out_free:
163 for (i = 0; i <= buddy->max_order; ++i)
164 kfree(buddy->bits[i]);
165
166 kfree(buddy->bits);
167
168 err_out:
169 return -ENOMEM;
170 }
171
172 static void mthca_buddy_cleanup(struct mthca_buddy *buddy)
173 {
174 int i;
175
176 for (i = 0; i <= buddy->max_order; ++i)
177 kfree(buddy->bits[i]);
178
179 kfree(buddy->bits);
180 }
181
182 static u32 mthca_alloc_mtt_range(struct mthca_dev *dev, int order,
183 struct mthca_buddy *buddy)
184 {
185 u32 seg = mthca_buddy_alloc(buddy, order);
186
187 if (seg == -1)
188 return -1;
189
190 if (mthca_is_memfree(dev))
191 if (mthca_table_get_range(dev, dev->mr_table.mtt_table, seg,
192 seg + (1 << order) - 1)) {
193 mthca_buddy_free(buddy, seg, order);
194 seg = -1;
195 }
196
197 return seg;
198 }
199
200 static struct mthca_mtt *__mthca_alloc_mtt(struct mthca_dev *dev, int size,
201 struct mthca_buddy *buddy)
202 {
203 struct mthca_mtt *mtt;
204 int i;
205
206 if (size <= 0)
207 return ERR_PTR(-EINVAL);
208
209 mtt = kmalloc(sizeof *mtt, GFP_KERNEL);
210 if (!mtt)
211 return ERR_PTR(-ENOMEM);
212
213 mtt->buddy = buddy;
214 mtt->order = 0;
215 for (i = MTHCA_MTT_SEG_SIZE / 8; i < size; i <<= 1)
216 ++mtt->order;
217
218 mtt->first_seg = mthca_alloc_mtt_range(dev, mtt->order, buddy);
219 if (mtt->first_seg == -1) {
220 kfree(mtt);
221 return ERR_PTR(-ENOMEM);
222 }
223
224 return mtt;
225 }
226
227 struct mthca_mtt *mthca_alloc_mtt(struct mthca_dev *dev, int size)
228 {
229 return __mthca_alloc_mtt(dev, size, &dev->mr_table.mtt_buddy);
230 }
231
232 void mthca_free_mtt(struct mthca_dev *dev, struct mthca_mtt *mtt)
233 {
234 if (!mtt)
235 return;
236
237 mthca_buddy_free(mtt->buddy, mtt->first_seg, mtt->order);
238
239 mthca_table_put_range(dev, dev->mr_table.mtt_table,
240 mtt->first_seg,
241 mtt->first_seg + (1 << mtt->order) - 1);
242
243 kfree(mtt);
244 }
245
246 static int __mthca_write_mtt(struct mthca_dev *dev, struct mthca_mtt *mtt,
247 int start_index, u64 *buffer_list, int list_len)
248 {
249 struct mthca_mailbox *mailbox;
250 __be64 *mtt_entry;
251 int err = 0;
252 u8 status;
253 int i;
254
255 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
256 if (IS_ERR(mailbox))
257 return PTR_ERR(mailbox);
258 mtt_entry = mailbox->buf;
259
260 while (list_len > 0) {
261 mtt_entry[0] = cpu_to_be64(dev->mr_table.mtt_base +
262 mtt->first_seg * MTHCA_MTT_SEG_SIZE +
263 start_index * 8);
264 mtt_entry[1] = 0;
265 for (i = 0; i < list_len && i < MTHCA_MAILBOX_SIZE / 8 - 2; ++i)
266 mtt_entry[i + 2] = cpu_to_be64(buffer_list[i] |
267 MTHCA_MTT_FLAG_PRESENT);
268
269 /*
270 * If we have an odd number of entries to write, add
271 * one more dummy entry for firmware efficiency.
272 */
273 if (i & 1)
274 mtt_entry[i + 2] = 0;
275
276 err = mthca_WRITE_MTT(dev, mailbox, (i + 1) & ~1, &status);
277 if (err) {
278 mthca_warn(dev, "WRITE_MTT failed (%d)\n", err);
279 goto out;
280 }
281 if (status) {
282 mthca_warn(dev, "WRITE_MTT returned status 0x%02x\n",
283 status);
284 err = -EINVAL;
285 goto out;
286 }
287
288 list_len -= i;
289 start_index += i;
290 buffer_list += i;
291 }
292
293 out:
294 mthca_free_mailbox(dev, mailbox);
295 return err;
296 }
297
298 int mthca_write_mtt_size(struct mthca_dev *dev)
299 {
300 if (dev->mr_table.fmr_mtt_buddy != &dev->mr_table.mtt_buddy ||
301 !(dev->mthca_flags & MTHCA_FLAG_FMR))
302 /*
303 * Be friendly to WRITE_MTT command
304 * and leave two empty slots for the
305 * index and reserved fields of the
306 * mailbox.
307 */
308 return PAGE_SIZE / sizeof (u64) - 2;
309
310 /* For Arbel, all MTTs must fit in the same page. */
311 return mthca_is_memfree(dev) ? (PAGE_SIZE / sizeof (u64)) : 0x7ffffff;
312 }
313
314 static void mthca_tavor_write_mtt_seg(struct mthca_dev *dev,
315 struct mthca_mtt *mtt, int start_index,
316 u64 *buffer_list, int list_len)
317 {
318 u64 __iomem *mtts;
319 int i;
320
321 mtts = dev->mr_table.tavor_fmr.mtt_base + mtt->first_seg * MTHCA_MTT_SEG_SIZE +
322 start_index * sizeof (u64);
323 for (i = 0; i < list_len; ++i)
324 mthca_write64_raw(cpu_to_be64(buffer_list[i] | MTHCA_MTT_FLAG_PRESENT),
325 mtts + i);
326 }
327
328 static void mthca_arbel_write_mtt_seg(struct mthca_dev *dev,
329 struct mthca_mtt *mtt, int start_index,
330 u64 *buffer_list, int list_len)
331 {
332 __be64 *mtts;
333 dma_addr_t dma_handle;
334 int i;
335 int s = start_index * sizeof (u64);
336
337 /* For Arbel, all MTTs must fit in the same page. */
338 BUG_ON(s / PAGE_SIZE != (s + list_len * sizeof(u64) - 1) / PAGE_SIZE);
339 /* Require full segments */
340 BUG_ON(s % MTHCA_MTT_SEG_SIZE);
341
342 mtts = mthca_table_find(dev->mr_table.mtt_table, mtt->first_seg +
343 s / MTHCA_MTT_SEG_SIZE, &dma_handle);
344
345 BUG_ON(!mtts);
346
347 for (i = 0; i < list_len; ++i)
348 mtts[i] = cpu_to_be64(buffer_list[i] | MTHCA_MTT_FLAG_PRESENT);
349
350 dma_sync_single(&dev->pdev->dev, dma_handle, list_len * sizeof (u64), DMA_TO_DEVICE);
351 }
352
353 int mthca_write_mtt(struct mthca_dev *dev, struct mthca_mtt *mtt,
354 int start_index, u64 *buffer_list, int list_len)
355 {
356 int size = mthca_write_mtt_size(dev);
357 int chunk;
358
359 if (dev->mr_table.fmr_mtt_buddy != &dev->mr_table.mtt_buddy ||
360 !(dev->mthca_flags & MTHCA_FLAG_FMR))
361 return __mthca_write_mtt(dev, mtt, start_index, buffer_list, list_len);
362
363 while (list_len > 0) {
364 chunk = min(size, list_len);
365 if (mthca_is_memfree(dev))
366 mthca_arbel_write_mtt_seg(dev, mtt, start_index,
367 buffer_list, chunk);
368 else
369 mthca_tavor_write_mtt_seg(dev, mtt, start_index,
370 buffer_list, chunk);
371
372 list_len -= chunk;
373 start_index += chunk;
374 buffer_list += chunk;
375 }
376
377 return 0;
378 }
379
380 static inline u32 tavor_hw_index_to_key(u32 ind)
381 {
382 return ind;
383 }
384
385 static inline u32 tavor_key_to_hw_index(u32 key)
386 {
387 return key;
388 }
389
390 static inline u32 arbel_hw_index_to_key(u32 ind)
391 {
392 return (ind >> 24) | (ind << 8);
393 }
394
395 static inline u32 arbel_key_to_hw_index(u32 key)
396 {
397 return (key << 24) | (key >> 8);
398 }
399
400 static inline u32 hw_index_to_key(struct mthca_dev *dev, u32 ind)
401 {
402 if (mthca_is_memfree(dev))
403 return arbel_hw_index_to_key(ind);
404 else
405 return tavor_hw_index_to_key(ind);
406 }
407
408 static inline u32 key_to_hw_index(struct mthca_dev *dev, u32 key)
409 {
410 if (mthca_is_memfree(dev))
411 return arbel_key_to_hw_index(key);
412 else
413 return tavor_key_to_hw_index(key);
414 }
415
416 static inline u32 adjust_key(struct mthca_dev *dev, u32 key)
417 {
418 if (dev->mthca_flags & MTHCA_FLAG_SINAI_OPT)
419 return ((key << 20) & 0x800000) | (key & 0x7fffff);
420 else
421 return key;
422 }
423
424 int mthca_mr_alloc(struct mthca_dev *dev, u32 pd, int buffer_size_shift,
425 u64 iova, u64 total_size, u32 access, struct mthca_mr *mr)
426 {
427 struct mthca_mailbox *mailbox;
428 struct mthca_mpt_entry *mpt_entry;
429 u32 key;
430 int i;
431 int err;
432 u8 status;
433
434 WARN_ON(buffer_size_shift >= 32);
435
436 key = mthca_alloc(&dev->mr_table.mpt_alloc);
437 if (key == -1)
438 return -ENOMEM;
439 key = adjust_key(dev, key);
440 mr->ibmr.rkey = mr->ibmr.lkey = hw_index_to_key(dev, key);
441
442 if (mthca_is_memfree(dev)) {
443 err = mthca_table_get(dev, dev->mr_table.mpt_table, key);
444 if (err)
445 goto err_out_mpt_free;
446 }
447
448 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
449 if (IS_ERR(mailbox)) {
450 err = PTR_ERR(mailbox);
451 goto err_out_table;
452 }
453 mpt_entry = mailbox->buf;
454
455 mpt_entry->flags = cpu_to_be32(MTHCA_MPT_FLAG_SW_OWNS |
456 MTHCA_MPT_FLAG_MIO |
457 MTHCA_MPT_FLAG_REGION |
458 access);
459 if (!mr->mtt)
460 mpt_entry->flags |= cpu_to_be32(MTHCA_MPT_FLAG_PHYSICAL);
461
462 mpt_entry->page_size = cpu_to_be32(buffer_size_shift - 12);
463 mpt_entry->key = cpu_to_be32(key);
464 mpt_entry->pd = cpu_to_be32(pd);
465 mpt_entry->start = cpu_to_be64(iova);
466 mpt_entry->length = cpu_to_be64(total_size);
467
468 memset(&mpt_entry->lkey, 0,
469 sizeof *mpt_entry - offsetof(struct mthca_mpt_entry, lkey));
470
471 if (mr->mtt)
472 mpt_entry->mtt_seg =
473 cpu_to_be64(dev->mr_table.mtt_base +
474 mr->mtt->first_seg * MTHCA_MTT_SEG_SIZE);
475
476 if (0) {
477 mthca_dbg(dev, "Dumping MPT entry %08x:\n", mr->ibmr.lkey);
478 for (i = 0; i < sizeof (struct mthca_mpt_entry) / 4; ++i) {
479 if (i % 4 == 0)
480 printk("[%02x] ", i * 4);
481 printk(" %08x", be32_to_cpu(((__be32 *) mpt_entry)[i]));
482 if ((i + 1) % 4 == 0)
483 printk("\n");
484 }
485 }
486
487 err = mthca_SW2HW_MPT(dev, mailbox,
488 key & (dev->limits.num_mpts - 1),
489 &status);
490 if (err) {
491 mthca_warn(dev, "SW2HW_MPT failed (%d)\n", err);
492 goto err_out_mailbox;
493 } else if (status) {
494 mthca_warn(dev, "SW2HW_MPT returned status 0x%02x\n",
495 status);
496 err = -EINVAL;
497 goto err_out_mailbox;
498 }
499
500 mthca_free_mailbox(dev, mailbox);
501 return err;
502
503 err_out_mailbox:
504 mthca_free_mailbox(dev, mailbox);
505
506 err_out_table:
507 mthca_table_put(dev, dev->mr_table.mpt_table, key);
508
509 err_out_mpt_free:
510 mthca_free(&dev->mr_table.mpt_alloc, key);
511 return err;
512 }
513
514 int mthca_mr_alloc_notrans(struct mthca_dev *dev, u32 pd,
515 u32 access, struct mthca_mr *mr)
516 {
517 mr->mtt = NULL;
518 return mthca_mr_alloc(dev, pd, 12, 0, ~0ULL, access, mr);
519 }
520
521 int mthca_mr_alloc_phys(struct mthca_dev *dev, u32 pd,
522 u64 *buffer_list, int buffer_size_shift,
523 int list_len, u64 iova, u64 total_size,
524 u32 access, struct mthca_mr *mr)
525 {
526 int err;
527
528 mr->mtt = mthca_alloc_mtt(dev, list_len);
529 if (IS_ERR(mr->mtt))
530 return PTR_ERR(mr->mtt);
531
532 err = mthca_write_mtt(dev, mr->mtt, 0, buffer_list, list_len);
533 if (err) {
534 mthca_free_mtt(dev, mr->mtt);
535 return err;
536 }
537
538 err = mthca_mr_alloc(dev, pd, buffer_size_shift, iova,
539 total_size, access, mr);
540 if (err)
541 mthca_free_mtt(dev, mr->mtt);
542
543 return err;
544 }
545
546 /* Free mr or fmr */
547 static void mthca_free_region(struct mthca_dev *dev, u32 lkey)
548 {
549 mthca_table_put(dev, dev->mr_table.mpt_table,
550 key_to_hw_index(dev, lkey));
551
552 mthca_free(&dev->mr_table.mpt_alloc, key_to_hw_index(dev, lkey));
553 }
554
555 void mthca_free_mr(struct mthca_dev *dev, struct mthca_mr *mr)
556 {
557 int err;
558 u8 status;
559
560 err = mthca_HW2SW_MPT(dev, NULL,
561 key_to_hw_index(dev, mr->ibmr.lkey) &
562 (dev->limits.num_mpts - 1),
563 &status);
564 if (err)
565 mthca_warn(dev, "HW2SW_MPT failed (%d)\n", err);
566 else if (status)
567 mthca_warn(dev, "HW2SW_MPT returned status 0x%02x\n",
568 status);
569
570 mthca_free_region(dev, mr->ibmr.lkey);
571 mthca_free_mtt(dev, mr->mtt);
572 }
573
574 int mthca_fmr_alloc(struct mthca_dev *dev, u32 pd,
575 u32 access, struct mthca_fmr *mr)
576 {
577 struct mthca_mpt_entry *mpt_entry;
578 struct mthca_mailbox *mailbox;
579 u64 mtt_seg;
580 u32 key, idx;
581 u8 status;
582 int list_len = mr->attr.max_pages;
583 int err = -ENOMEM;
584 int i;
585
586 if (mr->attr.page_shift < 12 || mr->attr.page_shift >= 32)
587 return -EINVAL;
588
589 /* For Arbel, all MTTs must fit in the same page. */
590 if (mthca_is_memfree(dev) &&
591 mr->attr.max_pages * sizeof *mr->mem.arbel.mtts > PAGE_SIZE)
592 return -EINVAL;
593
594 mr->maps = 0;
595
596 key = mthca_alloc(&dev->mr_table.mpt_alloc);
597 if (key == -1)
598 return -ENOMEM;
599 key = adjust_key(dev, key);
600
601 idx = key & (dev->limits.num_mpts - 1);
602 mr->ibmr.rkey = mr->ibmr.lkey = hw_index_to_key(dev, key);
603
604 if (mthca_is_memfree(dev)) {
605 err = mthca_table_get(dev, dev->mr_table.mpt_table, key);
606 if (err)
607 goto err_out_mpt_free;
608
609 mr->mem.arbel.mpt = mthca_table_find(dev->mr_table.mpt_table, key, NULL);
610 BUG_ON(!mr->mem.arbel.mpt);
611 } else
612 mr->mem.tavor.mpt = dev->mr_table.tavor_fmr.mpt_base +
613 sizeof *(mr->mem.tavor.mpt) * idx;
614
615 mr->mtt = __mthca_alloc_mtt(dev, list_len, dev->mr_table.fmr_mtt_buddy);
616 if (IS_ERR(mr->mtt)) {
617 err = PTR_ERR(mr->mtt);
618 goto err_out_table;
619 }
620
621 mtt_seg = mr->mtt->first_seg * MTHCA_MTT_SEG_SIZE;
622
623 if (mthca_is_memfree(dev)) {
624 mr->mem.arbel.mtts = mthca_table_find(dev->mr_table.mtt_table,
625 mr->mtt->first_seg,
626 &mr->mem.arbel.dma_handle);
627 BUG_ON(!mr->mem.arbel.mtts);
628 } else
629 mr->mem.tavor.mtts = dev->mr_table.tavor_fmr.mtt_base + mtt_seg;
630
631 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
632 if (IS_ERR(mailbox)) {
633 err = PTR_ERR(mailbox);
634 goto err_out_free_mtt;
635 }
636
637 mpt_entry = mailbox->buf;
638
639 mpt_entry->flags = cpu_to_be32(MTHCA_MPT_FLAG_SW_OWNS |
640 MTHCA_MPT_FLAG_MIO |
641 MTHCA_MPT_FLAG_REGION |
642 access);
643
644 mpt_entry->page_size = cpu_to_be32(mr->attr.page_shift - 12);
645 mpt_entry->key = cpu_to_be32(key);
646 mpt_entry->pd = cpu_to_be32(pd);
647 memset(&mpt_entry->start, 0,
648 sizeof *mpt_entry - offsetof(struct mthca_mpt_entry, start));
649 mpt_entry->mtt_seg = cpu_to_be64(dev->mr_table.mtt_base + mtt_seg);
650
651 if (0) {
652 mthca_dbg(dev, "Dumping MPT entry %08x:\n", mr->ibmr.lkey);
653 for (i = 0; i < sizeof (struct mthca_mpt_entry) / 4; ++i) {
654 if (i % 4 == 0)
655 printk("[%02x] ", i * 4);
656 printk(" %08x", be32_to_cpu(((__be32 *) mpt_entry)[i]));
657 if ((i + 1) % 4 == 0)
658 printk("\n");
659 }
660 }
661
662 err = mthca_SW2HW_MPT(dev, mailbox,
663 key & (dev->limits.num_mpts - 1),
664 &status);
665 if (err) {
666 mthca_warn(dev, "SW2HW_MPT failed (%d)\n", err);
667 goto err_out_mailbox_free;
668 }
669 if (status) {
670 mthca_warn(dev, "SW2HW_MPT returned status 0x%02x\n",
671 status);
672 err = -EINVAL;
673 goto err_out_mailbox_free;
674 }
675
676 mthca_free_mailbox(dev, mailbox);
677 return 0;
678
679 err_out_mailbox_free:
680 mthca_free_mailbox(dev, mailbox);
681
682 err_out_free_mtt:
683 mthca_free_mtt(dev, mr->mtt);
684
685 err_out_table:
686 mthca_table_put(dev, dev->mr_table.mpt_table, key);
687
688 err_out_mpt_free:
689 <<<<<<< HEAD:drivers/infiniband/hw/mthca/mthca_mr.c
690 mthca_free(&dev->mr_table.mpt_alloc, mr->ibmr.lkey);
691 =======
692 mthca_free(&dev->mr_table.mpt_alloc, key);
693 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/infiniband/hw/mthca/mthca_mr.c
694 return err;
695 }
696
697 int mthca_free_fmr(struct mthca_dev *dev, struct mthca_fmr *fmr)
698 {
699 if (fmr->maps)
700 return -EBUSY;
701
702 mthca_free_region(dev, fmr->ibmr.lkey);
703 mthca_free_mtt(dev, fmr->mtt);
704
705 return 0;
706 }
707
708 static inline int mthca_check_fmr(struct mthca_fmr *fmr, u64 *page_list,
709 int list_len, u64 iova)
710 {
711 int i, page_mask;
712
713 if (list_len > fmr->attr.max_pages)
714 return -EINVAL;
715
716 page_mask = (1 << fmr->attr.page_shift) - 1;
717
718 /* We are getting page lists, so va must be page aligned. */
719 if (iova & page_mask)
720 return -EINVAL;
721
722 /* Trust the user not to pass misaligned data in page_list */
723 if (0)
724 for (i = 0; i < list_len; ++i) {
725 if (page_list[i] & ~page_mask)
726 return -EINVAL;
727 }
728
729 if (fmr->maps >= fmr->attr.max_maps)
730 return -EINVAL;
731
732 return 0;
733 }
734
735
736 int mthca_tavor_map_phys_fmr(struct ib_fmr *ibfmr, u64 *page_list,
737 int list_len, u64 iova)
738 {
739 struct mthca_fmr *fmr = to_mfmr(ibfmr);
740 struct mthca_dev *dev = to_mdev(ibfmr->device);
741 struct mthca_mpt_entry mpt_entry;
742 u32 key;
743 int i, err;
744
745 err = mthca_check_fmr(fmr, page_list, list_len, iova);
746 if (err)
747 return err;
748
749 ++fmr->maps;
750
751 key = tavor_key_to_hw_index(fmr->ibmr.lkey);
752 key += dev->limits.num_mpts;
753 fmr->ibmr.lkey = fmr->ibmr.rkey = tavor_hw_index_to_key(key);
754
755 writeb(MTHCA_MPT_STATUS_SW, fmr->mem.tavor.mpt);
756
757 for (i = 0; i < list_len; ++i) {
758 __be64 mtt_entry = cpu_to_be64(page_list[i] |
759 MTHCA_MTT_FLAG_PRESENT);
760 mthca_write64_raw(mtt_entry, fmr->mem.tavor.mtts + i);
761 }
762
763 mpt_entry.lkey = cpu_to_be32(key);
764 mpt_entry.length = cpu_to_be64(list_len * (1ull << fmr->attr.page_shift));
765 mpt_entry.start = cpu_to_be64(iova);
766
767 __raw_writel((__force u32) mpt_entry.lkey, &fmr->mem.tavor.mpt->key);
768 memcpy_toio(&fmr->mem.tavor.mpt->start, &mpt_entry.start,
769 offsetof(struct mthca_mpt_entry, window_count) -
770 offsetof(struct mthca_mpt_entry, start));
771
772 writeb(MTHCA_MPT_STATUS_HW, fmr->mem.tavor.mpt);
773
774 return 0;
775 }
776
777 int mthca_arbel_map_phys_fmr(struct ib_fmr *ibfmr, u64 *page_list,
778 int list_len, u64 iova)
779 {
780 struct mthca_fmr *fmr = to_mfmr(ibfmr);
781 struct mthca_dev *dev = to_mdev(ibfmr->device);
782 u32 key;
783 int i, err;
784
785 err = mthca_check_fmr(fmr, page_list, list_len, iova);
786 if (err)
787 return err;
788
789 ++fmr->maps;
790
791 key = arbel_key_to_hw_index(fmr->ibmr.lkey);
792 if (dev->mthca_flags & MTHCA_FLAG_SINAI_OPT)
793 key += SINAI_FMR_KEY_INC;
794 else
795 key += dev->limits.num_mpts;
796 fmr->ibmr.lkey = fmr->ibmr.rkey = arbel_hw_index_to_key(key);
797
798 *(u8 *) fmr->mem.arbel.mpt = MTHCA_MPT_STATUS_SW;
799
800 wmb();
801
802 for (i = 0; i < list_len; ++i)
803 fmr->mem.arbel.mtts[i] = cpu_to_be64(page_list[i] |
804 MTHCA_MTT_FLAG_PRESENT);
805
806 dma_sync_single(&dev->pdev->dev, fmr->mem.arbel.dma_handle,
807 list_len * sizeof(u64), DMA_TO_DEVICE);
808
809 fmr->mem.arbel.mpt->key = cpu_to_be32(key);
810 fmr->mem.arbel.mpt->lkey = cpu_to_be32(key);
811 fmr->mem.arbel.mpt->length = cpu_to_be64(list_len * (1ull << fmr->attr.page_shift));
812 fmr->mem.arbel.mpt->start = cpu_to_be64(iova);
813
814 wmb();
815
816 *(u8 *) fmr->mem.arbel.mpt = MTHCA_MPT_STATUS_HW;
817
818 wmb();
819
820 return 0;
821 }
822
823 void mthca_tavor_fmr_unmap(struct mthca_dev *dev, struct mthca_fmr *fmr)
824 {
825 u32 key;
826
827 if (!fmr->maps)
828 return;
829
830 key = tavor_key_to_hw_index(fmr->ibmr.lkey);
831 key &= dev->limits.num_mpts - 1;
832 fmr->ibmr.lkey = fmr->ibmr.rkey = tavor_hw_index_to_key(key);
833
834 fmr->maps = 0;
835
836 writeb(MTHCA_MPT_STATUS_SW, fmr->mem.tavor.mpt);
837 }
838
839 void mthca_arbel_fmr_unmap(struct mthca_dev *dev, struct mthca_fmr *fmr)
840 {
841 u32 key;
842
843 if (!fmr->maps)
844 return;
845
846 key = arbel_key_to_hw_index(fmr->ibmr.lkey);
847 key &= dev->limits.num_mpts - 1;
848 key = adjust_key(dev, key);
849 fmr->ibmr.lkey = fmr->ibmr.rkey = arbel_hw_index_to_key(key);
850
851 fmr->maps = 0;
852
853 *(u8 *) fmr->mem.arbel.mpt = MTHCA_MPT_STATUS_SW;
854 }
855
856 int mthca_init_mr_table(struct mthca_dev *dev)
857 {
858 unsigned long addr;
859 int mpts, mtts, err, i;
860
861 err = mthca_alloc_init(&dev->mr_table.mpt_alloc,
862 dev->limits.num_mpts,
863 ~0, dev->limits.reserved_mrws);
864 if (err)
865 return err;
866
867 if (!mthca_is_memfree(dev) &&
868 (dev->mthca_flags & MTHCA_FLAG_DDR_HIDDEN))
869 dev->limits.fmr_reserved_mtts = 0;
870 else
871 dev->mthca_flags |= MTHCA_FLAG_FMR;
872
873 if (dev->mthca_flags & MTHCA_FLAG_SINAI_OPT)
874 mthca_dbg(dev, "Memory key throughput optimization activated.\n");
875
876 err = mthca_buddy_init(&dev->mr_table.mtt_buddy,
877 fls(dev->limits.num_mtt_segs - 1));
878
879 if (err)
880 goto err_mtt_buddy;
881
882 dev->mr_table.tavor_fmr.mpt_base = NULL;
883 dev->mr_table.tavor_fmr.mtt_base = NULL;
884
885 if (dev->limits.fmr_reserved_mtts) {
886 i = fls(dev->limits.fmr_reserved_mtts - 1);
887
888 if (i >= 31) {
889 mthca_warn(dev, "Unable to reserve 2^31 FMR MTTs.\n");
890 err = -EINVAL;
891 goto err_fmr_mpt;
892 }
893 mpts = mtts = 1 << i;
894 } else {
895 mtts = dev->limits.num_mtt_segs;
896 mpts = dev->limits.num_mpts;
897 }
898
899 if (!mthca_is_memfree(dev) &&
900 (dev->mthca_flags & MTHCA_FLAG_FMR)) {
901
902 addr = pci_resource_start(dev->pdev, 4) +
903 ((pci_resource_len(dev->pdev, 4) - 1) &
904 dev->mr_table.mpt_base);
905
906 dev->mr_table.tavor_fmr.mpt_base =
907 ioremap(addr, mpts * sizeof(struct mthca_mpt_entry));
908
909 if (!dev->mr_table.tavor_fmr.mpt_base) {
910 mthca_warn(dev, "MPT ioremap for FMR failed.\n");
911 err = -ENOMEM;
912 goto err_fmr_mpt;
913 }
914
915 addr = pci_resource_start(dev->pdev, 4) +
916 ((pci_resource_len(dev->pdev, 4) - 1) &
917 dev->mr_table.mtt_base);
918
919 dev->mr_table.tavor_fmr.mtt_base =
920 ioremap(addr, mtts * MTHCA_MTT_SEG_SIZE);
921 if (!dev->mr_table.tavor_fmr.mtt_base) {
922 mthca_warn(dev, "MTT ioremap for FMR failed.\n");
923 err = -ENOMEM;
924 goto err_fmr_mtt;
925 }
926 }
927
928 if (dev->limits.fmr_reserved_mtts) {
929 err = mthca_buddy_init(&dev->mr_table.tavor_fmr.mtt_buddy, fls(mtts - 1));
930 if (err)
931 goto err_fmr_mtt_buddy;
932
933 /* Prevent regular MRs from using FMR keys */
934 err = mthca_buddy_alloc(&dev->mr_table.mtt_buddy, fls(mtts - 1));
935 if (err)
936 goto err_reserve_fmr;
937
938 dev->mr_table.fmr_mtt_buddy =
939 &dev->mr_table.tavor_fmr.mtt_buddy;
940 } else
941 dev->mr_table.fmr_mtt_buddy = &dev->mr_table.mtt_buddy;
942
943 /* FMR table is always the first, take reserved MTTs out of there */
944 if (dev->limits.reserved_mtts) {
945 i = fls(dev->limits.reserved_mtts - 1);
946
947 if (mthca_alloc_mtt_range(dev, i,
948 dev->mr_table.fmr_mtt_buddy) == -1) {
949 mthca_warn(dev, "MTT table of order %d is too small.\n",
950 dev->mr_table.fmr_mtt_buddy->max_order);
951 err = -ENOMEM;
952 goto err_reserve_mtts;
953 }
954 }
955
956 return 0;
957
958 err_reserve_mtts:
959 err_reserve_fmr:
960 if (dev->limits.fmr_reserved_mtts)
961 mthca_buddy_cleanup(&dev->mr_table.tavor_fmr.mtt_buddy);
962
963 err_fmr_mtt_buddy:
964 if (dev->mr_table.tavor_fmr.mtt_base)
965 iounmap(dev->mr_table.tavor_fmr.mtt_base);
966
967 err_fmr_mtt:
968 if (dev->mr_table.tavor_fmr.mpt_base)
969 iounmap(dev->mr_table.tavor_fmr.mpt_base);
970
971 err_fmr_mpt:
972 mthca_buddy_cleanup(&dev->mr_table.mtt_buddy);
973
974 err_mtt_buddy:
975 mthca_alloc_cleanup(&dev->mr_table.mpt_alloc);
976
977 return err;
978 }
979
980 void mthca_cleanup_mr_table(struct mthca_dev *dev)
981 {
982 /* XXX check if any MRs are still allocated? */
983 if (dev->limits.fmr_reserved_mtts)
984 mthca_buddy_cleanup(&dev->mr_table.tavor_fmr.mtt_buddy);
985
986 mthca_buddy_cleanup(&dev->mr_table.mtt_buddy);
987
988 if (dev->mr_table.tavor_fmr.mtt_base)
989 iounmap(dev->mr_table.tavor_fmr.mtt_base);
990 if (dev->mr_table.tavor_fmr.mpt_base)
991 iounmap(dev->mr_table.tavor_fmr.mpt_base);
992
993 mthca_alloc_cleanup(&dev->mr_table.mpt_alloc);
994 }
WRT350N Kernel Patches