drivers/media/dvb/frontends/mt312.c

   1 /*
   2     Driver for Zarlink VP310/MT312 Satellite Channel Decoder
   3
   4     Copyright (C) 2003 Andreas Oberritter <obi@linuxtv.org>
   5
   6     This program is free software; you can redistribute it and/or modify
   7     it under the terms of the GNU General Public License as published by
   8     the Free Software Foundation; either version 2 of the License, or
   9     (at your option) any later version.
  10
  11     This program is distributed in the hope that it will be useful,
  12     but WITHOUT ANY WARRANTY; without even the implied warranty of
  13     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14
  15     GNU General Public License for more details.
  16
  17     You should have received a copy of the GNU General Public License
  18     along with this program; if not, write to the Free Software
  19     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20
  21     References:
  22     http://products.zarlink.com/product_profiles/MT312.htm
  23     http://products.zarlink.com/product_profiles/SL1935.htm
  24 */
  25
  26 #include <linux/delay.h>
  27 #include <linux/errno.h>
  28 #include <linux/init.h>
  29 #include <linux/kernel.h>
  30 #include <linux/module.h>
  31 #include <linux/string.h>
  32 #include <linux/slab.h>
  33
  34 #include "dvb_frontend.h"
  35 #include "mt312_priv.h"
  36 #include "mt312.h"
  37
  38
  39 struct mt312_state {
  40         struct i2c_adapter *i2c;
  41         /* configuration settings */
  42         const struct mt312_config *config;
  43         struct dvb_frontend frontend;
  44
  45         u8 id;
  46         u8 frequency;
  47 };
  48
  49 static int debug;
  50 #define dprintk(args...) \
  51         do { \
  52                 if (debug) \
  53                         printk(KERN_DEBUG "mt312: " args); \
  54         } while (0)
  55
  56 #define MT312_SYS_CLK           90000000UL      /* 90 MHz */
  57 #define MT312_LPOWER_SYS_CLK    60000000UL      /* 60 MHz */
  58 #define MT312_PLL_CLK           10000000UL      /* 10 MHz */
  59
  60 static int mt312_read(struct mt312_state *state, const enum mt312_reg_addr reg,
  61                       void *buf, const size_t count)
  62 {
  63         int ret;
  64         struct i2c_msg msg[2];
  65         u8 regbuf[1] = { reg };
  66
  67         msg[0].addr = state->config->demod_address;
  68         msg[0].flags = 0;
  69         msg[0].buf = regbuf;
  70         msg[0].len = 1;
  71         msg[1].addr = state->config->demod_address;
  72         msg[1].flags = I2C_M_RD;
  73         msg[1].buf = buf;
  74         msg[1].len = count;
  75
  76         ret = i2c_transfer(state->i2c, msg, 2);
  77
  78         if (ret != 2) {
  79                 printk(KERN_ERR "%s: ret == %d\n", __FUNCTION__, ret);
  80                 return -EREMOTEIO;
  81         }
  82
  83         if (debug) {
  84                 int i;
  85                 dprintk("R(%d):", reg & 0x7f);
  86                 for (i = 0; i < count; i++)
  87                         printk(" %02x", ((const u8 *) buf)[i]);
  88                 printk("\n");
  89         }
  90
  91         return 0;
  92 }
  93
  94 static int mt312_write(struct mt312_state *state, const enum mt312_reg_addr reg,
  95                        const void *src, const size_t count)
  96 {
  97         int ret;
  98         u8 buf[count + 1];
  99         struct i2c_msg msg;
 100
 101         if (debug) {
 102                 int i;
 103                 dprintk("W(%d):", reg & 0x7f);
 104                 for (i = 0; i < count; i++)
 105                         printk(" %02x", ((const u8 *) src)[i]);
 106                 printk("\n");
 107         }
 108
 109         buf[0] = reg;
 110         memcpy(&buf[1], src, count);
 111
 112         msg.addr = state->config->demod_address;
 113         msg.flags = 0;
 114         msg.buf = buf;
 115         msg.len = count + 1;
 116
 117         ret = i2c_transfer(state->i2c, &msg, 1);
 118
 119         if (ret != 1) {
 120                 dprintk("%s: ret == %d\n", __FUNCTION__, ret);
 121                 return -EREMOTEIO;
 122         }
 123
 124         return 0;
 125 }
 126
 127 static inline int mt312_readreg(struct mt312_state *state,
 128                                 const enum mt312_reg_addr reg, u8 *val)
 129 {
 130         return mt312_read(state, reg, val, 1);
 131 }
 132
 133 static inline int mt312_writereg(struct mt312_state *state,
 134                                  const enum mt312_reg_addr reg, const u8 val)
 135 {
 136         return mt312_write(state, reg, &val, 1);
 137 }
 138
 139 static inline u32 mt312_div(u32 a, u32 b)
 140 {
 141         return (a + (b / 2)) / b;
 142 }
 143
 144 static int mt312_reset(struct mt312_state *state, const u8 full)
 145 {
 146         return mt312_writereg(state, RESET, full ? 0x80 : 0x40);
 147 }
 148
 149 static int mt312_get_inversion(struct mt312_state *state,
 150                                fe_spectral_inversion_t *i)
 151 {
 152         int ret;
 153         u8 vit_mode;
 154
 155         ret = mt312_readreg(state, VIT_MODE, &vit_mode);
 156         if (ret < 0)
 157                 return ret;
 158
 159         if (vit_mode & 0x80)    /* auto inversion was used */
 160                 *i = (vit_mode & 0x40) ? INVERSION_ON : INVERSION_OFF;
 161
 162         return 0;
 163 }
 164
 165 static int mt312_get_symbol_rate(struct mt312_state *state, u32 *sr)
 166 {
 167         int ret;
 168         u8 sym_rate_h;
 169         u8 dec_ratio;
 170         u16 sym_rat_op;
 171         u16 monitor;
 172         u8 buf[2];
 173
 174         ret = mt312_readreg(state, SYM_RATE_H, &sym_rate_h);
 175         if (ret < 0)
 176                 return ret;
 177
 178         if (sym_rate_h & 0x80) {
 179                 /* symbol rate search was used */
 180                 ret = mt312_writereg(state, MON_CTRL, 0x03);
 181                 if (ret < 0)
 182                         return ret;
 183
 184                 ret = mt312_read(state, MONITOR_H, buf, sizeof(buf));
 185                 if (ret < 0)
 186                         return ret;
 187
 188                 monitor = (buf[0] << 8) | buf[1];
 189
 190                 dprintk("sr(auto) = %u\n",
 191                        mt312_div(monitor * 15625, 4));
 192         } else {
 193                 ret = mt312_writereg(state, MON_CTRL, 0x05);
 194                 if (ret < 0)
 195                         return ret;
 196
 197                 ret = mt312_read(state, MONITOR_H, buf, sizeof(buf));
 198                 if (ret < 0)
 199                         return ret;
 200
 201                 dec_ratio = ((buf[0] >> 5) & 0x07) * 32;
 202
 203                 ret = mt312_read(state, SYM_RAT_OP_H, buf, sizeof(buf));
 204                 if (ret < 0)
 205                         return ret;
 206
 207                 sym_rat_op = (buf[0] << 8) | buf[1];
 208
 209                 dprintk("sym_rat_op=%d dec_ratio=%d\n",
 210                        sym_rat_op, dec_ratio);
 211                 dprintk("*sr(manual) = %lu\n",
 212                        (((MT312_PLL_CLK * 8192) / (sym_rat_op + 8192)) *
 213                         2) - dec_ratio);
 214         }
 215
 216         return 0;
 217 }
 218
 219 static int mt312_get_code_rate(struct mt312_state *state, fe_code_rate_t *cr)
 220 {
 221         const fe_code_rate_t fec_tab[8] =
 222             { FEC_1_2, FEC_2_3, FEC_3_4, FEC_5_6, FEC_6_7, FEC_7_8,
 223                 FEC_AUTO, FEC_AUTO };
 224
 225         int ret;
 226         u8 fec_status;
 227
 228         ret = mt312_readreg(state, FEC_STATUS, &fec_status);
 229         if (ret < 0)
 230                 return ret;
 231
 232         *cr = fec_tab[(fec_status >> 4) & 0x07];
 233
 234         return 0;
 235 }
 236
 237 static int mt312_initfe(struct dvb_frontend *fe)
 238 {
 239         struct mt312_state *state = fe->demodulator_priv;
 240         int ret;
 241         u8 buf[2];
 242
 243         /* wake up */
 244         ret = mt312_writereg(state, CONFIG,
 245                         (state->frequency == 60 ? 0x88 : 0x8c));
 246         if (ret < 0)
 247                 return ret;
 248
 249         /* wait at least 150 usec */
 250         udelay(150);
 251
 252         /* full reset */
 253         ret = mt312_reset(state, 1);
 254         if (ret < 0)
 255                 return ret;
 256
 257 /* Per datasheet, write correct values. 09/28/03 ACCJr.
 258  * If we don't do this, we won't get FE_HAS_VITERBI in the VP310. */
 259         {
 260                 u8 buf_def[8] = { 0x14, 0x12, 0x03, 0x02,
 261                                   0x01, 0x00, 0x00, 0x00 };
 262
 263                 ret = mt312_write(state, VIT_SETUP, buf_def, sizeof(buf_def));
 264                 if (ret < 0)
 265                         return ret;
 266         }
 267
 268         /* SYS_CLK */
 269         buf[0] = mt312_div((state->frequency == 60 ? MT312_LPOWER_SYS_CLK :
 270                                 MT312_SYS_CLK) * 2, 1000000);
 271
 272         /* DISEQC_RATIO */
 273         buf[1] = mt312_div(MT312_PLL_CLK, 15000 * 4);
 274
 275         ret = mt312_write(state, SYS_CLK, buf, sizeof(buf));
 276         if (ret < 0)
 277                 return ret;
 278
 279         ret = mt312_writereg(state, SNR_THS_HIGH, 0x32);
 280         if (ret < 0)
 281                 return ret;
 282
 283         ret = mt312_writereg(state, OP_CTRL, 0x53);
 284         if (ret < 0)
 285                 return ret;
 286
 287         /* TS_SW_LIM */
 288         buf[0] = 0x8c;
 289         buf[1] = 0x98;
 290
 291         ret = mt312_write(state, TS_SW_LIM_L, buf, sizeof(buf));
 292         if (ret < 0)
 293                 return ret;
 294
 295         ret = mt312_writereg(state, CS_SW_LIM, 0x69);
 296         if (ret < 0)
 297                 return ret;
 298
 299         return 0;
 300 }
 301
 302 static int mt312_send_master_cmd(struct dvb_frontend *fe,
 303                                  struct dvb_diseqc_master_cmd *c)
 304 {
 305         struct mt312_state *state = fe->demodulator_priv;
 306         int ret;
 307         u8 diseqc_mode;
 308
 309         if ((c->msg_len == 0) || (c->msg_len > sizeof(c->msg)))
 310                 return -EINVAL;
 311
 312         ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode);
 313         if (ret < 0)
 314                 return ret;
 315
 316         ret = mt312_write(state, (0x80 | DISEQC_INSTR), c->msg, c->msg_len);
 317         if (ret < 0)
 318                 return ret;
 319
 320         ret = mt312_writereg(state, DISEQC_MODE,
 321                              (diseqc_mode & 0x40) | ((c->msg_len - 1) << 3)
 322                              | 0x04);
 323         if (ret < 0)
 324                 return ret;
 325
 326         /* set DISEQC_MODE[2:0] to zero if a return message is expected */
 327         if (c->msg[0] & 0x02) {
 328                 ret = mt312_writereg(state, DISEQC_MODE, (diseqc_mode & 0x40));
 329                 if (ret < 0)
 330                         return ret;
 331         }
 332
 333         return 0;
 334 }
 335
 336 static int mt312_send_burst(struct dvb_frontend *fe, const fe_sec_mini_cmd_t c)
 337 {
 338         struct mt312_state *state = fe->demodulator_priv;
 339         const u8 mini_tab[2] = { 0x02, 0x03 };
 340
 341         int ret;
 342         u8 diseqc_mode;
 343
 344         if (c > SEC_MINI_B)
 345                 return -EINVAL;
 346
 347         ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode);
 348         if (ret < 0)
 349                 return ret;
 350
 351         ret = mt312_writereg(state, DISEQC_MODE,
 352                              (diseqc_mode & 0x40) | mini_tab[c]);
 353         if (ret < 0)
 354                 return ret;
 355
 356         return 0;
 357 }
 358
 359 static int mt312_set_tone(struct dvb_frontend *fe, const fe_sec_tone_mode_t t)
 360 {
 361         struct mt312_state *state = fe->demodulator_priv;
 362         const u8 tone_tab[2] = { 0x01, 0x00 };
 363
 364         int ret;
 365         u8 diseqc_mode;
 366
 367         if (t > SEC_TONE_OFF)
 368                 return -EINVAL;
 369
 370         ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode);
 371         if (ret < 0)
 372                 return ret;
 373
 374         ret = mt312_writereg(state, DISEQC_MODE,
 375                              (diseqc_mode & 0x40) | tone_tab[t]);
 376         if (ret < 0)
 377                 return ret;
 378
 379         return 0;
 380 }
 381
 382 static int mt312_set_voltage(struct dvb_frontend *fe, const fe_sec_voltage_t v)
 383 {
 384         struct mt312_state *state = fe->demodulator_priv;
 385         const u8 volt_tab[3] = { 0x00, 0x40, 0x00 };
 386
 387         if (v > SEC_VOLTAGE_OFF)
 388                 return -EINVAL;
 389
 390         return mt312_writereg(state, DISEQC_MODE, volt_tab[v]);
 391 }
 392
 393 static int mt312_read_status(struct dvb_frontend *fe, fe_status_t *s)
 394 {
 395         struct mt312_state *state = fe->demodulator_priv;
 396         int ret;
 397         u8 status[3];
 398
 399         *s = 0;
 400
 401         ret = mt312_read(state, QPSK_STAT_H, status, sizeof(status));
 402         if (ret < 0)
 403                 return ret;
 404
 405         dprintk("QPSK_STAT_H: 0x%02x, QPSK_STAT_L: 0x%02x,"
 406                 " FEC_STATUS: 0x%02x\n", status[0], status[1], status[2]);
 407
 408         if (status[0] & 0xc0)
 409                 *s |= FE_HAS_SIGNAL;    /* signal noise ratio */
 410         if (status[0] & 0x04)
 411                 *s |= FE_HAS_CARRIER;   /* qpsk carrier lock */
 412         if (status[2] & 0x02)
 413                 *s |= FE_HAS_VITERBI;   /* viterbi lock */
 414         if (status[2] & 0x04)
 415                 *s |= FE_HAS_SYNC;      /* byte align lock */
 416         if (status[0] & 0x01)
 417                 *s |= FE_HAS_LOCK;      /* qpsk lock */
 418
 419         return 0;
 420 }
 421
 422 static int mt312_read_ber(struct dvb_frontend *fe, u32 *ber)
 423 {
 424         struct mt312_state *state = fe->demodulator_priv;
 425         int ret;
 426         u8 buf[3];
 427
 428         ret = mt312_read(state, RS_BERCNT_H, buf, 3);
 429         if (ret < 0)
 430                 return ret;
 431
 432         *ber = ((buf[0] << 16) | (buf[1] << 8) | buf[2]) * 64;
 433
 434         return 0;
 435 }
 436
 437 static int mt312_read_signal_strength(struct dvb_frontend *fe,
 438                                       u16 *signal_strength)
 439 {
 440         struct mt312_state *state = fe->demodulator_priv;
 441         int ret;
 442         u8 buf[3];
 443         u16 agc;
 444         s16 err_db;
 445
 446         ret = mt312_read(state, AGC_H, buf, sizeof(buf));
 447         if (ret < 0)
 448                 return ret;
 449
 450         agc = (buf[0] << 6) | (buf[1] >> 2);
 451         err_db = (s16) (((buf[1] & 0x03) << 14) | buf[2] << 6) >> 6;
 452
 453         *signal_strength = agc;
 454
 455         dprintk("agc=%08x err_db=%hd\n", agc, err_db);
 456
 457         return 0;
 458 }
 459
 460 static int mt312_read_snr(struct dvb_frontend *fe, u16 *snr)
 461 {
 462         struct mt312_state *state = fe->demodulator_priv;
 463         int ret;
 464         u8 buf[2];
 465
 466         ret = mt312_read(state, M_SNR_H, &buf, sizeof(buf));
 467         if (ret < 0)
 468                 return ret;
 469
 470         *snr = 0xFFFF - ((((buf[0] & 0x7f) << 8) | buf[1]) << 1);
 471
 472         return 0;
 473 }
 474
 475 static int mt312_read_ucblocks(struct dvb_frontend *fe, u32 *ubc)
 476 {
 477         struct mt312_state *state = fe->demodulator_priv;
 478         int ret;
 479         u8 buf[2];
 480
 481         ret = mt312_read(state, RS_UBC_H, &buf, sizeof(buf));
 482         if (ret < 0)
 483                 return ret;
 484
 485         *ubc = (buf[0] << 8) | buf[1];
 486
 487         return 0;
 488 }
 489
 490 static int mt312_set_frontend(struct dvb_frontend *fe,
 491                               struct dvb_frontend_parameters *p)
 492 {
 493         struct mt312_state *state = fe->demodulator_priv;
 494         int ret;
 495         u8 buf[5], config_val;
 496         u16 sr;
 497
 498         const u8 fec_tab[10] =
 499             { 0x00, 0x01, 0x02, 0x04, 0x3f, 0x08, 0x10, 0x20, 0x3f, 0x3f };
 500         const u8 inv_tab[3] = { 0x00, 0x40, 0x80 };
 501
 502         dprintk("%s: Freq %d\n", __FUNCTION__, p->frequency);
 503
 504         if ((p->frequency < fe->ops.info.frequency_min)
 505             || (p->frequency > fe->ops.info.frequency_max))
 506                 return -EINVAL;
 507
 508         if ((p->inversion < INVERSION_OFF)
 509             || (p->inversion > INVERSION_ON))
 510                 return -EINVAL;
 511
 512         if ((p->u.qpsk.symbol_rate < fe->ops.info.symbol_rate_min)
 513             || (p->u.qpsk.symbol_rate > fe->ops.info.symbol_rate_max))
 514                 return -EINVAL;
 515
 516         if ((p->u.qpsk.fec_inner < FEC_NONE)
 517             || (p->u.qpsk.fec_inner > FEC_AUTO))
 518                 return -EINVAL;
 519
 520         if ((p->u.qpsk.fec_inner == FEC_4_5)
 521             || (p->u.qpsk.fec_inner == FEC_8_9))
 522                 return -EINVAL;
 523
 524         switch (state->id) {
 525         case ID_VP310:
 526         /* For now we will do this only for the VP310.
 527          * It should be better for the mt312 as well,
 528          * but tuning will be slower. ACCJr 09/29/03
 529          */
 530                 ret = mt312_readreg(state, CONFIG, &config_val);
 531                 if (ret < 0)
 532                         return ret;
 533                 if (p->u.qpsk.symbol_rate >= 30000000) {
 534                         /* Note that 30MS/s should use 90MHz */
 535                         if ((config_val & 0x0c) == 0x08) {
 536                                 /* We are running 60MHz */
 537                                 state->frequency = 90;
 538                                 ret = mt312_initfe(fe);
 539                                 if (ret < 0)
 540                                         return ret;
 541                         }
 542                 } else {
 543                         if ((config_val & 0x0c) == 0x0C) {
 544                                 /* We are running 90MHz */
 545                                 state->frequency = 60;
 546                                 ret = mt312_initfe(fe);
 547                                 if (ret < 0)
 548                                         return ret;
 549                         }
 550                 }
 551                 break;
 552
 553         case ID_MT312:
 554                 break;
 555
 556         default:
 557                 return -EINVAL;
 558         }
 559
 560         if (fe->ops.tuner_ops.set_params) {
 561                 fe->ops.tuner_ops.set_params(fe, p);
 562                 if (fe->ops.i2c_gate_ctrl)
 563                         fe->ops.i2c_gate_ctrl(fe, 0);
 564         }
 565
 566         /* sr = (u16)(sr * 256.0 / 1000000.0) */
 567         sr = mt312_div(p->u.qpsk.symbol_rate * 4, 15625);
 568
 569         /* SYM_RATE */
 570         buf[0] = (sr >> 8) & 0x3f;
 571         buf[1] = (sr >> 0) & 0xff;
 572
 573         /* VIT_MODE */
 574         buf[2] = inv_tab[p->inversion] | fec_tab[p->u.qpsk.fec_inner];
 575
 576         /* QPSK_CTRL */
 577         buf[3] = 0x40;          /* swap I and Q before QPSK demodulation */
 578
 579         if (p->u.qpsk.symbol_rate < 10000000)
 580                 buf[3] |= 0x04; /* use afc mode */
 581
 582         /* GO */
 583         buf[4] = 0x01;
 584
 585         ret = mt312_write(state, SYM_RATE_H, buf, sizeof(buf));
 586         if (ret < 0)
 587                 return ret;
 588
 589         mt312_reset(state, 0);
 590
 591         return 0;
 592 }
 593
 594 static int mt312_get_frontend(struct dvb_frontend *fe,
 595                               struct dvb_frontend_parameters *p)
 596 {
 597         struct mt312_state *state = fe->demodulator_priv;
 598         int ret;
 599
 600         ret = mt312_get_inversion(state, &p->inversion);
 601         if (ret < 0)
 602                 return ret;
 603
 604         ret = mt312_get_symbol_rate(state, &p->u.qpsk.symbol_rate);
 605         if (ret < 0)
 606                 return ret;
 607
 608         ret = mt312_get_code_rate(state, &p->u.qpsk.fec_inner);
 609         if (ret < 0)
 610                 return ret;
 611
 612         return 0;
 613 }
 614
 615 static int mt312_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
 616 {
 617         struct mt312_state *state = fe->demodulator_priv;
 618
 619         if (enable) {
 620                 return mt312_writereg(state, GPP_CTRL, 0x40);
 621         } else {
 622                 return mt312_writereg(state, GPP_CTRL, 0x00);
 623         }
 624 }
 625
 626 static int mt312_sleep(struct dvb_frontend *fe)
 627 {
 628         struct mt312_state *state = fe->demodulator_priv;
 629         int ret;
 630         u8 config;
 631
 632         /* reset all registers to defaults */
 633         ret = mt312_reset(state, 1);
 634         if (ret < 0)
 635                 return ret;
 636
 637         ret = mt312_readreg(state, CONFIG, &config);
 638         if (ret < 0)
 639                 return ret;
 640
 641         /* enter standby */
 642         ret = mt312_writereg(state, CONFIG, config & 0x7f);
 643         if (ret < 0)
 644                 return ret;
 645
 646         return 0;
 647 }
 648
 649 static int mt312_get_tune_settings(struct dvb_frontend *fe,
 650                 struct dvb_frontend_tune_settings *fesettings)
 651 {
 652         fesettings->min_delay_ms = 50;
 653         fesettings->step_size = 0;
 654         fesettings->max_drift = 0;
 655         return 0;
 656 }
 657
 658 static void mt312_release(struct dvb_frontend *fe)
 659 {
 660         struct mt312_state *state = fe->demodulator_priv;
 661         kfree(state);
 662 }
 663
 664 static struct dvb_frontend_ops vp310_mt312_ops = {
 665
 666         .info = {
 667                 .name = "Zarlink ???? DVB-S",
 668                 .type = FE_QPSK,
 669                 .frequency_min = 950000,
 670                 .frequency_max = 2150000,
 671                 .frequency_stepsize = (MT312_PLL_CLK / 1000) / 128,
 672                 .symbol_rate_min = MT312_SYS_CLK / 128,
 673                 .symbol_rate_max = MT312_SYS_CLK / 2,
 674                 .caps =
 675                     FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
 676                     FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
 677                     FE_CAN_FEC_AUTO | FE_CAN_QPSK | FE_CAN_MUTE_TS |
 678                     FE_CAN_RECOVER
 679         },
 680
 681         .release = mt312_release,
 682
 683         .init = mt312_initfe,
 684         .sleep = mt312_sleep,
 685         .i2c_gate_ctrl = mt312_i2c_gate_ctrl,
 686
 687         .set_frontend = mt312_set_frontend,
 688         .get_frontend = mt312_get_frontend,
 689         .get_tune_settings = mt312_get_tune_settings,
 690
 691         .read_status = mt312_read_status,
 692         .read_ber = mt312_read_ber,
 693         .read_signal_strength = mt312_read_signal_strength,
 694         .read_snr = mt312_read_snr,
 695         .read_ucblocks = mt312_read_ucblocks,
 696
 697         .diseqc_send_master_cmd = mt312_send_master_cmd,
 698         .diseqc_send_burst = mt312_send_burst,
 699         .set_tone = mt312_set_tone,
 700         .set_voltage = mt312_set_voltage,
 701 };
 702
 703 struct dvb_frontend *vp310_mt312_attach(const struct mt312_config *config,
 704                                         struct i2c_adapter *i2c)
 705 {
 706         struct mt312_state *state = NULL;
 707
 708         /* allocate memory for the internal state */
 709         state = kmalloc(sizeof(struct mt312_state), GFP_KERNEL);
 710         if (state == NULL)
 711                 goto error;
 712
 713         /* setup the state */
 714         state->config = config;
 715         state->i2c = i2c;
 716
 717         /* check if the demod is there */
 718         if (mt312_readreg(state, ID, &state->id) < 0)
 719                 goto error;
 720
 721         /* create dvb_frontend */
 722         memcpy(&state->frontend.ops, &vp310_mt312_ops,
 723                 sizeof(struct dvb_frontend_ops));
 724         state->frontend.demodulator_priv = state;
 725
 726         switch (state->id) {
 727         case ID_VP310:
 728                 strcpy(state->frontend.ops.info.name, "Zarlink VP310 DVB-S");
 729                 state->frequency = 90;
 730                 break;
 731         case ID_MT312:
 732                 strcpy(state->frontend.ops.info.name, "Zarlink MT312 DVB-S");
 733                 state->frequency = 60;
 734                 break;
 735         default:
 736                 printk(KERN_WARNING "Only Zarlink VP310/MT312"
 737                         " are supported chips.\n");
 738                 goto error;
 739         }
 740
 741         return &state->frontend;
 742
 743 error:
 744         kfree(state);
 745         return NULL;
 746 }
 747 EXPORT_SYMBOL(vp310_mt312_attach);
 748
 749 module_param(debug, int, 0644);
 750 MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
 751
 752 MODULE_DESCRIPTION("Zarlink VP310/MT312 DVB-S Demodulator driver");
 753 MODULE_AUTHOR("Andreas Oberritter <obi@linuxtv.org>");
 754 MODULE_LICENSE("GPL");
 755