drivers/net/bnx2x.h

   1 /* bnx2x.h: Broadcom Everest network driver.
   2  *
   3 <<<<<<< HEAD:drivers/net/bnx2x.h
   4  * Copyright (c) 2007 Broadcom Corporation
   5 =======
   6  * Copyright (c) 2007-2008 Broadcom Corporation
   7 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/net/bnx2x.h
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation.
  12  *
  13  * Written by: Eliezer Tamir <eliezert@broadcom.com>
  14  * Based on code from Michael Chan's bnx2 driver
  15  */
  16
  17 #ifndef BNX2X_H
  18 #define BNX2X_H
  19
  20 /* error/debug prints */
  21
  22 #define DRV_MODULE_NAME         "bnx2x"
  23 #define PFX DRV_MODULE_NAME     ": "
  24
  25 /* for messages that are currently off */
  26 #define BNX2X_MSG_OFF                   0
  27 #define BNX2X_MSG_MCP                   0x10000 /* was: NETIF_MSG_HW */
  28 #define BNX2X_MSG_STATS                 0x20000 /* was: NETIF_MSG_TIMER */
  29 #define NETIF_MSG_NVM                   0x40000 /* was: NETIF_MSG_HW */
  30 #define NETIF_MSG_DMAE                  0x80000 /* was: NETIF_MSG_HW */
  31 <<<<<<< HEAD:drivers/net/bnx2x.h
  32 =======
  33 #define BNX2X_MSG_SP                    0x100000 /* was: NETIF_MSG_INTR */
  34 #define BNX2X_MSG_FP                    0x200000 /* was: NETIF_MSG_INTR */
  35 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/net/bnx2x.h
  36
  37 #define DP_LEVEL                        KERN_NOTICE     /* was: KERN_DEBUG */
  38
  39 /* regular debug print */
  40 #define DP(__mask, __fmt, __args...) do { \
  41         if (bp->msglevel & (__mask)) \
  42                 printk(DP_LEVEL "[%s:%d(%s)]" __fmt, __FUNCTION__, \
  43                 __LINE__, bp->dev?(bp->dev->name):"?", ##__args); \
  44         } while (0)
  45
  46 /* for errors (never masked) */
  47 #define BNX2X_ERR(__fmt, __args...) do { \
  48         printk(KERN_ERR "[%s:%d(%s)]" __fmt, __FUNCTION__, \
  49                 __LINE__, bp->dev?(bp->dev->name):"?", ##__args); \
  50         } while (0)
  51
  52 <<<<<<< HEAD:drivers/net/bnx2x.h
  53 =======
  54 /* for logging (never masked) */
  55 #define BNX2X_LOG(__fmt, __args...) do { \
  56         printk(KERN_NOTICE "[%s:%d(%s)]" __fmt, __FUNCTION__, \
  57                 __LINE__, bp->dev?(bp->dev->name):"?", ##__args); \
  58         } while (0)
  59
  60 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/net/bnx2x.h
  61 /* before we have a dev->name use dev_info() */
  62 #define BNX2X_DEV_INFO(__fmt, __args...) do { \
  63         if (bp->msglevel & NETIF_MSG_PROBE) \
  64                 dev_info(&bp->pdev->dev, __fmt, ##__args); \
  65         } while (0)
  66
  67
  68 #ifdef BNX2X_STOP_ON_ERROR
  69 #define bnx2x_panic() do { \
  70                 bp->panic = 1; \
  71                 BNX2X_ERR("driver assert\n"); \
  72                 bnx2x_disable_int(bp); \
  73                 bnx2x_panic_dump(bp); \
  74         } while (0)
  75 #else
  76 #define bnx2x_panic() do { \
  77                 BNX2X_ERR("driver assert\n"); \
  78                 bnx2x_panic_dump(bp); \
  79         } while (0)
  80 #endif
  81
  82
  83 #define U64_LO(x)                       (((u64)x) & 0xffffffff)
  84 #define U64_HI(x)                       (((u64)x) >> 32)
  85 #define HILO_U64(hi, lo)                (((u64)hi << 32) + lo)
  86
  87
  88 #define REG_ADDR(bp, offset)            (bp->regview + offset)
  89
  90 #define REG_RD(bp, offset)              readl(REG_ADDR(bp, offset))
  91 #define REG_RD8(bp, offset)             readb(REG_ADDR(bp, offset))
  92 #define REG_RD64(bp, offset)            readq(REG_ADDR(bp, offset))
  93
  94 #define REG_WR(bp, offset, val)         writel((u32)val, REG_ADDR(bp, offset))
  95 #define REG_WR8(bp, offset, val)        writeb((u8)val, REG_ADDR(bp, offset))
  96 #define REG_WR16(bp, offset, val)       writew((u16)val, REG_ADDR(bp, offset))
  97 #define REG_WR32(bp, offset, val)       REG_WR(bp, offset, val)
  98
  99 #define REG_RD_IND(bp, offset)          bnx2x_reg_rd_ind(bp, offset)
 100 #define REG_WR_IND(bp, offset, val)     bnx2x_reg_wr_ind(bp, offset, val)
 101
 102 #define REG_WR_DMAE(bp, offset, val, len32) \
 103         do { \
 104                 memcpy(bnx2x_sp(bp, wb_data[0]), val, len32 * 4); \
 105                 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \
 106                                  offset, len32); \
 107         } while (0)
 108
 109 #define SHMEM_RD(bp, type) \
 110         REG_RD(bp, bp->shmem_base + offsetof(struct shmem_region, type))
 111 #define SHMEM_WR(bp, type, val) \
 112         REG_WR(bp, bp->shmem_base + offsetof(struct shmem_region, type), val)
 113
 114 #define NIG_WR(reg, val)        REG_WR(bp, reg, val)
 115 #define EMAC_WR(reg, val)       REG_WR(bp, emac_base + reg, val)
 116 #define BMAC_WR(reg, val)       REG_WR(bp, GRCBASE_NIG + bmac_addr + reg, val)
 117
 118
 119 #define for_each_queue(bp, var) for (var = 0; var < bp->num_queues; var++)
 120
 121 #define for_each_nondefault_queue(bp, var) \
 122                                 for (var = 1; var < bp->num_queues; var++)
 123 #define is_multi(bp)            (bp->num_queues > 1)
 124
 125
 126 struct regp {
 127         u32 lo;
 128         u32 hi;
 129 };
 130
 131 struct bmac_stats {
 132         struct regp tx_gtpkt;
 133         struct regp tx_gtxpf;
 134         struct regp tx_gtfcs;
 135         struct regp tx_gtmca;
 136         struct regp tx_gtgca;
 137         struct regp tx_gtfrg;
 138         struct regp tx_gtovr;
 139         struct regp tx_gt64;
 140         struct regp tx_gt127;
 141         struct regp tx_gt255;   /* 10 */
 142         struct regp tx_gt511;
 143         struct regp tx_gt1023;
 144         struct regp tx_gt1518;
 145         struct regp tx_gt2047;
 146         struct regp tx_gt4095;
 147         struct regp tx_gt9216;
 148         struct regp tx_gt16383;
 149         struct regp tx_gtmax;
 150         struct regp tx_gtufl;
 151         struct regp tx_gterr;   /* 20 */
 152         struct regp tx_gtbyt;
 153
 154         struct regp rx_gr64;
 155         struct regp rx_gr127;
 156         struct regp rx_gr255;
 157         struct regp rx_gr511;
 158         struct regp rx_gr1023;
 159         struct regp rx_gr1518;
 160         struct regp rx_gr2047;
 161         struct regp rx_gr4095;
 162         struct regp rx_gr9216;  /* 30 */
 163         struct regp rx_gr16383;
 164         struct regp rx_grmax;
 165         struct regp rx_grpkt;
 166         struct regp rx_grfcs;
 167         struct regp rx_grmca;
 168         struct regp rx_grbca;
 169         struct regp rx_grxcf;
 170         struct regp rx_grxpf;
 171         struct regp rx_grxuo;
 172         struct regp rx_grjbr;   /* 40 */
 173         struct regp rx_grovr;
 174         struct regp rx_grflr;
 175         struct regp rx_grmeg;
 176         struct regp rx_grmeb;
 177         struct regp rx_grbyt;
 178         struct regp rx_grund;
 179         struct regp rx_grfrg;
 180         struct regp rx_grerb;
 181         struct regp rx_grfre;
 182         struct regp rx_gripj;   /* 50 */
 183 };
 184
 185 struct emac_stats {
 186         u32 rx_ifhcinoctets                        ;
 187         u32 rx_ifhcinbadoctets                     ;
 188         u32 rx_etherstatsfragments                 ;
 189         u32 rx_ifhcinucastpkts                     ;
 190         u32 rx_ifhcinmulticastpkts                 ;
 191         u32 rx_ifhcinbroadcastpkts                 ;
 192         u32 rx_dot3statsfcserrors                  ;
 193         u32 rx_dot3statsalignmenterrors            ;
 194         u32 rx_dot3statscarriersenseerrors         ;
 195         u32 rx_xonpauseframesreceived              ;    /* 10 */
 196         u32 rx_xoffpauseframesreceived             ;
 197         u32 rx_maccontrolframesreceived            ;
 198         u32 rx_xoffstateentered                    ;
 199         u32 rx_dot3statsframestoolong              ;
 200         u32 rx_etherstatsjabbers                   ;
 201         u32 rx_etherstatsundersizepkts             ;
 202         u32 rx_etherstatspkts64octets              ;
 203         u32 rx_etherstatspkts65octetsto127octets   ;
 204         u32 rx_etherstatspkts128octetsto255octets  ;
 205         u32 rx_etherstatspkts256octetsto511octets  ;    /* 20 */
 206         u32 rx_etherstatspkts512octetsto1023octets ;
 207         u32 rx_etherstatspkts1024octetsto1522octets;
 208         u32 rx_etherstatspktsover1522octets        ;
 209
 210         u32 rx_falsecarriererrors                  ;
 211
 212         u32 tx_ifhcoutoctets                       ;
 213         u32 tx_ifhcoutbadoctets                    ;
 214         u32 tx_etherstatscollisions                ;
 215         u32 tx_outxonsent                          ;
 216         u32 tx_outxoffsent                         ;
 217         u32 tx_flowcontroldone                     ;    /* 30 */
 218         u32 tx_dot3statssinglecollisionframes      ;
 219         u32 tx_dot3statsmultiplecollisionframes    ;
 220         u32 tx_dot3statsdeferredtransmissions      ;
 221         u32 tx_dot3statsexcessivecollisions        ;
 222         u32 tx_dot3statslatecollisions             ;
 223         u32 tx_ifhcoutucastpkts                    ;
 224         u32 tx_ifhcoutmulticastpkts                ;
 225         u32 tx_ifhcoutbroadcastpkts                ;
 226         u32 tx_etherstatspkts64octets              ;
 227         u32 tx_etherstatspkts65octetsto127octets   ;    /* 40 */
 228         u32 tx_etherstatspkts128octetsto255octets  ;
 229         u32 tx_etherstatspkts256octetsto511octets  ;
 230         u32 tx_etherstatspkts512octetsto1023octets ;
 231         u32 tx_etherstatspkts1024octetsto1522octet ;
 232         u32 tx_etherstatspktsover1522octets        ;
 233         u32 tx_dot3statsinternalmactransmiterrors  ;    /* 46 */
 234 };
 235
 236 union mac_stats {
 237         struct emac_stats emac;
 238         struct bmac_stats bmac;
 239 };
 240
 241 struct nig_stats {
 242         u32 brb_discard;
 243         u32 brb_packet;
 244         u32 brb_truncate;
 245         u32 flow_ctrl_discard;
 246         u32 flow_ctrl_octets;
 247         u32 flow_ctrl_packet;
 248         u32 mng_discard;
 249         u32 mng_octet_inp;
 250         u32 mng_octet_out;
 251         u32 mng_packet_inp;
 252         u32 mng_packet_out;
 253         u32 pbf_octets;
 254         u32 pbf_packet;
 255         u32 safc_inp;
 256         u32 done;
 257         u32 pad;
 258 };
 259
 260 struct bnx2x_eth_stats {
 261         u32 pad;        /* to make long counters u64 aligned */
 262         u32 mac_stx_start;
 263         u32 total_bytes_received_hi;
 264         u32 total_bytes_received_lo;
 265         u32 total_bytes_transmitted_hi;
 266         u32 total_bytes_transmitted_lo;
 267         u32 total_unicast_packets_received_hi;
 268         u32 total_unicast_packets_received_lo;
 269         u32 total_multicast_packets_received_hi;
 270         u32 total_multicast_packets_received_lo;
 271         u32 total_broadcast_packets_received_hi;
 272         u32 total_broadcast_packets_received_lo;
 273         u32 total_unicast_packets_transmitted_hi;
 274         u32 total_unicast_packets_transmitted_lo;
 275         u32 total_multicast_packets_transmitted_hi;
 276         u32 total_multicast_packets_transmitted_lo;
 277         u32 total_broadcast_packets_transmitted_hi;
 278         u32 total_broadcast_packets_transmitted_lo;
 279         u32 crc_receive_errors;
 280         u32 alignment_errors;
 281         u32 false_carrier_detections;
 282         u32 runt_packets_received;
 283         u32 jabber_packets_received;
 284         u32 pause_xon_frames_received;
 285         u32 pause_xoff_frames_received;
 286         u32 pause_xon_frames_transmitted;
 287         u32 pause_xoff_frames_transmitted;
 288         u32 single_collision_transmit_frames;
 289         u32 multiple_collision_transmit_frames;
 290         u32 late_collision_frames;
 291         u32 excessive_collision_frames;
 292         u32 control_frames_received;
 293         u32 frames_received_64_bytes;
 294         u32 frames_received_65_127_bytes;
 295         u32 frames_received_128_255_bytes;
 296         u32 frames_received_256_511_bytes;
 297         u32 frames_received_512_1023_bytes;
 298         u32 frames_received_1024_1522_bytes;
 299         u32 frames_received_1523_9022_bytes;
 300         u32 frames_transmitted_64_bytes;
 301         u32 frames_transmitted_65_127_bytes;
 302         u32 frames_transmitted_128_255_bytes;
 303         u32 frames_transmitted_256_511_bytes;
 304         u32 frames_transmitted_512_1023_bytes;
 305         u32 frames_transmitted_1024_1522_bytes;
 306         u32 frames_transmitted_1523_9022_bytes;
 307         u32 valid_bytes_received_hi;
 308         u32 valid_bytes_received_lo;
 309         u32 error_runt_packets_received;
 310         u32 error_jabber_packets_received;
 311         u32 mac_stx_end;
 312
 313         u32 pad2;
 314         u32 stat_IfHCInBadOctets_hi;
 315         u32 stat_IfHCInBadOctets_lo;
 316         u32 stat_IfHCOutBadOctets_hi;
 317         u32 stat_IfHCOutBadOctets_lo;
 318         u32 stat_Dot3statsFramesTooLong;
 319         u32 stat_Dot3statsInternalMacTransmitErrors;
 320         u32 stat_Dot3StatsCarrierSenseErrors;
 321         u32 stat_Dot3StatsDeferredTransmissions;
 322         u32 stat_FlowControlDone;
 323         u32 stat_XoffStateEntered;
 324
 325         u32 x_total_sent_bytes_hi;
 326         u32 x_total_sent_bytes_lo;
 327         u32 x_total_sent_pkts;
 328
 329         u32 t_rcv_unicast_bytes_hi;
 330         u32 t_rcv_unicast_bytes_lo;
 331         u32 t_rcv_broadcast_bytes_hi;
 332         u32 t_rcv_broadcast_bytes_lo;
 333         u32 t_rcv_multicast_bytes_hi;
 334         u32 t_rcv_multicast_bytes_lo;
 335         u32 t_total_rcv_pkt;
 336
 337         u32 checksum_discard;
 338         u32 packets_too_big_discard;
 339         u32 no_buff_discard;
 340         u32 ttl0_discard;
 341         u32 mac_discard;
 342         u32 mac_filter_discard;
 343         u32 xxoverflow_discard;
 344         u32 brb_truncate_discard;
 345
 346         u32 brb_discard;
 347         u32 brb_packet;
 348         u32 brb_truncate;
 349         u32 flow_ctrl_discard;
 350         u32 flow_ctrl_octets;
 351         u32 flow_ctrl_packet;
 352         u32 mng_discard;
 353         u32 mng_octet_inp;
 354         u32 mng_octet_out;
 355         u32 mng_packet_inp;
 356         u32 mng_packet_out;
 357         u32 pbf_octets;
 358         u32 pbf_packet;
 359         u32 safc_inp;
 360         u32 driver_xoff;
 361         u32 number_of_bugs_found_in_stats_spec; /* just kidding */
 362 };
 363
 364 #define MAC_STX_NA                      0xffffffff
 365
 366 #ifdef BNX2X_MULTI
 367 #define MAX_CONTEXT                     16
 368 #else
 369 #define MAX_CONTEXT                     1
 370 #endif
 371
 372 union cdu_context {
 373         struct eth_context eth;
 374         char pad[1024];
 375 };
 376
 377 #define MAX_DMAE_C                      5
 378
 379 /* DMA memory not used in fastpath */
 380 struct bnx2x_slowpath {
 381         union cdu_context               context[MAX_CONTEXT];
 382         struct eth_stats_query          fw_stats;
 383         struct mac_configuration_cmd    mac_config;
 384         struct mac_configuration_cmd    mcast_config;
 385
 386         /* used by dmae command executer */
 387         struct dmae_command             dmae[MAX_DMAE_C];
 388
 389         union mac_stats                 mac_stats;
 390         struct nig_stats                nig;
 391         struct bnx2x_eth_stats          eth_stats;
 392
 393         u32                             wb_comp;
 394 #define BNX2X_WB_COMP_VAL               0xe0d0d0ae
 395         u32                             wb_data[4];
 396 };
 397
 398 #define bnx2x_sp(bp, var)               (&bp->slowpath->var)
 399 #define bnx2x_sp_check(bp, var) ((bp->slowpath) ? (&bp->slowpath->var) : NULL)
 400 #define bnx2x_sp_mapping(bp, var) \
 401                 (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var))
 402
 403
 404 struct sw_rx_bd {
 405         struct sk_buff  *skb;
 406         DECLARE_PCI_UNMAP_ADDR(mapping)
 407 };
 408
 409 struct sw_tx_bd {
 410         struct sk_buff  *skb;
 411         u16             first_bd;
 412 };
 413
 414 struct bnx2x_fastpath {
 415
 416         struct napi_struct      napi;
 417
 418         struct host_status_block *status_blk;
 419         dma_addr_t              status_blk_mapping;
 420
 421         struct eth_tx_db_data   *hw_tx_prods;
 422         dma_addr_t              tx_prods_mapping;
 423
 424         struct sw_tx_bd         *tx_buf_ring;
 425
 426         struct eth_tx_bd        *tx_desc_ring;
 427         dma_addr_t              tx_desc_mapping;
 428
 429         struct sw_rx_bd         *rx_buf_ring;
 430
 431         struct eth_rx_bd        *rx_desc_ring;
 432         dma_addr_t              rx_desc_mapping;
 433
 434         union eth_rx_cqe        *rx_comp_ring;
 435         dma_addr_t              rx_comp_mapping;
 436
 437         int                     state;
 438 #define BNX2X_FP_STATE_CLOSED           0
 439 #define BNX2X_FP_STATE_IRQ              0x80000
 440 #define BNX2X_FP_STATE_OPENING          0x90000
 441 #define BNX2X_FP_STATE_OPEN             0xa0000
 442 #define BNX2X_FP_STATE_HALTING          0xb0000
 443 #define BNX2X_FP_STATE_HALTED           0xc0000
 444 <<<<<<< HEAD:drivers/net/bnx2x.h
 445 #define BNX2X_FP_STATE_DELETED          0xd0000
 446 #define BNX2X_FP_STATE_CLOSE_IRQ        0xe0000
 447 =======
 448 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/net/bnx2x.h
 449
 450         int                     index;
 451
 452         u16                     tx_pkt_prod;
 453         u16                     tx_pkt_cons;
 454         u16                     tx_bd_prod;
 455         u16                     tx_bd_cons;
 456         u16                     *tx_cons_sb;
 457
 458         u16                     fp_c_idx;
 459         u16                     fp_u_idx;
 460
 461         u16                     rx_bd_prod;
 462         u16                     rx_bd_cons;
 463         u16                     rx_comp_prod;
 464         u16                     rx_comp_cons;
 465         u16                     *rx_cons_sb;
 466
 467         unsigned long           tx_pkt,
 468                                 rx_pkt,
 469                                 rx_calls;
 470
 471         struct bnx2x            *bp; /* parent */
 472 };
 473
 474 #define bnx2x_fp(bp, nr, var)           (bp->fp[nr].var)
 475
 476
 477 /* attn group wiring */
 478 #define MAX_DYNAMIC_ATTN_GRPS           8
 479
 480 struct attn_route {
 481         u32     sig[4];
 482 };
 483
 484 struct bnx2x {
 485         /* Fields used in the tx and intr/napi performance paths
 486          * are grouped together in the beginning of the structure
 487          */
 488         struct bnx2x_fastpath   *fp;
 489         void __iomem            *regview;
 490         void __iomem            *doorbells;
 491
 492         struct net_device       *dev;
 493         struct pci_dev          *pdev;
 494
 495         atomic_t                intr_sem;
 496         struct msix_entry       msix_table[MAX_CONTEXT+1];
 497
 498         int                     tx_ring_size;
 499
 500 #ifdef BCM_VLAN
 501         struct vlan_group       *vlgrp;
 502 #endif
 503
 504         u32                     rx_csum;
 505         u32                     rx_offset;
 506         u32                     rx_buf_use_size;        /* useable size */
 507         u32                     rx_buf_size;            /* with alignment */
 508 #define ETH_OVREHEAD                    (ETH_HLEN + 8)  /* 8 for CRC + VLAN */
 509 #define ETH_MIN_PACKET_SIZE             60
 510 #define ETH_MAX_PACKET_SIZE             1500
 511 #define ETH_MAX_JUMBO_PACKET_SIZE       9600
 512
 513         struct host_def_status_block *def_status_blk;
 514 #define DEF_SB_ID               16
 515         u16                     def_c_idx;
 516         u16                     def_u_idx;
 517         u16                     def_t_idx;
 518         u16                     def_x_idx;
 519         u16                     def_att_idx;
 520         u32                     attn_state;
 521         struct attn_route       attn_group[MAX_DYNAMIC_ATTN_GRPS];
 522         u32                     aeu_mask;
 523         u32                     nig_mask;
 524
 525         /* slow path ring */
 526         struct eth_spe          *spq;
 527         dma_addr_t              spq_mapping;
 528         u16                     spq_prod_idx;
 529 <<<<<<< HEAD:drivers/net/bnx2x.h
 530         u16                     dsb_sp_prod_idx;
 531 =======
 532 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/net/bnx2x.h
 533         struct eth_spe          *spq_prod_bd;
 534         struct eth_spe          *spq_last_bd;
 535         u16                     *dsb_sp_prod;
 536         u16                     spq_left; /* serialize spq */
 537         spinlock_t              spq_lock;
 538
 539         /* Flag for marking that there is either
 540          * STAT_QUERY or CFC DELETE ramrod pending
 541          */
 542         u8                      stat_pending;
 543
 544 <<<<<<< HEAD:drivers/net/bnx2x.h
 545         /* End of fileds used in the performance code paths */
 546 =======
 547         /* End of fields used in the performance code paths */
 548 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/net/bnx2x.h
 549
 550         int                     panic;
 551         int                     msglevel;
 552
 553         u32                     flags;
 554 #define PCIX_FLAG                       1
 555 #define PCI_32BIT_FLAG                  2
 556 #define ONE_TDMA_FLAG                   4       /* no longer used */
 557 #define NO_WOL_FLAG                     8
 558 #define USING_DAC_FLAG                  0x10
 559 #define USING_MSIX_FLAG                 0x20
 560 #define ASF_ENABLE_FLAG                 0x40
 561
 562         int                     port;
 563
 564         int                     pm_cap;
 565         int                     pcie_cap;
 566
 567         /* Used to synchronize phy accesses */
 568         spinlock_t              phy_lock;
 569
 570         struct work_struct      reset_task;
 571 <<<<<<< HEAD:drivers/net/bnx2x.h
 572         u16                     in_reset_task;
 573
 574 =======
 575 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/net/bnx2x.h
 576         struct work_struct      sp_task;
 577
 578         struct timer_list       timer;
 579         int                     timer_interval;
 580         int                     current_interval;
 581
 582         u32                     shmem_base;
 583
 584         u32                     chip_id;
 585 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
 586 #define CHIP_ID(bp)                     (((bp)->chip_id) & 0xfffffff0)
 587
 588 #define CHIP_NUM(bp)                    (((bp)->chip_id) & 0xffff0000)
 589 <<<<<<< HEAD:drivers/net/bnx2x.h
 590 #define CHIP_NUM_5710                   0x57100000
 591 =======
 592 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/net/bnx2x.h
 593
 594 #define CHIP_REV(bp)                    (((bp)->chip_id) & 0x0000f000)
 595 #define CHIP_REV_Ax                     0x00000000
 596 #define CHIP_REV_Bx                     0x00001000
 597 #define CHIP_REV_Cx                     0x00002000
 598 #define CHIP_REV_EMUL                   0x0000e000
 599 #define CHIP_REV_FPGA                   0x0000f000
 600 #define CHIP_REV_IS_SLOW(bp)            ((CHIP_REV(bp) == CHIP_REV_EMUL) || \
 601                                          (CHIP_REV(bp) == CHIP_REV_FPGA))
 602
 603 #define CHIP_METAL(bp)                  (((bp)->chip_id) & 0x00000ff0)
 604 #define CHIP_BOND_ID(bp)                (((bp)->chip_id) & 0x0000000f)
 605
 606         u16                     fw_seq;
 607         u16                     fw_drv_pulse_wr_seq;
 608         u32                     fw_mb;
 609
 610         u32                     hw_config;
 611 <<<<<<< HEAD:drivers/net/bnx2x.h
 612         u32                     serdes_config;
 613 =======
 614         u32                     board;
 615         u32                     serdes_config;
 616 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/net/bnx2x.h
 617         u32                     lane_config;
 618         u32                     ext_phy_config;
 619 #define XGXS_EXT_PHY_TYPE(bp)           (bp->ext_phy_config & \
 620                                          PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK)
 621 #define SERDES_EXT_PHY_TYPE(bp)         (bp->ext_phy_config & \
 622                                          PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK)
 623
 624         u32                     speed_cap_mask;
 625         u32                     link_config;
 626 #define SWITCH_CFG_1G                   PORT_FEATURE_CON_SWITCH_1G_SWITCH
 627 #define SWITCH_CFG_10G                  PORT_FEATURE_CON_SWITCH_10G_SWITCH
 628 #define SWITCH_CFG_AUTO_DETECT          PORT_FEATURE_CON_SWITCH_AUTO_DETECT
 629 #define SWITCH_CFG_ONE_TIME_DETECT      \
 630                                 PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT
 631
 632         u8                      ser_lane;
 633         u8                      rx_lane_swap;
 634         u8                      tx_lane_swap;
 635
 636         u8                      link_up;
 637 <<<<<<< HEAD:drivers/net/bnx2x.h
 638 =======
 639         u8                      phy_link_up;
 640 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/net/bnx2x.h
 641
 642         u32                     supported;
 643 /* link settings - missing defines */
 644 #define SUPPORTED_2500baseT_Full        (1 << 15)
 645 <<<<<<< HEAD:drivers/net/bnx2x.h
 646 #define SUPPORTED_CX4                   (1 << 16)
 647 =======
 648 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/net/bnx2x.h
 649
 650         u32                     phy_flags;
 651 /*#define PHY_SERDES_FLAG                       0x1*/
 652 #define PHY_BMAC_FLAG                   0x2
 653 #define PHY_EMAC_FLAG                   0x4
 654 #define PHY_XGXS_FLAG                   0x8
 655 #define PHY_SGMII_FLAG                  0x10
 656 #define PHY_INT_MODE_MASK_FLAG          0x300
 657 #define PHY_INT_MODE_AUTO_POLLING_FLAG  0x100
 658 #define PHY_INT_MODE_LINK_READY_FLAG    0x200
 659
 660         u32                     phy_addr;
 661         u32                     phy_id;
 662
 663         u32                     autoneg;
 664 #define AUTONEG_CL37                    SHARED_HW_CFG_AN_ENABLE_CL37
 665 #define AUTONEG_CL73                    SHARED_HW_CFG_AN_ENABLE_CL73
 666 #define AUTONEG_BAM                     SHARED_HW_CFG_AN_ENABLE_BAM
 667 #define AUTONEG_PARALLEL                \
 668                                 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
 669 #define AUTONEG_SGMII_FIBER_AUTODET     \
 670                                 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
 671 #define AUTONEG_REMOTE_PHY              SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
 672
 673         u32                     req_autoneg;
 674 #define AUTONEG_SPEED                   0x1
 675 #define AUTONEG_FLOW_CTRL               0x2
 676
 677         u32                     req_line_speed;
 678 /* link settings - missing defines */
 679 #define SPEED_12000                     12000
 680 #define SPEED_12500                     12500
 681 #define SPEED_13000                     13000
 682 #define SPEED_15000                     15000
 683 #define SPEED_16000                     16000
 684
 685         u32                     req_duplex;
 686         u32                     req_flow_ctrl;
 687 #define FLOW_CTRL_AUTO                  PORT_FEATURE_FLOW_CONTROL_AUTO
 688 #define FLOW_CTRL_TX                    PORT_FEATURE_FLOW_CONTROL_TX
 689 #define FLOW_CTRL_RX                    PORT_FEATURE_FLOW_CONTROL_RX
 690 #define FLOW_CTRL_BOTH                  PORT_FEATURE_FLOW_CONTROL_BOTH
 691 #define FLOW_CTRL_NONE                  PORT_FEATURE_FLOW_CONTROL_NONE
 692
 693 <<<<<<< HEAD:drivers/net/bnx2x.h
 694         u32                     pause_mode;
 695 #define PAUSE_NONE                      0
 696 #define PAUSE_SYMMETRIC                 1
 697 #define PAUSE_ASYMMETRIC                2
 698 #define PAUSE_BOTH                      3
 699
 700 =======
 701 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/net/bnx2x.h
 702         u32                     advertising;
 703 /* link settings - missing defines */
 704 #define ADVERTISED_2500baseT_Full       (1 << 15)
 705 <<<<<<< HEAD:drivers/net/bnx2x.h
 706 #define ADVERTISED_CX4                  (1 << 16)
 707 =======
 708 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/net/bnx2x.h
 709
 710         u32                     link_status;
 711         u32                     line_speed;
 712         u32                     duplex;
 713         u32                     flow_ctrl;
 714
 715         u32                     bc_ver;
 716
 717         int                     flash_size;
 718 #define NVRAM_1MB_SIZE                  0x20000 /* 1M bit in bytes */
 719 #define NVRAM_TIMEOUT_COUNT             30000
 720 #define NVRAM_PAGE_SIZE                 256
 721
 722 <<<<<<< HEAD:drivers/net/bnx2x.h
 723 =======
 724         u8                      wol;
 725
 726 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/net/bnx2x.h
 727         int                     rx_ring_size;
 728
 729         u16                     tx_quick_cons_trip_int;
 730         u16                     tx_quick_cons_trip;
 731         u16                     tx_ticks_int;
 732         u16                     tx_ticks;
 733
 734         u16                     rx_quick_cons_trip_int;
 735         u16                     rx_quick_cons_trip;
 736         u16                     rx_ticks_int;
 737         u16                     rx_ticks;
 738
 739         u32                     stats_ticks;
 740
 741         int                     state;
 742 #define BNX2X_STATE_CLOSED              0x0
 743 #define BNX2X_STATE_OPENING_WAIT4_LOAD  0x1000
 744 #define BNX2X_STATE_OPENING_WAIT4_PORT  0x2000
 745 #define BNX2X_STATE_OPEN                0x3000
 746 #define BNX2X_STATE_CLOSING_WAIT4_HALT  0x4000
 747 #define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000
 748 #define BNX2X_STATE_CLOSING_WAIT4_UNLOAD 0x6000
 749 #define BNX2X_STATE_ERROR               0xF000
 750
 751         int                     num_queues;
 752
 753         u32                     rx_mode;
 754 #define BNX2X_RX_MODE_NONE              0
 755 #define BNX2X_RX_MODE_NORMAL            1
 756 #define BNX2X_RX_MODE_ALLMULTI          2
 757 #define BNX2X_RX_MODE_PROMISC           3
 758 #define BNX2X_MAX_MULTICAST             64
 759 #define BNX2X_MAX_EMUL_MULTI            16
 760
 761         dma_addr_t              def_status_blk_mapping;
 762
 763         struct bnx2x_slowpath   *slowpath;
 764         dma_addr_t              slowpath_mapping;
 765
 766 #ifdef BCM_ISCSI
 767         void                    *t1;
 768         dma_addr_t              t1_mapping;
 769         void                    *t2;
 770         dma_addr_t              t2_mapping;
 771         void                    *timers;
 772         dma_addr_t              timers_mapping;
 773         void                    *qm;
 774         dma_addr_t              qm_mapping;
 775 #endif
 776
 777         char                    *name;
 778 <<<<<<< HEAD:drivers/net/bnx2x.h
 779         u16                     bus_speed_mhz;
 780         u8                      wol;
 781         u8                      pad;
 782 =======
 783 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/net/bnx2x.h
 784
 785         /* used to synchronize stats collecting */
 786         int                     stats_state;
 787 #define STATS_STATE_DISABLE             0
 788 #define STATS_STATE_ENABLE              1
 789 #define STATS_STATE_STOP                2 /* stop stats on next iteration */
 790
 791         /* used by dmae command loader */
 792         struct dmae_command     dmae;
 793         int                     executer_idx;
 794
 795         u32                     old_brb_discard;
 796         struct bmac_stats       old_bmac;
 797         struct tstorm_per_client_stats old_tclient;
 798         struct z_stream_s       *strm;
 799         void                    *gunzip_buf;
 800         dma_addr_t              gunzip_mapping;
 801         int                     gunzip_outlen;
 802 #define FW_BUF_SIZE                     0x8000
 803
 804 };
 805
 806
 807 /* DMAE command defines */
 808 #define DMAE_CMD_SRC_PCI                0
 809 #define DMAE_CMD_SRC_GRC                DMAE_COMMAND_SRC
 810
 811 #define DMAE_CMD_DST_PCI                (1 << DMAE_COMMAND_DST_SHIFT)
 812 #define DMAE_CMD_DST_GRC                (2 << DMAE_COMMAND_DST_SHIFT)
 813
 814 #define DMAE_CMD_C_DST_PCI              0
 815 #define DMAE_CMD_C_DST_GRC              (1 << DMAE_COMMAND_C_DST_SHIFT)
 816
 817 #define DMAE_CMD_C_ENABLE               DMAE_COMMAND_C_TYPE_ENABLE
 818
 819 #define DMAE_CMD_ENDIANITY_NO_SWAP      (0 << DMAE_COMMAND_ENDIANITY_SHIFT)
 820 #define DMAE_CMD_ENDIANITY_B_SWAP       (1 << DMAE_COMMAND_ENDIANITY_SHIFT)
 821 #define DMAE_CMD_ENDIANITY_DW_SWAP      (2 << DMAE_COMMAND_ENDIANITY_SHIFT)
 822 #define DMAE_CMD_ENDIANITY_B_DW_SWAP    (3 << DMAE_COMMAND_ENDIANITY_SHIFT)
 823
 824 #define DMAE_CMD_PORT_0                 0
 825 #define DMAE_CMD_PORT_1                 DMAE_COMMAND_PORT
 826
 827 #define DMAE_CMD_SRC_RESET              DMAE_COMMAND_SRC_RESET
 828 #define DMAE_CMD_DST_RESET              DMAE_COMMAND_DST_RESET
 829
 830 #define DMAE_LEN32_MAX                  0x400
 831
 832
 833 /* MC hsi */
 834 #define RX_COPY_THRESH                  92
 835 #define BCM_PAGE_BITS                   12
 836 #define BCM_PAGE_SIZE                   (1 << BCM_PAGE_BITS)
 837
 838 #define NUM_TX_RINGS                    16
 839 #define TX_DESC_CNT             (BCM_PAGE_SIZE / sizeof(struct eth_tx_bd))
 840 #define MAX_TX_DESC_CNT                 (TX_DESC_CNT - 1)
 841 #define NUM_TX_BD                       (TX_DESC_CNT * NUM_TX_RINGS)
 842 #define MAX_TX_BD                       (NUM_TX_BD - 1)
 843 #define MAX_TX_AVAIL                    (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2)
 844 #define NEXT_TX_IDX(x)          ((((x) & MAX_TX_DESC_CNT) == \
 845                                  (MAX_TX_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
 846 #define TX_BD(x)                        ((x) & MAX_TX_BD)
 847 #define TX_BD_POFF(x)                   ((x) & MAX_TX_DESC_CNT)
 848
 849 /* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */
 850 #define NUM_RX_RINGS                    8
 851 #define RX_DESC_CNT             (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd))
 852 #define MAX_RX_DESC_CNT                 (RX_DESC_CNT - 2)
 853 #define RX_DESC_MASK                    (RX_DESC_CNT - 1)
 854 #define NUM_RX_BD                       (RX_DESC_CNT * NUM_RX_RINGS)
 855 #define MAX_RX_BD                       (NUM_RX_BD - 1)
 856 #define MAX_RX_AVAIL                    (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2)
 857 #define NEXT_RX_IDX(x)          ((((x) & RX_DESC_MASK) == \
 858                                  (MAX_RX_DESC_CNT - 1)) ? (x) + 3 : (x) + 1)
 859 #define RX_BD(x)                        ((x) & MAX_RX_BD)
 860
 861 #define NUM_RCQ_RINGS                   (NUM_RX_RINGS * 2)
 862 #define RCQ_DESC_CNT            (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe))
 863 #define MAX_RCQ_DESC_CNT                (RCQ_DESC_CNT - 1)
 864 #define NUM_RCQ_BD                      (RCQ_DESC_CNT * NUM_RCQ_RINGS)
 865 #define MAX_RCQ_BD                      (NUM_RCQ_BD - 1)
 866 #define MAX_RCQ_AVAIL                   (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2)
 867 #define NEXT_RCQ_IDX(x)         ((((x) & MAX_RCQ_DESC_CNT) == \
 868                                  (MAX_RCQ_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
 869 #define RCQ_BD(x)                       ((x) & MAX_RCQ_BD)
 870
 871
 872 /* used on a CID received from the HW */
 873 #define SW_CID(x)                       (le32_to_cpu(x) & \
 874                                          (COMMON_RAMROD_ETH_RX_CQE_CID >> 1))
 875 #define CQE_CMD(x)                      (le32_to_cpu(x) >> \
 876                                         COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
 877
 878 #define BD_UNMAP_ADDR(bd)               HILO_U64(le32_to_cpu((bd)->addr_hi), \
 879                                                  le32_to_cpu((bd)->addr_lo))
 880 #define BD_UNMAP_LEN(bd)                (le16_to_cpu((bd)->nbytes))
 881
 882
 883 #define STROM_ASSERT_ARRAY_SIZE         50
 884
 885
 886 #define MDIO_INDIRECT_REG_ADDR          0x1f
 887 #define MDIO_SET_REG_BANK(bp, reg_bank) \
 888                 bnx2x_mdio22_write(bp, MDIO_INDIRECT_REG_ADDR, reg_bank)
 889
 890 #define MDIO_ACCESS_TIMEOUT             1000
 891
 892
 893 /* must be used on a CID before placing it on a HW ring */
 894 #define HW_CID(bp, x)                   (x | (bp->port << 23))
 895
 896 #define SP_DESC_CNT             (BCM_PAGE_SIZE / sizeof(struct eth_spe))
 897 #define MAX_SP_DESC_CNT                 (SP_DESC_CNT - 1)
 898
 899 #define ATTN_NIG_FOR_FUNC               (1L << 8)
 900 #define ATTN_SW_TIMER_4_FUNC            (1L << 9)
 901 #define GPIO_2_FUNC                     (1L << 10)
 902 #define GPIO_3_FUNC                     (1L << 11)
 903 #define GPIO_4_FUNC                     (1L << 12)
 904 #define ATTN_GENERAL_ATTN_1             (1L << 13)
 905 #define ATTN_GENERAL_ATTN_2             (1L << 14)
 906 #define ATTN_GENERAL_ATTN_3             (1L << 15)
 907 #define ATTN_GENERAL_ATTN_4             (1L << 13)
 908 #define ATTN_GENERAL_ATTN_5             (1L << 14)
 909 #define ATTN_GENERAL_ATTN_6             (1L << 15)
 910
 911 #define ATTN_HARD_WIRED_MASK            0xff00
 912 #define ATTENTION_ID                    4
 913
 914
 915 #define BNX2X_BTR                       3
 916 #define MAX_SPQ_PENDING                 8
 917
 918
 919 <<<<<<< HEAD:drivers/net/bnx2x.h
 920 #define BNX2X_NUM_STATS                 31
 921 #define BNX2X_NUM_TESTS                 2
 922 =======
 923 #define BNX2X_NUM_STATS                 34
 924 #define BNX2X_NUM_TESTS                 1
 925 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/net/bnx2x.h
 926
 927
 928 #define DPM_TRIGER_TYPE                 0x40
 929 #define DOORBELL(bp, cid, val) \
 930         do { \
 931                 writel((u32)val, (bp)->doorbells + (BCM_PAGE_SIZE * cid) + \
 932                        DPM_TRIGER_TYPE); \
 933         } while (0)
 934
 935 <<<<<<< HEAD:drivers/net/bnx2x.h
 936 =======
 937 /* PCIE link and speed */
 938 #define PCICFG_LINK_WIDTH               0x1f00000
 939 #define PCICFG_LINK_WIDTH_SHIFT         20
 940 #define PCICFG_LINK_SPEED               0xf0000
 941 #define PCICFG_LINK_SPEED_SHIFT         16
 942
 943 #define BMAC_CONTROL_RX_ENABLE          2
 944
 945 #define pbd_tcp_flags(skb)      (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff)
 946 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/net/bnx2x.h
 947
 948 /* stuff added to make the code fit 80Col */
 949
 950 #define TPA_TYPE_START                  ETH_FAST_PATH_RX_CQE_START_FLG
 951 #define TPA_TYPE_END                    ETH_FAST_PATH_RX_CQE_END_FLG
 952 #define TPA_TYPE(cqe)           (cqe->fast_path_cqe.error_type_flags & \
 953                                  (TPA_TYPE_START | TPA_TYPE_END))
 954 #define BNX2X_RX_SUM_OK(cqe) \
 955                         (!(cqe->fast_path_cqe.status_flags & \
 956                          (ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG | \
 957                           ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG)))
 958
 959 #define BNX2X_RX_SUM_FIX(cqe) \
 960                         ((le16_to_cpu(cqe->fast_path_cqe.pars_flags.flags) & \
 961                           PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) == \
 962                          (1 << PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT))
 963
 964
 965 #define MDIO_AN_CL73_OR_37_COMPLETE \
 966                 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
 967                  MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
 968
 969 #define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
 970                         MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
 971 #define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
 972                         MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
 973 #define GP_STATUS_SPEED_MASK \
 974                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
 975 #define GP_STATUS_10M   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
 976 #define GP_STATUS_100M  MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
 977 #define GP_STATUS_1G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
 978 #define GP_STATUS_2_5G  MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
 979 #define GP_STATUS_5G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
 980 #define GP_STATUS_6G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
 981 #define GP_STATUS_10G_HIG \
 982                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
 983 #define GP_STATUS_10G_CX4 \
 984                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
 985 #define GP_STATUS_12G_HIG \
 986                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG
 987 #define GP_STATUS_12_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G
 988 #define GP_STATUS_13G   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G
 989 #define GP_STATUS_15G   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G
 990 #define GP_STATUS_16G   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G
 991 #define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
 992 #define GP_STATUS_10G_KX4 \
 993                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
 994
 995 #define LINK_10THD                      LINK_STATUS_SPEED_AND_DUPLEX_10THD
 996 #define LINK_10TFD                      LINK_STATUS_SPEED_AND_DUPLEX_10TFD
 997 #define LINK_100TXHD                    LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
 998 #define LINK_100T4                      LINK_STATUS_SPEED_AND_DUPLEX_100T4
 999 #define LINK_100TXFD                    LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
1000 #define LINK_1000THD                    LINK_STATUS_SPEED_AND_DUPLEX_1000THD
1001 #define LINK_1000TFD                    LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
1002 #define LINK_1000XFD                    LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
1003 #define LINK_2500THD                    LINK_STATUS_SPEED_AND_DUPLEX_2500THD
1004 #define LINK_2500TFD                    LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
1005 #define LINK_2500XFD                    LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
1006 #define LINK_10GTFD                     LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
1007 #define LINK_10GXFD                     LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
1008 #define LINK_12GTFD                     LINK_STATUS_SPEED_AND_DUPLEX_12GTFD
1009 #define LINK_12GXFD                     LINK_STATUS_SPEED_AND_DUPLEX_12GXFD
1010 #define LINK_12_5GTFD                   LINK_STATUS_SPEED_AND_DUPLEX_12_5GTFD
1011 #define LINK_12_5GXFD                   LINK_STATUS_SPEED_AND_DUPLEX_12_5GXFD
1012 #define LINK_13GTFD                     LINK_STATUS_SPEED_AND_DUPLEX_13GTFD
1013 #define LINK_13GXFD                     LINK_STATUS_SPEED_AND_DUPLEX_13GXFD
1014 #define LINK_15GTFD                     LINK_STATUS_SPEED_AND_DUPLEX_15GTFD
1015 #define LINK_15GXFD                     LINK_STATUS_SPEED_AND_DUPLEX_15GXFD
1016 #define LINK_16GTFD                     LINK_STATUS_SPEED_AND_DUPLEX_16GTFD
1017 #define LINK_16GXFD                     LINK_STATUS_SPEED_AND_DUPLEX_16GXFD
1018
1019 <<<<<<< HEAD:drivers/net/bnx2x.h
1020 #define NIG_STATUS_INTERRUPT_XGXS0_LINK10G \
1021 =======
1022 #define NIG_STATUS_XGXS0_LINK10G \
1023 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/net/bnx2x.h
1024                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
1025 <<<<<<< HEAD:drivers/net/bnx2x.h
1026 #define NIG_XGXS0_LINK_STATUS \
1027 =======
1028 #define NIG_STATUS_XGXS0_LINK_STATUS \
1029 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/net/bnx2x.h
1030                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
1031 <<<<<<< HEAD:drivers/net/bnx2x.h
1032 #define NIG_XGXS0_LINK_STATUS_SIZE \
1033 =======
1034 #define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
1035 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/net/bnx2x.h
1036                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
1037 <<<<<<< HEAD:drivers/net/bnx2x.h
1038 #define NIG_SERDES0_LINK_STATUS \
1039 =======
1040 #define NIG_STATUS_SERDES0_LINK_STATUS \
1041 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/net/bnx2x.h
1042                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
1043 #define NIG_MASK_MI_INT \
1044                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
1045 #define NIG_MASK_XGXS0_LINK10G \
1046                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
1047 #define NIG_MASK_XGXS0_LINK_STATUS \
1048                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
1049 #define NIG_MASK_SERDES0_LINK_STATUS \
1050                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
1051
1052 #define XGXS_RESET_BITS \
1053         (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW |   \
1054          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ |      \
1055          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN |    \
1056          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
1057          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
1058
1059 #define SERDES_RESET_BITS \
1060         (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
1061          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ |    \
1062          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN |  \
1063          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
1064
1065
1066 #define BNX2X_MC_ASSERT_BITS \
1067         (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1068          GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1069          GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1070          GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT))
1071
1072 #define BNX2X_MCP_ASSERT \
1073         GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT)
1074
1075 #define BNX2X_DOORQ_ASSERT \
1076         AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT
1077
1078 #define HW_INTERRUT_ASSERT_SET_0 \
1079                                 (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \
1080                                  AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \
1081                                  AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \
1082                                  AEU_INPUTS_ATTN_BITS_PBF_HW_INTERRUPT)
1083 #define HW_PRTY_ASSERT_SET_0    (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \
1084                                  AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \
1085                                  AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \
1086                                  AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\
1087                                  AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR)
1088 #define HW_INTERRUT_ASSERT_SET_1 \
1089                                 (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \
1090                                  AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \
1091                                  AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \
1092                                  AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \
1093                                  AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \
1094                                  AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \
1095                                  AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \
1096                                  AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \
1097                                  AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \
1098                                  AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \
1099                                  AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)
1100 #define HW_PRTY_ASSERT_SET_1    (AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR |\
1101                                  AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \
1102                                  AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \
1103                                  AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \
1104                                 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\
1105                             AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\
1106                                  AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \
1107                                  AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \
1108                                  AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \
1109                                  AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \
1110                                  AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR)
1111 #define HW_INTERRUT_ASSERT_SET_2 \
1112                                 (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \
1113                                  AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \
1114                                  AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \
1115                         AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\
1116                                  AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT)
1117 #define HW_PRTY_ASSERT_SET_2    (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \
1118                                  AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \
1119                         AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\
1120                                  AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \
1121                                  AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \
1122                                  AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \
1123                                  AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
1124
1125
1126 #define ETH_RX_ERROR_FALGS      (ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG | \
1127                                  ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG | \
1128                                  ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG)
1129
1130
1131 #define MULTI_FLAGS \
1132         (TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY     | \
1133          TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY | \
1134          TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY     | \
1135          TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY | \
1136          TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_ENABLE)
1137
1138 #define MULTI_MASK      0x7f
1139
1140
1141 #define U_SB_ETH_RX_CQ_INDEX            HC_INDEX_U_ETH_RX_CQ_CONS
1142 #define C_SB_ETH_TX_CQ_INDEX            HC_INDEX_C_ETH_TX_CQ_CONS
1143 #define C_DEF_SB_SP_INDEX               HC_INDEX_DEF_C_ETH_SLOW_PATH
1144
1145 #define BNX2X_RX_SB_INDEX \
1146         &fp->status_blk->u_status_block.index_values[U_SB_ETH_RX_CQ_INDEX]
1147
1148 #define BNX2X_TX_SB_INDEX \
1149         &fp->status_blk->c_status_block.index_values[C_SB_ETH_TX_CQ_INDEX]
1150
1151 #define BNX2X_SP_DSB_INDEX \
1152 &bp->def_status_blk->c_def_status_block.index_values[C_DEF_SB_SP_INDEX]
1153
1154
1155 #define CAM_IS_INVALID(x) \
1156 (x.target_table_entry.flags == TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE)
1157
1158 #define CAM_INVALIDATE(x) \
1159 x.target_table_entry.flags = TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE
1160
1161
1162 /* MISC_REG_RESET_REG - this is here for the hsi to work don't touch */
1163
1164 #endif /* bnx2x.h */