drivers/net/bnx2x_fw_defs.h

   1 /* bnx2x_fw_defs.h: Broadcom Everest network driver.
   2  *
   3 <<<<<<< HEAD:drivers/net/bnx2x_fw_defs.h
   4  * Copyright (c) 2007 Broadcom Corporation
   5 =======
   6  * Copyright (c) 2007-2008 Broadcom Corporation
   7 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/net/bnx2x_fw_defs.h
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation.
  12  */
  13
  14
  15 #define CSTORM_DEF_SB_HC_DISABLE_OFFSET(port, index)\
  16         (0x1922 + (port * 0x40) + (index * 0x4))
  17 #define CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(port)\
  18         (0x1900 + (port * 0x40))
  19 #define CSTORM_HC_BTR_OFFSET(port)\
  20         (0x1984 + (port * 0xc0))
  21 #define CSTORM_SB_HC_DISABLE_OFFSET(port, cpu_id, index)\
  22         (0x141a + (port * 0x280) + (cpu_id * 0x28) + (index * 0x4))
  23 #define CSTORM_SB_HC_TIMEOUT_OFFSET(port, cpu_id, index)\
  24         (0x1418 + (port * 0x280) + (cpu_id * 0x28) + (index * 0x4))
  25 #define CSTORM_SB_HOST_SB_ADDR_OFFSET(port, cpu_id)\
  26         (0x1400 + (port * 0x280) + (cpu_id * 0x28))
  27 #define CSTORM_STATS_FLAGS_OFFSET(port)                 (0x5108 + (port * 0x8))
  28 #define TSTORM_CLIENT_CONFIG_OFFSET(port, client_id)\
  29         (0x1510 + (port * 0x240) + (client_id * 0x20))
  30 #define TSTORM_DEF_SB_HC_DISABLE_OFFSET(port, index)\
  31         (0x138a + (port * 0x28) + (index * 0x4))
  32 #define TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(port)\
  33         (0x1370 + (port * 0x28))
  34 #define TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(port)\
  35         (0x4b70 + (port * 0x8))
  36 #define TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(function)\
  37         (0x1418 + (function * 0x30))
  38 #define TSTORM_HC_BTR_OFFSET(port)\
  39         (0x13c4 + (port * 0x18))
  40 #define TSTORM_INDIRECTION_TABLE_OFFSET(port)\
  41         (0x22c8 + (port * 0x80))
  42 #define TSTORM_INDIRECTION_TABLE_SIZE                   0x80
  43 #define TSTORM_MAC_FILTER_CONFIG_OFFSET(port)\
  44         (0x1420 + (port * 0x30))
  45 #define TSTORM_RCQ_PROD_OFFSET(port, client_id)\
  46         (0x1508 + (port * 0x240) + (client_id * 0x20))
  47 #define TSTORM_STATS_FLAGS_OFFSET(port)                 (0x4b90 + (port * 0x8))
  48 #define USTORM_DEF_SB_HC_DISABLE_OFFSET(port, index)\
  49         (0x191a + (port * 0x28) + (index * 0x4))
  50 #define USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(port)\
  51         (0x1900 + (port * 0x28))
  52 #define USTORM_HC_BTR_OFFSET(port)\
  53         (0x1954 + (port * 0xb8))
  54 #define USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(port)\
  55         (0x5408 + (port * 0x8))
  56 #define USTORM_SB_HC_DISABLE_OFFSET(port, cpu_id, index)\
  57         (0x141a + (port * 0x280) + (cpu_id * 0x28) + (index * 0x4))
  58 #define USTORM_SB_HC_TIMEOUT_OFFSET(port, cpu_id, index)\
  59         (0x1418 + (port * 0x280) + (cpu_id * 0x28) + (index * 0x4))
  60 #define USTORM_SB_HOST_SB_ADDR_OFFSET(port, cpu_id)\
  61         (0x1400 + (port * 0x280) + (cpu_id * 0x28))
  62 #define XSTORM_ASSERT_LIST_INDEX_OFFSET                 0x1000
  63 #define XSTORM_ASSERT_LIST_OFFSET(idx)                  (0x1020 + (idx * 0x10))
  64 #define XSTORM_DEF_SB_HC_DISABLE_OFFSET(port, index)\
  65         (0x141a + (port * 0x28) + (index * 0x4))
  66 #define XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(port)\
  67         (0x1400 + (port * 0x28))
  68 #define XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(port)\
  69         (0x5408 + (port * 0x8))
  70 #define XSTORM_HC_BTR_OFFSET(port)\
  71         (0x1454 + (port * 0x18))
  72 #define XSTORM_SPQ_PAGE_BASE_OFFSET(port)\
  73         (0x5328 + (port * 0x18))
  74 #define XSTORM_SPQ_PROD_OFFSET(port)\
  75         (0x5330 + (port * 0x18))
  76 #define XSTORM_STATS_FLAGS_OFFSET(port)                 (0x53f8 + (port * 0x8))
  77 #define COMMON_ASM_INVALID_ASSERT_OPCODE 0x0
  78
  79 /**
  80 * This file defines HSI constatnts for the ETH flow
  81 */
  82
  83 /* hash types */
  84 #define DEFAULT_HASH_TYPE                       0
  85 #define IPV4_HASH_TYPE                          1
  86 #define TCP_IPV4_HASH_TYPE                      2
  87 #define IPV6_HASH_TYPE                          3
  88 #define TCP_IPV6_HASH_TYPE                      4
  89
  90 /* values of command IDs in the ramrod message */
  91 #define RAMROD_CMD_ID_ETH_PORT_SETUP                    (80)
  92 #define RAMROD_CMD_ID_ETH_CLIENT_SETUP                  (85)
  93 #define RAMROD_CMD_ID_ETH_STAT_QUERY                    (90)
  94 #define RAMROD_CMD_ID_ETH_UPDATE                        (100)
  95 #define RAMROD_CMD_ID_ETH_HALT                          (105)
  96 #define RAMROD_CMD_ID_ETH_SET_MAC                       (110)
  97 #define RAMROD_CMD_ID_ETH_CFC_DEL                       (115)
  98 #define RAMROD_CMD_ID_ETH_PORT_DEL                      (120)
  99 #define RAMROD_CMD_ID_ETH_FORWARD_SETUP                 (125)
 100
 101
 102 /* command values for set mac command */
 103 #define T_ETH_MAC_COMMAND_SET                           0
 104 #define T_ETH_MAC_COMMAND_INVALIDATE                    1
 105
 106 #define T_ETH_INDIRECTION_TABLE_SIZE                    128
 107
 108 /* Maximal L2 clients supported */
 109 #define ETH_MAX_RX_CLIENTS                              (18)
 110
 111 /**
 112 * This file defines HSI constatnts common to all microcode flows
 113 */
 114
 115 /* Connection types */
 116 #define ETH_CONNECTION_TYPE                     0
 117
 118 #define PROTOCOL_STATE_BIT_OFFSET               6
 119
 120 #define ETH_STATE       (ETH_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
 121
 122 /* microcode fixed page page size 4K (chains and ring segments) */
 123 #define MC_PAGE_SIZE                                            (4096)
 124
 125 /* Host coalescing constants */
 126
 127 /* IGU constants */
 128 #define IGU_PORT_BASE                           0x0400
 129
 130 #define IGU_ADDR_MSIX                           0x0000
 131 #define IGU_ADDR_INT_ACK                        0x0200
 132 #define IGU_ADDR_PROD_UPD                       0x0201
 133 #define IGU_ADDR_ATTN_BITS_UPD                  0x0202
 134 #define IGU_ADDR_ATTN_BITS_SET                  0x0203
 135 #define IGU_ADDR_ATTN_BITS_CLR                  0x0204
 136 #define IGU_ADDR_COALESCE_NOW                   0x0205
 137 #define IGU_ADDR_SIMD_MASK                      0x0206
 138 #define IGU_ADDR_SIMD_NOMASK                    0x0207
 139 #define IGU_ADDR_MSI_CTL                        0x0210
 140 #define IGU_ADDR_MSI_ADDR_LO                    0x0211
 141 #define IGU_ADDR_MSI_ADDR_HI                    0x0212
 142 #define IGU_ADDR_MSI_DATA                       0x0213
 143
 144 #define IGU_INT_ENABLE                          0
 145 #define IGU_INT_DISABLE                         1
 146 #define IGU_INT_NOP                             2
 147 #define IGU_INT_NOP2                            3
 148
 149 /* index numbers */
 150 #define HC_USTORM_DEF_SB_NUM_INDICES            4
 151 #define HC_CSTORM_DEF_SB_NUM_INDICES            8
 152 #define HC_XSTORM_DEF_SB_NUM_INDICES            4
 153 #define HC_TSTORM_DEF_SB_NUM_INDICES            4
 154 #define HC_USTORM_SB_NUM_INDICES                4
 155 #define HC_CSTORM_SB_NUM_INDICES                4
 156
 157 /* index values - which counterto update */
 158
 159 #define HC_INDEX_U_ETH_RX_CQ_CONS               1
 160
 161 #define HC_INDEX_C_ETH_TX_CQ_CONS               1
 162
 163 #define HC_INDEX_DEF_X_SPQ_CONS                 0
 164
 165 #define HC_INDEX_DEF_C_ETH_FW_TX_CQ_CONS        2
 166 #define HC_INDEX_DEF_C_ETH_SLOW_PATH            3
 167
 168 /* used by the driver to get the SB offset */
 169 #define USTORM_ID                       0
 170 #define CSTORM_ID                       1
 171 #define XSTORM_ID                       2
 172 #define TSTORM_ID                       3
 173 #define ATTENTION_ID                    4
 174
 175 /* max number of slow path commands per port */
 176 #define MAX_RAMRODS_PER_PORT            (8)
 177
 178 /* values for RX ETH CQE type field */
 179 #define RX_ETH_CQE_TYPE_ETH_FASTPATH    (0)
 180 #define RX_ETH_CQE_TYPE_ETH_RAMROD              (1)
 181
 182 /* MAC address list size */
 183 #define T_MAC_ADDRESS_LIST_SIZE         (96)
 184
 185 #define XSTORM_IP_ID_ROLL_HALF 0x8000
 186 #define XSTORM_IP_ID_ROLL_ALL 0
 187
 188 #define FW_LOG_LIST_SIZE        (50)
 189
 190 #define NUM_OF_PROTOCOLS                4
 191 #define MAX_COS_NUMBER                  16
 192 #define MAX_T_STAT_COUNTER_ID   18
 193
 194 #define T_FAIR                                                  1
 195 #define FAIR_MEM                                                2
 196 #define RS_PERIODIC_TIMEOUT_IN_SDM_TICS 25
 197
 198 #define UNKNOWN_ADDRESS         0
 199 #define UNICAST_ADDRESS         1
 200 #define MULTICAST_ADDRESS       2
 201 #define BROADCAST_ADDRESS       3
 202