| blob | 1862d33b704c9e88161de5fab96387ee655c9f34 |
1 /* bnx2x_reg.h: Broadcom Everest network driver.
2 *
3 <<<<<<< HEAD:drivers/net/bnx2x_reg.h
4 * Copyright (c) 2007 Broadcom Corporation
5 =======
6 * Copyright (c) 2007-2008 Broadcom Corporation
7 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/net/bnx2x_reg.h
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation.
12 *
13 * The registers description starts with the regsister Access type followed
14 * by size in bits. For example [RW 32]. The access types are:
15 * R - Read only
16 * RC - Clear on read
17 * RW - Read/Write
18 * ST - Statistics register (clear on read)
19 * W - Write only
20 * WB - Wide bus register - the size is over 32 bits and it should be
21 * read/write in consecutive 32 bits accesses
22 * WR - Write Clear (write 1 to clear the bit)
23 *
24 */
27 /* [R 19] Interrupt register #0 read */
28 #define BRB1_REG_BRB1_INT_STS 0x6011c
29 /* [RW 4] Parity mask register #0 read/write */
30 #define BRB1_REG_BRB1_PRTY_MASK 0x60138
32 =======
33 /* [R 4] Parity register #0 read */
34 #define BRB1_REG_BRB1_PRTY_STS 0x6012c
36 /* [RW 10] At address BRB1_IND_FREE_LIST_PRS_CRDT initialize free head. At
37 address BRB1_IND_FREE_LIST_PRS_CRDT+1 initialize free tail. At address
38 BRB1_IND_FREE_LIST_PRS_CRDT+2 initialize parser initial credit. */
39 #define BRB1_REG_FREE_LIST_PRS_CRDT 0x60200
40 /* [RW 23] LL RAM data. */
41 #define BRB1_REG_LL_RAM 0x61000
42 /* [R 24] The number of full blocks. */
43 #define BRB1_REG_NUM_OF_FULL_BLOCKS 0x60090
44 /* [ST 32] The number of cycles that the write_full signal towards MAC #0
45 was asserted. */
46 #define BRB1_REG_NUM_OF_FULL_CYCLES_0 0x600c8
47 #define BRB1_REG_NUM_OF_FULL_CYCLES_1 0x600cc
48 #define BRB1_REG_NUM_OF_FULL_CYCLES_2 0x600d0
49 #define BRB1_REG_NUM_OF_FULL_CYCLES_3 0x600d4
50 #define BRB1_REG_NUM_OF_FULL_CYCLES_4 0x600d8
51 /* [ST 32] The number of cycles that the pause signal towards MAC #0 was
52 asserted. */
53 #define BRB1_REG_NUM_OF_PAUSE_CYCLES_0 0x600b8
54 #define BRB1_REG_NUM_OF_PAUSE_CYCLES_1 0x600bc
55 #define BRB1_REG_NUM_OF_PAUSE_CYCLES_2 0x600c0
56 #define BRB1_REG_NUM_OF_PAUSE_CYCLES_3 0x600c4
57 /* [RW 10] Write client 0: De-assert pause threshold. */
58 #define BRB1_REG_PAUSE_HIGH_THRESHOLD_0 0x60078
59 #define BRB1_REG_PAUSE_HIGH_THRESHOLD_1 0x6007c
60 /* [RW 10] Write client 0: Assert pause threshold. */
61 #define BRB1_REG_PAUSE_LOW_THRESHOLD_0 0x60068
62 #define BRB1_REG_PAUSE_LOW_THRESHOLD_1 0x6006c
63 /* [RW 1] Reset the design by software. */
64 #define BRB1_REG_SOFT_RESET 0x600dc
65 /* [R 5] Used to read the value of the XX protection CAM occupancy counter. */
66 #define CCM_REG_CAM_OCCUP 0xd0188
67 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
68 acknowledge output is deasserted; all other signals are treated as usual;
69 if 1 - normal activity. */
70 #define CCM_REG_CCM_CFC_IFEN 0xd003c
71 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
72 disregarded; valid is deasserted; all other signals are treated as usual;
73 if 1 - normal activity. */
74 #define CCM_REG_CCM_CQM_IFEN 0xd000c
75 /* [RW 1] If set the Q index; received from the QM is inserted to event ID.
76 Otherwise 0 is inserted. */
77 #define CCM_REG_CCM_CQM_USE_Q 0xd00c0
78 /* [RW 11] Interrupt mask register #0 read/write */
79 #define CCM_REG_CCM_INT_MASK 0xd01e4
80 /* [R 11] Interrupt register #0 read */
81 #define CCM_REG_CCM_INT_STS 0xd01d8
82 /* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS
83 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
84 Is used to determine the number of the AG context REG-pairs written back;
85 when the input message Reg1WbFlg isn't set. */
86 #define CCM_REG_CCM_REG0_SZ 0xd00c4
87 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
88 disregarded; valid is deasserted; all other signals are treated as usual;
89 if 1 - normal activity. */
90 #define CCM_REG_CCM_STORM0_IFEN 0xd0004
91 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
92 disregarded; valid is deasserted; all other signals are treated as usual;
93 if 1 - normal activity. */
94 #define CCM_REG_CCM_STORM1_IFEN 0xd0008
95 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is
96 disregarded; valid output is deasserted; all other signals are treated as
97 usual; if 1 - normal activity. */
98 #define CCM_REG_CDU_AG_RD_IFEN 0xd0030
99 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
100 are disregarded; all other signals are treated as usual; if 1 - normal
101 activity. */
102 #define CCM_REG_CDU_AG_WR_IFEN 0xd002c
103 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
104 disregarded; valid output is deasserted; all other signals are treated as
105 usual; if 1 - normal activity. */
106 #define CCM_REG_CDU_SM_RD_IFEN 0xd0038
107 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
108 input is disregarded; all other signals are treated as usual; if 1 -
109 normal activity. */
110 #define CCM_REG_CDU_SM_WR_IFEN 0xd0034
111 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
112 the initial credit value; read returns the current value of the credit
113 counter. Must be initialized to 1 at start-up. */
114 #define CCM_REG_CFC_INIT_CRD 0xd0204
115 /* [RW 2] Auxillary counter flag Q number 1. */
116 #define CCM_REG_CNT_AUX1_Q 0xd00c8
117 /* [RW 2] Auxillary counter flag Q number 2. */
118 #define CCM_REG_CNT_AUX2_Q 0xd00cc
119 /* [RW 28] The CM header value for QM request (primary). */
120 #define CCM_REG_CQM_CCM_HDR_P 0xd008c
121 /* [RW 28] The CM header value for QM request (secondary). */
122 #define CCM_REG_CQM_CCM_HDR_S 0xd0090
123 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
124 acknowledge output is deasserted; all other signals are treated as usual;
125 if 1 - normal activity. */
126 #define CCM_REG_CQM_CCM_IFEN 0xd0014
127 /* [RW 6] QM output initial credit. Max credit available - 32. Write writes
128 the initial credit value; read returns the current value of the credit
129 counter. Must be initialized to 32 at start-up. */
130 #define CCM_REG_CQM_INIT_CRD 0xd020c
131 /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
132 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
133 prioritised); 2 stands for weight 2; tc. */
134 #define CCM_REG_CQM_P_WEIGHT 0xd00b8
135 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
136 acknowledge output is deasserted; all other signals are treated as usual;
137 if 1 - normal activity. */
138 #define CCM_REG_CSDM_IFEN 0xd0018
139 /* [RC 1] Set when the message length mismatch (relative to last indication)
140 at the SDM interface is detected. */
141 #define CCM_REG_CSDM_LENGTH_MIS 0xd0170
142 /* [RW 28] The CM header for QM formatting in case of an error in the QM
143 inputs. */
144 #define CCM_REG_ERR_CCM_HDR 0xd0094
145 /* [RW 8] The Event ID in case the input message ErrorFlg is set. */
146 #define CCM_REG_ERR_EVNT_ID 0xd0098
147 /* [RW 8] FIC0 output initial credit. Max credit available - 255. Write
148 writes the initial credit value; read returns the current value of the
149 credit counter. Must be initialized to 64 at start-up. */
150 #define CCM_REG_FIC0_INIT_CRD 0xd0210
151 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
152 writes the initial credit value; read returns the current value of the
153 credit counter. Must be initialized to 64 at start-up. */
154 #define CCM_REG_FIC1_INIT_CRD 0xd0214
155 /* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
156 - strict priority defined by ~ccm_registers_gr_ag_pr.gr_ag_pr;
157 ~ccm_registers_gr_ld0_pr.gr_ld0_pr and
158 ~ccm_registers_gr_ld1_pr.gr_ld1_pr. Groups are according to channels and
159 outputs to STORM: aggregation; load FIC0; load FIC1 and store. */
160 #define CCM_REG_GR_ARB_TYPE 0xd015c
161 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
162 highest priority is 3. It is supposed; that the Store channel priority is
163 the compliment to 4 of the rest priorities - Aggregation channel; Load
164 (FIC0) channel and Load (FIC1). */
165 #define CCM_REG_GR_LD0_PR 0xd0164
166 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
167 highest priority is 3. It is supposed; that the Store channel priority is
168 the compliment to 4 of the rest priorities - Aggregation channel; Load
169 (FIC0) channel and Load (FIC1). */
170 #define CCM_REG_GR_LD1_PR 0xd0168
171 /* [RW 2] General flags index. */
172 #define CCM_REG_INV_DONE_Q 0xd0108
173 /* [RW 4] The number of double REG-pairs(128 bits); loaded from the STORM
174 context and sent to STORM; for a specific connection type. The double
175 REG-pairs are used in order to align to STORM context row size of 128
176 bits. The offset of these data in the STORM context is always 0. Index
177 _(0..15) stands for the connection type (one of 16). */
178 #define CCM_REG_N_SM_CTX_LD_0 0xd004c
179 #define CCM_REG_N_SM_CTX_LD_1 0xd0050
180 #define CCM_REG_N_SM_CTX_LD_10 0xd0074
181 #define CCM_REG_N_SM_CTX_LD_11 0xd0078
182 #define CCM_REG_N_SM_CTX_LD_12 0xd007c
183 #define CCM_REG_N_SM_CTX_LD_13 0xd0080
184 #define CCM_REG_N_SM_CTX_LD_14 0xd0084
185 #define CCM_REG_N_SM_CTX_LD_15 0xd0088
186 #define CCM_REG_N_SM_CTX_LD_2 0xd0054
187 #define CCM_REG_N_SM_CTX_LD_3 0xd0058
188 #define CCM_REG_N_SM_CTX_LD_4 0xd005c
189 /* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
190 acknowledge output is deasserted; all other signals are treated as usual;
191 if 1 - normal activity. */
192 #define CCM_REG_PBF_IFEN 0xd0028
193 /* [RC 1] Set when the message length mismatch (relative to last indication)
194 at the pbf interface is detected. */
195 #define CCM_REG_PBF_LENGTH_MIS 0xd0180
196 /* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for
197 weight 8 (the most prioritised); 1 stands for weight 1(least
198 prioritised); 2 stands for weight 2; tc. */
199 #define CCM_REG_PBF_WEIGHT 0xd00ac
200 /* [RW 6] The physical queue number of queue number 1 per port index. */
201 #define CCM_REG_PHYS_QNUM1_0 0xd0134
202 #define CCM_REG_PHYS_QNUM1_1 0xd0138
203 /* [RW 6] The physical queue number of queue number 2 per port index. */
204 #define CCM_REG_PHYS_QNUM2_0 0xd013c
205 #define CCM_REG_PHYS_QNUM2_1 0xd0140
206 /* [RW 6] The physical queue number of queue number 3 per port index. */
207 #define CCM_REG_PHYS_QNUM3_0 0xd0144
208 /* [RW 6] The physical queue number of queue number 0 with QOS equal 0 port
209 index 0. */
210 #define CCM_REG_QOS_PHYS_QNUM0_0 0xd0114
211 #define CCM_REG_QOS_PHYS_QNUM0_1 0xd0118
212 /* [RW 6] The physical queue number of queue number 0 with QOS equal 1 port
213 index 0. */
214 #define CCM_REG_QOS_PHYS_QNUM1_0 0xd011c
215 #define CCM_REG_QOS_PHYS_QNUM1_1 0xd0120
216 /* [RW 6] The physical queue number of queue number 0 with QOS equal 2 port
217 index 0. */
218 #define CCM_REG_QOS_PHYS_QNUM2_0 0xd0124
219 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
220 disregarded; acknowledge output is deasserted; all other signals are
221 treated as usual; if 1 - normal activity. */
222 #define CCM_REG_STORM_CCM_IFEN 0xd0010
223 /* [RC 1] Set when the message length mismatch (relative to last indication)
224 at the STORM interface is detected. */
225 #define CCM_REG_STORM_LENGTH_MIS 0xd016c
226 /* [RW 1] Input tsem Interface enable. If 0 - the valid input is
227 disregarded; acknowledge output is deasserted; all other signals are
228 treated as usual; if 1 - normal activity. */
229 #define CCM_REG_TSEM_IFEN 0xd001c
230 /* [RC 1] Set when the message length mismatch (relative to last indication)
231 at the tsem interface is detected. */
232 #define CCM_REG_TSEM_LENGTH_MIS 0xd0174
233 /* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for
234 weight 8 (the most prioritised); 1 stands for weight 1(least
235 prioritised); 2 stands for weight 2; tc. */
236 #define CCM_REG_TSEM_WEIGHT 0xd00a0
237 /* [RW 1] Input usem Interface enable. If 0 - the valid input is
238 disregarded; acknowledge output is deasserted; all other signals are
239 treated as usual; if 1 - normal activity. */
240 #define CCM_REG_USEM_IFEN 0xd0024
241 /* [RC 1] Set when message length mismatch (relative to last indication) at
242 the usem interface is detected. */
243 #define CCM_REG_USEM_LENGTH_MIS 0xd017c
244 /* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for
245 weight 8 (the most prioritised); 1 stands for weight 1(least
246 prioritised); 2 stands for weight 2; tc. */
247 #define CCM_REG_USEM_WEIGHT 0xd00a8
248 /* [RW 1] Input xsem Interface enable. If 0 - the valid input is
249 disregarded; acknowledge output is deasserted; all other signals are
250 treated as usual; if 1 - normal activity. */
251 #define CCM_REG_XSEM_IFEN 0xd0020
252 /* [RC 1] Set when the message length mismatch (relative to last indication)
253 at the xsem interface is detected. */
254 #define CCM_REG_XSEM_LENGTH_MIS 0xd0178
255 /* [RW 3] The weight of the input xsem in the WRR mechanism. 0 stands for
256 weight 8 (the most prioritised); 1 stands for weight 1(least
257 prioritised); 2 stands for weight 2; tc. */
258 #define CCM_REG_XSEM_WEIGHT 0xd00a4
259 /* [RW 19] Indirect access to the descriptor table of the XX protection
260 mechanism. The fields are: [5:0] - message length; [12:6] - message
261 pointer; 18:13] - next pointer. */
262 #define CCM_REG_XX_DESCR_TABLE 0xd0300
263 /* [R 7] Used to read the value of XX protection Free counter. */
264 #define CCM_REG_XX_FREE 0xd0184
265 /* [RW 6] Initial value for the credit counter; responsible for fulfilling
266 of the Input Stage XX protection buffer by the XX protection pending
267 messages. Max credit available - 127. Write writes the initial credit
268 value; read returns the current value of the credit counter. Must be
269 initialized to maximum XX protected message size - 2 at start-up. */
270 #define CCM_REG_XX_INIT_CRD 0xd0220
271 /* [RW 7] The maximum number of pending messages; which may be stored in XX
272 protection. At read the ~ccm_registers_xx_free.xx_free counter is read.
273 At write comprises the start value of the ~ccm_registers_xx_free.xx_free
274 counter. */
275 #define CCM_REG_XX_MSG_NUM 0xd0224
276 /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
277 #define CCM_REG_XX_OVFL_EVNT_ID 0xd0044
278 /* [RW 18] Indirect access to the XX table of the XX protection mechanism.
279 The fields are: [5:0] - tail pointer; 11:6] - Link List size; 17:12] -
280 header pointer. */
281 #define CCM_REG_XX_TABLE 0xd0280
282 #define CDU_REG_CDU_CHK_MASK0 0x101000
283 #define CDU_REG_CDU_CHK_MASK1 0x101004
284 #define CDU_REG_CDU_CONTROL0 0x101008
285 #define CDU_REG_CDU_DEBUG 0x101010
286 #define CDU_REG_CDU_GLOBAL_PARAMS 0x101020
287 /* [RW 7] Interrupt mask register #0 read/write */
288 #define CDU_REG_CDU_INT_MASK 0x10103c
289 /* [R 7] Interrupt register #0 read */
290 #define CDU_REG_CDU_INT_STS 0x101030
291 /* [RW 5] Parity mask register #0 read/write */
292 #define CDU_REG_CDU_PRTY_MASK 0x10104c
294 =======
295 /* [R 5] Parity register #0 read */
296 #define CDU_REG_CDU_PRTY_STS 0x101040
298 /* [RC 32] logging of error data in case of a CDU load error:
299 {expected_cid[15:0]; xpected_type[2:0]; xpected_region[2:0]; ctive_error;
300 ype_error; ctual_active; ctual_compressed_context}; */
301 #define CDU_REG_ERROR_DATA 0x101014
302 /* [WB 216] L1TT ram access. each entry has the following format :
303 {mrege_regions[7:0]; ffset12[5:0]...offset0[5:0];
304 ength12[5:0]...length0[5:0]; d12[3:0]...id0[3:0]} */
305 #define CDU_REG_L1TT 0x101800
306 /* [WB 24] MATT ram access. each entry has the following
307 format:{RegionLength[11:0]; egionOffset[11:0]} */
308 #define CDU_REG_MATT 0x101100
309 /* [R 1] indication the initializing the activity counter by the hardware
310 was done. */
311 #define CFC_REG_AC_INIT_DONE 0x104078
312 /* [RW 13] activity counter ram access */
313 #define CFC_REG_ACTIVITY_COUNTER 0x104400
314 #define CFC_REG_ACTIVITY_COUNTER_SIZE 256
315 /* [R 1] indication the initializing the cams by the hardware was done. */
316 #define CFC_REG_CAM_INIT_DONE 0x10407c
317 /* [RW 2] Interrupt mask register #0 read/write */
318 #define CFC_REG_CFC_INT_MASK 0x104108
319 /* [R 2] Interrupt register #0 read */
320 #define CFC_REG_CFC_INT_STS 0x1040fc
321 /* [RC 2] Interrupt register #0 read clear */
322 #define CFC_REG_CFC_INT_STS_CLR 0x104100
323 /* [RW 4] Parity mask register #0 read/write */
324 #define CFC_REG_CFC_PRTY_MASK 0x104118
326 =======
327 /* [R 4] Parity register #0 read */
328 #define CFC_REG_CFC_PRTY_STS 0x10410c
330 /* [RW 21] CID cam access (21:1 - Data; alid - 0) */
331 #define CFC_REG_CID_CAM 0x104800
332 #define CFC_REG_CONTROL0 0x104028
333 #define CFC_REG_DEBUG0 0x104050
334 /* [RW 14] indicates per error (in #cfc_registers_cfc_error_vector.cfc_error
335 vector) whether the cfc should be disabled upon it */
336 #define CFC_REG_DISABLE_ON_ERROR 0x104044
337 /* [RC 14] CFC error vector. when the CFC detects an internal error it will
338 set one of these bits. the bit description can be found in CFC
339 specifications */
340 #define CFC_REG_ERROR_VECTOR 0x10403c
341 #define CFC_REG_INIT_REG 0x10404c
342 /* [RW 24] {weight_load_client7[2:0] to weight_load_client0[2:0]}. this
343 field allows changing the priorities of the weighted-round-robin arbiter
344 which selects which CFC load client should be served next */
345 #define CFC_REG_LCREQ_WEIGHTS 0x104084
346 /* [R 1] indication the initializing the link list by the hardware was done. */
347 #define CFC_REG_LL_INIT_DONE 0x104074
348 /* [R 9] Number of allocated LCIDs which are at empty state */
349 #define CFC_REG_NUM_LCIDS_ALLOC 0x104020
350 /* [R 9] Number of Arriving LCIDs in Link List Block */
351 #define CFC_REG_NUM_LCIDS_ARRIVING 0x104004
352 /* [R 9] Number of Inside LCIDs in Link List Block */
353 #define CFC_REG_NUM_LCIDS_INSIDE 0x104008
354 /* [R 9] Number of Leaving LCIDs in Link List Block */
355 #define CFC_REG_NUM_LCIDS_LEAVING 0x104018
356 /* [RW 8] The event id for aggregated interrupt 0 */
357 #define CSDM_REG_AGG_INT_EVENT_0 0xc2038
358 /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
359 #define CSDM_REG_CFC_RSP_START_ADDR 0xc2008
360 /* [RW 16] The maximum value of the competion counter #0 */
361 #define CSDM_REG_CMP_COUNTER_MAX0 0xc201c
362 /* [RW 16] The maximum value of the competion counter #1 */
363 #define CSDM_REG_CMP_COUNTER_MAX1 0xc2020
364 /* [RW 16] The maximum value of the competion counter #2 */
365 #define CSDM_REG_CMP_COUNTER_MAX2 0xc2024
366 /* [RW 16] The maximum value of the competion counter #3 */
367 #define CSDM_REG_CMP_COUNTER_MAX3 0xc2028
368 /* [RW 13] The start address in the internal RAM for the completion
369 counters. */
370 #define CSDM_REG_CMP_COUNTER_START_ADDR 0xc200c
371 /* [RW 32] Interrupt mask register #0 read/write */
372 #define CSDM_REG_CSDM_INT_MASK_0 0xc229c
373 #define CSDM_REG_CSDM_INT_MASK_1 0xc22ac
374 /* [RW 11] Parity mask register #0 read/write */
375 #define CSDM_REG_CSDM_PRTY_MASK 0xc22bc
377 =======
378 /* [R 11] Parity register #0 read */
379 #define CSDM_REG_CSDM_PRTY_STS 0xc22b0
381 #define CSDM_REG_ENABLE_IN1 0xc2238
382 #define CSDM_REG_ENABLE_IN2 0xc223c
383 #define CSDM_REG_ENABLE_OUT1 0xc2240
384 #define CSDM_REG_ENABLE_OUT2 0xc2244
385 /* [RW 4] The initial number of messages that can be sent to the pxp control
386 interface without receiving any ACK. */
387 #define CSDM_REG_INIT_CREDIT_PXP_CTRL 0xc24bc
388 /* [ST 32] The number of ACK after placement messages received */
389 #define CSDM_REG_NUM_OF_ACK_AFTER_PLACE 0xc227c
390 /* [ST 32] The number of packet end messages received from the parser */
391 #define CSDM_REG_NUM_OF_PKT_END_MSG 0xc2274
392 /* [ST 32] The number of requests received from the pxp async if */
393 #define CSDM_REG_NUM_OF_PXP_ASYNC_REQ 0xc2278
394 /* [ST 32] The number of commands received in queue 0 */
395 #define CSDM_REG_NUM_OF_Q0_CMD 0xc2248
396 /* [ST 32] The number of commands received in queue 10 */
397 #define CSDM_REG_NUM_OF_Q10_CMD 0xc226c
398 /* [ST 32] The number of commands received in queue 11 */
399 #define CSDM_REG_NUM_OF_Q11_CMD 0xc2270
400 /* [ST 32] The number of commands received in queue 1 */
401 #define CSDM_REG_NUM_OF_Q1_CMD 0xc224c
402 /* [ST 32] The number of commands received in queue 3 */
403 #define CSDM_REG_NUM_OF_Q3_CMD 0xc2250
404 /* [ST 32] The number of commands received in queue 4 */
405 #define CSDM_REG_NUM_OF_Q4_CMD 0xc2254
406 /* [ST 32] The number of commands received in queue 5 */
407 #define CSDM_REG_NUM_OF_Q5_CMD 0xc2258
408 /* [ST 32] The number of commands received in queue 6 */
409 #define CSDM_REG_NUM_OF_Q6_CMD 0xc225c
410 /* [ST 32] The number of commands received in queue 7 */
411 #define CSDM_REG_NUM_OF_Q7_CMD 0xc2260
412 /* [ST 32] The number of commands received in queue 8 */
413 #define CSDM_REG_NUM_OF_Q8_CMD 0xc2264
414 /* [ST 32] The number of commands received in queue 9 */
415 #define CSDM_REG_NUM_OF_Q9_CMD 0xc2268
416 /* [RW 13] The start address in the internal RAM for queue counters */
417 #define CSDM_REG_Q_COUNTER_START_ADDR 0xc2010
418 /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
419 #define CSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0xc2548
420 /* [R 1] parser fifo empty in sdm_sync block */
421 #define CSDM_REG_SYNC_PARSER_EMPTY 0xc2550
422 /* [R 1] parser serial fifo empty in sdm_sync block */
423 #define CSDM_REG_SYNC_SYNC_EMPTY 0xc2558
424 /* [RW 32] Tick for timer counter. Applicable only when
425 ~csdm_registers_timer_tick_enable.timer_tick_enable =1 */
426 #define CSDM_REG_TIMER_TICK 0xc2000
427 /* [RW 5] The number of time_slots in the arbitration cycle */
428 #define CSEM_REG_ARB_CYCLE_SIZE 0x200034
429 /* [RW 3] The source that is associated with arbitration element 0. Source
430 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
431 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
432 #define CSEM_REG_ARB_ELEMENT0 0x200020
433 /* [RW 3] The source that is associated with arbitration element 1. Source
434 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
435 sleeping thread with priority 1; 4- sleeping thread with priority 2.
436 Could not be equal to register ~csem_registers_arb_element0.arb_element0 */
437 #define CSEM_REG_ARB_ELEMENT1 0x200024
438 /* [RW 3] The source that is associated with arbitration element 2. Source
439 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
440 sleeping thread with priority 1; 4- sleeping thread with priority 2.
441 Could not be equal to register ~csem_registers_arb_element0.arb_element0
442 and ~csem_registers_arb_element1.arb_element1 */
443 #define CSEM_REG_ARB_ELEMENT2 0x200028
444 /* [RW 3] The source that is associated with arbitration element 3. Source
445 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
446 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
447 not be equal to register ~csem_registers_arb_element0.arb_element0 and
448 ~csem_registers_arb_element1.arb_element1 and
449 ~csem_registers_arb_element2.arb_element2 */
450 #define CSEM_REG_ARB_ELEMENT3 0x20002c
451 /* [RW 3] The source that is associated with arbitration element 4. Source
452 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
453 sleeping thread with priority 1; 4- sleeping thread with priority 2.
454 Could not be equal to register ~csem_registers_arb_element0.arb_element0
455 and ~csem_registers_arb_element1.arb_element1 and
456 ~csem_registers_arb_element2.arb_element2 and
457 ~csem_registers_arb_element3.arb_element3 */
458 #define CSEM_REG_ARB_ELEMENT4 0x200030
459 /* [RW 32] Interrupt mask register #0 read/write */
460 #define CSEM_REG_CSEM_INT_MASK_0 0x200110
461 #define CSEM_REG_CSEM_INT_MASK_1 0x200120
462 /* [RW 32] Parity mask register #0 read/write */
463 #define CSEM_REG_CSEM_PRTY_MASK_0 0x200130
464 #define CSEM_REG_CSEM_PRTY_MASK_1 0x200140
466 =======
467 /* [R 32] Parity register #0 read */
468 #define CSEM_REG_CSEM_PRTY_STS_0 0x200124
469 #define CSEM_REG_CSEM_PRTY_STS_1 0x200134
471 #define CSEM_REG_ENABLE_IN 0x2000a4
472 #define CSEM_REG_ENABLE_OUT 0x2000a8
473 /* [RW 32] This address space contains all registers and memories that are
474 placed in SEM_FAST block. The SEM_FAST registers are described in
475 appendix B. In order to access the SEM_FAST registers the base address
476 CSEM_REGISTERS_FAST_MEMORY (Offset: 0x220000) should be added to each
477 SEM_FAST register offset. */
478 #define CSEM_REG_FAST_MEMORY 0x220000
479 /* [RW 1] Disables input messages from FIC0 May be updated during run_time
480 by the microcode */
481 #define CSEM_REG_FIC0_DISABLE 0x200224
482 /* [RW 1] Disables input messages from FIC1 May be updated during run_time
483 by the microcode */
484 #define CSEM_REG_FIC1_DISABLE 0x200234
485 /* [RW 15] Interrupt table Read and write access to it is not possible in
486 the middle of the work */
487 #define CSEM_REG_INT_TABLE 0x200400
488 /* [ST 24] Statistics register. The number of messages that entered through
489 FIC0 */
490 #define CSEM_REG_MSG_NUM_FIC0 0x200000
491 /* [ST 24] Statistics register. The number of messages that entered through
492 FIC1 */
493 #define CSEM_REG_MSG_NUM_FIC1 0x200004
494 /* [ST 24] Statistics register. The number of messages that were sent to
495 FOC0 */
496 #define CSEM_REG_MSG_NUM_FOC0 0x200008
497 /* [ST 24] Statistics register. The number of messages that were sent to
498 FOC1 */
499 #define CSEM_REG_MSG_NUM_FOC1 0x20000c
500 /* [ST 24] Statistics register. The number of messages that were sent to
501 FOC2 */
502 #define CSEM_REG_MSG_NUM_FOC2 0x200010
503 /* [ST 24] Statistics register. The number of messages that were sent to
504 FOC3 */
505 #define CSEM_REG_MSG_NUM_FOC3 0x200014
506 /* [RW 1] Disables input messages from the passive buffer May be updated
507 during run_time by the microcode */
508 #define CSEM_REG_PAS_DISABLE 0x20024c
509 /* [WB 128] Debug only. Passive buffer memory */
510 #define CSEM_REG_PASSIVE_BUFFER 0x202000
511 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
512 #define CSEM_REG_PRAM 0x240000
513 /* [R 16] Valid sleeping threads indication have bit per thread */
514 #define CSEM_REG_SLEEP_THREADS_VALID 0x20026c
515 /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
516 #define CSEM_REG_SLOW_EXT_STORE_EMPTY 0x2002a0
517 /* [RW 16] List of free threads . There is a bit per thread. */
518 #define CSEM_REG_THREADS_LIST 0x2002e4
519 /* [RW 3] The arbitration scheme of time_slot 0 */
520 #define CSEM_REG_TS_0_AS 0x200038
521 /* [RW 3] The arbitration scheme of time_slot 10 */
522 #define CSEM_REG_TS_10_AS 0x200060
523 /* [RW 3] The arbitration scheme of time_slot 11 */
524 #define CSEM_REG_TS_11_AS 0x200064
525 /* [RW 3] The arbitration scheme of time_slot 12 */
526 #define CSEM_REG_TS_12_AS 0x200068
527 /* [RW 3] The arbitration scheme of time_slot 13 */
528 #define CSEM_REG_TS_13_AS 0x20006c
529 /* [RW 3] The arbitration scheme of time_slot 14 */
530 #define CSEM_REG_TS_14_AS 0x200070
531 /* [RW 3] The arbitration scheme of time_slot 15 */
532 #define CSEM_REG_TS_15_AS 0x200074
533 /* [RW 3] The arbitration scheme of time_slot 16 */
534 #define CSEM_REG_TS_16_AS 0x200078
535 /* [RW 3] The arbitration scheme of time_slot 17 */
536 #define CSEM_REG_TS_17_AS 0x20007c
537 /* [RW 3] The arbitration scheme of time_slot 18 */
538 #define CSEM_REG_TS_18_AS 0x200080
539 /* [RW 3] The arbitration scheme of time_slot 1 */
540 #define CSEM_REG_TS_1_AS 0x20003c
541 /* [RW 3] The arbitration scheme of time_slot 2 */
542 #define CSEM_REG_TS_2_AS 0x200040
543 /* [RW 3] The arbitration scheme of time_slot 3 */
544 #define CSEM_REG_TS_3_AS 0x200044
545 /* [RW 3] The arbitration scheme of time_slot 4 */
546 #define CSEM_REG_TS_4_AS 0x200048
547 /* [RW 3] The arbitration scheme of time_slot 5 */
548 #define CSEM_REG_TS_5_AS 0x20004c
549 /* [RW 3] The arbitration scheme of time_slot 6 */
550 #define CSEM_REG_TS_6_AS 0x200050
551 /* [RW 3] The arbitration scheme of time_slot 7 */
552 #define CSEM_REG_TS_7_AS 0x200054
553 /* [RW 3] The arbitration scheme of time_slot 8 */
554 #define CSEM_REG_TS_8_AS 0x200058
555 /* [RW 3] The arbitration scheme of time_slot 9 */
556 #define CSEM_REG_TS_9_AS 0x20005c
557 /* [RW 1] Parity mask register #0 read/write */
558 #define DBG_REG_DBG_PRTY_MASK 0xc0a8
560 =======
561 /* [R 1] Parity register #0 read */
562 #define DBG_REG_DBG_PRTY_STS 0xc09c
564 /* [RW 2] debug only: These bits indicate the credit for PCI request type 4
565 interface; MUST be configured AFTER pci_ext_buffer_strt_addr_lsb/msb are
566 configured */
567 #define DBG_REG_PCI_REQ_CREDIT 0xc120
568 /* [RW 32] Commands memory. The address to command X; row Y is to calculated
569 as 14*X+Y. */
570 #define DMAE_REG_CMD_MEM 0x102400
571 /* [RW 1] If 0 - the CRC-16c initial value is all zeroes; if 1 - the CRC-16c
572 initial value is all ones. */
573 #define DMAE_REG_CRC16C_INIT 0x10201c
574 /* [RW 1] If 0 - the CRC-16 T10 initial value is all zeroes; if 1 - the
575 CRC-16 T10 initial value is all ones. */
576 #define DMAE_REG_CRC16T10_INIT 0x102020
577 /* [RW 2] Interrupt mask register #0 read/write */
578 #define DMAE_REG_DMAE_INT_MASK 0x102054
579 /* [RW 4] Parity mask register #0 read/write */
580 #define DMAE_REG_DMAE_PRTY_MASK 0x102064
582 =======
583 /* [R 4] Parity register #0 read */
584 #define DMAE_REG_DMAE_PRTY_STS 0x102058
586 /* [RW 1] Command 0 go. */
587 #define DMAE_REG_GO_C0 0x102080
588 /* [RW 1] Command 1 go. */
589 #define DMAE_REG_GO_C1 0x102084
590 /* [RW 1] Command 10 go. */
591 #define DMAE_REG_GO_C10 0x102088
592 #define DMAE_REG_GO_C10_SIZE 1
593 /* [RW 1] Command 11 go. */
594 #define DMAE_REG_GO_C11 0x10208c
595 #define DMAE_REG_GO_C11_SIZE 1
596 /* [RW 1] Command 12 go. */
597 #define DMAE_REG_GO_C12 0x102090
598 #define DMAE_REG_GO_C12_SIZE 1
599 /* [RW 1] Command 13 go. */
600 #define DMAE_REG_GO_C13 0x102094
601 #define DMAE_REG_GO_C13_SIZE 1
602 /* [RW 1] Command 14 go. */
603 #define DMAE_REG_GO_C14 0x102098
604 #define DMAE_REG_GO_C14_SIZE 1
605 /* [RW 1] Command 15 go. */
606 #define DMAE_REG_GO_C15 0x10209c
607 #define DMAE_REG_GO_C15_SIZE 1
608 /* [RW 1] Command 10 go. */
609 #define DMAE_REG_GO_C10 0x102088
610 /* [RW 1] Command 11 go. */
611 #define DMAE_REG_GO_C11 0x10208c
612 /* [RW 1] Command 12 go. */
613 #define DMAE_REG_GO_C12 0x102090
614 /* [RW 1] Command 13 go. */
615 #define DMAE_REG_GO_C13 0x102094
616 /* [RW 1] Command 14 go. */
617 #define DMAE_REG_GO_C14 0x102098
618 /* [RW 1] Command 15 go. */
619 #define DMAE_REG_GO_C15 0x10209c
620 /* [RW 1] Command 2 go. */
621 #define DMAE_REG_GO_C2 0x1020a0
622 /* [RW 1] Command 3 go. */
623 #define DMAE_REG_GO_C3 0x1020a4
624 /* [RW 1] Command 4 go. */
625 #define DMAE_REG_GO_C4 0x1020a8
626 /* [RW 1] Command 5 go. */
627 #define DMAE_REG_GO_C5 0x1020ac
628 /* [RW 1] Command 6 go. */
629 #define DMAE_REG_GO_C6 0x1020b0
630 /* [RW 1] Command 7 go. */
631 #define DMAE_REG_GO_C7 0x1020b4
632 /* [RW 1] Command 8 go. */
633 #define DMAE_REG_GO_C8 0x1020b8
634 /* [RW 1] Command 9 go. */
635 #define DMAE_REG_GO_C9 0x1020bc
636 /* [RW 1] DMAE GRC Interface (Target; aster) enable. If 0 - the acknowledge
637 input is disregarded; valid is deasserted; all other signals are treated
638 as usual; if 1 - normal activity. */
639 #define DMAE_REG_GRC_IFEN 0x102008
640 /* [RW 1] DMAE PCI Interface (Request; ead; rite) enable. If 0 - the
641 acknowledge input is disregarded; valid is deasserted; full is asserted;
642 all other signals are treated as usual; if 1 - normal activity. */
643 #define DMAE_REG_PCI_IFEN 0x102004
644 /* [RW 4] DMAE- PCI Request Interface initial credit. Write writes the
645 initial value to the credit counter; related to the address. Read returns
646 the current value of the counter. */
647 #define DMAE_REG_PXP_REQ_INIT_CRD 0x1020c0
648 /* [RW 8] Aggregation command. */
649 #define DORQ_REG_AGG_CMD0 0x170060
650 /* [RW 8] Aggregation command. */
651 #define DORQ_REG_AGG_CMD1 0x170064
652 /* [RW 8] Aggregation command. */
653 #define DORQ_REG_AGG_CMD2 0x170068
654 /* [RW 8] Aggregation command. */
655 #define DORQ_REG_AGG_CMD3 0x17006c
656 /* [RW 28] UCM Header. */
657 #define DORQ_REG_CMHEAD_RX 0x170050
658 /* [RW 5] Interrupt mask register #0 read/write */
659 #define DORQ_REG_DORQ_INT_MASK 0x170180
660 /* [R 5] Interrupt register #0 read */
661 #define DORQ_REG_DORQ_INT_STS 0x170174
662 /* [RC 5] Interrupt register #0 read clear */
663 #define DORQ_REG_DORQ_INT_STS_CLR 0x170178
664 /* [RW 2] Parity mask register #0 read/write */
665 #define DORQ_REG_DORQ_PRTY_MASK 0x170190
667 =======
668 /* [R 2] Parity register #0 read */
669 #define DORQ_REG_DORQ_PRTY_STS 0x170184
671 /* [RW 8] The address to write the DPM CID to STORM. */
672 #define DORQ_REG_DPM_CID_ADDR 0x170044
673 /* [RW 5] The DPM mode CID extraction offset. */
674 #define DORQ_REG_DPM_CID_OFST 0x170030
675 /* [RW 12] The threshold of the DQ FIFO to send the almost full interrupt. */
676 #define DORQ_REG_DQ_FIFO_AFULL_TH 0x17007c
677 /* [RW 12] The threshold of the DQ FIFO to send the full interrupt. */
678 #define DORQ_REG_DQ_FIFO_FULL_TH 0x170078
679 /* [R 13] Current value of the DQ FIFO fill level according to following
680 pointer. The range is 0 - 256 FIFO rows; where each row stands for the
681 doorbell. */
682 #define DORQ_REG_DQ_FILL_LVLF 0x1700a4
683 /* [R 1] DQ FIFO full status. Is set; when FIFO filling level is more or
684 equal to full threshold; reset on full clear. */
685 #define DORQ_REG_DQ_FULL_ST 0x1700c0
686 /* [RW 28] The value sent to CM header in the case of CFC load error. */
687 #define DORQ_REG_ERR_CMHEAD 0x170058
688 #define DORQ_REG_IF_EN 0x170004
689 #define DORQ_REG_MODE_ACT 0x170008
690 /* [RW 5] The normal mode CID extraction offset. */
691 #define DORQ_REG_NORM_CID_OFST 0x17002c
692 /* [RW 28] TCM Header when only TCP context is loaded. */
693 #define DORQ_REG_NORM_CMHEAD_TX 0x17004c
694 /* [RW 3] The number of simultaneous outstanding requests to Context Fetch
695 Interface. */
696 #define DORQ_REG_OUTST_REQ 0x17003c
697 #define DORQ_REG_REGN 0x170038
698 /* [R 4] Current value of response A counter credit. Initial credit is
699 configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd
700 register. */
701 #define DORQ_REG_RSPA_CRD_CNT 0x1700ac
702 /* [R 4] Current value of response B counter credit. Initial credit is
703 configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd
704 register. */
705 #define DORQ_REG_RSPB_CRD_CNT 0x1700b0
706 /* [RW 4] The initial credit at the Doorbell Response Interface. The write
707 writes the same initial credit to the rspa_crd_cnt and rspb_crd_cnt. The
708 read reads this written value. */
709 #define DORQ_REG_RSP_INIT_CRD 0x170048
710 /* [RW 4] Initial activity counter value on the load request; when the
711 shortcut is done. */
712 #define DORQ_REG_SHRT_ACT_CNT 0x170070
713 /* [RW 28] TCM Header when both ULP and TCP context is loaded. */
714 #define DORQ_REG_SHRT_CMHEAD 0x170054
715 #define HC_CONFIG_0_REG_ATTN_BIT_EN_0 (0x1<<4)
716 #define HC_CONFIG_0_REG_INT_LINE_EN_0 (0x1<<3)
717 #define HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 (0x1<<2)
718 #define HC_CONFIG_0_REG_SINGLE_ISR_EN_0 (0x1<<1)
719 #define HC_REG_AGG_INT_0 0x108050
720 #define HC_REG_AGG_INT_1 0x108054
721 /* [RW 16] attention bit and attention acknowledge bits status for port 0
722 and 1 according to the following address map: addr 0 - attn_bit_0; addr 1
723 - attn_ack_bit_0; addr 2 - attn_bit_1; addr 3 - attn_ack_bit_1; */
724 #define HC_REG_ATTN_BIT 0x108120
725 /* [RW 16] attn bits status index for attn bit msg; addr 0 - function 0;
726 addr 1 - functin 1 */
727 #define HC_REG_ATTN_IDX 0x108100
728 /* [RW 32] port 0 lower 32 bits address field for attn messag. */
729 #define HC_REG_ATTN_MSG0_ADDR_L 0x108018
730 /* [RW 32] port 1 lower 32 bits address field for attn messag. */
731 #define HC_REG_ATTN_MSG1_ADDR_L 0x108020
732 /* [RW 8] status block number for attn bit msg - function 0; */
733 #define HC_REG_ATTN_NUM_P0 0x108038
734 /* [RW 8] status block number for attn bit msg - function 1 */
735 #define HC_REG_ATTN_NUM_P1 0x10803c
736 #define HC_REG_CONFIG_0 0x108000
737 #define HC_REG_CONFIG_1 0x108004
738 /* [RW 3] Parity mask register #0 read/write */
739 #define HC_REG_HC_PRTY_MASK 0x1080a0
741 =======
742 /* [R 3] Parity register #0 read */
743 #define HC_REG_HC_PRTY_STS 0x108094
745 /* [RW 17] status block interrupt mask; one in each bit means unmask; zerow
746 in each bit means mask; bit 0 - default SB; bit 1 - SB_0; bit 2 - SB_1...
747 bit 16- SB_15; addr 0 - port 0; addr 1 - port 1 */
748 #define HC_REG_INT_MASK 0x108108
749 /* [RW 16] port 0 attn bit condition monitoring; each bit that is set will
750 lock a change fron 0 to 1 in the corresponding attention signals that
751 comes from the AEU */
752 #define HC_REG_LEADING_EDGE_0 0x108040
753 #define HC_REG_LEADING_EDGE_1 0x108048
754 /* [RW 16] all producer and consumer of port 0 according to the following
755 addresses; U_prod: 0-15; C_prod: 16-31; U_cons: 32-47; C_cons:48-63;
756 Defoult_prod: U/C/X/T/Attn-64/65/66/67/68; Defoult_cons:
757 U/C/X/T/Attn-69/70/71/72/73 */
758 #define HC_REG_P0_PROD_CONS 0x108200
759 /* [RW 16] all producer and consumer of port 1according to the following
760 addresses; U_prod: 0-15; C_prod: 16-31; U_cons: 32-47; C_cons:48-63;
761 Defoult_prod: U/C/X/T/Attn-64/65/66/67/68; Defoult_cons:
762 U/C/X/T/Attn-69/70/71/72/73 */
763 #define HC_REG_P1_PROD_CONS 0x108400
764 /* [W 1] This register is write only and has 4 addresses as follow: 0 =
765 clear all PBA bits port 0; 1 = clear all pending interrupts request
766 port0; 2 = clear all PBA bits port 1; 3 = clear all pending interrupts
767 request port1; here is no meaning for the data in this register */
768 #define HC_REG_PBA_COMMAND 0x108140
769 #define HC_REG_PCI_CONFIG_0 0x108010
770 #define HC_REG_PCI_CONFIG_1 0x108014
771 /* [RW 24] all counters acording to the following address: LSB: 0=read; 1=
772 read_clear; 0-71 = HW counters (the inside order is the same as the
773 interrupt table in the spec); 72-219 = SW counters 1 (stops after first
774 consumer upd) the inside order is: 72-103 - U_non_default_p0; 104-135
775 C_non_defaul_p0; 36-145 U/C/X/T/Attn_default_p0; 146-177
776 U_non_default_p1; 178-209 C_non_defaul_p1; 10-219 U/C/X/T/Attn_default_p1
777 ; 220-367 = SW counters 2 (stops when prod=cons) the inside order is:
778 220-251 - U_non_default_p0; 252-283 C_non_defaul_p0; 84-293
779 U/C/X/T/Attn_default_p0; 294-325 U_non_default_p1; 326-357
780 C_non_defaul_p1; 58-367 U/C/X/T/Attn_default_p1 ; 368-515 = mailbox
781 counters; (the inside order of the mailbox counter is 368-431 U and C
782 non_default_p0; 432-441 U/C/X/T/Attn_default_p0; 442-505 U and C
783 non_default_p1; 506-515 U/C/X/T/Attn_default_p1) */
784 #define HC_REG_STATISTIC_COUNTERS 0x109000
785 /* [RW 16] port 0 attn bit condition monitoring; each bit that is set will
786 lock a change fron 1 to 0 in the corresponding attention signals that
787 comes from the AEU */
788 #define HC_REG_TRAILING_EDGE_0 0x108044
789 #define HC_REG_TRAILING_EDGE_1 0x10804c
790 #define HC_REG_UC_RAM_ADDR_0 0x108028
791 #define HC_REG_UC_RAM_ADDR_1 0x108030
792 /* [RW 16] ustorm address for coalesc now message */
793 #define HC_REG_USTORM_ADDR_FOR_COALESCE 0x108068
794 #define HC_REG_VQID_0 0x108008
795 #define HC_REG_VQID_1 0x10800c
796 #define MCP_REG_MCPR_NVM_ACCESS_ENABLE 0x86424
797 #define MCP_REG_MCPR_NVM_ADDR 0x8640c
798 #define MCP_REG_MCPR_NVM_CFG4 0x8642c
799 #define MCP_REG_MCPR_NVM_COMMAND 0x86400
800 #define MCP_REG_MCPR_NVM_READ 0x86410
801 #define MCP_REG_MCPR_NVM_SW_ARB 0x86420
802 #define MCP_REG_MCPR_NVM_WRITE 0x86408
803 #define MCP_REG_MCPR_NVM_WRITE1 0x86428
804 #define MCP_REG_MCPR_SCRATCH 0xa0000
805 /* [R 32] read first 32 bit after inversion of function 0. mapped as
806 follows: [0] NIG attention for function0; [1] NIG attention for
807 function1; [2] GPIO1 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp;
808 [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9]
809 GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE
810 glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0;
811 [13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16]
812 MSI/X indication for mcp; [17] MSI/X indication for function 1; [18] BRB
813 Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw
814 interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity
815 error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] TCM Hw
816 interrupt; [28] TSEMI Parity error; [29] TSEMI Hw interrupt; [30] PBF
817 Parity error; [31] PBF Hw interrupt; */
818 #define MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 0xa42c
819 #define MISC_REG_AEU_AFTER_INVERT_1_FUNC_1 0xa430
820 /* [R 32] read first 32 bit after inversion of mcp. mapped as follows: [0]
821 NIG attention for function0; [1] NIG attention for function1; [2] GPIO1
822 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1;
823 [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10]
824 PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event
825 function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP
826 Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for
827 mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19]
828 BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC
829 Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw
830 interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI
831 Parity error; [29] TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw
832 interrupt; */
833 #define MISC_REG_AEU_AFTER_INVERT_1_MCP 0xa434
834 /* [R 32] read second 32 bit after inversion of function 0. mapped as
835 follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
836 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
837 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
838 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
839 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
840 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
841 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
842 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
843 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
844 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
845 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
846 interrupt; */
847 #define MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 0xa438
848 #define MISC_REG_AEU_AFTER_INVERT_2_FUNC_1 0xa43c
849 /* [R 32] read second 32 bit after inversion of mcp. mapped as follows: [0]
850 PBClient Parity error; [1] PBClient Hw interrupt; [2] QM Parity error;
851 [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw interrupt;
852 [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9]
853 XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12]
854 DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity
855 error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux
856 PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt;
857 [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error;
858 [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt;
859 [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error;
860 [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt; */
861 #define MISC_REG_AEU_AFTER_INVERT_2_MCP 0xa440
862 /* [R 32] read third 32 bit after inversion of function 0. mapped as
863 follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity
864 error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; [5]
865 PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
866 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
867 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
868 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
869 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
870 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
871 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
872 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
873 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
874 attn1; */
875 #define MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 0xa444
876 #define MISC_REG_AEU_AFTER_INVERT_3_FUNC_1 0xa448
877 /* [R 32] read third 32 bit after inversion of mcp. mapped as follows: [0]
878 CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity error; [3] PXP
879 Hw interrupt; [4] PXPpciClockClient Parity error; [5] PXPpciClockClient
880 Hw interrupt; [6] CFC Parity error; [7] CFC Hw interrupt; [8] CDU Parity
881 error; [9] CDU Hw interrupt; [10] DMAE Parity error; [11] DMAE Hw
882 interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) Hw interrupt; [14]
883 MISC Parity error; [15] MISC Hw interrupt; [16] pxp_misc_mps_attn; [17]
884 Flash event; [18] SMB event; [19] MCP attn0; [20] MCP attn1; [21] SW
885 timers attn_1 func0; [22] SW timers attn_2 func0; [23] SW timers attn_3
886 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW timers attn_1
887 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 func1; [29] SW
888 timers attn_4 func1; [30] General attn0; [31] General attn1; */
889 #define MISC_REG_AEU_AFTER_INVERT_3_MCP 0xa44c
890 /* [R 32] read fourth 32 bit after inversion of function 0. mapped as
891 follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
892 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
893 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
894 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
895 [14] General attn16; [15] General attn17; [16] General attn18; [17]
896 General attn19; [18] General attn20; [19] General attn21; [20] Main power
897 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
898 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
899 Latched timeout attention; [27] GRC Latched reserved access attention;
900 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
901 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
902 #define MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 0xa450
903 #define MISC_REG_AEU_AFTER_INVERT_4_FUNC_1 0xa454
904 /* [R 32] read fourth 32 bit after inversion of mcp. mapped as follows: [0]
905 General attn2; [1] General attn3; [2] General attn4; [3] General attn5;
906 [4] General attn6; [5] General attn7; [6] General attn8; [7] General
907 attn9; [8] General attn10; [9] General attn11; [10] General attn12; [11]
908 General attn13; [12] General attn14; [13] General attn15; [14] General
909 attn16; [15] General attn17; [16] General attn18; [17] General attn19;
910 [18] General attn20; [19] General attn21; [20] Main power interrupt; [21]
911 RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN Latched attn; [24]
912 RBCU Latched attn; [25] RBCP Latched attn; [26] GRC Latched timeout
913 attention; [27] GRC Latched reserved access attention; [28] MCP Latched
914 rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched
915 ump_tx_parity; [31] MCP Latched scpad_parity; */
916 #define MISC_REG_AEU_AFTER_INVERT_4_MCP 0xa458
917 /* [W 11] write to this register results with the clear of the latched
918 signals; one in d0 clears RBCR latch; one in d1 clears RBCT latch; one in
919 d2 clears RBCN latch; one in d3 clears RBCU latch; one in d4 clears RBCP
920 latch; one in d5 clears GRC Latched timeout attention; one in d6 clears
921 GRC Latched reserved access attention; one in d7 clears Latched
922 rom_parity; one in d8 clears Latched ump_rx_parity; one in d9 clears
923 Latched ump_tx_parity; one in d10 clears Latched scpad_parity; read from
924 this register return zero */
925 #define MISC_REG_AEU_CLR_LATCH_SIGNAL 0xa45c
926 /* [RW 32] first 32b for enabling the output for function 0 output0. mapped
927 as follows: [0] NIG attention for function0; [1] NIG attention for
928 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
929 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
930 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
931 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
932 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
933 SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X
934 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
935 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
936 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
937 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
938 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
939 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0 0xa06c
940 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1 0xa07c
941 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_3 0xa09c
942 /* [RW 32] first 32b for enabling the output for function 1 output0. mapped
943 as follows: [0] NIG attention for function0; [1] NIG attention for
944 function1; [2] GPIO1 function 1; [3] GPIO2 function 1; [4] GPIO3 function
945 1; [5] GPIO4 function 1; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
946 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
947 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
948 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
949 SPIO4; [15] SPIO5; [16] MSI/X indication for function 1; [17] MSI/X
950 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
951 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
952 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
953 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
954 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
955 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 0xa10c
956 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 0xa11c
957 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_3 0xa13c
958 /* [RW 32] first 32b for enabling the output for close the gate nig 0.
959 mapped as follows: [0] NIG attention for function0; [1] NIG attention for
960 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
961 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
962 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
963 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
964 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
965 SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X
966 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
967 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
968 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
969 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
970 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
971 #define MISC_REG_AEU_ENABLE1_NIG_0 0xa0ec
972 #define MISC_REG_AEU_ENABLE1_NIG_1 0xa18c
973 /* [RW 32] first 32b for enabling the output for close the gate pxp 0.
974 mapped as follows: [0] NIG attention for function0; [1] NIG attention for
975 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
976 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
977 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
978 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
979 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
980 SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X
981 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
982 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
983 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
984 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
985 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
986 #define MISC_REG_AEU_ENABLE1_PXP_0 0xa0fc
987 #define MISC_REG_AEU_ENABLE1_PXP_1 0xa19c
988 /* [RW 32] second 32b for enabling the output for function 0 output0. mapped
989 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
990 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
991 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
992 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
993 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
994 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
995 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
996 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
997 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
998 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
999 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
1000 interrupt; */
1001 #define MISC_REG_AEU_ENABLE2_FUNC_0_OUT_0 0xa070
1002 #define MISC_REG_AEU_ENABLE2_FUNC_0_OUT_1 0xa080
1003 /* [RW 32] second 32b for enabling the output for function 1 output0. mapped
1004 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1005 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1006 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
1007 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
1008 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
1009 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
1010 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
1011 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
1012 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
1013 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
1014 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
1015 interrupt; */
1016 #define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_0 0xa110
1017 #define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_1 0xa120
1018 /* [RW 32] second 32b for enabling the output for close the gate nig 0.
1019 mapped as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt;
1020 [2] QM Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5]
1021 Timers Hw interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8]
1022 XCM Parity error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11]
1023 XSEMI Hw interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw
1024 interrupt; [14] NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI
1025 core Parity error; [17] Vaux PCI core Hw interrupt; [18] Debug Parity
1026 error; [19] Debug Hw interrupt; [20] USDM Parity error; [21] USDM Hw
1027 interrupt; [22] UCM Parity error; [23] UCM Hw interrupt; [24] USEMI
1028 Parity error; [25] USEMI Hw interrupt; [26] UPB Parity error; [27] UPB Hw
1029 interrupt; [28] CSDM Parity error; [29] CSDM Hw interrupt; [30] CCM
1030 Parity error; [31] CCM Hw interrupt; */
1031 #define MISC_REG_AEU_ENABLE2_NIG_0 0xa0f0
1032 #define MISC_REG_AEU_ENABLE2_NIG_1 0xa190
1033 /* [RW 32] second 32b for enabling the output for close the gate pxp 0.
1034 mapped as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt;
1035 [2] QM Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5]
1036 Timers Hw interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8]
1037 XCM Parity error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11]
1038 XSEMI Hw interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw
1039 interrupt; [14] NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI
1040 core Parity error; [17] Vaux PCI core Hw interrupt; [18] Debug Parity
1041 error; [19] Debug Hw interrupt; [20] USDM Parity error; [21] USDM Hw
1042 interrupt; [22] UCM Parity error; [23] UCM Hw interrupt; [24] USEMI
1043 Parity error; [25] USEMI Hw interrupt; [26] UPB Parity error; [27] UPB Hw
1044 interrupt; [28] CSDM Parity error; [29] CSDM Hw interrupt; [30] CCM
1045 Parity error; [31] CCM Hw interrupt; */
1046 #define MISC_REG_AEU_ENABLE2_PXP_0 0xa100
1047 #define MISC_REG_AEU_ENABLE2_PXP_1 0xa1a0
1048 /* [RW 32] third 32b for enabling the output for function 0 output0. mapped
1049 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1050 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1051 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1052 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1053 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1054 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1055 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1056 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1057 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1058 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1059 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1060 attn1; */
1061 #define MISC_REG_AEU_ENABLE3_FUNC_0_OUT_0 0xa074
1062 #define MISC_REG_AEU_ENABLE3_FUNC_0_OUT_1 0xa084
1063 /* [RW 32] third 32b for enabling the output for function 1 output0. mapped
1064 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1065 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1066 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1067 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1068 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1069 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1070 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1071 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1072 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1073 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1074 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1075 attn1; */
1076 #define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_0 0xa114
1077 #define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_1 0xa124
1078 /* [RW 32] third 32b for enabling the output for close the gate nig 0.
1079 mapped as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2]
1080 PXP Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity
1081 error; [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC
1082 Hw interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE
1083 Parity error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13]
1084 IGU (HC) Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt;
1085 [16] pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0;
1086 [20] MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0;
1087 [23] SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST;
1088 [26] SW timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers
1089 attn_3 func1; [29] SW timers attn_4 func1; [30] General attn0; [31]
1090 General attn1; */
1091 #define MISC_REG_AEU_ENABLE3_NIG_0 0xa0f4
1092 #define MISC_REG_AEU_ENABLE3_NIG_1 0xa194
1093 /* [RW 32] third 32b for enabling the output for close the gate pxp 0.
1094 mapped as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2]
1095 PXP Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity
1096 error; [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC
1097 Hw interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE
1098 Parity error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13]
1099 IGU (HC) Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt;
1100 [16] pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0;
1101 [20] MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0;
1102 [23] SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST;
1103 [26] SW timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers
1104 attn_3 func1; [29] SW timers attn_4 func1; [30] General attn0; [31]
1105 General attn1; */
1106 #define MISC_REG_AEU_ENABLE3_PXP_0 0xa104
1107 #define MISC_REG_AEU_ENABLE3_PXP_1 0xa1a4
1108 /* [RW 32] fourth 32b for enabling the output for function 0 output0.mapped
1109 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1110 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1111 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1112 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1113 [14] General attn16; [15] General attn17; [16] General attn18; [17]
1114 General attn19; [18] General attn20; [19] General attn21; [20] Main power
1115 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1116 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1117 Latched timeout attention; [27] GRC Latched reserved access attention;
1118 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1119 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1120 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0 0xa078
1121 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_2 0xa098
1122 /* [RW 32] fourth 32b for enabling the output for function 1 output0.mapped
1123 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1124 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1125 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1126 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1127 [14] General attn16; [15] General attn17; [16] General attn18; [17]
1128 General attn19; [18] General attn20; [19] General attn21; [20] Main power
1129 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1130 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1131 Latched timeout attention; [27] GRC Latched reserved access attention;
1132 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1133 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1134 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0 0xa118
1135 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_2 0xa138
1136 /* [RW 32] fourth 32b for enabling the output for close the gate nig
1137 0.mapped as follows: [0] General attn2; [1] General attn3; [2] General
1138 attn4; [3] General attn5; [4] General attn6; [5] General attn7; [6]
1139 General attn8; [7] General attn9; [8] General attn10; [9] General attn11;
1140 [10] General attn12; [11] General attn13; [12] General attn14; [13]
1141 General attn15; [14] General attn16; [15] General attn17; [16] General
1142 attn18; [17] General attn19; [18] General attn20; [19] General attn21;
1143 [20] Main power interrupt; [21] RBCR Latched attn; [22] RBCT Latched
1144 attn; [23] RBCN Latched attn; [24] RBCU Latched attn; [25] RBCP Latched
1145 attn; [26] GRC Latched timeout attention; [27] GRC Latched reserved
1146 access attention; [28] MCP Latched rom_parity; [29] MCP Latched
1147 ump_rx_parity; [30] MCP Latched ump_tx_parity; [31] MCP Latched
1148 scpad_parity; */
1149 #define MISC_REG_AEU_ENABLE4_NIG_0 0xa0f8
1150 #define MISC_REG_AEU_ENABLE4_NIG_1 0xa198
1151 /* [RW 32] fourth 32b for enabling the output for close the gate pxp
1152 0.mapped as follows: [0] General attn2; [1] General attn3; [2] General
1153 attn4; [3] General attn5; [4] General attn6; [5] General attn7; [6]
1154 General attn8; [7] General attn9; [8] General attn10; [9] General attn11;
1155 [10] General attn12; [11] General attn13; [12] General attn14; [13]
1156 General attn15; [14] General attn16; [15] General attn17; [16] General
1157 attn18; [17] General attn19; [18] General attn20; [19] General attn21;
1158 [20] Main power interrupt; [21] RBCR Latched attn; [22] RBCT Latched
1159 attn; [23] RBCN Latched attn; [24] RBCU Latched attn; [25] RBCP Latched
1160 attn; [26] GRC Latched timeout attention; [27] GRC Latched reserved
1161 access attention; [28] MCP Latched rom_parity; [29] MCP Latched
1162 ump_rx_parity; [30] MCP Latched ump_tx_parity; [31] MCP Latched
1163 scpad_parity; */
1164 #define MISC_REG_AEU_ENABLE4_PXP_0 0xa108
1165 #define MISC_REG_AEU_ENABLE4_PXP_1 0xa1a8
1166 /* [RW 1] set/clr general attention 0; this will set/clr bit 94 in the aeu
1167 128 bit vector */
1168 #define MISC_REG_AEU_GENERAL_ATTN_0 0xa000
1169 #define MISC_REG_AEU_GENERAL_ATTN_1 0xa004
1170 #define MISC_REG_AEU_GENERAL_ATTN_10 0xa028
1171 #define MISC_REG_AEU_GENERAL_ATTN_11 0xa02c
1172 #define MISC_REG_AEU_GENERAL_ATTN_12 0xa030
1173 #define MISC_REG_AEU_GENERAL_ATTN_13 0xa034
1174 #define MISC_REG_AEU_GENERAL_ATTN_14 0xa038
1175 #define MISC_REG_AEU_GENERAL_ATTN_15 0xa03c
1176 #define MISC_REG_AEU_GENERAL_ATTN_16 0xa040
1177 #define MISC_REG_AEU_GENERAL_ATTN_17 0xa044
1178 #define MISC_REG_AEU_GENERAL_ATTN_18 0xa048
1179 #define MISC_REG_AEU_GENERAL_ATTN_19 0xa04c
1181 =======
1182 #define MISC_REG_AEU_GENERAL_ATTN_10 0xa028
1184 #define MISC_REG_AEU_GENERAL_ATTN_11 0xa02c
1185 #define MISC_REG_AEU_GENERAL_ATTN_2 0xa008
1186 #define MISC_REG_AEU_GENERAL_ATTN_20 0xa050
1187 #define MISC_REG_AEU_GENERAL_ATTN_21 0xa054
1188 #define MISC_REG_AEU_GENERAL_ATTN_3 0xa00c
1189 #define MISC_REG_AEU_GENERAL_ATTN_4 0xa010
1190 #define MISC_REG_AEU_GENERAL_ATTN_5 0xa014
1191 #define MISC_REG_AEU_GENERAL_ATTN_6 0xa018
1193 =======
1194 #define MISC_REG_AEU_GENERAL_ATTN_7 0xa01c
1195 #define MISC_REG_AEU_GENERAL_ATTN_8 0xa020
1196 #define MISC_REG_AEU_GENERAL_ATTN_9 0xa024
1198 /* [RW 32] first 32b for inverting the input for function 0; for each bit:
1199 0= do not invert; 1= invert; mapped as follows: [0] NIG attention for
1200 function0; [1] NIG attention for function1; [2] GPIO1 mcp; [3] GPIO2 mcp;
1201 [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1; [7] GPIO2 function 1;
1202 [8] GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
1203 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
1204 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
1205 SPIO4; [15] SPIO5; [16] MSI/X indication for mcp; [17] MSI/X indication
1206 for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; [20] PRS
1207 Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] SRC Hw
1208 interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] TCM
1209 Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] TSEMI
1210 Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
1211 #define MISC_REG_AEU_INVERTER_1_FUNC_0 0xa22c
1212 #define MISC_REG_AEU_INVERTER_1_FUNC_1 0xa23c
1213 /* [RW 32] second 32b for inverting the input for function 0; for each bit:
1214 0= do not invert; 1= invert. mapped as follows: [0] PBClient Parity
1215 error; [1] PBClient Hw interrupt; [2] QM Parity error; [3] QM Hw
1216 interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; [6] XSDM
1217 Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] XCM Hw
1218 interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12]
1219 DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity
1220 error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux
1221 PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt;
1222 [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error;
1223 [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt;
1224 [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error;
1225 [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt; */
1226 #define MISC_REG_AEU_INVERTER_2_FUNC_0 0xa230
1227 #define MISC_REG_AEU_INVERTER_2_FUNC_1 0xa240
1228 /* [RW 10] [7:0] = mask 8 attention output signals toward IGU function0;
1229 [9:8] = mask close the gates signals of function 0 toward PXP [8] and NIG
1230 [9]. Zero = mask; one = unmask */
1231 #define MISC_REG_AEU_MASK_ATTN_FUNC_0 0xa060
1232 #define MISC_REG_AEU_MASK_ATTN_FUNC_1 0xa064
1233 /* [R 4] This field indicates the type of the device. '0' - 2 Ports; '1' - 1
1234 Port. */
1235 #define MISC_REG_BOND_ID 0xa400
1236 /* [R 8] These bits indicate the metal revision of the chip. This value
1237 starts at 0x00 for each all-layer tape-out and increments by one for each
1238 tape-out. */
1239 #define MISC_REG_CHIP_METAL 0xa404
1240 /* [R 16] These bits indicate the part number for the chip. */
1241 #define MISC_REG_CHIP_NUM 0xa408
1242 /* [R 4] These bits indicate the base revision of the chip. This value
1243 starts at 0x0 for the A0 tape-out and increments by one for each
1244 all-layer tape-out. */
1245 #define MISC_REG_CHIP_REV 0xa40c
1247 =======
1248 /* [RW 32] The following driver registers(1..6) represent 6 drivers and 32
1249 clients. Each client can be controlled by one driver only. One in each
1250 bit represent that this driver control the appropriate client (Ex: bit 5
1251 is set means this driver control client number 5). addr1 = set; addr0 =
1252 clear; read from both addresses will give the same result = status. write
1253 to address 1 will set a request to control all the clients that their
1254 appropriate bit (in the write command) is set. if the client is free (the
1255 appropriate bit in all the other drivers is clear) one will be written to
1256 that driver register; if the client isn't free the bit will remain zero.
1257 if the appropriate bit is set (the driver request to gain control on a
1258 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
1259 interrupt will be asserted). write to address 0 will set a request to
1260 free all the clients that their appropriate bit (in the write command) is
1261 set. if the appropriate bit is clear (the driver request to free a client
1262 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
1263 be asserted). */
1264 #define MISC_REG_DRIVER_CONTROL_1 0xa510
1265 /* [RW 32] GPIO. [31-28] FLOAT port 0; [27-24] FLOAT port 0; When any of
1266 these bits is written as a '1'; the corresponding SPIO bit will turn off
1267 it's drivers and become an input. This is the reset state of all GPIO
1268 pins. The read value of these bits will be a '1' if that last command
1269 (#SET; #CLR; or #FLOAT) for this bit was a #FLOAT. (reset value 0xff).
1270 [23-20] CLR port 1; 19-16] CLR port 0; When any of these bits is written
1271 as a '1'; the corresponding GPIO bit will drive low. The read value of
1272 these bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for
1273 this bit was a #CLR. (reset value 0). [15-12] SET port 1; 11-8] port 0;
1274 SET When any of these bits is written as a '1'; the corresponding GPIO
1275 bit will drive high (if it has that capability). The read value of these
1276 bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for this
1277 bit was a #SET. (reset value 0). [7-4] VALUE port 1; [3-0] VALUE port 0;
1278 RO; These bits indicate the read value of each of the eight GPIO pins.
1279 This is the result value of the pin; not the drive value. Writing these
1280 bits will have not effect. */
1281 #define MISC_REG_GPIO 0xa490
1283 /* [RW 1] Setting this bit enables a timer in the GRC block to timeout any
1284 access that does not finish within
1285 ~misc_registers_grc_timout_val.grc_timeout_val cycles. When this bit is
1286 cleared; this timeout is disabled. If this timeout occurs; the GRC shall
1287 assert it attention output. */
1288 #define MISC_REG_GRC_TIMEOUT_EN 0xa280
1289 /* [RW 28] 28 LSB of LCPLL first register; reset val = 521. inside order of
1290 the bits is: [2:0] OAC reset value 001) CML output buffer bias control;
1291 111 for +40%; 011 for +20%; 001 for 0%; 000 for -20%. [5:3] Icp_ctrl
1292 (reset value 001) Charge pump current control; 111 for 720u; 011 for
1293 600u; 001 for 480u and 000 for 360u. [7:6] Bias_ctrl (reset value 00)
1294 Global bias control; When bit 7 is high bias current will be 10 0gh; When
1295 bit 6 is high bias will be 100w; Valid values are 00; 10; 01. [10:8]
1296 Pll_observe (reset value 010) Bits to control observability. bit 10 is
1297 for test bias; bit 9 is for test CK; bit 8 is test Vc. [12:11] Vth_ctrl
1298 (reset value 00) Comparator threshold control. 00 for 0.6V; 01 for 0.54V
1299 and 10 for 0.66V. [13] pllSeqStart (reset value 0) Enables VCO tuning
1300 sequencer: 1= sequencer disabled; 0= sequencer enabled (inverted
1301 internally). [14] reserved (reset value 0) Reset for VCO sequencer is
1302 connected to RESET input directly. [15] capRetry_en (reset value 0)
1303 enable retry on cap search failure (inverted). [16] freqMonitor_e (reset
1304 value 0) bit to continuously monitor vco freq (inverted). [17]
1305 freqDetRestart_en (reset value 0) bit to enable restart when not freq
1306 locked (inverted). [18] freqDetRetry_en (reset value 0) bit to enable
1307 retry on freq det failure(inverted). [19] pllForceFdone_en (reset value
1308 0) bit to enable pllForceFdone & pllForceFpass into pllSeq. [20]
1309 pllForceFdone (reset value 0) bit to force freqDone. [21] pllForceFpass
1310 (reset value 0) bit to force freqPass. [22] pllForceDone_en (reset value
1311 0) bit to enable pllForceCapDone. [23] pllForceCapDone (reset value 0)
1312 bit to force capDone. [24] pllForceCapPass_en (reset value 0) bit to
1313 enable pllForceCapPass. [25] pllForceCapPass (reset value 0) bit to force
1314 capPass. [26] capRestart (reset value 0) bit to force cap sequencer to
1315 restart. [27] capSelectM_en (reset value 0) bit to enable cap select
1316 register bits. */
1317 #define MISC_REG_LCPLL_CTRL_1 0xa2a4
1318 #define MISC_REG_LCPLL_CTRL_REG_2 0xa2a8
1319 /* [RW 4] Interrupt mask register #0 read/write */
1320 #define MISC_REG_MISC_INT_MASK 0xa388
1321 /* [RW 1] Parity mask register #0 read/write */
1322 #define MISC_REG_MISC_PRTY_MASK 0xa398
1324 =======
1325 /* [R 1] Parity register #0 read */
1326 #define MISC_REG_MISC_PRTY_STS 0xa38c
1328 /* [RW 32] 32 LSB of storm PLL first register; reset val = 0x 071d2911.
1329 inside order of the bits is: [0] P1 divider[0] (reset value 1); [1] P1
1330 divider[1] (reset value 0); [2] P1 divider[2] (reset value 0); [3] P1
1331 divider[3] (reset value 0); [4] P2 divider[0] (reset value 1); [5] P2
1332 divider[1] (reset value 0); [6] P2 divider[2] (reset value 0); [7] P2
1333 divider[3] (reset value 0); [8] ph_det_dis (reset value 1); [9]
1334 freq_det_dis (reset value 0); [10] Icpx[0] (reset value 0); [11] Icpx[1]
1335 (reset value 1); [12] Icpx[2] (reset value 0); [13] Icpx[3] (reset value
1336 1); [14] Icpx[4] (reset value 0); [15] Icpx[5] (reset value 0); [16]
1337 Rx[0] (reset value 1); [17] Rx[1] (reset value 0); [18] vc_en (reset
1338 value 1); [19] vco_rng[0] (reset value 1); [20] vco_rng[1] (reset value
1339 1); [21] Kvco_xf[0] (reset value 0); [22] Kvco_xf[1] (reset value 0);
1340 [23] Kvco_xf[2] (reset value 0); [24] Kvco_xs[0] (reset value 1); [25]
1341 Kvco_xs[1] (reset value 1); [26] Kvco_xs[2] (reset value 1); [27]
1342 testd_en (reset value 0); [28] testd_sel[0] (reset value 0); [29]
1343 testd_sel[1] (reset value 0); [30] testd_sel[2] (reset value 0); [31]
1344 testa_en (reset value 0); */
1345 #define MISC_REG_PLL_STORM_CTRL_1 0xa294
1346 #define MISC_REG_PLL_STORM_CTRL_2 0xa298
1347 #define MISC_REG_PLL_STORM_CTRL_3 0xa29c
1348 #define MISC_REG_PLL_STORM_CTRL_4 0xa2a0
1349 /* [RW 32] reset reg#1; rite/read one = the specific block is out of reset;
1350 write/read zero = the specific block is in reset; addr 0-wr- the write
1351 value will be written to the register; addr 1-set - one will be written
1352 to all the bits that have the value of one in the data written (bits that
1353 have the value of zero will not be change) ; addr 2-clear - zero will be
1354 written to all the bits that have the value of one in the data written
1355 (bits that have the value of zero will not be change); addr 3-ignore;
1356 read ignore from all addr except addr 00; inside order of the bits is:
1357 [0] rst_brb1; [1] rst_prs; [2] rst_src; [3] rst_tsdm; [4] rst_tsem; [5]
1358 rst_tcm; [6] rst_rbcr; [7] rst_nig; [8] rst_usdm; [9] rst_ucm; [10]
1359 rst_usem; [11] rst_upb; [12] rst_ccm; [13] rst_csem; [14] rst_csdm; [15]
1360 rst_rbcu; [16] rst_pbf; [17] rst_qm; [18] rst_tm; [19] rst_dorq; [20]
1361 rst_xcm; [21] rst_xsdm; [22] rst_xsem; [23] rst_rbct; [24] rst_cdu; [25]
1362 rst_cfc; [26] rst_pxp; [27] rst_pxpv; [28] rst_rbcp; [29] rst_hc; [30]
1363 rst_dmae; [31] rst_semi_rtc; */
1364 #define MISC_REG_RESET_REG_1 0xa580
1365 #define MISC_REG_RESET_REG_2 0xa590
1366 /* [RW 20] 20 bit GRC address where the scratch-pad of the MCP that is
1367 shared with the driver resides */
1368 #define MISC_REG_SHARED_MEM_ADDR 0xa2b4
1370 =======
1371 /* [RW 32] SPIO. [31-24] FLOAT When any of these bits is written as a '1';
1372 the corresponding SPIO bit will turn off it's drivers and become an
1373 input. This is the reset state of all SPIO pins. The read value of these
1374 bits will be a '1' if that last command (#SET; #CL; or #FLOAT) for this
1375 bit was a #FLOAT. (reset value 0xff). [23-16] CLR When any of these bits
1376 is written as a '1'; the corresponding SPIO bit will drive low. The read
1377 value of these bits will be a '1' if that last command (#SET; #CLR; or
1378 #FLOAT) for this bit was a #CLR. (reset value 0). [15-8] SET When any of
1379 these bits is written as a '1'; the corresponding SPIO bit will drive
1380 high (if it has that capability). The read value of these bits will be a
1381 '1' if that last command (#SET; #CLR; or #FLOAT) for this bit was a #SET.
1382 (reset value 0). [7-0] VALUE RO; These bits indicate the read value of
1383 each of the eight SPIO pins. This is the result value of the pin; not the
1384 drive value. Writing these bits will have not effect. Each 8 bits field
1385 is divided as follows: [0] VAUX Enable; when pulsed low; enables supply
1386 from VAUX. (This is an output pin only; the FLOAT field is not applicable
1387 for this pin); [1] VAUX Disable; when pulsed low; disables supply form
1388 VAUX. (This is an output pin only; FLOAT field is not applicable for this
1389 pin); [2] SEL_VAUX_B - Control to power switching logic. Drive low to
1390 select VAUX supply. (This is an output pin only; it is not controlled by
1391 the SET and CLR fields; it is controlled by the Main Power SM; the FLOAT
1392 field is not applicable for this pin; only the VALUE fields is relevant -
1393 it reflects the output value); [3] reserved; [4] spio_4; [5] spio_5; [6]
1394 Bit 0 of UMP device ID select; read by UMP firmware; [7] Bit 1 of UMP
1395 device ID select; read by UMP firmware. */
1396 #define MISC_REG_SPIO 0xa4fc
1397 /* [RW 8] These bits enable the SPIO_INTs to signals event to the IGU/MC.
1398 according to the following map: [3:0] reserved; [4] spio_4 [5] spio_5;
1399 [7:0] reserved */
1400 #define MISC_REG_SPIO_EVENT_EN 0xa2b8
1401 /* [RW 32] SPIO INT. [31-24] OLD_CLR Writing a '1' to these bit clears the
1402 corresponding bit in the #OLD_VALUE register. This will acknowledge an
1403 interrupt on the falling edge of corresponding SPIO input (reset value
1404 0). [23-16] OLD_SET Writing a '1' to these bit sets the corresponding bit
1405 in the #OLD_VALUE register. This will acknowledge an interrupt on the
1406 rising edge of corresponding SPIO input (reset value 0). [15-8] OLD_VALUE
1407 RO; These bits indicate the old value of the SPIO input value. When the
1408 ~INT_STATE bit is set; this bit indicates the OLD value of the pin such
1409 that if ~INT_STATE is set and this bit is '0'; then the interrupt is due
1410 to a low to high edge. If ~INT_STATE is set and this bit is '1'; then the
1411 interrupt is due to a high to low edge (reset value 0). [7-0] INT_STATE
1412 RO; These bits indicate the current SPIO interrupt state for each SPIO
1413 pin. This bit is cleared when the appropriate #OLD_SET or #OLD_CLR
1414 command bit is written. This bit is set when the SPIO input does not
1415 match the current value in #OLD_VALUE (reset value 0). */
1416 #define MISC_REG_SPIO_INT 0xa500
1417 /* [RW 1] Set by the MCP to remember if one or more of the drivers is/are
1418 loaded; 0-prepare; -unprepare */
1419 #define MISC_REG_UNPREPARED 0xa424
1421 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT (0x1<<0)
1422 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS (0x1<<9)
1423 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G (0x1<<15)
1424 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS (0xf<<18)
1425 /* [RW 1] Input enable for RX_BMAC0 IF */
1426 #define NIG_REG_BMAC0_IN_EN 0x100ac
1427 /* [RW 1] output enable for TX_BMAC0 IF */
1428 #define NIG_REG_BMAC0_OUT_EN 0x100e0
1429 /* [RW 1] output enable for TX BMAC pause port 0 IF */
1430 #define NIG_REG_BMAC0_PAUSE_OUT_EN 0x10110
1431 /* [RW 1] output enable for RX_BMAC0_REGS IF */
1432 #define NIG_REG_BMAC0_REGS_OUT_EN 0x100e8
1433 /* [RW 1] output enable for RX BRB1 port0 IF */
1434 #define NIG_REG_BRB0_OUT_EN 0x100f8
1435 /* [RW 1] Input enable for TX BRB1 pause port 0 IF */
1436 #define NIG_REG_BRB0_PAUSE_IN_EN 0x100c4
1437 /* [RW 1] output enable for RX BRB1 port1 IF */
1438 #define NIG_REG_BRB1_OUT_EN 0x100fc
1439 /* [RW 1] Input enable for TX BRB1 pause port 1 IF */
1440 #define NIG_REG_BRB1_PAUSE_IN_EN 0x100c8
1441 /* [RW 1] output enable for RX BRB1 LP IF */
1442 #define NIG_REG_BRB_LB_OUT_EN 0x10100
1443 /* [WB_W 72] Debug packet to LP from RBC; Data spelling:[63:0] data; 64]
1444 error; [67:65]eop_bvalid; [68]eop; [69]sop; [70]port_id; 71]flush */
1445 #define NIG_REG_DEBUG_PACKET_LB 0x10800
1446 /* [RW 1] Input enable for TX Debug packet */
1447 #define NIG_REG_EGRESS_DEBUG_IN_EN 0x100dc
1448 /* [RW 1] If 1 - egress drain mode for port0 is active. In this mode all
1449 packets from PBFare not forwarded to the MAC and just deleted from FIFO.
1450 First packet may be deleted from the middle. And last packet will be
1451 always deleted till the end. */
1452 #define NIG_REG_EGRESS_DRAIN0_MODE 0x10060
1453 /* [RW 1] Output enable to EMAC0 */
1454 #define NIG_REG_EGRESS_EMAC0_OUT_EN 0x10120
1455 /* [RW 1] MAC configuration for packets of port0. If 1 - all packet outputs
1456 to emac for port0; other way to bmac for port0 */
1457 #define NIG_REG_EGRESS_EMAC0_PORT 0x10058
1458 /* [RW 1] Input enable for TX PBF user packet port0 IF */
1459 #define NIG_REG_EGRESS_PBF0_IN_EN 0x100cc
1460 /* [RW 1] Input enable for TX PBF user packet port1 IF */
1461 #define NIG_REG_EGRESS_PBF1_IN_EN 0x100d0
1462 /* [RW 1] Input enable for RX_EMAC0 IF */
1463 #define NIG_REG_EMAC0_IN_EN 0x100a4
1464 /* [RW 1] output enable for TX EMAC pause port 0 IF */
1465 #define NIG_REG_EMAC0_PAUSE_OUT_EN 0x10118
1466 /* [R 1] status from emac0. This bit is set when MDINT from either the
1467 EXT_MDINT pin or from the Copper PHY is driven low. This condition must
1468 be cleared in the attached PHY device that is driving the MINT pin. */
1469 #define NIG_REG_EMAC0_STATUS_MISC_MI_INT 0x10494
1470 /* [WB 48] This address space contains BMAC0 registers. The BMAC registers
1471 are described in appendix A. In order to access the BMAC0 registers; the
1472 base address; NIG_REGISTERS_INGRESS_BMAC0_MEM; Offset: 0x10c00; should be
1473 added to each BMAC register offset */
1474 #define NIG_REG_INGRESS_BMAC0_MEM 0x10c00
1475 /* [WB 48] This address space contains BMAC1 registers. The BMAC registers
1476 are described in appendix A. In order to access the BMAC0 registers; the
1477 base address; NIG_REGISTERS_INGRESS_BMAC1_MEM; Offset: 0x11000; should be
1478 added to each BMAC register offset */
1479 #define NIG_REG_INGRESS_BMAC1_MEM 0x11000
1480 /* [R 1] FIFO empty in EOP descriptor FIFO of LP in NIG_RX_EOP */
1481 #define NIG_REG_INGRESS_EOP_LB_EMPTY 0x104e0
1482 /* [RW 17] Debug only. RX_EOP_DSCR_lb_FIFO in NIG_RX_EOP. Data
1483 packet_length[13:0]; mac_error[14]; trunc_error[15]; parity[16] */
1484 #define NIG_REG_INGRESS_EOP_LB_FIFO 0x104e4
1485 /* [RW 1] led 10g for port 0 */
1486 #define NIG_REG_LED_10G_P0 0x10320
1487 /* [RW 1] Port0: This bit is set to enable the use of the
1488 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 field
1489 defined below. If this bit is cleared; then the blink rate will be about
1490 8Hz. */
1491 #define NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 0x10318
1492 /* [RW 12] Port0: Specifies the period of each blink cycle (on + off) for
1493 Traffic LED in milliseconds. Must be a non-zero value. This 12-bit field
1494 is reset to 0x080; giving a default blink period of approximately 8Hz. */
1495 #define NIG_REG_LED_CONTROL_BLINK_RATE_P0 0x10310
1496 /* [RW 1] Port0: If set along with the
1497 nig_registers_led_control_override_traffic_p0.led_control_override_traffic_p0
1498 bit and ~nig_registers_led_control_traffic_p0.led_control_traffic_p0 LED
1499 bit; the Traffic LED will blink with the blink rate specified in
1500 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and
1501 ~nig_registers_led_control_blink_rate_ena_p0.led_control_blink_rate_ena_p0
1502 fields. */
1503 #define NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 0x10308
1504 /* [RW 1] Port0: If set overrides hardware control of the Traffic LED. The
1505 Traffic LED will then be controlled via bit ~nig_registers_
1506 led_control_traffic_p0.led_control_traffic_p0 and bit
1507 ~nig_registers_led_control_blink_traffic_p0.led_control_blink_traffic_p0 */
1508 #define NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 0x102f8
1509 /* [RW 1] Port0: If set along with the led_control_override_trafic_p0 bit;
1510 turns on the Traffic LED. If the led_control_blink_traffic_p0 bit is also
1511 set; the LED will blink with blink rate specified in
1512 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and
1513 ~nig_regsters_led_control_blink_rate_ena_p0.led_control_blink_rate_ena_p0
1514 fields. */
1515 #define NIG_REG_LED_CONTROL_TRAFFIC_P0 0x10300
1516 /* [RW 4] led mode for port0: 0 MAC; 1-3 PHY1; 4 MAC2; 5-7 PHY4; 8-MAC3;
1517 9-11PHY7; 12 MAC4; 13-15 PHY10; */
1518 #define NIG_REG_LED_MODE_P0 0x102f0
1519 #define NIG_REG_LLH0_BRB1_DRV_MASK 0x10244
1520 /* [RW 1] send to BRB1 if no match on any of RMP rules. */
1521 #define NIG_REG_LLH0_BRB1_NOT_MCP 0x1025c
1522 /* [RW 32] cm header for llh0 */
1523 #define NIG_REG_LLH0_CM_HEADER 0x1007c
1524 #define NIG_REG_LLH0_ERROR_MASK 0x1008c
1525 /* [RW 8] event id for llh0 */
1526 #define NIG_REG_LLH0_EVENT_ID 0x10084
1527 /* [RW 8] init credit counter for port0 in LLH */
1528 #define NIG_REG_LLH0_XCM_INIT_CREDIT 0x10554
1529 #define NIG_REG_LLH0_XCM_MASK 0x10130
1530 /* [RW 1] send to BRB1 if no match on any of RMP rules. */
1531 #define NIG_REG_LLH1_BRB1_NOT_MCP 0x102dc
1532 /* [RW 32] cm header for llh1 */
1533 #define NIG_REG_LLH1_CM_HEADER 0x10080
1534 #define NIG_REG_LLH1_ERROR_MASK 0x10090
1535 /* [RW 8] event id for llh1 */
1536 #define NIG_REG_LLH1_EVENT_ID 0x10088
1537 /* [RW 8] init credit counter for port1 in LLH */
1538 #define NIG_REG_LLH1_XCM_INIT_CREDIT 0x10564
1539 #define NIG_REG_LLH1_XCM_MASK 0x10134
1540 #define NIG_REG_MASK_INTERRUPT_PORT0 0x10330
1541 #define NIG_REG_MASK_INTERRUPT_PORT1 0x10334
1542 /* [RW 1] Output signal from NIG to EMAC0. When set enables the EMAC0 block. */
1543 #define NIG_REG_NIG_EMAC0_EN 0x1003c
1544 /* [RW 1] Output signal from NIG to TX_EMAC0. When set indicates to the
1545 EMAC0 to strip the CRC from the ingress packets. */
1546 #define NIG_REG_NIG_INGRESS_EMAC0_NO_CRC 0x10044
1547 /* [RW 1] Input enable for RX PBF LP IF */
1548 #define NIG_REG_PBF_LB_IN_EN 0x100b4
1550 =======
1551 /* [RW 1] Value of this register will be transmitted to port swap when
1552 ~nig_registers_strap_override.strap_override =1 */
1553 #define NIG_REG_PORT_SWAP 0x10394
1555 /* [RW 1] output enable for RX parser descriptor IF */
1556 #define NIG_REG_PRS_EOP_OUT_EN 0x10104
1557 /* [RW 1] Input enable for RX parser request IF */
1558 #define NIG_REG_PRS_REQ_IN_EN 0x100b8
1559 /* [RW 5] control to serdes - CL22 PHY_ADD and CL45 PRTAD */
1560 #define NIG_REG_SERDES0_CTRL_PHY_ADDR 0x10374
1561 /* [R 1] status from serdes0 that inputs to interrupt logic of link status */
1562 #define NIG_REG_SERDES0_STATUS_LINK_STATUS 0x10578
1563 /* [R 32] Rx statistics : In user packets discarded due to BRB backpressure
1564 for port0 */
1565 #define NIG_REG_STAT0_BRB_DISCARD 0x105f0
1566 /* [R 32] Rx statistics : In user packets discarded due to BRB backpressure
1567 for port1 */
1568 #define NIG_REG_STAT1_BRB_DISCARD 0x10628
1569 /* [WB_R 64] Rx statistics : User octets received for LP */
1570 #define NIG_REG_STAT2_BRB_OCTET 0x107e0
1571 #define NIG_REG_STATUS_INTERRUPT_PORT0 0x10328
1572 #define NIG_REG_STATUS_INTERRUPT_PORT1 0x1032c
1574 =======
1575 /* [RW 1] port swap mux selection. If this register equal to 0 then port
1576 swap is equal to SPIO pin that inputs from ifmux_serdes_swap. If 1 then
1577 ort swap is equal to ~nig_registers_port_swap.port_swap */
1578 #define NIG_REG_STRAP_OVERRIDE 0x10398
1580 /* [RW 1] output enable for RX_XCM0 IF */
1581 #define NIG_REG_XCM0_OUT_EN 0x100f0
1582 /* [RW 1] output enable for RX_XCM1 IF */
1583 #define NIG_REG_XCM1_OUT_EN 0x100f4
1584 /* [RW 5] control to xgxs - CL45 DEVAD */
1585 #define NIG_REG_XGXS0_CTRL_MD_DEVAD 0x1033c
1586 /* [RW 5] control to xgxs - CL22 PHY_ADD and CL45 PRTAD */
1587 #define NIG_REG_XGXS0_CTRL_PHY_ADDR 0x10340
1588 /* [R 1] status from xgxs0 that inputs to interrupt logic of link10g. */
1589 #define NIG_REG_XGXS0_STATUS_LINK10G 0x10680
1590 /* [R 4] status from xgxs0 that inputs to interrupt logic of link status */
1591 #define NIG_REG_XGXS0_STATUS_LINK_STATUS 0x10684
1592 /* [RW 2] selection for XGXS lane of port 0 in NIG_MUX block */
1593 #define NIG_REG_XGXS_LANE_SEL_P0 0x102e8
1594 /* [RW 1] selection for port0 for NIG_MUX block : 0 = SerDes; 1 = XGXS */
1595 #define NIG_REG_XGXS_SERDES0_MODE_SEL 0x102e0
1596 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS (0x1<<9)
1597 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G (0x1<<15)
1598 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS (0xf<<18)
1599 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE 18
1600 /* [RW 1] Disable processing further tasks from port 0 (after ending the
1601 current task in process). */
1602 #define PBF_REG_DISABLE_NEW_TASK_PROC_P0 0x14005c
1603 /* [RW 1] Disable processing further tasks from port 1 (after ending the
1604 current task in process). */
1605 #define PBF_REG_DISABLE_NEW_TASK_PROC_P1 0x140060
1606 /* [RW 1] Disable processing further tasks from port 4 (after ending the
1607 current task in process). */
1608 #define PBF_REG_DISABLE_NEW_TASK_PROC_P4 0x14006c
1609 #define PBF_REG_IF_ENABLE_REG 0x140044
1610 /* [RW 1] Init bit. When set the initial credits are copied to the credit
1611 registers (except the port credits). Should be set and then reset after
1612 the configuration of the block has ended. */
1613 #define PBF_REG_INIT 0x140000
1614 /* [RW 1] Init bit for port 0. When set the initial credit of port 0 is
1615 copied to the credit register. Should be set and then reset after the
1616 configuration of the port has ended. */
1617 #define PBF_REG_INIT_P0 0x140004
1618 /* [RW 1] Init bit for port 1. When set the initial credit of port 1 is
1619 copied to the credit register. Should be set and then reset after the
1620 configuration of the port has ended. */
1621 #define PBF_REG_INIT_P1 0x140008
1622 /* [RW 1] Init bit for port 4. When set the initial credit of port 4 is
1623 copied to the credit register. Should be set and then reset after the
1624 configuration of the port has ended. */
1625 #define PBF_REG_INIT_P4 0x14000c
1626 /* [RW 1] Enable for mac interface 0. */
1627 #define PBF_REG_MAC_IF0_ENABLE 0x140030
1628 /* [RW 1] Enable for mac interface 1. */
1629 #define PBF_REG_MAC_IF1_ENABLE 0x140034
1630 /* [RW 1] Enable for the loopback interface. */
1631 #define PBF_REG_MAC_LB_ENABLE 0x140040
1632 /* [RW 10] Port 0 threshold used by arbiter in 16 byte lines used when pause
1633 not suppoterd. */
1634 #define PBF_REG_P0_ARB_THRSH 0x1400e4
1635 /* [R 11] Current credit for port 0 in the tx port buffers in 16 byte lines. */
1636 #define PBF_REG_P0_CREDIT 0x140200
1637 /* [RW 11] Initial credit for port 0 in the tx port buffers in 16 byte
1638 lines. */
1639 #define PBF_REG_P0_INIT_CRD 0x1400d0
1640 /* [RW 1] Indication that pause is enabled for port 0. */
1641 #define PBF_REG_P0_PAUSE_ENABLE 0x140014
1642 /* [R 8] Number of tasks in port 0 task queue. */
1643 #define PBF_REG_P0_TASK_CNT 0x140204
1644 /* [R 11] Current credit for port 1 in the tx port buffers in 16 byte lines. */
1645 #define PBF_REG_P1_CREDIT 0x140208
1646 /* [RW 11] Initial credit for port 1 in the tx port buffers in 16 byte
1647 lines. */
1648 #define PBF_REG_P1_INIT_CRD 0x1400d4
1649 /* [R 8] Number of tasks in port 1 task queue. */
1650 #define PBF_REG_P1_TASK_CNT 0x14020c
1651 /* [R 11] Current credit for port 4 in the tx port buffers in 16 byte lines. */
1652 #define PBF_REG_P4_CREDIT 0x140210
1653 /* [RW 11] Initial credit for port 4 in the tx port buffers in 16 byte
1654 lines. */
1655 #define PBF_REG_P4_INIT_CRD 0x1400e0
1656 /* [R 8] Number of tasks in port 4 task queue. */
1657 #define PBF_REG_P4_TASK_CNT 0x140214
1658 /* [RW 5] Interrupt mask register #0 read/write */
1659 #define PBF_REG_PBF_INT_MASK 0x1401d4
1660 /* [R 5] Interrupt register #0 read */
1661 #define PBF_REG_PBF_INT_STS 0x1401c8
1662 #define PB_REG_CONTROL 0
1663 /* [RW 2] Interrupt mask register #0 read/write */
1664 #define PB_REG_PB_INT_MASK 0x28
1665 /* [R 2] Interrupt register #0 read */
1666 #define PB_REG_PB_INT_STS 0x1c
1667 /* [RW 4] Parity mask register #0 read/write */
1668 #define PB_REG_PB_PRTY_MASK 0x38
1670 =======
1671 /* [R 4] Parity register #0 read */
1672 #define PB_REG_PB_PRTY_STS 0x2c
1674 #define PRS_REG_A_PRSU_20 0x40134
1675 /* [R 8] debug only: CFC load request current credit. Transaction based. */
1676 #define PRS_REG_CFC_LD_CURRENT_CREDIT 0x40164
1677 /* [R 8] debug only: CFC search request current credit. Transaction based. */
1678 #define PRS_REG_CFC_SEARCH_CURRENT_CREDIT 0x40168
1679 /* [RW 6] The initial credit for the search message to the CFC interface.
1680 Credit is transaction based. */
1681 #define PRS_REG_CFC_SEARCH_INITIAL_CREDIT 0x4011c
1682 /* [RW 24] CID for port 0 if no match */
1683 #define PRS_REG_CID_PORT_0 0x400fc
1684 #define PRS_REG_CID_PORT_1 0x40100
1685 /* [RW 32] The CM header for flush message where 'load existed' bit in CFC
1686 load response is reset and packet type is 0. Used in packet start message
1687 to TCM. */
1688 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_0 0x400dc
1689 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_1 0x400e0
1690 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_2 0x400e4
1691 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_3 0x400e8
1692 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_4 0x400ec
1693 /* [RW 32] The CM header for flush message where 'load existed' bit in CFC
1694 load response is set and packet type is 0. Used in packet start message
1695 to TCM. */
1696 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_0 0x400bc
1697 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_1 0x400c0
1698 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_2 0x400c4
1699 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_3 0x400c8
1700 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_4 0x400cc
1701 /* [RW 32] The CM header for a match and packet type 1 for loopback port.
1702 Used in packet start message to TCM. */
1703 #define PRS_REG_CM_HDR_LOOPBACK_TYPE_1 0x4009c
1704 #define PRS_REG_CM_HDR_LOOPBACK_TYPE_2 0x400a0
1705 #define PRS_REG_CM_HDR_LOOPBACK_TYPE_3 0x400a4
1706 #define PRS_REG_CM_HDR_LOOPBACK_TYPE_4 0x400a8
1707 /* [RW 32] The CM header for a match and packet type 0. Used in packet start
1708 message to TCM. */
1709 #define PRS_REG_CM_HDR_TYPE_0 0x40078
1710 #define PRS_REG_CM_HDR_TYPE_1 0x4007c
1711 #define PRS_REG_CM_HDR_TYPE_2 0x40080
1712 #define PRS_REG_CM_HDR_TYPE_3 0x40084
1713 #define PRS_REG_CM_HDR_TYPE_4 0x40088
1714 /* [RW 32] The CM header in case there was not a match on the connection */
1715 #define PRS_REG_CM_NO_MATCH_HDR 0x400b8
1716 /* [RW 8] The 8-bit event ID for a match and packet type 1. Used in packet
1717 start message to TCM. */
1718 #define PRS_REG_EVENT_ID_1 0x40054
1719 #define PRS_REG_EVENT_ID_2 0x40058
1720 #define PRS_REG_EVENT_ID_3 0x4005c
1721 /* [RW 8] Context region for flush packet with packet type 0. Used in CFC
1722 load request message. */
1723 #define PRS_REG_FLUSH_REGIONS_TYPE_0 0x40004
1724 #define PRS_REG_FLUSH_REGIONS_TYPE_1 0x40008
1725 #define PRS_REG_FLUSH_REGIONS_TYPE_2 0x4000c
1726 #define PRS_REG_FLUSH_REGIONS_TYPE_3 0x40010
1727 #define PRS_REG_FLUSH_REGIONS_TYPE_4 0x40014
1728 #define PRS_REG_FLUSH_REGIONS_TYPE_5 0x40018
1729 #define PRS_REG_FLUSH_REGIONS_TYPE_6 0x4001c
1730 #define PRS_REG_FLUSH_REGIONS_TYPE_7 0x40020
1731 /* [RW 4] The increment value to send in the CFC load request message */
1732 #define PRS_REG_INC_VALUE 0x40048
1733 /* [RW 1] If set indicates not to send messages to CFC on received packets */
1734 #define PRS_REG_NIC_MODE 0x40138
1735 /* [RW 8] The 8-bit event ID for cases where there is no match on the
1736 connection. Used in packet start message to TCM. */
1737 #define PRS_REG_NO_MATCH_EVENT_ID 0x40070
1738 /* [ST 24] The number of input CFC flush packets */
1739 #define PRS_REG_NUM_OF_CFC_FLUSH_MESSAGES 0x40128
1740 /* [ST 32] The number of cycles the Parser halted its operation since it
1741 could not allocate the next serial number */
1742 #define PRS_REG_NUM_OF_DEAD_CYCLES 0x40130
1743 /* [ST 24] The number of input packets */
1744 #define PRS_REG_NUM_OF_PACKETS 0x40124
1745 /* [ST 24] The number of input transparent flush packets */
1746 #define PRS_REG_NUM_OF_TRANSPARENT_FLUSH_MESSAGES 0x4012c
1747 /* [RW 8] Context region for received Ethernet packet with a match and
1748 packet type 0. Used in CFC load request message */
1749 #define PRS_REG_PACKET_REGIONS_TYPE_0 0x40028
1750 #define PRS_REG_PACKET_REGIONS_TYPE_1 0x4002c
1751 #define PRS_REG_PACKET_REGIONS_TYPE_2 0x40030
1752 #define PRS_REG_PACKET_REGIONS_TYPE_3 0x40034
1753 #define PRS_REG_PACKET_REGIONS_TYPE_4 0x40038
1754 #define PRS_REG_PACKET_REGIONS_TYPE_5 0x4003c
1755 #define PRS_REG_PACKET_REGIONS_TYPE_6 0x40040
1756 #define PRS_REG_PACKET_REGIONS_TYPE_7 0x40044
1757 /* [R 2] debug only: Number of pending requests for CAC on port 0. */
1758 #define PRS_REG_PENDING_BRB_CAC0_RQ 0x40174
1759 /* [R 2] debug only: Number of pending requests for header parsing. */
1760 #define PRS_REG_PENDING_BRB_PRS_RQ 0x40170
1761 /* [R 1] Interrupt register #0 read */
1762 #define PRS_REG_PRS_INT_STS 0x40188
1763 /* [RW 8] Parity mask register #0 read/write */
1764 #define PRS_REG_PRS_PRTY_MASK 0x401a4
1766 =======
1767 /* [R 8] Parity register #0 read */
1768 #define PRS_REG_PRS_PRTY_STS 0x40198
1770 /* [RW 8] Context region for pure acknowledge packets. Used in CFC load
1771 request message */
1772 #define PRS_REG_PURE_REGIONS 0x40024
1773 /* [R 32] debug only: Serial number status lsb 32 bits. '1' indicates this
1774 serail number was released by SDM but cannot be used because a previous
1775 serial number was not released. */
1776 #define PRS_REG_SERIAL_NUM_STATUS_LSB 0x40154
1777 /* [R 32] debug only: Serial number status msb 32 bits. '1' indicates this
1778 serail number was released by SDM but cannot be used because a previous
1779 serial number was not released. */
1780 #define PRS_REG_SERIAL_NUM_STATUS_MSB 0x40158
1781 /* [R 4] debug only: SRC current credit. Transaction based. */
1782 #define PRS_REG_SRC_CURRENT_CREDIT 0x4016c
1783 /* [R 8] debug only: TCM current credit. Cycle based. */
1784 #define PRS_REG_TCM_CURRENT_CREDIT 0x40160
1785 /* [R 8] debug only: TSDM current credit. Transaction based. */
1786 #define PRS_REG_TSDM_CURRENT_CREDIT 0x4015c
1787 /* [R 6] Debug only: Number of used entries in the data FIFO */
1788 #define PXP2_REG_HST_DATA_FIFO_STATUS 0x12047c
1789 /* [R 7] Debug only: Number of used entries in the header FIFO */
1790 #define PXP2_REG_HST_HEADER_FIFO_STATUS 0x120478
1791 #define PXP2_REG_PGL_CONTROL0 0x120490
1792 #define PXP2_REG_PGL_CONTROL1 0x120514
1793 /* [RW 32] Inbound interrupt table for CSDM: bits[31:16]-mask;
1794 its[15:0]-address */
1795 #define PXP2_REG_PGL_INT_CSDM_0 0x1204f4
1796 #define PXP2_REG_PGL_INT_CSDM_1 0x1204f8
1797 #define PXP2_REG_PGL_INT_CSDM_2 0x1204fc
1798 #define PXP2_REG_PGL_INT_CSDM_3 0x120500
1799 #define PXP2_REG_PGL_INT_CSDM_4 0x120504
1800 #define PXP2_REG_PGL_INT_CSDM_5 0x120508
1801 #define PXP2_REG_PGL_INT_CSDM_6 0x12050c
1802 #define PXP2_REG_PGL_INT_CSDM_7 0x120510
1803 /* [RW 32] Inbound interrupt table for TSDM: bits[31:16]-mask;
1804 its[15:0]-address */
1805 #define PXP2_REG_PGL_INT_TSDM_0 0x120494
1806 #define PXP2_REG_PGL_INT_TSDM_1 0x120498
1807 #define PXP2_REG_PGL_INT_TSDM_2 0x12049c
1808 #define PXP2_REG_PGL_INT_TSDM_3 0x1204a0
1809 #define PXP2_REG_PGL_INT_TSDM_4 0x1204a4
1810 #define PXP2_REG_PGL_INT_TSDM_5 0x1204a8
1811 #define PXP2_REG_PGL_INT_TSDM_6 0x1204ac
1812 #define PXP2_REG_PGL_INT_TSDM_7 0x1204b0
1813 /* [RW 32] Inbound interrupt table for USDM: bits[31:16]-mask;
1814 its[15:0]-address */
1815 #define PXP2_REG_PGL_INT_USDM_0 0x1204b4
1816 #define PXP2_REG_PGL_INT_USDM_1 0x1204b8
1817 #define PXP2_REG_PGL_INT_USDM_2 0x1204bc
1818 #define PXP2_REG_PGL_INT_USDM_3 0x1204c0
1819 #define PXP2_REG_PGL_INT_USDM_4 0x1204c4
1820 #define PXP2_REG_PGL_INT_USDM_5 0x1204c8
1821 #define PXP2_REG_PGL_INT_USDM_6 0x1204cc
1822 #define PXP2_REG_PGL_INT_USDM_7 0x1204d0
1823 /* [RW 32] Inbound interrupt table for XSDM: bits[31:16]-mask;
1824 its[15:0]-address */
1825 #define PXP2_REG_PGL_INT_XSDM_0 0x1204d4
1826 #define PXP2_REG_PGL_INT_XSDM_1 0x1204d8
1827 #define PXP2_REG_PGL_INT_XSDM_2 0x1204dc
1828 #define PXP2_REG_PGL_INT_XSDM_3 0x1204e0
1829 #define PXP2_REG_PGL_INT_XSDM_4 0x1204e4
1830 #define PXP2_REG_PGL_INT_XSDM_5 0x1204e8
1831 #define PXP2_REG_PGL_INT_XSDM_6 0x1204ec
1832 #define PXP2_REG_PGL_INT_XSDM_7 0x1204f0
1833 /* [R 1] this bit indicates that a read request was blocked because of
1834 bus_master_en was deasserted */
1835 #define PXP2_REG_PGL_READ_BLOCKED 0x120568
1836 /* [R 6] debug only */
1837 #define PXP2_REG_PGL_TXR_CDTS 0x120528
1838 /* [R 18] debug only */
1839 #define PXP2_REG_PGL_TXW_CDTS 0x12052c
1840 /* [R 1] this bit indicates that a write request was blocked because of
1841 bus_master_en was deasserted */
1842 #define PXP2_REG_PGL_WRITE_BLOCKED 0x120564
1843 #define PXP2_REG_PSWRQ_BW_ADD1 0x1201c0
1844 #define PXP2_REG_PSWRQ_BW_ADD10 0x1201e4
1845 #define PXP2_REG_PSWRQ_BW_ADD11 0x1201e8
1846 #define PXP2_REG_PSWRQ_BW_ADD10 0x1201e4
1847 #define PXP2_REG_PSWRQ_BW_ADD11 0x1201e8
1848 #define PXP2_REG_PSWRQ_BW_ADD2 0x1201c4
1849 #define PXP2_REG_PSWRQ_BW_ADD28 0x120228
1850 #define PXP2_REG_PSWRQ_BW_ADD28 0x120228
1851 #define PXP2_REG_PSWRQ_BW_ADD3 0x1201c8
1852 #define PXP2_REG_PSWRQ_BW_ADD6 0x1201d4
1853 #define PXP2_REG_PSWRQ_BW_ADD7 0x1201d8
1854 #define PXP2_REG_PSWRQ_BW_ADD8 0x1201dc
1855 #define PXP2_REG_PSWRQ_BW_ADD9 0x1201e0
1856 #define PXP2_REG_PSWRQ_BW_CREDIT 0x12032c
1857 #define PXP2_REG_PSWRQ_BW_L1 0x1202b0
1858 #define PXP2_REG_PSWRQ_BW_L10 0x1202d4
1859 #define PXP2_REG_PSWRQ_BW_L11 0x1202d8
1860 #define PXP2_REG_PSWRQ_BW_L10 0x1202d4
1861 #define PXP2_REG_PSWRQ_BW_L11 0x1202d8
1862 #define PXP2_REG_PSWRQ_BW_L2 0x1202b4
1863 #define PXP2_REG_PSWRQ_BW_L28 0x120318
1864 #define PXP2_REG_PSWRQ_BW_L28 0x120318
1865 #define PXP2_REG_PSWRQ_BW_L3 0x1202b8
1866 #define PXP2_REG_PSWRQ_BW_L6 0x1202c4
1867 #define PXP2_REG_PSWRQ_BW_L7 0x1202c8
1868 #define PXP2_REG_PSWRQ_BW_L8 0x1202cc
1869 #define PXP2_REG_PSWRQ_BW_L9 0x1202d0
1870 #define PXP2_REG_PSWRQ_BW_RD 0x120324
1871 #define PXP2_REG_PSWRQ_BW_UB1 0x120238
1872 #define PXP2_REG_PSWRQ_BW_UB10 0x12025c
1873 #define PXP2_REG_PSWRQ_BW_UB11 0x120260
1874 #define PXP2_REG_PSWRQ_BW_UB10 0x12025c
1875 #define PXP2_REG_PSWRQ_BW_UB11 0x120260
1876 #define PXP2_REG_PSWRQ_BW_UB2 0x12023c
1877 #define PXP2_REG_PSWRQ_BW_UB28 0x1202a0
1878 #define PXP2_REG_PSWRQ_BW_UB28 0x1202a0
1879 #define PXP2_REG_PSWRQ_BW_UB3 0x120240
1880 #define PXP2_REG_PSWRQ_BW_UB6 0x12024c
1881 #define PXP2_REG_PSWRQ_BW_UB7 0x120250
1882 #define PXP2_REG_PSWRQ_BW_UB8 0x120254
1883 #define PXP2_REG_PSWRQ_BW_UB9 0x120258
1884 #define PXP2_REG_PSWRQ_BW_WR 0x120328
1885 #define PXP2_REG_PSWRQ_CDU0_L2P 0x120000
1886 #define PXP2_REG_PSWRQ_QM0_L2P 0x120038
1887 #define PXP2_REG_PSWRQ_SRC0_L2P 0x120054
1888 #define PXP2_REG_PSWRQ_TM0_L2P 0x12001c
1889 /* [RW 25] Interrupt mask register #0 read/write */
1890 #define PXP2_REG_PXP2_INT_MASK 0x120578
1891 /* [R 25] Interrupt register #0 read */
1892 #define PXP2_REG_PXP2_INT_STS 0x12056c
1893 /* [RC 25] Interrupt register #0 read clear */
1894 #define PXP2_REG_PXP2_INT_STS_CLR 0x120570
1895 /* [RW 32] Parity mask register #0 read/write */
1896 #define PXP2_REG_PXP2_PRTY_MASK_0 0x120588
1897 #define PXP2_REG_PXP2_PRTY_MASK_1 0x120598
1899 =======
1900 /* [R 32] Parity register #0 read */
1901 #define PXP2_REG_PXP2_PRTY_STS_0 0x12057c
1902 #define PXP2_REG_PXP2_PRTY_STS_1 0x12058c
1904 /* [R 1] Debug only: The 'almost full' indication from each fifo (gives
1905 indication about backpressure) */
1906 #define PXP2_REG_RD_ALMOST_FULL_0 0x120424
1907 /* [R 8] Debug only: The blocks counter - number of unused block ids */
1908 #define PXP2_REG_RD_BLK_CNT 0x120418
1909 /* [RW 8] Debug only: Total number of available blocks in Tetris Buffer.
1910 Must be bigger than 6. Normally should not be changed. */
1911 #define PXP2_REG_RD_BLK_NUM_CFG 0x12040c
1912 /* [RW 2] CDU byte swapping mode configuration for master read requests */
1913 #define PXP2_REG_RD_CDURD_SWAP_MODE 0x120404
1914 /* [RW 1] When '1'; inputs to the PSWRD block are ignored */
1915 #define PXP2_REG_RD_DISABLE_INPUTS 0x120374
1916 /* [R 1] PSWRD internal memories initialization is done */
1917 #define PXP2_REG_RD_INIT_DONE 0x120370
1918 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
1919 allocated for vq10 */
1920 #define PXP2_REG_RD_MAX_BLKS_VQ10 0x1203a0
1921 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
1922 allocated for vq11 */
1923 #define PXP2_REG_RD_MAX_BLKS_VQ11 0x1203a4
1924 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
1925 allocated for vq17 */
1926 #define PXP2_REG_RD_MAX_BLKS_VQ17 0x1203bc
1927 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
1928 allocated for vq18 */
1929 #define PXP2_REG_RD_MAX_BLKS_VQ18 0x1203c0
1930 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
1931 allocated for vq19 */
1932 #define PXP2_REG_RD_MAX_BLKS_VQ19 0x1203c4
1933 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
1934 allocated for vq22 */
1935 #define PXP2_REG_RD_MAX_BLKS_VQ22 0x1203d0
1936 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
1937 allocated for vq6 */
1938 #define PXP2_REG_RD_MAX_BLKS_VQ6 0x120390
1939 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
1940 allocated for vq9 */
1941 #define PXP2_REG_RD_MAX_BLKS_VQ9 0x12039c
1942 /* [RW 2] PBF byte swapping mode configuration for master read requests */
1943 #define PXP2_REG_RD_PBF_SWAP_MODE 0x1203f4
1944 /* [R 1] Debug only: Indication if delivery ports are idle */
1945 #define PXP2_REG_RD_PORT_IS_IDLE_0 0x12041c
1946 #define PXP2_REG_RD_PORT_IS_IDLE_1 0x120420
1947 /* [RW 2] QM byte swapping mode configuration for master read requests */
1948 #define PXP2_REG_RD_QM_SWAP_MODE 0x1203f8
1949 /* [R 7] Debug only: The SR counter - number of unused sub request ids */
1950 #define PXP2_REG_RD_SR_CNT 0x120414
1951 /* [RW 2] SRC byte swapping mode configuration for master read requests */
1952 #define PXP2_REG_RD_SRC_SWAP_MODE 0x120400
1953 /* [RW 7] Debug only: Total number of available PCI read sub-requests. Must
1954 be bigger than 1. Normally should not be changed. */
1955 #define PXP2_REG_RD_SR_NUM_CFG 0x120408
1956 /* [RW 1] Signals the PSWRD block to start initializing internal memories */
1957 #define PXP2_REG_RD_START_INIT 0x12036c
1958 /* [RW 2] TM byte swapping mode configuration for master read requests */
1959 #define PXP2_REG_RD_TM_SWAP_MODE 0x1203fc
1960 /* [RW 10] Bandwidth addition to VQ0 write requests */
1961 #define PXP2_REG_RQ_BW_RD_ADD0 0x1201bc
1962 /* [RW 10] Bandwidth addition to VQ12 read requests */
1963 #define PXP2_REG_RQ_BW_RD_ADD12 0x1201ec
1964 /* [RW 10] Bandwidth addition to VQ13 read requests */
1965 #define PXP2_REG_RQ_BW_RD_ADD13 0x1201f0
1966 /* [RW 10] Bandwidth addition to VQ14 read requests */
1967 #define PXP2_REG_RQ_BW_RD_ADD14 0x1201f4
1968 /* [RW 10] Bandwidth addition to VQ15 read requests */
1969 #define PXP2_REG_RQ_BW_RD_ADD15 0x1201f8
1970 /* [RW 10] Bandwidth addition to VQ16 read requests */
1971 #define PXP2_REG_RQ_BW_RD_ADD16 0x1201fc
1972 /* [RW 10] Bandwidth addition to VQ17 read requests */
1973 #define PXP2_REG_RQ_BW_RD_ADD17 0x120200
1974 /* [RW 10] Bandwidth addition to VQ18 read requests */
1975 #define PXP2_REG_RQ_BW_RD_ADD18 0x120204
1976 /* [RW 10] Bandwidth addition to VQ19 read requests */
1977 #define PXP2_REG_RQ_BW_RD_ADD19 0x120208
1978 /* [RW 10] Bandwidth addition to VQ20 read requests */
1979 #define PXP2_REG_RQ_BW_RD_ADD20 0x12020c
1980 /* [RW 10] Bandwidth addition to VQ22 read requests */
1981 #define PXP2_REG_RQ_BW_RD_ADD22 0x120210
1982 /* [RW 10] Bandwidth addition to VQ23 read requests */
1983 #define PXP2_REG_RQ_BW_RD_ADD23 0x120214
1984 /* [RW 10] Bandwidth addition to VQ24 read requests */
1985 #define PXP2_REG_RQ_BW_RD_ADD24 0x120218
1986 /* [RW 10] Bandwidth addition to VQ25 read requests */
1987 #define PXP2_REG_RQ_BW_RD_ADD25 0x12021c
1988 /* [RW 10] Bandwidth addition to VQ26 read requests */
1989 #define PXP2_REG_RQ_BW_RD_ADD26 0x120220
1990 /* [RW 10] Bandwidth addition to VQ27 read requests */
1991 #define PXP2_REG_RQ_BW_RD_ADD27 0x120224
1992 /* [RW 10] Bandwidth addition to VQ4 read requests */
1993 #define PXP2_REG_RQ_BW_RD_ADD4 0x1201cc
1994 /* [RW 10] Bandwidth addition to VQ5 read requests */
1995 #define PXP2_REG_RQ_BW_RD_ADD5 0x1201d0
1996 /* [RW 10] Bandwidth Typical L for VQ0 Read requests */
1997 #define PXP2_REG_RQ_BW_RD_L0 0x1202ac
1998 /* [RW 10] Bandwidth Typical L for VQ12 Read requests */
1999 #define PXP2_REG_RQ_BW_RD_L12 0x1202dc
2000 /* [RW 10] Bandwidth Typical L for VQ13 Read requests */
2001 #define PXP2_REG_RQ_BW_RD_L13 0x1202e0
2002 /* [RW 10] Bandwidth Typical L for VQ14 Read requests */
2003 #define PXP2_REG_RQ_BW_RD_L14 0x1202e4
2004 /* [RW 10] Bandwidth Typical L for VQ15 Read requests */
2005 #define PXP2_REG_RQ_BW_RD_L15 0x1202e8
2006 /* [RW 10] Bandwidth Typical L for VQ16 Read requests */
2007 #define PXP2_REG_RQ_BW_RD_L16 0x1202ec
2008 /* [RW 10] Bandwidth Typical L for VQ17 Read requests */
2009 #define PXP2_REG_RQ_BW_RD_L17 0x1202f0
2010 /* [RW 10] Bandwidth Typical L for VQ18 Read requests */
2011 #define PXP2_REG_RQ_BW_RD_L18 0x1202f4
2012 /* [RW 10] Bandwidth Typical L for VQ19 Read requests */
2013 #define PXP2_REG_RQ_BW_RD_L19 0x1202f8
2014 /* [RW 10] Bandwidth Typical L for VQ20 Read requests */
2015 #define PXP2_REG_RQ_BW_RD_L20 0x1202fc
2016 /* [RW 10] Bandwidth Typical L for VQ22 Read requests */
2017 #define PXP2_REG_RQ_BW_RD_L22 0x120300
2018 /* [RW 10] Bandwidth Typical L for VQ23 Read requests */
2019 #define PXP2_REG_RQ_BW_RD_L23 0x120304
2020 /* [RW 10] Bandwidth Typical L for VQ24 Read requests */
2021 #define PXP2_REG_RQ_BW_RD_L24 0x120308
2022 /* [RW 10] Bandwidth Typical L for VQ25 Read requests */
2023 #define PXP2_REG_RQ_BW_RD_L25 0x12030c
2024 /* [RW 10] Bandwidth Typical L for VQ26 Read requests */
2025 #define PXP2_REG_RQ_BW_RD_L26 0x120310
2026 /* [RW 10] Bandwidth Typical L for VQ27 Read requests */
2027 #define PXP2_REG_RQ_BW_RD_L27 0x120314
2028 /* [RW 10] Bandwidth Typical L for VQ4 Read requests */
2029 #define PXP2_REG_RQ_BW_RD_L4 0x1202bc
2030 /* [RW 10] Bandwidth Typical L for VQ5 Read- currently not used */
2031 #define PXP2_REG_RQ_BW_RD_L5 0x1202c0
2032 /* [RW 7] Bandwidth upper bound for VQ0 read requests */
2033 #define PXP2_REG_RQ_BW_RD_UBOUND0 0x120234
2034 /* [RW 7] Bandwidth upper bound for VQ12 read requests */
2035 #define PXP2_REG_RQ_BW_RD_UBOUND12 0x120264
2036 /* [RW 7] Bandwidth upper bound for VQ13 read requests */
2037 #define PXP2_REG_RQ_BW_RD_UBOUND13 0x120268
2038 /* [RW 7] Bandwidth upper bound for VQ14 read requests */
2039 #define PXP2_REG_RQ_BW_RD_UBOUND14 0x12026c
2040 /* [RW 7] Bandwidth upper bound for VQ15 read requests */
2041 #define PXP2_REG_RQ_BW_RD_UBOUND15 0x120270
2042 /* [RW 7] Bandwidth upper bound for VQ16 read requests */
2043 #define PXP2_REG_RQ_BW_RD_UBOUND16 0x120274
2044 /* [RW 7] Bandwidth upper bound for VQ17 read requests */
2045 #define PXP2_REG_RQ_BW_RD_UBOUND17 0x120278
2046 /* [RW 7] Bandwidth upper bound for VQ18 read requests */
2047 #define PXP2_REG_RQ_BW_RD_UBOUND18 0x12027c
2048 /* [RW 7] Bandwidth upper bound for VQ19 read requests */
2049 #define PXP2_REG_RQ_BW_RD_UBOUND19 0x120280
2050 /* [RW 7] Bandwidth upper bound for VQ20 read requests */
2051 #define PXP2_REG_RQ_BW_RD_UBOUND20 0x120284
2052 /* [RW 7] Bandwidth upper bound for VQ22 read requests */
2053 #define PXP2_REG_RQ_BW_RD_UBOUND22 0x120288
2054 /* [RW 7] Bandwidth upper bound for VQ23 read requests */
2055 #define PXP2_REG_RQ_BW_RD_UBOUND23 0x12028c
2056 /* [RW 7] Bandwidth upper bound for VQ24 read requests */
2057 #define PXP2_REG_RQ_BW_RD_UBOUND24 0x120290
2058 /* [RW 7] Bandwidth upper bound for VQ25 read requests */
2059 #define PXP2_REG_RQ_BW_RD_UBOUND25 0x120294
2060 /* [RW 7] Bandwidth upper bound for VQ26 read requests */
2061 #define PXP2_REG_RQ_BW_RD_UBOUND26 0x120298
2062 /* [RW 7] Bandwidth upper bound for VQ27 read requests */
2063 #define PXP2_REG_RQ_BW_RD_UBOUND27 0x12029c
2064 /* [RW 7] Bandwidth upper bound for VQ4 read requests */
2065 #define PXP2_REG_RQ_BW_RD_UBOUND4 0x120244
2066 /* [RW 7] Bandwidth upper bound for VQ5 read requests */
2067 #define PXP2_REG_RQ_BW_RD_UBOUND5 0x120248
2068 /* [RW 10] Bandwidth addition to VQ29 write requests */
2069 #define PXP2_REG_RQ_BW_WR_ADD29 0x12022c
2070 /* [RW 10] Bandwidth addition to VQ30 write requests */
2071 #define PXP2_REG_RQ_BW_WR_ADD30 0x120230
2072 /* [RW 10] Bandwidth Typical L for VQ29 Write requests */
2073 #define PXP2_REG_RQ_BW_WR_L29 0x12031c
2074 /* [RW 10] Bandwidth Typical L for VQ30 Write requests */
2075 #define PXP2_REG_RQ_BW_WR_L30 0x120320
2076 /* [RW 7] Bandwidth upper bound for VQ29 */
2077 #define PXP2_REG_RQ_BW_WR_UBOUND29 0x1202a4
2078 /* [RW 7] Bandwidth upper bound for VQ30 */
2079 #define PXP2_REG_RQ_BW_WR_UBOUND30 0x1202a8
2080 /* [RW 2] Endian mode for cdu */
2081 #define PXP2_REG_RQ_CDU_ENDIAN_M 0x1201a0
2082 /* [RW 3] page size in L2P table for CDU module; -4k; -8k; -16k; -32k; -64k;
2083 -128k */
2084 #define PXP2_REG_RQ_CDU_P_SIZE 0x120018
2085 /* [R 1] 1' indicates that the requester has finished its internal
2086 configuration */
2087 #define PXP2_REG_RQ_CFG_DONE 0x1201b4
2088 /* [RW 2] Endian mode for debug */
2089 #define PXP2_REG_RQ_DBG_ENDIAN_M 0x1201a4
2090 /* [RW 1] When '1'; requests will enter input buffers but wont get out
2091 towards the glue */
2092 #define PXP2_REG_RQ_DISABLE_INPUTS 0x120330
2093 /* [RW 2] Endian mode for hc */
2094 #define PXP2_REG_RQ_HC_ENDIAN_M 0x1201a8
2095 /* [WB 53] Onchip address table */
2096 #define PXP2_REG_RQ_ONCHIP_AT 0x122000
2098 =======
2099 /* [RW 13] Pending read limiter threshold; in Dwords */
2100 #define PXP2_REG_RQ_PDR_LIMIT 0x12033c
2102 /* [RW 2] Endian mode for qm */
2103 #define PXP2_REG_RQ_QM_ENDIAN_M 0x120194
2104 /* [RW 3] page size in L2P table for QM module; -4k; -8k; -16k; -32k; -64k;
2105 -128k */
2106 #define PXP2_REG_RQ_QM_P_SIZE 0x120050
2107 /* [RW 1] 1' indicates that the RBC has finished configurating the PSWRQ */
2108 #define PXP2_REG_RQ_RBC_DONE 0x1201b0
2109 /* [RW 3] Max burst size filed for read requests port 0; 000 - 128B;
2110 001:256B; 010: 512B; 11:1K:100:2K; 01:4K */
2111 #define PXP2_REG_RQ_RD_MBS0 0x120160
2113 =======
2114 /* [RW 3] Max burst size filed for read requests port 1; 000 - 128B;
2115 001:256B; 010: 512B; 11:1K:100:2K; 01:4K */
2116 #define PXP2_REG_RQ_RD_MBS1 0x120168
2118 /* [RW 2] Endian mode for src */
2119 #define PXP2_REG_RQ_SRC_ENDIAN_M 0x12019c
2120 /* [RW 3] page size in L2P table for SRC module; -4k; -8k; -16k; -32k; -64k;
2121 -128k */
2122 #define PXP2_REG_RQ_SRC_P_SIZE 0x12006c
2123 /* [RW 2] Endian mode for tm */
2124 #define PXP2_REG_RQ_TM_ENDIAN_M 0x120198
2125 /* [RW 3] page size in L2P table for TM module; -4k; -8k; -16k; -32k; -64k;
2126 -128k */
2127 #define PXP2_REG_RQ_TM_P_SIZE 0x120034
2128 /* [R 5] Number of entries in the ufifo; his fifo has l2p completions */
2129 #define PXP2_REG_RQ_UFIFO_NUM_OF_ENTRY 0x12080c
2130 /* [R 8] Number of entries occupied by vq 0 in pswrq memory */
2131 #define PXP2_REG_RQ_VQ0_ENTRY_CNT 0x120810
2132 /* [R 8] Number of entries occupied by vq 10 in pswrq memory */
2133 #define PXP2_REG_RQ_VQ10_ENTRY_CNT 0x120818
2134 /* [R 8] Number of entries occupied by vq 11 in pswrq memory */
2135 #define PXP2_REG_RQ_VQ11_ENTRY_CNT 0x120820
2136 /* [R 8] Number of entries occupied by vq 12 in pswrq memory */
2137 #define PXP2_REG_RQ_VQ12_ENTRY_CNT 0x120828
2138 /* [R 8] Number of entries occupied by vq 13 in pswrq memory */
2139 #define PXP2_REG_RQ_VQ13_ENTRY_CNT 0x120830
2140 /* [R 8] Number of entries occupied by vq 14 in pswrq memory */
2141 #define PXP2_REG_RQ_VQ14_ENTRY_CNT 0x120838
2142 /* [R 8] Number of entries occupied by vq 15 in pswrq memory */
2143 #define PXP2_REG_RQ_VQ15_ENTRY_CNT 0x120840
2144 /* [R 8] Number of entries occupied by vq 16 in pswrq memory */
2145 #define PXP2_REG_RQ_VQ16_ENTRY_CNT 0x120848
2146 /* [R 8] Number of entries occupied by vq 17 in pswrq memory */
2147 #define PXP2_REG_RQ_VQ17_ENTRY_CNT 0x120850
2148 /* [R 8] Number of entries occupied by vq 18 in pswrq memory */
2149 #define PXP2_REG_RQ_VQ18_ENTRY_CNT 0x120858
2150 /* [R 8] Number of entries occupied by vq 19 in pswrq memory */
2151 #define PXP2_REG_RQ_VQ19_ENTRY_CNT 0x120860
2152 /* [R 8] Number of entries occupied by vq 1 in pswrq memory */
2153 #define PXP2_REG_RQ_VQ1_ENTRY_CNT 0x120868
2154 /* [R 8] Number of entries occupied by vq 20 in pswrq memory */
2155 #define PXP2_REG_RQ_VQ20_ENTRY_CNT 0x120870
2156 /* [R 8] Number of entries occupied by vq 21 in pswrq memory */
2157 #define PXP2_REG_RQ_VQ21_ENTRY_CNT 0x120878
2158 /* [R 8] Number of entries occupied by vq 22 in pswrq memory */
2159 #define PXP2_REG_RQ_VQ22_ENTRY_CNT 0x120880
2160 /* [R 8] Number of entries occupied by vq 23 in pswrq memory */
2161 #define PXP2_REG_RQ_VQ23_ENTRY_CNT 0x120888
2162 /* [R 8] Number of entries occupied by vq 24 in pswrq memory */
2163 #define PXP2_REG_RQ_VQ24_ENTRY_CNT 0x120890
2164 /* [R 8] Number of entries occupied by vq 25 in pswrq memory */
2165 #define PXP2_REG_RQ_VQ25_ENTRY_CNT 0x120898
2166 /* [R 8] Number of entries occupied by vq 26 in pswrq memory */
2167 #define PXP2_REG_RQ_VQ26_ENTRY_CNT 0x1208a0
2168 /* [R 8] Number of entries occupied by vq 27 in pswrq memory */
2169 #define PXP2_REG_RQ_VQ27_ENTRY_CNT 0x1208a8
2170 /* [R 8] Number of entries occupied by vq 28 in pswrq memory */
2171 #define PXP2_REG_RQ_VQ28_ENTRY_CNT 0x1208b0
2172 /* [R 8] Number of entries occupied by vq 29 in pswrq memory */
2173 #define PXP2_REG_RQ_VQ29_ENTRY_CNT 0x1208b8
2174 /* [R 8] Number of entries occupied by vq 2 in pswrq memory */
2175 #define PXP2_REG_RQ_VQ2_ENTRY_CNT 0x1208c0
2176 /* [R 8] Number of entries occupied by vq 30 in pswrq memory */
2177 #define PXP2_REG_RQ_VQ30_ENTRY_CNT 0x1208c8
2178 /* [R 8] Number of entries occupied by vq 31 in pswrq memory */
2179 #define PXP2_REG_RQ_VQ31_ENTRY_CNT 0x1208d0
2180 /* [R 8] Number of entries occupied by vq 3 in pswrq memory */
2181 #define PXP2_REG_RQ_VQ3_ENTRY_CNT 0x1208d8
2182 /* [R 8] Number of entries occupied by vq 4 in pswrq memory */
2183 #define PXP2_REG_RQ_VQ4_ENTRY_CNT 0x1208e0
2184 /* [R 8] Number of entries occupied by vq 5 in pswrq memory */
2185 #define PXP2_REG_RQ_VQ5_ENTRY_CNT 0x1208e8
2186 /* [R 8] Number of entries occupied by vq 6 in pswrq memory */
2187 #define PXP2_REG_RQ_VQ6_ENTRY_CNT 0x1208f0
2188 /* [R 8] Number of entries occupied by vq 7 in pswrq memory */
2189 #define PXP2_REG_RQ_VQ7_ENTRY_CNT 0x1208f8
2190 /* [R 8] Number of entries occupied by vq 8 in pswrq memory */
2191 #define PXP2_REG_RQ_VQ8_ENTRY_CNT 0x120900
2192 /* [R 8] Number of entries occupied by vq 9 in pswrq memory */
2193 #define PXP2_REG_RQ_VQ9_ENTRY_CNT 0x120908
2194 /* [RW 3] Max burst size filed for write requests port 0; 000 - 128B;
2195 001:256B; 010: 512B; */
2196 #define PXP2_REG_RQ_WR_MBS0 0x12015c
2198 =======
2199 /* [RW 3] Max burst size filed for write requests port 1; 000 - 128B;
2200 001:256B; 010: 512B; */
2201 #define PXP2_REG_RQ_WR_MBS1 0x120164
2203 /* [RW 10] if Number of entries in dmae fifo will be higer than this
2204 threshold then has_payload indication will be asserted; the default value
2205 should be equal to > write MBS size! */
2206 #define PXP2_REG_WR_DMAE_TH 0x120368
2208 =======
2209 /* [RW 10] if Number of entries in usdmdp fifo will be higer than this
2210 threshold then has_payload indication will be asserted; the default value
2211 should be equal to > write MBS size! */
2212 #define PXP2_REG_WR_USDMDP_TH 0x120348
2214 /* [R 1] debug only: Indication if PSWHST arbiter is idle */
2215 #define PXP_REG_HST_ARB_IS_IDLE 0x103004
2216 /* [R 8] debug only: A bit mask for all PSWHST arbiter clients. '1' means
2217 this client is waiting for the arbiter. */
2218 #define PXP_REG_HST_CLIENTS_WAITING_TO_ARB 0x103008
2219 /* [WB 160] Used for initialization of the inbound interrupts memory */
2220 #define PXP_REG_HST_INBOUND_INT 0x103800
2221 /* [RW 32] Interrupt mask register #0 read/write */
2222 #define PXP_REG_PXP_INT_MASK_0 0x103074
2223 #define PXP_REG_PXP_INT_MASK_1 0x103084
2224 /* [R 32] Interrupt register #0 read */
2225 #define PXP_REG_PXP_INT_STS_0 0x103068
2226 #define PXP_REG_PXP_INT_STS_1 0x103078
2227 /* [RC 32] Interrupt register #0 read clear */
2228 #define PXP_REG_PXP_INT_STS_CLR_0 0x10306c
2229 /* [RW 26] Parity mask register #0 read/write */
2230 #define PXP_REG_PXP_PRTY_MASK 0x103094
2232 =======
2233 /* [R 26] Parity register #0 read */
2234 #define PXP_REG_PXP_PRTY_STS 0x103088
2236 /* [RW 4] The activity counter initial increment value sent in the load
2237 request */
2238 #define QM_REG_ACTCTRINITVAL_0 0x168040
2239 #define QM_REG_ACTCTRINITVAL_1 0x168044
2240 #define QM_REG_ACTCTRINITVAL_2 0x168048
2241 #define QM_REG_ACTCTRINITVAL_3 0x16804c
2242 /* [RW 32] The base logical address (in bytes) of each physical queue. The
2243 index I represents the physical queue number. The 12 lsbs are ignore and
2244 considered zero so practically there are only 20 bits in this register. */
2245 #define QM_REG_BASEADDR 0x168900
2246 /* [RW 16] The byte credit cost for each task. This value is for both ports */
2247 #define QM_REG_BYTECRDCOST 0x168234
2248 /* [RW 16] The initial byte credit value for both ports. */
2249 #define QM_REG_BYTECRDINITVAL 0x168238
2250 /* [RW 32] A bit per physical queue. If the bit is cleared then the physical
2251 queue uses port 0 else it uses port 1. */
2252 #define QM_REG_BYTECRDPORT_LSB 0x168228
2253 /* [RW 32] A bit per physical queue. If the bit is cleared then the physical
2254 queue uses port 0 else it uses port 1. */
2255 #define QM_REG_BYTECRDPORT_MSB 0x168224
2256 /* [RW 16] The byte credit value that if above the QM is considered almost
2257 full */
2258 #define QM_REG_BYTECREDITAFULLTHR 0x168094
2259 /* [RW 4] The initial credit for interface */
2260 #define QM_REG_CMINITCRD_0 0x1680cc
2261 #define QM_REG_CMINITCRD_1 0x1680d0
2262 #define QM_REG_CMINITCRD_2 0x1680d4
2263 #define QM_REG_CMINITCRD_3 0x1680d8
2264 #define QM_REG_CMINITCRD_4 0x1680dc
2265 #define QM_REG_CMINITCRD_5 0x1680e0
2266 #define QM_REG_CMINITCRD_6 0x1680e4
2267 #define QM_REG_CMINITCRD_7 0x1680e8
2268 /* [RW 8] A mask bit per CM interface. If this bit is 0 then this interface
2269 is masked */
2270 #define QM_REG_CMINTEN 0x1680ec
2271 /* [RW 12] A bit vector which indicates which one of the queues are tied to
2272 interface 0 */
2273 #define QM_REG_CMINTVOQMASK_0 0x1681f4
2274 #define QM_REG_CMINTVOQMASK_1 0x1681f8
2275 #define QM_REG_CMINTVOQMASK_2 0x1681fc
2276 #define QM_REG_CMINTVOQMASK_3 0x168200
2277 #define QM_REG_CMINTVOQMASK_4 0x168204
2278 #define QM_REG_CMINTVOQMASK_5 0x168208
2279 #define QM_REG_CMINTVOQMASK_6 0x16820c
2280 #define QM_REG_CMINTVOQMASK_7 0x168210
2281 /* [RW 20] The number of connections divided by 16 which dictates the size
2282 of each queue per port 0 */
2283 #define QM_REG_CONNNUM_0 0x168020
2284 /* [R 6] Keep the fill level of the fifo from write client 4 */
2285 #define QM_REG_CQM_WRC_FIFOLVL 0x168018
2286 /* [RW 8] The context regions sent in the CFC load request */
2287 #define QM_REG_CTXREG_0 0x168030
2288 #define QM_REG_CTXREG_1 0x168034
2289 #define QM_REG_CTXREG_2 0x168038
2290 #define QM_REG_CTXREG_3 0x16803c
2291 /* [RW 12] The VOQ mask used to select the VOQs which needs to be full for
2292 bypass enable */
2293 #define QM_REG_ENBYPVOQMASK 0x16823c
2294 /* [RW 32] A bit mask per each physical queue. If a bit is set then the
2295 physical queue uses the byte credit */
2296 #define QM_REG_ENBYTECRD_LSB 0x168220
2297 /* [RW 32] A bit mask per each physical queue. If a bit is set then the
2298 physical queue uses the byte credit */
2299 #define QM_REG_ENBYTECRD_MSB 0x16821c
2300 /* [RW 4] If cleared then the secondary interface will not be served by the
2301 RR arbiter */
2302 #define QM_REG_ENSEC 0x1680f0
2303 /* [RW 32] A bit vector per each physical queue which selects which function
2304 number to use on PCI access for that queue. */
2305 #define QM_REG_FUNCNUMSEL_LSB 0x168230
2306 /* [RW 32] A bit vector per each physical queue which selects which function
2307 number to use on PCI access for that queue. */
2308 #define QM_REG_FUNCNUMSEL_MSB 0x16822c
2309 /* [RW 32] A mask register to mask the Almost empty signals which will not
2310 be use for the almost empty indication to the HW block */
2311 #define QM_REG_HWAEMPTYMASK_LSB 0x168218
2312 /* [RW 32] A mask register to mask the Almost empty signals which will not
2313 be use for the almost empty indication to the HW block */
2314 #define QM_REG_HWAEMPTYMASK_MSB 0x168214
2315 /* [RW 4] The number of outstanding request to CFC */
2316 #define QM_REG_OUTLDREQ 0x168804
2317 /* [RC 1] A flag to indicate that overflow error occurred in one of the
2318 queues. */
2319 #define QM_REG_OVFERROR 0x16805c
2320 /* [RC 6] the Q were the qverflow occurs */
2321 #define QM_REG_OVFQNUM 0x168058
2322 /* [R 32] Pause state for physical queues 31-0 */
2323 #define QM_REG_PAUSESTATE0 0x168410
2324 /* [R 32] Pause state for physical queues 64-32 */
2325 #define QM_REG_PAUSESTATE1 0x168414
2326 /* [RW 2] The PCI attributes field used in the PCI request. */
2327 #define QM_REG_PCIREQAT 0x168054
2328 /* [R 16] The byte credit of port 0 */
2329 #define QM_REG_PORT0BYTECRD 0x168300
2330 /* [R 16] The byte credit of port 1 */
2331 #define QM_REG_PORT1BYTECRD 0x168304
2332 /* [WB 54] Pointer Table Memory; The mapping is as follow: ptrtbl[53:30]
2333 read pointer; ptrtbl[29:6] write pointer; ptrtbl[5:4] read bank0;
2334 ptrtbl[3:2] read bank 1; ptrtbl[1:0] write bank; */
2335 #define QM_REG_PTRTBL 0x168a00
2336 /* [RW 2] Interrupt mask register #0 read/write */
2337 #define QM_REG_QM_INT_MASK 0x168444
2338 /* [R 2] Interrupt register #0 read */
2339 #define QM_REG_QM_INT_STS 0x168438
2340 /* [RW 9] Parity mask register #0 read/write */
2341 #define QM_REG_QM_PRTY_MASK 0x168454
2343 =======
2344 /* [R 9] Parity register #0 read */
2345 #define QM_REG_QM_PRTY_STS 0x168448
2347 /* [R 32] Current queues in pipeline: Queues from 32 to 63 */
2348 #define QM_REG_QSTATUS_HIGH 0x16802c
2349 /* [R 32] Current queues in pipeline: Queues from 0 to 31 */
2350 #define QM_REG_QSTATUS_LOW 0x168028
2351 /* [R 24] The number of tasks queued for each queue */
2352 #define QM_REG_QTASKCTR_0 0x168308
2353 /* [RW 4] Queue tied to VOQ */
2354 #define QM_REG_QVOQIDX_0 0x1680f4
2355 #define QM_REG_QVOQIDX_10 0x16811c
2356 #define QM_REG_QVOQIDX_11 0x168120
2357 #define QM_REG_QVOQIDX_12 0x168124
2358 #define QM_REG_QVOQIDX_13 0x168128
2359 #define QM_REG_QVOQIDX_14 0x16812c
2360 #define QM_REG_QVOQIDX_15 0x168130
2361 #define QM_REG_QVOQIDX_16 0x168134
2362 #define QM_REG_QVOQIDX_17 0x168138
2363 #define QM_REG_QVOQIDX_21 0x168148
2364 #define QM_REG_QVOQIDX_25 0x168158
2365 #define QM_REG_QVOQIDX_29 0x168168
2366 #define QM_REG_QVOQIDX_32 0x168174
2367 #define QM_REG_QVOQIDX_33 0x168178
2368 #define QM_REG_QVOQIDX_34 0x16817c
2369 #define QM_REG_QVOQIDX_35 0x168180
2370 #define QM_REG_QVOQIDX_36 0x168184
2371 #define QM_REG_QVOQIDX_37 0x168188
2372 #define QM_REG_QVOQIDX_38 0x16818c
2373 #define QM_REG_QVOQIDX_39 0x168190
2374 #define QM_REG_QVOQIDX_40 0x168194
2375 #define QM_REG_QVOQIDX_41 0x168198
2376 #define QM_REG_QVOQIDX_42 0x16819c
2377 #define QM_REG_QVOQIDX_43 0x1681a0
2378 #define QM_REG_QVOQIDX_44 0x1681a4
2379 #define QM_REG_QVOQIDX_45 0x1681a8
2380 #define QM_REG_QVOQIDX_46 0x1681ac
2381 #define QM_REG_QVOQIDX_47 0x1681b0
2382 #define QM_REG_QVOQIDX_48 0x1681b4
2383 #define QM_REG_QVOQIDX_49 0x1681b8
2384 #define QM_REG_QVOQIDX_5 0x168108
2385 #define QM_REG_QVOQIDX_50 0x1681bc
2386 #define QM_REG_QVOQIDX_51 0x1681c0
2387 #define QM_REG_QVOQIDX_52 0x1681c4
2388 #define QM_REG_QVOQIDX_53 0x1681c8
2389 #define QM_REG_QVOQIDX_54 0x1681cc
2390 #define QM_REG_QVOQIDX_55 0x1681d0
2391 #define QM_REG_QVOQIDX_56 0x1681d4
2392 #define QM_REG_QVOQIDX_57 0x1681d8
2393 #define QM_REG_QVOQIDX_58 0x1681dc
2394 #define QM_REG_QVOQIDX_59 0x1681e0
2395 #define QM_REG_QVOQIDX_50 0x1681bc
2396 #define QM_REG_QVOQIDX_51 0x1681c0
2397 #define QM_REG_QVOQIDX_52 0x1681c4
2398 #define QM_REG_QVOQIDX_53 0x1681c8
2399 #define QM_REG_QVOQIDX_54 0x1681cc
2400 #define QM_REG_QVOQIDX_55 0x1681d0
2401 #define QM_REG_QVOQIDX_56 0x1681d4
2402 #define QM_REG_QVOQIDX_57 0x1681d8
2403 #define QM_REG_QVOQIDX_58 0x1681dc
2404 #define QM_REG_QVOQIDX_59 0x1681e0
2405 #define QM_REG_QVOQIDX_6 0x16810c
2406 #define QM_REG_QVOQIDX_60 0x1681e4
2407 #define QM_REG_QVOQIDX_61 0x1681e8
2408 #define QM_REG_QVOQIDX_62 0x1681ec
2409 #define QM_REG_QVOQIDX_63 0x1681f0
2410 #define QM_REG_QVOQIDX_60 0x1681e4
2411 #define QM_REG_QVOQIDX_61 0x1681e8
2412 #define QM_REG_QVOQIDX_62 0x1681ec
2413 #define QM_REG_QVOQIDX_63 0x1681f0
2414 #define QM_REG_QVOQIDX_7 0x168110
2415 #define QM_REG_QVOQIDX_8 0x168114
2416 #define QM_REG_QVOQIDX_9 0x168118
2417 /* [R 24] Remaining pause timeout for port 0 */
2418 #define QM_REG_REMAINPAUSETM0 0x168418
2419 /* [R 24] Remaining pause timeout for port 1 */
2420 #define QM_REG_REMAINPAUSETM1 0x16841c
2421 /* [RW 1] Initialization bit command */
2422 #define QM_REG_SOFT_RESET 0x168428
2423 /* [RW 8] The credit cost per every task in the QM. A value per each VOQ */
2424 #define QM_REG_TASKCRDCOST_0 0x16809c
2425 #define QM_REG_TASKCRDCOST_1 0x1680a0
2426 #define QM_REG_TASKCRDCOST_10 0x1680c4
2427 #define QM_REG_TASKCRDCOST_11 0x1680c8
2428 #define QM_REG_TASKCRDCOST_2 0x1680a4
2429 #define QM_REG_TASKCRDCOST_4 0x1680ac
2430 #define QM_REG_TASKCRDCOST_5 0x1680b0
2431 /* [R 6] Keep the fill level of the fifo from write client 3 */
2432 #define QM_REG_TQM_WRC_FIFOLVL 0x168010
2433 /* [R 6] Keep the fill level of the fifo from write client 2 */
2434 #define QM_REG_UQM_WRC_FIFOLVL 0x168008
2435 /* [RC 32] Credit update error register */
2436 #define QM_REG_VOQCRDERRREG 0x168408
2437 /* [R 16] The credit value for each VOQ */
2438 #define QM_REG_VOQCREDIT_0 0x1682d0
2439 #define QM_REG_VOQCREDIT_1 0x1682d4
2440 #define QM_REG_VOQCREDIT_10 0x1682f8
2441 #define QM_REG_VOQCREDIT_11 0x1682fc
2442 #define QM_REG_VOQCREDIT_4 0x1682e0
2443 /* [RW 16] The credit value that if above the QM is considered almost full */
2444 #define QM_REG_VOQCREDITAFULLTHR 0x168090
2445 /* [RW 16] The init and maximum credit for each VoQ */
2446 #define QM_REG_VOQINITCREDIT_0 0x168060
2447 #define QM_REG_VOQINITCREDIT_1 0x168064
2448 #define QM_REG_VOQINITCREDIT_10 0x168088
2449 #define QM_REG_VOQINITCREDIT_11 0x16808c
2450 #define QM_REG_VOQINITCREDIT_2 0x168068
2451 #define QM_REG_VOQINITCREDIT_4 0x168070
2452 #define QM_REG_VOQINITCREDIT_5 0x168074
2453 /* [RW 1] The port of which VOQ belongs */
2454 #define QM_REG_VOQPORT_1 0x1682a4
2455 #define QM_REG_VOQPORT_10 0x1682c8
2456 #define QM_REG_VOQPORT_11 0x1682cc
2457 #define QM_REG_VOQPORT_2 0x1682a8
2458 /* [RW 32] The physical queue number associated with each VOQ */
2459 #define QM_REG_VOQQMASK_0_LSB 0x168240
2460 /* [RW 32] The physical queue number associated with each VOQ */
2461 #define QM_REG_VOQQMASK_0_MSB 0x168244
2462 /* [RW 32] The physical queue number associated with each VOQ */
2463 #define QM_REG_VOQQMASK_1_MSB 0x16824c
2464 /* [RW 32] The physical queue number associated with each VOQ */
2465 #define QM_REG_VOQQMASK_2_LSB 0x168250
2466 /* [RW 32] The physical queue number associated with each VOQ */
2467 #define QM_REG_VOQQMASK_2_MSB 0x168254
2468 /* [RW 32] The physical queue number associated with each VOQ */
2469 #define QM_REG_VOQQMASK_3_LSB 0x168258
2470 /* [RW 32] The physical queue number associated with each VOQ */
2471 #define QM_REG_VOQQMASK_4_LSB 0x168260
2472 /* [RW 32] The physical queue number associated with each VOQ */
2473 #define QM_REG_VOQQMASK_4_MSB 0x168264
2474 /* [RW 32] The physical queue number associated with each VOQ */
2475 #define QM_REG_VOQQMASK_5_LSB 0x168268
2476 /* [RW 32] The physical queue number associated with each VOQ */
2477 #define QM_REG_VOQQMASK_5_MSB 0x16826c
2478 /* [RW 32] The physical queue number associated with each VOQ */
2479 #define QM_REG_VOQQMASK_6_LSB 0x168270
2480 /* [RW 32] The physical queue number associated with each VOQ */
2481 #define QM_REG_VOQQMASK_6_MSB 0x168274
2482 /* [RW 32] The physical queue number associated with each VOQ */
2483 #define QM_REG_VOQQMASK_7_LSB 0x168278
2484 /* [RW 32] The physical queue number associated with each VOQ */
2485 #define QM_REG_VOQQMASK_7_MSB 0x16827c
2486 /* [RW 32] The physical queue number associated with each VOQ */
2487 #define QM_REG_VOQQMASK_8_LSB 0x168280
2488 /* [RW 32] The physical queue number associated with each VOQ */
2489 #define QM_REG_VOQQMASK_8_MSB 0x168284
2490 /* [RW 32] The physical queue number associated with each VOQ */
2491 #define QM_REG_VOQQMASK_9_LSB 0x168288
2492 /* [RW 32] Wrr weights */
2493 #define QM_REG_WRRWEIGHTS_0 0x16880c
2494 #define QM_REG_WRRWEIGHTS_1 0x168810
2495 #define QM_REG_WRRWEIGHTS_10 0x168814
2496 #define QM_REG_WRRWEIGHTS_10_SIZE 1
2497 /* [RW 32] Wrr weights */
2498 #define QM_REG_WRRWEIGHTS_11 0x168818
2499 #define QM_REG_WRRWEIGHTS_11_SIZE 1
2500 /* [RW 32] Wrr weights */
2501 #define QM_REG_WRRWEIGHTS_12 0x16881c
2502 #define QM_REG_WRRWEIGHTS_12_SIZE 1
2503 /* [RW 32] Wrr weights */
2504 #define QM_REG_WRRWEIGHTS_13 0x168820
2505 #define QM_REG_WRRWEIGHTS_13_SIZE 1
2506 /* [RW 32] Wrr weights */
2507 #define QM_REG_WRRWEIGHTS_14 0x168824
2508 #define QM_REG_WRRWEIGHTS_14_SIZE 1
2509 /* [RW 32] Wrr weights */
2510 #define QM_REG_WRRWEIGHTS_15 0x168828
2511 #define QM_REG_WRRWEIGHTS_15_SIZE 1
2512 /* [RW 32] Wrr weights */
2513 #define QM_REG_WRRWEIGHTS_10 0x168814
2514 #define QM_REG_WRRWEIGHTS_11 0x168818
2515 #define QM_REG_WRRWEIGHTS_12 0x16881c
2516 #define QM_REG_WRRWEIGHTS_13 0x168820
2517 #define QM_REG_WRRWEIGHTS_14 0x168824
2518 #define QM_REG_WRRWEIGHTS_15 0x168828
2519 #define QM_REG_WRRWEIGHTS_2 0x16882c
2520 #define QM_REG_WRRWEIGHTS_3 0x168830
2521 #define QM_REG_WRRWEIGHTS_4 0x168834
2522 #define QM_REG_WRRWEIGHTS_5 0x168838
2523 #define QM_REG_WRRWEIGHTS_6 0x16883c
2524 #define QM_REG_WRRWEIGHTS_7 0x168840
2525 #define QM_REG_WRRWEIGHTS_8 0x168844
2526 #define QM_REG_WRRWEIGHTS_9 0x168848
2527 /* [R 6] Keep the fill level of the fifo from write client 1 */
2528 #define QM_REG_XQM_WRC_FIFOLVL 0x168000
2529 #define DORQ_DORQ_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
2530 #define DORQ_DORQ_INT_STS_REG_ADDRESS_ERROR_SIZE 0
2531 #define DORQ_DORQ_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
2532 #define DORQ_DORQ_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
2533 #define DORQ_DORQ_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
2534 #define DORQ_DORQ_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
2535 #define DORQ_DORQ_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
2536 #define DORQ_DORQ_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
2537 #define NIG_NIG_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
2538 #define NIG_NIG_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
2539 #define NIG_NIG_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
2540 #define NIG_NIG_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
2541 #define NIG_NIG_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
2542 #define NIG_NIG_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
2543 #define NIG_NIG_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
2544 #define NIG_NIG_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
2545 #define TCM_TCM_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
2546 #define TCM_TCM_INT_STS_REG_ADDRESS_ERROR_SIZE 0
2547 #define TCM_TCM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
2548 #define TCM_TCM_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
2549 #define TCM_TCM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
2550 #define TCM_TCM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
2551 #define TCM_TCM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
2552 #define TCM_TCM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
2553 #define CFC_DEBUG1_REG_WRITE_AC (0x1<<4)
2554 #define CFC_DEBUG1_REG_WRITE_AC_SIZE 4
2555 /* [R 1] debug only: This bit indicates wheter indicates that external
2556 buffer was wrapped (oldest data was thrown); Relevant only when
2557 ~dbg_registers_debug_target=2 (PCI) & ~dbg_registers_full_mode=1 (wrap); */
2558 #define DBG_REG_WRAP_ON_EXT_BUFFER 0xc124
2559 #define DBG_REG_WRAP_ON_EXT_BUFFER_SIZE 1
2560 /* [R 1] debug only: This bit indicates wheter the internal buffer was
2561 wrapped (oldest data was thrown) Relevant only when
2562 ~dbg_registers_debug_target=0 (internal buffer) */
2563 #define DBG_REG_WRAP_ON_INT_BUFFER 0xc128
2564 #define DBG_REG_WRAP_ON_INT_BUFFER_SIZE 1
2565 /* [RW 32] Wrr weights */
2566 #define QM_REG_WRRWEIGHTS_0 0x16880c
2567 #define QM_REG_WRRWEIGHTS_0_SIZE 1
2568 /* [RW 32] Wrr weights */
2569 #define QM_REG_WRRWEIGHTS_1 0x168810
2570 #define QM_REG_WRRWEIGHTS_1_SIZE 1
2571 /* [RW 32] Wrr weights */
2572 #define QM_REG_WRRWEIGHTS_10 0x168814
2573 #define QM_REG_WRRWEIGHTS_10_SIZE 1
2574 /* [RW 32] Wrr weights */
2575 #define QM_REG_WRRWEIGHTS_11 0x168818
2576 #define QM_REG_WRRWEIGHTS_11_SIZE 1
2577 /* [RW 32] Wrr weights */
2578 #define QM_REG_WRRWEIGHTS_12 0x16881c
2579 #define QM_REG_WRRWEIGHTS_12_SIZE 1
2580 /* [RW 32] Wrr weights */
2581 #define QM_REG_WRRWEIGHTS_13 0x168820
2582 #define QM_REG_WRRWEIGHTS_13_SIZE 1
2583 /* [RW 32] Wrr weights */
2584 #define QM_REG_WRRWEIGHTS_14 0x168824
2585 #define QM_REG_WRRWEIGHTS_14_SIZE 1
2586 /* [RW 32] Wrr weights */
2587 #define QM_REG_WRRWEIGHTS_15 0x168828
2588 #define QM_REG_WRRWEIGHTS_15_SIZE 1
2589 /* [RW 32] Wrr weights */
2590 #define QM_REG_WRRWEIGHTS_2 0x16882c
2591 #define QM_REG_WRRWEIGHTS_2_SIZE 1
2592 /* [RW 32] Wrr weights */
2593 #define QM_REG_WRRWEIGHTS_3 0x168830
2594 #define QM_REG_WRRWEIGHTS_3_SIZE 1
2595 /* [RW 32] Wrr weights */
2596 #define QM_REG_WRRWEIGHTS_4 0x168834
2597 #define QM_REG_WRRWEIGHTS_4_SIZE 1
2598 /* [RW 32] Wrr weights */
2599 #define QM_REG_WRRWEIGHTS_5 0x168838
2600 #define QM_REG_WRRWEIGHTS_5_SIZE 1
2601 /* [RW 32] Wrr weights */
2602 #define QM_REG_WRRWEIGHTS_6 0x16883c
2603 #define QM_REG_WRRWEIGHTS_6_SIZE 1
2604 /* [RW 32] Wrr weights */
2605 #define QM_REG_WRRWEIGHTS_7 0x168840
2606 #define QM_REG_WRRWEIGHTS_7_SIZE 1
2607 /* [RW 32] Wrr weights */
2608 #define QM_REG_WRRWEIGHTS_8 0x168844
2609 #define QM_REG_WRRWEIGHTS_8_SIZE 1
2610 /* [RW 32] Wrr weights */
2611 #define QM_REG_WRRWEIGHTS_9 0x168848
2612 #define QM_REG_WRRWEIGHTS_9_SIZE 1
2613 /* [RW 22] Number of free element in the free list of T2 entries - port 0. */
2614 #define SRC_REG_COUNTFREE0 0x40500
2615 /* [WB 64] First free element in the free list of T2 entries - port 0. */
2616 #define SRC_REG_FIRSTFREE0 0x40510
2617 #define SRC_REG_KEYRSS0_0 0x40408
2618 #define SRC_REG_KEYRSS1_9 0x40454
2619 /* [WB 64] Last free element in the free list of T2 entries - port 0. */
2620 #define SRC_REG_LASTFREE0 0x40530
2621 /* [RW 5] The number of hash bits used for the search (h); Values can be 8
2622 to 24. */
2623 #define SRC_REG_NUMBER_HASH_BITS0 0x40400
2624 /* [RW 1] Reset internal state machines. */
2625 #define SRC_REG_SOFT_RST 0x4049c
2626 /* [R 1] Interrupt register #0 read */
2627 #define SRC_REG_SRC_INT_STS 0x404ac
2628 /* [RW 3] Parity mask register #0 read/write */
2629 #define SRC_REG_SRC_PRTY_MASK 0x404c8
2631 =======
2632 /* [R 3] Parity register #0 read */
2633 #define SRC_REG_SRC_PRTY_STS 0x404bc
2635 /* [R 4] Used to read the value of the XX protection CAM occupancy counter. */
2636 #define TCM_REG_CAM_OCCUP 0x5017c
2637 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is
2638 disregarded; valid output is deasserted; all other signals are treated as
2639 usual; if 1 - normal activity. */
2640 #define TCM_REG_CDU_AG_RD_IFEN 0x50034
2641 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
2642 are disregarded; all other signals are treated as usual; if 1 - normal
2643 activity. */
2644 #define TCM_REG_CDU_AG_WR_IFEN 0x50030
2645 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
2646 disregarded; valid output is deasserted; all other signals are treated as
2647 usual; if 1 - normal activity. */
2648 #define TCM_REG_CDU_SM_RD_IFEN 0x5003c
2649 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
2650 input is disregarded; all other signals are treated as usual; if 1 -
2651 normal activity. */
2652 #define TCM_REG_CDU_SM_WR_IFEN 0x50038
2653 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
2654 the initial credit value; read returns the current value of the credit
2655 counter. Must be initialized to 1 at start-up. */
2656 #define TCM_REG_CFC_INIT_CRD 0x50204
2657 /* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for
2658 weight 8 (the most prioritised); 1 stands for weight 1(least
2659 prioritised); 2 stands for weight 2; tc. */
2660 #define TCM_REG_CP_WEIGHT 0x500c0
2661 /* [RW 1] Input csem Interface enable. If 0 - the valid input is
2662 disregarded; acknowledge output is deasserted; all other signals are
2663 treated as usual; if 1 - normal activity. */
2664 #define TCM_REG_CSEM_IFEN 0x5002c
2665 /* [RC 1] Message length mismatch (relative to last indication) at the In#9
2666 interface. */
2667 #define TCM_REG_CSEM_LENGTH_MIS 0x50174
2668 /* [RW 8] The Event ID in case of ErrorFlg is set in the input message. */
2669 #define TCM_REG_ERR_EVNT_ID 0x500a0
2670 /* [RW 28] The CM erroneous header for QM and Timers formatting. */
2671 #define TCM_REG_ERR_TCM_HDR 0x5009c
2672 /* [RW 8] The Event ID for Timers expiration. */
2673 #define TCM_REG_EXPR_EVNT_ID 0x500a4
2674 /* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
2675 writes the initial credit value; read returns the current value of the
2676 credit counter. Must be initialized to 64 at start-up. */
2677 #define TCM_REG_FIC0_INIT_CRD 0x5020c
2678 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
2679 writes the initial credit value; read returns the current value of the
2680 credit counter. Must be initialized to 64 at start-up. */
2681 #define TCM_REG_FIC1_INIT_CRD 0x50210
2682 /* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
2683 - strict priority defined by ~tcm_registers_gr_ag_pr.gr_ag_pr;
2684 ~tcm_registers_gr_ld0_pr.gr_ld0_pr and
2685 ~tcm_registers_gr_ld1_pr.gr_ld1_pr. */
2686 #define TCM_REG_GR_ARB_TYPE 0x50114
2687 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
2688 highest priority is 3. It is supposed that the Store channel is the
2689 compliment of the other 3 groups. */
2690 #define TCM_REG_GR_LD0_PR 0x5011c
2691 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
2692 highest priority is 3. It is supposed that the Store channel is the
2693 compliment of the other 3 groups. */
2694 #define TCM_REG_GR_LD1_PR 0x50120
2695 /* [RW 4] The number of double REG-pairs; loaded from the STORM context and
2696 sent to STORM; for a specific connection type. The double REG-pairs are
2697 used to align to STORM context row size of 128 bits. The offset of these
2698 data in the STORM context is always 0. Index _i stands for the connection
2699 type (one of 16). */
2700 #define TCM_REG_N_SM_CTX_LD_0 0x50050
2701 #define TCM_REG_N_SM_CTX_LD_1 0x50054
2702 #define TCM_REG_N_SM_CTX_LD_10 0x50078
2703 #define TCM_REG_N_SM_CTX_LD_11 0x5007c
2704 #define TCM_REG_N_SM_CTX_LD_12 0x50080
2705 #define TCM_REG_N_SM_CTX_LD_13 0x50084
2706 #define TCM_REG_N_SM_CTX_LD_14 0x50088
2707 #define TCM_REG_N_SM_CTX_LD_15 0x5008c
2708 #define TCM_REG_N_SM_CTX_LD_2 0x50058
2709 #define TCM_REG_N_SM_CTX_LD_3 0x5005c
2710 #define TCM_REG_N_SM_CTX_LD_4 0x50060
2711 /* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
2712 acknowledge output is deasserted; all other signals are treated as usual;
2713 if 1 - normal activity. */
2714 #define TCM_REG_PBF_IFEN 0x50024
2715 /* [RC 1] Message length mismatch (relative to last indication) at the In#7
2716 interface. */
2717 #define TCM_REG_PBF_LENGTH_MIS 0x5016c
2718 /* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for
2719 weight 8 (the most prioritised); 1 stands for weight 1(least
2720 prioritised); 2 stands for weight 2; tc. */
2721 #define TCM_REG_PBF_WEIGHT 0x500b4
2722 /* [RW 6] The physical queue number 0 per port index. */
2723 #define TCM_REG_PHYS_QNUM0_0 0x500e0
2724 #define TCM_REG_PHYS_QNUM0_1 0x500e4
2725 /* [RW 6] The physical queue number 1 per port index. */
2726 #define TCM_REG_PHYS_QNUM1_0 0x500e8
2727 /* [RW 1] Input prs Interface enable. If 0 - the valid input is disregarded;
2728 acknowledge output is deasserted; all other signals are treated as usual;
2729 if 1 - normal activity. */
2730 #define TCM_REG_PRS_IFEN 0x50020
2731 /* [RC 1] Message length mismatch (relative to last indication) at the In#6
2732 interface. */
2733 #define TCM_REG_PRS_LENGTH_MIS 0x50168
2734 /* [RW 3] The weight of the input prs in the WRR mechanism. 0 stands for
2735 weight 8 (the most prioritised); 1 stands for weight 1(least
2736 prioritised); 2 stands for weight 2; tc. */
2737 #define TCM_REG_PRS_WEIGHT 0x500b0
2738 /* [RW 8] The Event ID for Timers formatting in case of stop done. */
2739 #define TCM_REG_STOP_EVNT_ID 0x500a8
2740 /* [RC 1] Message length mismatch (relative to last indication) at the STORM
2741 interface. */
2742 #define TCM_REG_STORM_LENGTH_MIS 0x50160
2743 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
2744 disregarded; acknowledge output is deasserted; all other signals are
2745 treated as usual; if 1 - normal activity. */
2746 #define TCM_REG_STORM_TCM_IFEN 0x50010
2747 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
2748 acknowledge output is deasserted; all other signals are treated as usual;
2749 if 1 - normal activity. */
2750 #define TCM_REG_TCM_CFC_IFEN 0x50040
2751 /* [RW 11] Interrupt mask register #0 read/write */
2752 #define TCM_REG_TCM_INT_MASK 0x501dc
2753 /* [R 11] Interrupt register #0 read */
2754 #define TCM_REG_TCM_INT_STS 0x501d0
2755 /* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS
2756 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
2757 Is used to determine the number of the AG context REG-pairs written back;
2758 when the input message Reg1WbFlg isn't set. */
2759 #define TCM_REG_TCM_REG0_SZ 0x500d8
2760 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
2761 disregarded; valid is deasserted; all other signals are treated as usual;
2762 if 1 - normal activity. */
2763 #define TCM_REG_TCM_STORM0_IFEN 0x50004
2764 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
2765 disregarded; valid is deasserted; all other signals are treated as usual;
2766 if 1 - normal activity. */
2767 #define TCM_REG_TCM_STORM1_IFEN 0x50008
2768 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
2769 disregarded; valid is deasserted; all other signals are treated as usual;
2770 if 1 - normal activity. */
2771 #define TCM_REG_TCM_TQM_IFEN 0x5000c
2772 /* [RW 1] If set the Q index; received from the QM is inserted to event ID. */
2773 #define TCM_REG_TCM_TQM_USE_Q 0x500d4
2774 /* [RW 28] The CM header for Timers expiration command. */
2775 #define TCM_REG_TM_TCM_HDR 0x50098
2776 /* [RW 1] Timers - CM Interface enable. If 0 - the valid input is
2777 disregarded; acknowledge output is deasserted; all other signals are
2778 treated as usual; if 1 - normal activity. */
2779 #define TCM_REG_TM_TCM_IFEN 0x5001c
2780 /* [RW 6] QM output initial credit. Max credit available - 32.Write writes
2781 the initial credit value; read returns the current value of the credit
2782 counter. Must be initialized to 32 at start-up. */
2783 #define TCM_REG_TQM_INIT_CRD 0x5021c
2784 /* [RW 28] The CM header value for QM request (primary). */
2785 #define TCM_REG_TQM_TCM_HDR_P 0x50090
2786 /* [RW 28] The CM header value for QM request (secondary). */
2787 #define TCM_REG_TQM_TCM_HDR_S 0x50094
2788 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
2789 acknowledge output is deasserted; all other signals are treated as usual;
2790 if 1 - normal activity. */
2791 #define TCM_REG_TQM_TCM_IFEN 0x50014
2792 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
2793 acknowledge output is deasserted; all other signals are treated as usual;
2794 if 1 - normal activity. */
2795 #define TCM_REG_TSDM_IFEN 0x50018
2796 /* [RC 1] Message length mismatch (relative to last indication) at the SDM
2797 interface. */
2798 #define TCM_REG_TSDM_LENGTH_MIS 0x50164
2799 /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
2800 weight 8 (the most prioritised); 1 stands for weight 1(least
2801 prioritised); 2 stands for weight 2; tc. */
2802 #define TCM_REG_TSDM_WEIGHT 0x500c4
2803 /* [RW 1] Input usem Interface enable. If 0 - the valid input is
2804 disregarded; acknowledge output is deasserted; all other signals are
2805 treated as usual; if 1 - normal activity. */
2806 #define TCM_REG_USEM_IFEN 0x50028
2807 /* [RC 1] Message length mismatch (relative to last indication) at the In#8
2808 interface. */
2809 #define TCM_REG_USEM_LENGTH_MIS 0x50170
2810 /* [RW 21] Indirect access to the descriptor table of the XX protection
2811 mechanism. The fields are: [5:0] - length of the message; 15:6] - message
2812 pointer; 20:16] - next pointer. */
2813 #define TCM_REG_XX_DESCR_TABLE 0x50280
2814 /* [R 6] Use to read the value of XX protection Free counter. */
2815 #define TCM_REG_XX_FREE 0x50178
2816 /* [RW 6] Initial value for the credit counter; responsible for fulfilling
2817 of the Input Stage XX protection buffer by the XX protection pending
2818 messages. Max credit available - 127.Write writes the initial credit
2819 value; read returns the current value of the credit counter. Must be
2820 initialized to 19 at start-up. */
2821 #define TCM_REG_XX_INIT_CRD 0x50220
2822 /* [RW 6] Maximum link list size (messages locked) per connection in the XX
2823 protection. */
2824 #define TCM_REG_XX_MAX_LL_SZ 0x50044
2825 /* [RW 6] The maximum number of pending messages; which may be stored in XX
2826 protection. ~tcm_registers_xx_free.xx_free is read on read. */
2827 #define TCM_REG_XX_MSG_NUM 0x50224
2828 /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
2829 #define TCM_REG_XX_OVFL_EVNT_ID 0x50048
2830 /* [RW 16] Indirect access to the XX table of the XX protection mechanism.
2831 The fields are:[4:0] - tail pointer; [10:5] - Link List size; 15:11] -
2832 header pointer. */
2833 #define TCM_REG_XX_TABLE 0x50240
2834 /* [RW 4] Load value for for cfc ac credit cnt. */
2835 #define TM_REG_CFC_AC_CRDCNT_VAL 0x164208
2836 /* [RW 4] Load value for cfc cld credit cnt. */
2837 #define TM_REG_CFC_CLD_CRDCNT_VAL 0x164210
2838 /* [RW 8] Client0 context region. */
2839 #define TM_REG_CL0_CONT_REGION 0x164030
2840 /* [RW 8] Client1 context region. */
2841 #define TM_REG_CL1_CONT_REGION 0x164034
2842 /* [RW 8] Client2 context region. */
2843 #define TM_REG_CL2_CONT_REGION 0x164038
2844 /* [RW 2] Client in High priority client number. */
2845 #define TM_REG_CLIN_PRIOR0_CLIENT 0x164024
2846 /* [RW 4] Load value for clout0 cred cnt. */
2847 #define TM_REG_CLOUT_CRDCNT0_VAL 0x164220
2848 /* [RW 4] Load value for clout1 cred cnt. */
2849 #define TM_REG_CLOUT_CRDCNT1_VAL 0x164228
2850 /* [RW 4] Load value for clout2 cred cnt. */
2851 #define TM_REG_CLOUT_CRDCNT2_VAL 0x164230
2852 /* [RW 1] Enable client0 input. */
2853 #define TM_REG_EN_CL0_INPUT 0x164008
2854 /* [RW 1] Enable client1 input. */
2855 #define TM_REG_EN_CL1_INPUT 0x16400c
2856 /* [RW 1] Enable client2 input. */
2857 #define TM_REG_EN_CL2_INPUT 0x164010
2858 /* [RW 1] Enable real time counter. */
2859 #define TM_REG_EN_REAL_TIME_CNT 0x1640d8
2860 /* [RW 1] Enable for Timers state machines. */
2861 #define TM_REG_EN_TIMERS 0x164000
2862 /* [RW 4] Load value for expiration credit cnt. CFC max number of
2863 outstanding load requests for timers (expiration) context loading. */
2864 #define TM_REG_EXP_CRDCNT_VAL 0x164238
2865 /* [RW 18] Linear0 Max active cid. */
2866 #define TM_REG_LIN0_MAX_ACTIVE_CID 0x164048
2867 /* [WB 64] Linear0 phy address. */
2868 #define TM_REG_LIN0_PHY_ADDR 0x164270
2869 /* [RW 24] Linear0 array scan timeout. */
2870 #define TM_REG_LIN0_SCAN_TIME 0x16403c
2871 /* [WB 64] Linear1 phy address. */
2872 #define TM_REG_LIN1_PHY_ADDR 0x164280
2873 /* [RW 6] Linear timer set_clear fifo threshold. */
2874 #define TM_REG_LIN_SETCLR_FIFO_ALFULL_THR 0x164070
2875 /* [RW 2] Load value for pci arbiter credit cnt. */
2876 #define TM_REG_PCIARB_CRDCNT_VAL 0x164260
2877 /* [RW 1] Timer software reset - active high. */
2878 #define TM_REG_TIMER_SOFT_RST 0x164004
2879 /* [RW 20] The amount of hardware cycles for each timer tick. */
2880 #define TM_REG_TIMER_TICK_SIZE 0x16401c
2881 /* [RW 8] Timers Context region. */
2882 #define TM_REG_TM_CONTEXT_REGION 0x164044
2883 /* [RW 1] Interrupt mask register #0 read/write */
2884 #define TM_REG_TM_INT_MASK 0x1640fc
2885 /* [R 1] Interrupt register #0 read */
2886 #define TM_REG_TM_INT_STS 0x1640f0
2887 /* [RW 8] The event id for aggregated interrupt 0 */
2888 #define TSDM_REG_AGG_INT_EVENT_0 0x42038
2889 /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
2890 #define TSDM_REG_CFC_RSP_START_ADDR 0x42008
2891 /* [RW 16] The maximum value of the competion counter #0 */
2892 #define TSDM_REG_CMP_COUNTER_MAX0 0x4201c
2893 /* [RW 16] The maximum value of the competion counter #1 */
2894 #define TSDM_REG_CMP_COUNTER_MAX1 0x42020
2895 /* [RW 16] The maximum value of the competion counter #2 */
2896 #define TSDM_REG_CMP_COUNTER_MAX2 0x42024
2897 /* [RW 16] The maximum value of the competion counter #3 */
2898 #define TSDM_REG_CMP_COUNTER_MAX3 0x42028
2899 /* [RW 13] The start address in the internal RAM for the completion
2900 counters. */
2901 #define TSDM_REG_CMP_COUNTER_START_ADDR 0x4200c
2902 #define TSDM_REG_ENABLE_IN1 0x42238
2903 #define TSDM_REG_ENABLE_IN2 0x4223c
2904 #define TSDM_REG_ENABLE_OUT1 0x42240
2905 #define TSDM_REG_ENABLE_OUT2 0x42244
2906 /* [RW 4] The initial number of messages that can be sent to the pxp control
2907 interface without receiving any ACK. */
2908 #define TSDM_REG_INIT_CREDIT_PXP_CTRL 0x424bc
2909 /* [ST 32] The number of ACK after placement messages received */
2910 #define TSDM_REG_NUM_OF_ACK_AFTER_PLACE 0x4227c
2911 /* [ST 32] The number of packet end messages received from the parser */
2912 #define TSDM_REG_NUM_OF_PKT_END_MSG 0x42274
2913 /* [ST 32] The number of requests received from the pxp async if */
2914 #define TSDM_REG_NUM_OF_PXP_ASYNC_REQ 0x42278
2915 /* [ST 32] The number of commands received in queue 0 */
2916 #define TSDM_REG_NUM_OF_Q0_CMD 0x42248
2917 /* [ST 32] The number of commands received in queue 10 */
2918 #define TSDM_REG_NUM_OF_Q10_CMD 0x4226c
2919 /* [ST 32] The number of commands received in queue 11 */
2920 #define TSDM_REG_NUM_OF_Q11_CMD 0x42270
2921 /* [ST 32] The number of commands received in queue 1 */
2922 #define TSDM_REG_NUM_OF_Q1_CMD 0x4224c
2923 /* [ST 32] The number of commands received in queue 3 */
2924 #define TSDM_REG_NUM_OF_Q3_CMD 0x42250
2925 /* [ST 32] The number of commands received in queue 4 */
2926 #define TSDM_REG_NUM_OF_Q4_CMD 0x42254
2927 /* [ST 32] The number of commands received in queue 5 */
2928 #define TSDM_REG_NUM_OF_Q5_CMD 0x42258
2929 /* [ST 32] The number of commands received in queue 6 */
2930 #define TSDM_REG_NUM_OF_Q6_CMD 0x4225c
2931 /* [ST 32] The number of commands received in queue 7 */
2932 #define TSDM_REG_NUM_OF_Q7_CMD 0x42260
2933 /* [ST 32] The number of commands received in queue 8 */
2934 #define TSDM_REG_NUM_OF_Q8_CMD 0x42264
2935 /* [ST 32] The number of commands received in queue 9 */
2936 #define TSDM_REG_NUM_OF_Q9_CMD 0x42268
2937 /* [RW 13] The start address in the internal RAM for the packet end message */
2938 #define TSDM_REG_PCK_END_MSG_START_ADDR 0x42014
2939 /* [RW 13] The start address in the internal RAM for queue counters */
2940 #define TSDM_REG_Q_COUNTER_START_ADDR 0x42010
2941 /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
2942 #define TSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0x42548
2943 /* [R 1] parser fifo empty in sdm_sync block */
2944 #define TSDM_REG_SYNC_PARSER_EMPTY 0x42550
2945 /* [R 1] parser serial fifo empty in sdm_sync block */
2946 #define TSDM_REG_SYNC_SYNC_EMPTY 0x42558
2947 /* [RW 32] Tick for timer counter. Applicable only when
2948 ~tsdm_registers_timer_tick_enable.timer_tick_enable =1 */
2949 #define TSDM_REG_TIMER_TICK 0x42000
2950 /* [RW 32] Interrupt mask register #0 read/write */
2951 #define TSDM_REG_TSDM_INT_MASK_0 0x4229c
2952 #define TSDM_REG_TSDM_INT_MASK_1 0x422ac
2953 /* [RW 11] Parity mask register #0 read/write */
2954 #define TSDM_REG_TSDM_PRTY_MASK 0x422bc
2956 =======
2957 /* [R 11] Parity register #0 read */
2958 #define TSDM_REG_TSDM_PRTY_STS 0x422b0
2960 /* [RW 5] The number of time_slots in the arbitration cycle */
2961 #define TSEM_REG_ARB_CYCLE_SIZE 0x180034
2962 /* [RW 3] The source that is associated with arbitration element 0. Source
2963 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
2964 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
2965 #define TSEM_REG_ARB_ELEMENT0 0x180020
2966 /* [RW 3] The source that is associated with arbitration element 1. Source
2967 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
2968 sleeping thread with priority 1; 4- sleeping thread with priority 2.
2969 Could not be equal to register ~tsem_registers_arb_element0.arb_element0 */
2970 #define TSEM_REG_ARB_ELEMENT1 0x180024
2971 /* [RW 3] The source that is associated with arbitration element 2. Source
2972 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
2973 sleeping thread with priority 1; 4- sleeping thread with priority 2.
2974 Could not be equal to register ~tsem_registers_arb_element0.arb_element0
2975 and ~tsem_registers_arb_element1.arb_element1 */
2976 #define TSEM_REG_ARB_ELEMENT2 0x180028
2977 /* [RW 3] The source that is associated with arbitration element 3. Source
2978 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
2979 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
2980 not be equal to register ~tsem_registers_arb_element0.arb_element0 and
2981 ~tsem_registers_arb_element1.arb_element1 and
2982 ~tsem_registers_arb_element2.arb_element2 */
2983 #define TSEM_REG_ARB_ELEMENT3 0x18002c
2984 /* [RW 3] The source that is associated with arbitration element 4. Source
2985 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
2986 sleeping thread with priority 1; 4- sleeping thread with priority 2.
2987 Could not be equal to register ~tsem_registers_arb_element0.arb_element0
2988 and ~tsem_registers_arb_element1.arb_element1 and
2989 ~tsem_registers_arb_element2.arb_element2 and
2990 ~tsem_registers_arb_element3.arb_element3 */
2991 #define TSEM_REG_ARB_ELEMENT4 0x180030
2992 #define TSEM_REG_ENABLE_IN 0x1800a4
2993 #define TSEM_REG_ENABLE_OUT 0x1800a8
2994 /* [RW 32] This address space contains all registers and memories that are
2995 placed in SEM_FAST block. The SEM_FAST registers are described in
2996 appendix B. In order to access the SEM_FAST registers the base address
2997 TSEM_REGISTERS_FAST_MEMORY (Offset: 0x1a0000) should be added to each
2998 SEM_FAST register offset. */
2999 #define TSEM_REG_FAST_MEMORY 0x1a0000
3000 /* [RW 1] Disables input messages from FIC0 May be updated during run_time
3001 by the microcode */
3002 #define TSEM_REG_FIC0_DISABLE 0x180224
3003 /* [RW 1] Disables input messages from FIC1 May be updated during run_time
3004 by the microcode */
3005 #define TSEM_REG_FIC1_DISABLE 0x180234
3006 /* [RW 15] Interrupt table Read and write access to it is not possible in
3007 the middle of the work */
3008 #define TSEM_REG_INT_TABLE 0x180400
3009 /* [ST 24] Statistics register. The number of messages that entered through
3010 FIC0 */
3011 #define TSEM_REG_MSG_NUM_FIC0 0x180000
3012 /* [ST 24] Statistics register. The number of messages that entered through
3013 FIC1 */
3014 #define TSEM_REG_MSG_NUM_FIC1 0x180004
3015 /* [ST 24] Statistics register. The number of messages that were sent to
3016 FOC0 */
3017 #define TSEM_REG_MSG_NUM_FOC0 0x180008
3018 /* [ST 24] Statistics register. The number of messages that were sent to
3019 FOC1 */
3020 #define TSEM_REG_MSG_NUM_FOC1 0x18000c
3021 /* [ST 24] Statistics register. The number of messages that were sent to
3022 FOC2 */
3023 #define TSEM_REG_MSG_NUM_FOC2 0x180010
3024 /* [ST 24] Statistics register. The number of messages that were sent to
3025 FOC3 */
3026 #define TSEM_REG_MSG_NUM_FOC3 0x180014
3027 /* [RW 1] Disables input messages from the passive buffer May be updated
3028 during run_time by the microcode */
3029 #define TSEM_REG_PAS_DISABLE 0x18024c
3030 /* [WB 128] Debug only. Passive buffer memory */
3031 #define TSEM_REG_PASSIVE_BUFFER 0x181000
3032 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
3033 #define TSEM_REG_PRAM 0x1c0000
3034 /* [R 8] Valid sleeping threads indication have bit per thread */
3035 #define TSEM_REG_SLEEP_THREADS_VALID 0x18026c
3036 /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
3037 #define TSEM_REG_SLOW_EXT_STORE_EMPTY 0x1802a0
3038 /* [RW 8] List of free threads . There is a bit per thread. */
3039 #define TSEM_REG_THREADS_LIST 0x1802e4
3040 /* [RW 3] The arbitration scheme of time_slot 0 */
3041 #define TSEM_REG_TS_0_AS 0x180038
3042 /* [RW 3] The arbitration scheme of time_slot 10 */
3043 #define TSEM_REG_TS_10_AS 0x180060
3044 /* [RW 3] The arbitration scheme of time_slot 11 */
3045 #define TSEM_REG_TS_11_AS 0x180064
3046 /* [RW 3] The arbitration scheme of time_slot 12 */
3047 #define TSEM_REG_TS_12_AS 0x180068
3048 /* [RW 3] The arbitration scheme of time_slot 13 */
3049 #define TSEM_REG_TS_13_AS 0x18006c
3050 /* [RW 3] The arbitration scheme of time_slot 14 */
3051 #define TSEM_REG_TS_14_AS 0x180070
3052 /* [RW 3] The arbitration scheme of time_slot 15 */
3053 #define TSEM_REG_TS_15_AS 0x180074
3054 /* [RW 3] The arbitration scheme of time_slot 16 */
3055 #define TSEM_REG_TS_16_AS 0x180078
3056 /* [RW 3] The arbitration scheme of time_slot 17 */
3057 #define TSEM_REG_TS_17_AS 0x18007c
3058 /* [RW 3] The arbitration scheme of time_slot 18 */
3059 #define TSEM_REG_TS_18_AS 0x180080
3060 /* [RW 3] The arbitration scheme of time_slot 1 */
3061 #define TSEM_REG_TS_1_AS 0x18003c
3062 /* [RW 3] The arbitration scheme of time_slot 2 */
3063 #define TSEM_REG_TS_2_AS 0x180040
3064 /* [RW 3] The arbitration scheme of time_slot 3 */
3065 #define TSEM_REG_TS_3_AS 0x180044
3066 /* [RW 3] The arbitration scheme of time_slot 4 */
3067 #define TSEM_REG_TS_4_AS 0x180048
3068 /* [RW 3] The arbitration scheme of time_slot 5 */
3069 #define TSEM_REG_TS_5_AS 0x18004c
3070 /* [RW 3] The arbitration scheme of time_slot 6 */
3071 #define TSEM_REG_TS_6_AS 0x180050
3072 /* [RW 3] The arbitration scheme of time_slot 7 */
3073 #define TSEM_REG_TS_7_AS 0x180054
3074 /* [RW 3] The arbitration scheme of time_slot 8 */
3075 #define TSEM_REG_TS_8_AS 0x180058
3076 /* [RW 3] The arbitration scheme of time_slot 9 */
3077 #define TSEM_REG_TS_9_AS 0x18005c
3078 /* [RW 32] Interrupt mask register #0 read/write */
3079 #define TSEM_REG_TSEM_INT_MASK_0 0x180100
3080 #define TSEM_REG_TSEM_INT_MASK_1 0x180110
3081 /* [RW 32] Parity mask register #0 read/write */
3082 #define TSEM_REG_TSEM_PRTY_MASK_0 0x180120
3083 #define TSEM_REG_TSEM_PRTY_MASK_1 0x180130
3085 =======
3086 /* [R 32] Parity register #0 read */
3087 #define TSEM_REG_TSEM_PRTY_STS_0 0x180114
3088 #define TSEM_REG_TSEM_PRTY_STS_1 0x180124
3090 /* [R 5] Used to read the XX protection CAM occupancy counter. */
3091 #define UCM_REG_CAM_OCCUP 0xe0170
3092 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is
3093 disregarded; valid output is deasserted; all other signals are treated as
3094 usual; if 1 - normal activity. */
3095 #define UCM_REG_CDU_AG_RD_IFEN 0xe0038
3096 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
3097 are disregarded; all other signals are treated as usual; if 1 - normal
3098 activity. */
3099 #define UCM_REG_CDU_AG_WR_IFEN 0xe0034
3100 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
3101 disregarded; valid output is deasserted; all other signals are treated as
3102 usual; if 1 - normal activity. */
3103 #define UCM_REG_CDU_SM_RD_IFEN 0xe0040
3104 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
3105 input is disregarded; all other signals are treated as usual; if 1 -
3106 normal activity. */
3107 #define UCM_REG_CDU_SM_WR_IFEN 0xe003c
3108 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
3109 the initial credit value; read returns the current value of the credit
3110 counter. Must be initialized to 1 at start-up. */
3111 #define UCM_REG_CFC_INIT_CRD 0xe0204
3112 /* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for
3113 weight 8 (the most prioritised); 1 stands for weight 1(least
3114 prioritised); 2 stands for weight 2; tc. */
3115 #define UCM_REG_CP_WEIGHT 0xe00c4
3116 /* [RW 1] Input csem Interface enable. If 0 - the valid input is
3117 disregarded; acknowledge output is deasserted; all other signals are
3118 treated as usual; if 1 - normal activity. */
3119 #define UCM_REG_CSEM_IFEN 0xe0028
3120 /* [RC 1] Set when the message length mismatch (relative to last indication)
3121 at the csem interface is detected. */
3122 #define UCM_REG_CSEM_LENGTH_MIS 0xe0160
3123 /* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for
3124 weight 8 (the most prioritised); 1 stands for weight 1(least
3125 prioritised); 2 stands for weight 2; tc. */
3126 #define UCM_REG_CSEM_WEIGHT 0xe00b8
3127 /* [RW 1] Input dorq Interface enable. If 0 - the valid input is
3128 disregarded; acknowledge output is deasserted; all other signals are
3129 treated as usual; if 1 - normal activity. */
3130 #define UCM_REG_DORQ_IFEN 0xe0030
3131 /* [RC 1] Set when the message length mismatch (relative to last indication)
3132 at the dorq interface is detected. */
3133 #define UCM_REG_DORQ_LENGTH_MIS 0xe0168
3134 /* [RW 8] The Event ID in case ErrorFlg input message bit is set. */
3135 #define UCM_REG_ERR_EVNT_ID 0xe00a4
3136 /* [RW 28] The CM erroneous header for QM and Timers formatting. */
3137 #define UCM_REG_ERR_UCM_HDR 0xe00a0
3138 /* [RW 8] The Event ID for Timers expiration. */
3139 #define UCM_REG_EXPR_EVNT_ID 0xe00a8
3140 /* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
3141 writes the initial credit value; read returns the current value of the
3142 credit counter. Must be initialized to 64 at start-up. */
3143 #define UCM_REG_FIC0_INIT_CRD 0xe020c
3144 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
3145 writes the initial credit value; read returns the current value of the
3146 credit counter. Must be initialized to 64 at start-up. */
3147 #define UCM_REG_FIC1_INIT_CRD 0xe0210
3148 /* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
3149 - strict priority defined by ~ucm_registers_gr_ag_pr.gr_ag_pr;
3150 ~ucm_registers_gr_ld0_pr.gr_ld0_pr and
3151 ~ucm_registers_gr_ld1_pr.gr_ld1_pr. */
3152 #define UCM_REG_GR_ARB_TYPE 0xe0144
3153 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
3154 highest priority is 3. It is supposed that the Store channel group is
3155 compliment to the others. */
3156 #define UCM_REG_GR_LD0_PR 0xe014c
3157 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
3158 highest priority is 3. It is supposed that the Store channel group is
3159 compliment to the others. */
3160 #define UCM_REG_GR_LD1_PR 0xe0150
3161 /* [RW 2] The queue index for invalidate counter flag decision. */
3162 #define UCM_REG_INV_CFLG_Q 0xe00e4
3163 /* [RW 5] The number of double REG-pairs; loaded from the STORM context and
3164 sent to STORM; for a specific connection type. the double REG-pairs are
3165 used in order to align to STORM context row size of 128 bits. The offset
3166 of these data in the STORM context is always 0. Index _i stands for the
3167 connection type (one of 16). */
3168 #define UCM_REG_N_SM_CTX_LD_0 0xe0054
3169 #define UCM_REG_N_SM_CTX_LD_1 0xe0058
3170 #define UCM_REG_N_SM_CTX_LD_10 0xe007c
3171 #define UCM_REG_N_SM_CTX_LD_11 0xe0080
3172 #define UCM_REG_N_SM_CTX_LD_12 0xe0084
3173 #define UCM_REG_N_SM_CTX_LD_13 0xe0088
3174 #define UCM_REG_N_SM_CTX_LD_14 0xe008c
3175 #define UCM_REG_N_SM_CTX_LD_15 0xe0090
3176 #define UCM_REG_N_SM_CTX_LD_2 0xe005c
3177 #define UCM_REG_N_SM_CTX_LD_3 0xe0060
3178 #define UCM_REG_N_SM_CTX_LD_4 0xe0064
3179 /* [RW 6] The physical queue number 0 per port index (CID[23]) */
3180 #define UCM_REG_PHYS_QNUM0_0 0xe0110
3181 #define UCM_REG_PHYS_QNUM0_1 0xe0114
3182 /* [RW 6] The physical queue number 1 per port index (CID[23]) */
3183 #define UCM_REG_PHYS_QNUM1_0 0xe0118
3184 #define UCM_REG_PHYS_QNUM1_1 0xe011c
3185 /* [RW 8] The Event ID for Timers formatting in case of stop done. */
3186 #define UCM_REG_STOP_EVNT_ID 0xe00ac
3187 /* [RC 1] Set when the message length mismatch (relative to last indication)
3188 at the STORM interface is detected. */
3189 #define UCM_REG_STORM_LENGTH_MIS 0xe0154
3190 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
3191 disregarded; acknowledge output is deasserted; all other signals are
3192 treated as usual; if 1 - normal activity. */
3193 #define UCM_REG_STORM_UCM_IFEN 0xe0010
3194 /* [RW 4] Timers output initial credit. Max credit available - 15.Write
3195 writes the initial credit value; read returns the current value of the
3196 credit counter. Must be initialized to 4 at start-up. */
3197 #define UCM_REG_TM_INIT_CRD 0xe021c
3198 /* [RW 28] The CM header for Timers expiration command. */
3199 #define UCM_REG_TM_UCM_HDR 0xe009c
3200 /* [RW 1] Timers - CM Interface enable. If 0 - the valid input is
3201 disregarded; acknowledge output is deasserted; all other signals are
3202 treated as usual; if 1 - normal activity. */
3203 #define UCM_REG_TM_UCM_IFEN 0xe001c
3204 /* [RW 1] Input tsem Interface enable. If 0 - the valid input is
3205 disregarded; acknowledge output is deasserted; all other signals are
3206 treated as usual; if 1 - normal activity. */
3207 #define UCM_REG_TSEM_IFEN 0xe0024
3208 /* [RC 1] Set when the message length mismatch (relative to last indication)
3209 at the tsem interface is detected. */
3210 #define UCM_REG_TSEM_LENGTH_MIS 0xe015c
3211 /* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for
3212 weight 8 (the most prioritised); 1 stands for weight 1(least
3213 prioritised); 2 stands for weight 2; tc. */
3214 #define UCM_REG_TSEM_WEIGHT 0xe00b4
3215 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
3216 acknowledge output is deasserted; all other signals are treated as usual;
3217 if 1 - normal activity. */
3218 #define UCM_REG_UCM_CFC_IFEN 0xe0044
3219 /* [RW 11] Interrupt mask register #0 read/write */
3220 #define UCM_REG_UCM_INT_MASK 0xe01d4
3221 /* [R 11] Interrupt register #0 read */
3222 #define UCM_REG_UCM_INT_STS 0xe01c8
3223 /* [RW 2] The size of AG context region 0 in REG-pairs. Designates the MS
3224 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
3225 Is used to determine the number of the AG context REG-pairs written back;
3226 when the Reg1WbFlg isn't set. */
3227 #define UCM_REG_UCM_REG0_SZ 0xe00dc
3228 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
3229 disregarded; valid is deasserted; all other signals are treated as usual;
3230 if 1 - normal activity. */
3231 #define UCM_REG_UCM_STORM0_IFEN 0xe0004
3232 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
3233 disregarded; valid is deasserted; all other signals are treated as usual;
3234 if 1 - normal activity. */
3235 #define UCM_REG_UCM_STORM1_IFEN 0xe0008
3236 /* [RW 1] CM - Timers Interface enable. If 0 - the valid input is
3237 disregarded; acknowledge output is deasserted; all other signals are
3238 treated as usual; if 1 - normal activity. */
3239 #define UCM_REG_UCM_TM_IFEN 0xe0020
3240 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
3241 disregarded; valid is deasserted; all other signals are treated as usual;
3242 if 1 - normal activity. */
3243 #define UCM_REG_UCM_UQM_IFEN 0xe000c
3244 /* [RW 1] If set the Q index; received from the QM is inserted to event ID. */
3245 #define UCM_REG_UCM_UQM_USE_Q 0xe00d8
3246 /* [RW 6] QM output initial credit. Max credit available - 32.Write writes
3247 the initial credit value; read returns the current value of the credit
3248 counter. Must be initialized to 32 at start-up. */
3249 #define UCM_REG_UQM_INIT_CRD 0xe0220
3250 /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
3251 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
3252 prioritised); 2 stands for weight 2; tc. */
3253 #define UCM_REG_UQM_P_WEIGHT 0xe00cc
3254 /* [RW 28] The CM header value for QM request (primary). */
3255 #define UCM_REG_UQM_UCM_HDR_P 0xe0094
3256 /* [RW 28] The CM header value for QM request (secondary). */
3257 #define UCM_REG_UQM_UCM_HDR_S 0xe0098
3258 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
3259 acknowledge output is deasserted; all other signals are treated as usual;
3260 if 1 - normal activity. */
3261 #define UCM_REG_UQM_UCM_IFEN 0xe0014
3262 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
3263 acknowledge output is deasserted; all other signals are treated as usual;
3264 if 1 - normal activity. */
3265 #define UCM_REG_USDM_IFEN 0xe0018
3266 /* [RC 1] Set when the message length mismatch (relative to last indication)
3267 at the SDM interface is detected. */
3268 #define UCM_REG_USDM_LENGTH_MIS 0xe0158
3269 /* [RW 1] Input xsem Interface enable. If 0 - the valid input is
3270 disregarded; acknowledge output is deasserted; all other signals are
3271 treated as usual; if 1 - normal activity. */
3272 #define UCM_REG_XSEM_IFEN 0xe002c
3273 /* [RC 1] Set when the message length mismatch (relative to last indication)
3274 at the xsem interface isdetected. */
3275 #define UCM_REG_XSEM_LENGTH_MIS 0xe0164
3276 /* [RW 20] Indirect access to the descriptor table of the XX protection
3277 mechanism. The fields are:[5:0] - message length; 14:6] - message
3278 pointer; 19:15] - next pointer. */
3279 #define UCM_REG_XX_DESCR_TABLE 0xe0280
3280 /* [R 6] Use to read the XX protection Free counter. */
3281 #define UCM_REG_XX_FREE 0xe016c
3282 /* [RW 6] Initial value for the credit counter; responsible for fulfilling
3283 of the Input Stage XX protection buffer by the XX protection pending
3284 messages. Write writes the initial credit value; read returns the current
3285 value of the credit counter. Must be initialized to 12 at start-up. */
3286 #define UCM_REG_XX_INIT_CRD 0xe0224
3287 /* [RW 6] The maximum number of pending messages; which may be stored in XX
3288 protection. ~ucm_registers_xx_free.xx_free read on read. */
3289 #define UCM_REG_XX_MSG_NUM 0xe0228
3290 /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
3291 #define UCM_REG_XX_OVFL_EVNT_ID 0xe004c
3292 /* [RW 16] Indirect access to the XX table of the XX protection mechanism.
3293 The fields are: [4:0] - tail pointer; 10:5] - Link List size; 15:11] -
3294 header pointer. */
3295 #define UCM_REG_XX_TABLE 0xe0300
3296 /* [RW 8] The event id for aggregated interrupt 0 */
3297 #define USDM_REG_AGG_INT_EVENT_0 0xc4038
3298 #define USDM_REG_AGG_INT_EVENT_1 0xc403c
3299 #define USDM_REG_AGG_INT_EVENT_10 0xc4060
3300 #define USDM_REG_AGG_INT_EVENT_11 0xc4064
3301 #define USDM_REG_AGG_INT_EVENT_12 0xc4068
3302 #define USDM_REG_AGG_INT_EVENT_13 0xc406c
3303 #define USDM_REG_AGG_INT_EVENT_14 0xc4070
3304 #define USDM_REG_AGG_INT_EVENT_15 0xc4074
3305 #define USDM_REG_AGG_INT_EVENT_16 0xc4078
3306 #define USDM_REG_AGG_INT_EVENT_17 0xc407c
3307 #define USDM_REG_AGG_INT_EVENT_18 0xc4080
3308 #define USDM_REG_AGG_INT_EVENT_19 0xc4084
3309 /* [RW 1] For each aggregated interrupt index whether the mode is normal (0)
3310 or auto-mask-mode (1) */
3311 #define USDM_REG_AGG_INT_MODE_0 0xc41b8
3312 #define USDM_REG_AGG_INT_MODE_1 0xc41bc
3313 #define USDM_REG_AGG_INT_MODE_10 0xc41e0
3314 #define USDM_REG_AGG_INT_MODE_11 0xc41e4
3315 #define USDM_REG_AGG_INT_MODE_12 0xc41e8
3316 #define USDM_REG_AGG_INT_MODE_13 0xc41ec
3317 #define USDM_REG_AGG_INT_MODE_14 0xc41f0
3318 #define USDM_REG_AGG_INT_MODE_15 0xc41f4
3319 #define USDM_REG_AGG_INT_MODE_16 0xc41f8
3320 #define USDM_REG_AGG_INT_MODE_17 0xc41fc
3321 #define USDM_REG_AGG_INT_MODE_18 0xc4200
3322 #define USDM_REG_AGG_INT_MODE_19 0xc4204
3323 /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
3324 #define USDM_REG_CFC_RSP_START_ADDR 0xc4008
3325 /* [RW 16] The maximum value of the competion counter #0 */
3326 #define USDM_REG_CMP_COUNTER_MAX0 0xc401c
3327 /* [RW 16] The maximum value of the competion counter #1 */
3328 #define USDM_REG_CMP_COUNTER_MAX1 0xc4020
3329 /* [RW 16] The maximum value of the competion counter #2 */
3330 #define USDM_REG_CMP_COUNTER_MAX2 0xc4024
3331 /* [RW 16] The maximum value of the competion counter #3 */
3332 #define USDM_REG_CMP_COUNTER_MAX3 0xc4028
3333 /* [RW 13] The start address in the internal RAM for the completion
3334 counters. */
3335 #define USDM_REG_CMP_COUNTER_START_ADDR 0xc400c
3336 #define USDM_REG_ENABLE_IN1 0xc4238
3337 #define USDM_REG_ENABLE_IN2 0xc423c
3338 #define USDM_REG_ENABLE_OUT1 0xc4240
3339 #define USDM_REG_ENABLE_OUT2 0xc4244
3340 /* [RW 4] The initial number of messages that can be sent to the pxp control
3341 interface without receiving any ACK. */
3342 #define USDM_REG_INIT_CREDIT_PXP_CTRL 0xc44c0
3343 /* [ST 32] The number of ACK after placement messages received */
3344 #define USDM_REG_NUM_OF_ACK_AFTER_PLACE 0xc4280
3345 /* [ST 32] The number of packet end messages received from the parser */
3346 #define USDM_REG_NUM_OF_PKT_END_MSG 0xc4278
3347 /* [ST 32] The number of requests received from the pxp async if */
3348 #define USDM_REG_NUM_OF_PXP_ASYNC_REQ 0xc427c
3349 /* [ST 32] The number of commands received in queue 0 */
3350 #define USDM_REG_NUM_OF_Q0_CMD 0xc4248
3351 /* [ST 32] The number of commands received in queue 10 */
3352 #define USDM_REG_NUM_OF_Q10_CMD 0xc4270
3353 /* [ST 32] The number of commands received in queue 11 */
3354 #define USDM_REG_NUM_OF_Q11_CMD 0xc4274
3355 /* [ST 32] The number of commands received in queue 1 */
3356 #define USDM_REG_NUM_OF_Q1_CMD 0xc424c
3357 /* [ST 32] The number of commands received in queue 2 */
3358 #define USDM_REG_NUM_OF_Q2_CMD 0xc4250
3359 /* [ST 32] The number of commands received in queue 3 */
3360 #define USDM_REG_NUM_OF_Q3_CMD 0xc4254
3361 /* [ST 32] The number of commands received in queue 4 */
3362 #define USDM_REG_NUM_OF_Q4_CMD 0xc4258
3363 /* [ST 32] The number of commands received in queue 5 */
3364 #define USDM_REG_NUM_OF_Q5_CMD 0xc425c
3365 /* [ST 32] The number of commands received in queue 6 */
3366 #define USDM_REG_NUM_OF_Q6_CMD 0xc4260
3367 /* [ST 32] The number of commands received in queue 7 */
3368 #define USDM_REG_NUM_OF_Q7_CMD 0xc4264
3369 /* [ST 32] The number of commands received in queue 8 */
3370 #define USDM_REG_NUM_OF_Q8_CMD 0xc4268
3371 /* [ST 32] The number of commands received in queue 9 */
3372 #define USDM_REG_NUM_OF_Q9_CMD 0xc426c
3373 /* [RW 13] The start address in the internal RAM for the packet end message */
3374 #define USDM_REG_PCK_END_MSG_START_ADDR 0xc4014
3375 /* [RW 13] The start address in the internal RAM for queue counters */
3376 #define USDM_REG_Q_COUNTER_START_ADDR 0xc4010
3377 /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
3378 #define USDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0xc4550
3379 /* [R 1] parser fifo empty in sdm_sync block */
3380 #define USDM_REG_SYNC_PARSER_EMPTY 0xc4558
3381 /* [R 1] parser serial fifo empty in sdm_sync block */
3382 #define USDM_REG_SYNC_SYNC_EMPTY 0xc4560
3383 /* [RW 32] Tick for timer counter. Applicable only when
3384 ~usdm_registers_timer_tick_enable.timer_tick_enable =1 */
3385 #define USDM_REG_TIMER_TICK 0xc4000
3386 /* [RW 32] Interrupt mask register #0 read/write */
3387 #define USDM_REG_USDM_INT_MASK_0 0xc42a0
3388 #define USDM_REG_USDM_INT_MASK_1 0xc42b0
3389 /* [RW 11] Parity mask register #0 read/write */
3390 #define USDM_REG_USDM_PRTY_MASK 0xc42c0
3392 =======
3393 /* [R 11] Parity register #0 read */
3394 #define USDM_REG_USDM_PRTY_STS 0xc42b4
3396 /* [RW 5] The number of time_slots in the arbitration cycle */
3397 #define USEM_REG_ARB_CYCLE_SIZE 0x300034
3398 /* [RW 3] The source that is associated with arbitration element 0. Source
3399 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3400 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
3401 #define USEM_REG_ARB_ELEMENT0 0x300020
3402 /* [RW 3] The source that is associated with arbitration element 1. Source
3403 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3404 sleeping thread with priority 1; 4- sleeping thread with priority 2.
3405 Could not be equal to register ~usem_registers_arb_element0.arb_element0 */
3406 #define USEM_REG_ARB_ELEMENT1 0x300024
3407 /* [RW 3] The source that is associated with arbitration element 2. Source
3408 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3409 sleeping thread with priority 1; 4- sleeping thread with priority 2.
3410 Could not be equal to register ~usem_registers_arb_element0.arb_element0
3411 and ~usem_registers_arb_element1.arb_element1 */
3412 #define USEM_REG_ARB_ELEMENT2 0x300028
3413 /* [RW 3] The source that is associated with arbitration element 3. Source
3414 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3415 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
3416 not be equal to register ~usem_registers_arb_element0.arb_element0 and
3417 ~usem_registers_arb_element1.arb_element1 and
3418 ~usem_registers_arb_element2.arb_element2 */
3419 #define USEM_REG_ARB_ELEMENT3 0x30002c
3420 /* [RW 3] The source that is associated with arbitration element 4. Source
3421 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3422 sleeping thread with priority 1; 4- sleeping thread with priority 2.
3423 Could not be equal to register ~usem_registers_arb_element0.arb_element0
3424 and ~usem_registers_arb_element1.arb_element1 and
3425 ~usem_registers_arb_element2.arb_element2 and
3426 ~usem_registers_arb_element3.arb_element3 */
3427 #define USEM_REG_ARB_ELEMENT4 0x300030
3428 #define USEM_REG_ENABLE_IN 0x3000a4
3429 #define USEM_REG_ENABLE_OUT 0x3000a8
3430 /* [RW 32] This address space contains all registers and memories that are
3431 placed in SEM_FAST block. The SEM_FAST registers are described in
3432 appendix B. In order to access the SEM_FAST registers... the base address
3433 USEM_REGISTERS_FAST_MEMORY (Offset: 0x320000) should be added to each
3434 SEM_FAST register offset. */
3435 #define USEM_REG_FAST_MEMORY 0x320000
3436 /* [RW 1] Disables input messages from FIC0 May be updated during run_time
3437 by the microcode */
3438 #define USEM_REG_FIC0_DISABLE 0x300224
3439 /* [RW 1] Disables input messages from FIC1 May be updated during run_time
3440 by the microcode */
3441 #define USEM_REG_FIC1_DISABLE 0x300234
3442 /* [RW 15] Interrupt table Read and write access to it is not possible in
3443 the middle of the work */
3444 #define USEM_REG_INT_TABLE 0x300400
3445 /* [ST 24] Statistics register. The number of messages that entered through
3446 FIC0 */
3447 #define USEM_REG_MSG_NUM_FIC0 0x300000
3448 /* [ST 24] Statistics register. The number of messages that entered through
3449 FIC1 */
3450 #define USEM_REG_MSG_NUM_FIC1 0x300004
3451 /* [ST 24] Statistics register. The number of messages that were sent to
3452 FOC0 */
3453 #define USEM_REG_MSG_NUM_FOC0 0x300008
3454 /* [ST 24] Statistics register. The number of messages that were sent to
3455 FOC1 */
3456 #define USEM_REG_MSG_NUM_FOC1 0x30000c
3457 /* [ST 24] Statistics register. The number of messages that were sent to
3458 FOC2 */
3459 #define USEM_REG_MSG_NUM_FOC2 0x300010
3460 /* [ST 24] Statistics register. The number of messages that were sent to
3461 FOC3 */
3462 #define USEM_REG_MSG_NUM_FOC3 0x300014
3463 /* [RW 1] Disables input messages from the passive buffer May be updated
3464 during run_time by the microcode */
3465 #define USEM_REG_PAS_DISABLE 0x30024c
3466 /* [WB 128] Debug only. Passive buffer memory */
3467 #define USEM_REG_PASSIVE_BUFFER 0x302000
3468 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
3469 #define USEM_REG_PRAM 0x340000
3470 /* [R 16] Valid sleeping threads indication have bit per thread */
3471 #define USEM_REG_SLEEP_THREADS_VALID 0x30026c
3472 /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
3473 #define USEM_REG_SLOW_EXT_STORE_EMPTY 0x3002a0
3474 /* [RW 16] List of free threads . There is a bit per thread. */
3475 #define USEM_REG_THREADS_LIST 0x3002e4
3476 /* [RW 3] The arbitration scheme of time_slot 0 */
3477 #define USEM_REG_TS_0_AS 0x300038
3478 /* [RW 3] The arbitration scheme of time_slot 10 */
3479 #define USEM_REG_TS_10_AS 0x300060
3480 /* [RW 3] The arbitration scheme of time_slot 11 */
3481 #define USEM_REG_TS_11_AS 0x300064
3482 /* [RW 3] The arbitration scheme of time_slot 12 */
3483 #define USEM_REG_TS_12_AS 0x300068
3484 /* [RW 3] The arbitration scheme of time_slot 13 */
3485 #define USEM_REG_TS_13_AS 0x30006c
3486 /* [RW 3] The arbitration scheme of time_slot 14 */
3487 #define USEM_REG_TS_14_AS 0x300070
3488 /* [RW 3] The arbitration scheme of time_slot 15 */
3489 #define USEM_REG_TS_15_AS 0x300074
3490 /* [RW 3] The arbitration scheme of time_slot 16 */
3491 #define USEM_REG_TS_16_AS 0x300078
3492 /* [RW 3] The arbitration scheme of time_slot 17 */
3493 #define USEM_REG_TS_17_AS 0x30007c
3494 /* [RW 3] The arbitration scheme of time_slot 18 */
3495 #define USEM_REG_TS_18_AS 0x300080
3496 /* [RW 3] The arbitration scheme of time_slot 1 */
3497 #define USEM_REG_TS_1_AS 0x30003c
3498 /* [RW 3] The arbitration scheme of time_slot 2 */
3499 #define USEM_REG_TS_2_AS 0x300040
3500 /* [RW 3] The arbitration scheme of time_slot 3 */
3501 #define USEM_REG_TS_3_AS 0x300044
3502 /* [RW 3] The arbitration scheme of time_slot 4 */
3503 #define USEM_REG_TS_4_AS 0x300048
3504 /* [RW 3] The arbitration scheme of time_slot 5 */
3505 #define USEM_REG_TS_5_AS 0x30004c
3506 /* [RW 3] The arbitration scheme of time_slot 6 */
3507 #define USEM_REG_TS_6_AS 0x300050
3508 /* [RW 3] The arbitration scheme of time_slot 7 */
3509 #define USEM_REG_TS_7_AS 0x300054
3510 /* [RW 3] The arbitration scheme of time_slot 8 */
3511 #define USEM_REG_TS_8_AS 0x300058
3512 /* [RW 3] The arbitration scheme of time_slot 9 */
3513 #define USEM_REG_TS_9_AS 0x30005c
3514 /* [RW 32] Interrupt mask register #0 read/write */
3515 #define USEM_REG_USEM_INT_MASK_0 0x300110
3516 #define USEM_REG_USEM_INT_MASK_1 0x300120
3517 /* [RW 32] Parity mask register #0 read/write */
3518 #define USEM_REG_USEM_PRTY_MASK_0 0x300130
3519 #define USEM_REG_USEM_PRTY_MASK_1 0x300140
3521 =======
3522 /* [R 32] Parity register #0 read */
3523 #define USEM_REG_USEM_PRTY_STS_0 0x300124
3524 #define USEM_REG_USEM_PRTY_STS_1 0x300134
3526 /* [RW 2] The queue index for registration on Aux1 counter flag. */
3527 #define XCM_REG_AUX1_Q 0x20134
3528 /* [RW 2] Per each decision rule the queue index to register to. */
3529 #define XCM_REG_AUX_CNT_FLG_Q_19 0x201b0
3530 /* [R 5] Used to read the XX protection CAM occupancy counter. */
3531 #define XCM_REG_CAM_OCCUP 0x20244
3532 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is
3533 disregarded; valid output is deasserted; all other signals are treated as
3534 usual; if 1 - normal activity. */
3535 #define XCM_REG_CDU_AG_RD_IFEN 0x20044
3536 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
3537 are disregarded; all other signals are treated as usual; if 1 - normal
3538 activity. */
3539 #define XCM_REG_CDU_AG_WR_IFEN 0x20040
3540 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
3541 disregarded; valid output is deasserted; all other signals are treated as
3542 usual; if 1 - normal activity. */
3543 #define XCM_REG_CDU_SM_RD_IFEN 0x2004c
3544 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
3545 input is disregarded; all other signals are treated as usual; if 1 -
3546 normal activity. */
3547 #define XCM_REG_CDU_SM_WR_IFEN 0x20048
3548 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
3549 the initial credit value; read returns the current value of the credit
3550 counter. Must be initialized to 1 at start-up. */
3551 #define XCM_REG_CFC_INIT_CRD 0x20404
3552 /* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for
3553 weight 8 (the most prioritised); 1 stands for weight 1(least
3554 prioritised); 2 stands for weight 2; tc. */
3555 #define XCM_REG_CP_WEIGHT 0x200dc
3556 /* [RW 1] Input csem Interface enable. If 0 - the valid input is
3557 disregarded; acknowledge output is deasserted; all other signals are
3558 treated as usual; if 1 - normal activity. */
3559 #define XCM_REG_CSEM_IFEN 0x20028
3560 /* [RC 1] Set at message length mismatch (relative to last indication) at
3561 the csem interface. */
3562 #define XCM_REG_CSEM_LENGTH_MIS 0x20228
3563 /* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for
3564 weight 8 (the most prioritised); 1 stands for weight 1(least
3565 prioritised); 2 stands for weight 2; tc. */
3566 #define XCM_REG_CSEM_WEIGHT 0x200c4
3567 /* [RW 1] Input dorq Interface enable. If 0 - the valid input is
3568 disregarded; acknowledge output is deasserted; all other signals are
3569 treated as usual; if 1 - normal activity. */
3570 #define XCM_REG_DORQ_IFEN 0x20030
3571 /* [RC 1] Set at message length mismatch (relative to last indication) at
3572 the dorq interface. */
3573 #define XCM_REG_DORQ_LENGTH_MIS 0x20230
3574 /* [RW 8] The Event ID in case the ErrorFlg input message bit is set. */
3575 #define XCM_REG_ERR_EVNT_ID 0x200b0
3576 /* [RW 28] The CM erroneous header for QM and Timers formatting. */
3577 #define XCM_REG_ERR_XCM_HDR 0x200ac
3578 /* [RW 8] The Event ID for Timers expiration. */
3579 #define XCM_REG_EXPR_EVNT_ID 0x200b4
3580 /* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
3581 writes the initial credit value; read returns the current value of the
3582 credit counter. Must be initialized to 64 at start-up. */
3583 #define XCM_REG_FIC0_INIT_CRD 0x2040c
3584 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
3585 writes the initial credit value; read returns the current value of the
3586 credit counter. Must be initialized to 64 at start-up. */
3587 #define XCM_REG_FIC1_INIT_CRD 0x20410
3588 /* [RW 8] The maximum delayed ACK counter value.Must be at least 2. Per port
3589 value. */
3590 #define XCM_REG_GLB_DEL_ACK_MAX_CNT_0 0x20118
3591 #define XCM_REG_GLB_DEL_ACK_MAX_CNT_1 0x2011c
3592 /* [RW 28] The delayed ACK timeout in ticks. Per port value. */
3593 #define XCM_REG_GLB_DEL_ACK_TMR_VAL_0 0x20108
3594 #define XCM_REG_GLB_DEL_ACK_TMR_VAL_1 0x2010c
3595 /* [RW 1] Arbitratiojn between Input Arbiter groups: 0 - fair Round-Robin; 1
3596 - strict priority defined by ~xcm_registers_gr_ag_pr.gr_ag_pr;
3597 ~xcm_registers_gr_ld0_pr.gr_ld0_pr and
3598 ~xcm_registers_gr_ld1_pr.gr_ld1_pr. */
3599 #define XCM_REG_GR_ARB_TYPE 0x2020c
3600 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
3601 highest priority is 3. It is supposed that the Channel group is the
3602 compliment of the other 3 groups. */
3603 #define XCM_REG_GR_LD0_PR 0x20214
3604 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
3605 highest priority is 3. It is supposed that the Channel group is the
3606 compliment of the other 3 groups. */
3607 #define XCM_REG_GR_LD1_PR 0x20218
3608 /* [RW 1] Input nig0 Interface enable. If 0 - the valid input is
3609 disregarded; acknowledge output is deasserted; all other signals are
3610 treated as usual; if 1 - normal activity. */
3611 #define XCM_REG_NIG0_IFEN 0x20038
3612 /* [RC 1] Set at message length mismatch (relative to last indication) at
3613 the nig0 interface. */
3614 #define XCM_REG_NIG0_LENGTH_MIS 0x20238
3615 /* [RW 1] Input nig1 Interface enable. If 0 - the valid input is
3616 disregarded; acknowledge output is deasserted; all other signals are
3617 treated as usual; if 1 - normal activity. */
3618 #define XCM_REG_NIG1_IFEN 0x2003c
3619 /* [RC 1] Set at message length mismatch (relative to last indication) at
3620 the nig1 interface. */
3621 #define XCM_REG_NIG1_LENGTH_MIS 0x2023c
3622 /* [RW 3] The weight of the input nig1 in the WRR mechanism. 0 stands for
3623 weight 8 (the most prioritised); 1 stands for weight 1(least
3624 prioritised); 2 stands for weight 2; tc. */
3625 #define XCM_REG_NIG1_WEIGHT 0x200d8
3626 /* [RW 5] The number of double REG-pairs; loaded from the STORM context and
3627 sent to STORM; for a specific connection type. The double REG-pairs are
3628 used in order to align to STORM context row size of 128 bits. The offset
3629 of these data in the STORM context is always 0. Index _i stands for the
3630 connection type (one of 16). */
3631 #define XCM_REG_N_SM_CTX_LD_0 0x20060
3632 #define XCM_REG_N_SM_CTX_LD_1 0x20064
3633 #define XCM_REG_N_SM_CTX_LD_10 0x20088
3634 #define XCM_REG_N_SM_CTX_LD_11 0x2008c
3635 #define XCM_REG_N_SM_CTX_LD_12 0x20090
3636 #define XCM_REG_N_SM_CTX_LD_13 0x20094
3637 #define XCM_REG_N_SM_CTX_LD_14 0x20098
3638 #define XCM_REG_N_SM_CTX_LD_15 0x2009c
3639 #define XCM_REG_N_SM_CTX_LD_2 0x20068
3640 #define XCM_REG_N_SM_CTX_LD_3 0x2006c
3641 #define XCM_REG_N_SM_CTX_LD_4 0x20070
3642 /* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
3643 acknowledge output is deasserted; all other signals are treated as usual;
3644 if 1 - normal activity. */
3645 #define XCM_REG_PBF_IFEN 0x20034
3646 /* [RC 1] Set at message length mismatch (relative to last indication) at
3647 the pbf interface. */
3648 #define XCM_REG_PBF_LENGTH_MIS 0x20234
3649 /* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for
3650 weight 8 (the most prioritised); 1 stands for weight 1(least
3651 prioritised); 2 stands for weight 2; tc. */
3652 #define XCM_REG_PBF_WEIGHT 0x200d0
3653 /* [RW 8] The Event ID for Timers formatting in case of stop done. */
3654 #define XCM_REG_STOP_EVNT_ID 0x200b8
3655 /* [RC 1] Set at message length mismatch (relative to last indication) at
3656 the STORM interface. */
3657 #define XCM_REG_STORM_LENGTH_MIS 0x2021c
3658 /* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for
3659 weight 8 (the most prioritised); 1 stands for weight 1(least
3660 prioritised); 2 stands for weight 2; tc. */
3661 #define XCM_REG_STORM_WEIGHT 0x200bc
3662 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
3663 disregarded; acknowledge output is deasserted; all other signals are
3664 treated as usual; if 1 - normal activity. */
3665 #define XCM_REG_STORM_XCM_IFEN 0x20010
3666 /* [RW 4] Timers output initial credit. Max credit available - 15.Write
3667 writes the initial credit value; read returns the current value of the
3668 credit counter. Must be initialized to 4 at start-up. */
3669 #define XCM_REG_TM_INIT_CRD 0x2041c
3670 /* [RW 28] The CM header for Timers expiration command. */
3671 #define XCM_REG_TM_XCM_HDR 0x200a8
3672 /* [RW 1] Timers - CM Interface enable. If 0 - the valid input is
3673 disregarded; acknowledge output is deasserted; all other signals are
3674 treated as usual; if 1 - normal activity. */
3675 #define XCM_REG_TM_XCM_IFEN 0x2001c
3676 /* [RW 1] Input tsem Interface enable. If 0 - the valid input is
3677 disregarded; acknowledge output is deasserted; all other signals are
3678 treated as usual; if 1 - normal activity. */
3679 #define XCM_REG_TSEM_IFEN 0x20024
3680 /* [RC 1] Set at message length mismatch (relative to last indication) at
3681 the tsem interface. */
3682 #define XCM_REG_TSEM_LENGTH_MIS 0x20224
3683 /* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for
3684 weight 8 (the most prioritised); 1 stands for weight 1(least
3685 prioritised); 2 stands for weight 2; tc. */
3686 #define XCM_REG_TSEM_WEIGHT 0x200c0
3687 /* [RW 2] The queue index for registration on UNA greater NXT decision rule. */
3688 #define XCM_REG_UNA_GT_NXT_Q 0x20120
3689 /* [RW 1] Input usem Interface enable. If 0 - the valid input is
3690 disregarded; acknowledge output is deasserted; all other signals are
3691 treated as usual; if 1 - normal activity. */
3692 #define XCM_REG_USEM_IFEN 0x2002c
3693 /* [RC 1] Message length mismatch (relative to last indication) at the usem
3694 interface. */
3695 #define XCM_REG_USEM_LENGTH_MIS 0x2022c
3696 /* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for
3697 weight 8 (the most prioritised); 1 stands for weight 1(least
3698 prioritised); 2 stands for weight 2; tc. */
3699 #define XCM_REG_USEM_WEIGHT 0x200c8
3700 /* [RW 2] DA counter command; used in case of window update doorbell.The
3701 first index stands for the value DaEnable of that connection. The second
3702 index stands for port number. */
3703 #define XCM_REG_WU_DA_CNT_CMD00 0x201d4
3704 /* [RW 2] DA counter command; used in case of window update doorbell.The
3705 first index stands for the value DaEnable of that connection. The second
3706 index stands for port number. */
3707 #define XCM_REG_WU_DA_CNT_CMD01 0x201d8
3708 /* [RW 2] DA counter command; used in case of window update doorbell.The
3709 first index stands for the value DaEnable of that connection. The second
3710 index stands for port number. */
3711 #define XCM_REG_WU_DA_CNT_CMD10 0x201dc
3712 /* [RW 2] DA counter command; used in case of window update doorbell.The
3713 first index stands for the value DaEnable of that connection. The second
3714 index stands for port number. */
3715 #define XCM_REG_WU_DA_CNT_CMD11 0x201e0
3716 /* [RW 8] DA counter update value used in case of window update doorbell.The
3717 first index stands for the value DaEnable of that connection. The second
3718 index stands for port number. */
3719 #define XCM_REG_WU_DA_CNT_UPD_VAL00 0x201e4
3720 /* [RW 8] DA counter update value; used in case of window update
3721 doorbell.The first index stands for the value DaEnable of that
3722 connection. The second index stands for port number. */
3723 #define XCM_REG_WU_DA_CNT_UPD_VAL01 0x201e8
3724 /* [RW 8] DA counter update value; used in case of window update
3725 doorbell.The first index stands for the value DaEnable of that
3726 connection. The second index stands for port number. */
3727 #define XCM_REG_WU_DA_CNT_UPD_VAL10 0x201ec
3728 /* [RW 8] DA counter update value; used in case of window update
3729 doorbell.The first index stands for the value DaEnable of that
3730 connection. The second index stands for port number. */
3731 #define XCM_REG_WU_DA_CNT_UPD_VAL11 0x201f0
3732 /* [RW 1] DA timer command; used in case of window update doorbell.The first
3733 index stands for the value DaEnable of that connection. The second index
3734 stands for port number. */
3735 #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00 0x201c4
3736 /* [RW 1] DA timer command; used in case of window update doorbell.The first
3737 index stands for the value DaEnable of that connection. The second index
3738 stands for port number. */
3739 #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01 0x201c8
3740 /* [RW 1] DA timer command; used in case of window update doorbell.The first
3741 index stands for the value DaEnable of that connection. The second index
3742 stands for port number. */
3743 #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10 0x201cc
3744 /* [RW 1] DA timer command; used in case of window update doorbell.The first
3745 index stands for the value DaEnable of that connection. The second index
3746 stands for port number. */
3747 #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11 0x201d0
3748 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
3749 acknowledge output is deasserted; all other signals are treated as usual;
3750 if 1 - normal activity. */
3751 #define XCM_REG_XCM_CFC_IFEN 0x20050
3752 /* [RW 14] Interrupt mask register #0 read/write */
3753 #define XCM_REG_XCM_INT_MASK 0x202b4
3754 /* [R 14] Interrupt register #0 read */
3755 #define XCM_REG_XCM_INT_STS 0x202a8
3756 /* [RW 4] The size of AG context region 0 in REG-pairs. Designates the MS
3757 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
3758 Is used to determine the number of the AG context REG-pairs written back;
3759 when the Reg1WbFlg isn't set. */
3760 #define XCM_REG_XCM_REG0_SZ 0x200f4
3761 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
3762 disregarded; valid is deasserted; all other signals are treated as usual;
3763 if 1 - normal activity. */
3764 #define XCM_REG_XCM_STORM0_IFEN 0x20004
3765 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
3766 disregarded; valid is deasserted; all other signals are treated as usual;
3767 if 1 - normal activity. */
3768 #define XCM_REG_XCM_STORM1_IFEN 0x20008
3769 /* [RW 1] CM - Timers Interface enable. If 0 - the valid input is
3770 disregarded; acknowledge output is deasserted; all other signals are
3771 treated as usual; if 1 - normal activity. */
3772 #define XCM_REG_XCM_TM_IFEN 0x20020
3773 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
3774 disregarded; valid is deasserted; all other signals are treated as usual;
3775 if 1 - normal activity. */
3776 #define XCM_REG_XCM_XQM_IFEN 0x2000c
3777 /* [RW 1] If set the Q index; received from the QM is inserted to event ID. */
3778 #define XCM_REG_XCM_XQM_USE_Q 0x200f0
3779 /* [RW 4] The value by which CFC updates the activity counter at QM bypass. */
3780 #define XCM_REG_XQM_BYP_ACT_UPD 0x200fc
3781 /* [RW 6] QM output initial credit. Max credit available - 32.Write writes
3782 the initial credit value; read returns the current value of the credit
3783 counter. Must be initialized to 32 at start-up. */
3784 #define XCM_REG_XQM_INIT_CRD 0x20420
3785 /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
3786 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
3787 prioritised); 2 stands for weight 2; tc. */
3788 #define XCM_REG_XQM_P_WEIGHT 0x200e4
3789 /* [RW 28] The CM header value for QM request (primary). */
3790 #define XCM_REG_XQM_XCM_HDR_P 0x200a0
3791 /* [RW 28] The CM header value for QM request (secondary). */
3792 #define XCM_REG_XQM_XCM_HDR_S 0x200a4
3793 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
3794 acknowledge output is deasserted; all other signals are treated as usual;
3795 if 1 - normal activity. */
3796 #define XCM_REG_XQM_XCM_IFEN 0x20014
3797 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
3798 acknowledge output is deasserted; all other signals are treated as usual;
3799 if 1 - normal activity. */
3800 #define XCM_REG_XSDM_IFEN 0x20018
3801 /* [RC 1] Set at message length mismatch (relative to last indication) at
3802 the SDM interface. */
3803 #define XCM_REG_XSDM_LENGTH_MIS 0x20220
3804 /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
3805 weight 8 (the most prioritised); 1 stands for weight 1(least
3806 prioritised); 2 stands for weight 2; tc. */
3807 #define XCM_REG_XSDM_WEIGHT 0x200e0
3808 /* [RW 17] Indirect access to the descriptor table of the XX protection
3809 mechanism. The fields are: [5:0] - message length; 11:6] - message
3810 pointer; 16:12] - next pointer. */
3811 #define XCM_REG_XX_DESCR_TABLE 0x20480
3812 /* [R 6] Used to read the XX protection Free counter. */
3813 #define XCM_REG_XX_FREE 0x20240
3814 /* [RW 6] Initial value for the credit counter; responsible for fulfilling
3815 of the Input Stage XX protection buffer by the XX protection pending
3816 messages. Max credit available - 3.Write writes the initial credit value;
3817 read returns the current value of the credit counter. Must be initialized
3818 to 2 at start-up. */
3819 #define XCM_REG_XX_INIT_CRD 0x20424
3820 /* [RW 6] The maximum number of pending messages; which may be stored in XX
3821 protection. ~xcm_registers_xx_free.xx_free read on read. */
3822 #define XCM_REG_XX_MSG_NUM 0x20428
3823 /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
3824 #define XCM_REG_XX_OVFL_EVNT_ID 0x20058
3825 /* [RW 15] Indirect access to the XX table of the XX protection mechanism.
3826 The fields are:[4:0] - tail pointer; 9:5] - Link List size; 14:10] -
3827 header pointer. */
3828 #define XCM_REG_XX_TABLE 0x20500
3829 /* [RW 8] The event id for aggregated interrupt 0 */
3830 #define XSDM_REG_AGG_INT_EVENT_0 0x166038
3831 #define XSDM_REG_AGG_INT_EVENT_1 0x16603c
3832 #define XSDM_REG_AGG_INT_EVENT_10 0x166060
3833 #define XSDM_REG_AGG_INT_EVENT_11 0x166064
3834 #define XSDM_REG_AGG_INT_EVENT_12 0x166068
3835 #define XSDM_REG_AGG_INT_EVENT_13 0x16606c
3836 #define XSDM_REG_AGG_INT_EVENT_14 0x166070
3837 #define XSDM_REG_AGG_INT_EVENT_15 0x166074
3838 #define XSDM_REG_AGG_INT_EVENT_16 0x166078
3839 #define XSDM_REG_AGG_INT_EVENT_17 0x16607c
3840 #define XSDM_REG_AGG_INT_EVENT_18 0x166080
3841 #define XSDM_REG_AGG_INT_EVENT_19 0x166084
3842 #define XSDM_REG_AGG_INT_EVENT_2 0x166040
3843 #define XSDM_REG_AGG_INT_EVENT_20 0x166088
3844 #define XSDM_REG_AGG_INT_EVENT_21 0x16608c
3845 #define XSDM_REG_AGG_INT_EVENT_22 0x166090
3846 #define XSDM_REG_AGG_INT_EVENT_23 0x166094
3847 #define XSDM_REG_AGG_INT_EVENT_24 0x166098
3848 #define XSDM_REG_AGG_INT_EVENT_25 0x16609c
3849 #define XSDM_REG_AGG_INT_EVENT_26 0x1660a0
3850 #define XSDM_REG_AGG_INT_EVENT_27 0x1660a4
3851 #define XSDM_REG_AGG_INT_EVENT_28 0x1660a8
3852 #define XSDM_REG_AGG_INT_EVENT_29 0x1660ac
3853 /* [RW 1] For each aggregated interrupt index whether the mode is normal (0)
3854 or auto-mask-mode (1) */
3855 #define XSDM_REG_AGG_INT_MODE_0 0x1661b8
3856 #define XSDM_REG_AGG_INT_MODE_1 0x1661bc
3857 #define XSDM_REG_AGG_INT_MODE_10 0x1661e0
3858 #define XSDM_REG_AGG_INT_MODE_11 0x1661e4
3859 #define XSDM_REG_AGG_INT_MODE_12 0x1661e8
3860 #define XSDM_REG_AGG_INT_MODE_13 0x1661ec
3861 #define XSDM_REG_AGG_INT_MODE_14 0x1661f0
3862 #define XSDM_REG_AGG_INT_MODE_15 0x1661f4
3863 #define XSDM_REG_AGG_INT_MODE_16 0x1661f8
3864 #define XSDM_REG_AGG_INT_MODE_17 0x1661fc
3865 #define XSDM_REG_AGG_INT_MODE_18 0x166200
3866 #define XSDM_REG_AGG_INT_MODE_19 0x166204
3867 /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
3868 #define XSDM_REG_CFC_RSP_START_ADDR 0x166008
3869 /* [RW 16] The maximum value of the competion counter #0 */
3870 #define XSDM_REG_CMP_COUNTER_MAX0 0x16601c
3871 /* [RW 16] The maximum value of the competion counter #1 */
3872 #define XSDM_REG_CMP_COUNTER_MAX1 0x166020
3873 /* [RW 16] The maximum value of the competion counter #2 */
3874 #define XSDM_REG_CMP_COUNTER_MAX2 0x166024
3875 /* [RW 16] The maximum value of the competion counter #3 */
3876 #define XSDM_REG_CMP_COUNTER_MAX3 0x166028
3877 /* [RW 13] The start address in the internal RAM for the completion
3878 counters. */
3879 #define XSDM_REG_CMP_COUNTER_START_ADDR 0x16600c
3880 #define XSDM_REG_ENABLE_IN1 0x166238
3881 #define XSDM_REG_ENABLE_IN2 0x16623c
3882 #define XSDM_REG_ENABLE_OUT1 0x166240
3883 #define XSDM_REG_ENABLE_OUT2 0x166244
3884 /* [RW 4] The initial number of messages that can be sent to the pxp control
3885 interface without receiving any ACK. */
3886 #define XSDM_REG_INIT_CREDIT_PXP_CTRL 0x1664bc
3887 /* [ST 32] The number of ACK after placement messages received */
3888 #define XSDM_REG_NUM_OF_ACK_AFTER_PLACE 0x16627c
3889 /* [ST 32] The number of packet end messages received from the parser */
3890 #define XSDM_REG_NUM_OF_PKT_END_MSG 0x166274
3891 /* [ST 32] The number of requests received from the pxp async if */
3892 #define XSDM_REG_NUM_OF_PXP_ASYNC_REQ 0x166278
3893 /* [ST 32] The number of commands received in queue 0 */
3894 #define XSDM_REG_NUM_OF_Q0_CMD 0x166248
3895 /* [ST 32] The number of commands received in queue 10 */
3896 #define XSDM_REG_NUM_OF_Q10_CMD 0x16626c
3897 /* [ST 32] The number of commands received in queue 11 */
3898 #define XSDM_REG_NUM_OF_Q11_CMD 0x166270
3899 /* [ST 32] The number of commands received in queue 1 */
3900 #define XSDM_REG_NUM_OF_Q1_CMD 0x16624c
3901 /* [ST 32] The number of commands received in queue 3 */
3902 #define XSDM_REG_NUM_OF_Q3_CMD 0x166250
3903 /* [ST 32] The number of commands received in queue 4 */
3904 #define XSDM_REG_NUM_OF_Q4_CMD 0x166254
3905 /* [ST 32] The number of commands received in queue 5 */
3906 #define XSDM_REG_NUM_OF_Q5_CMD 0x166258
3907 /* [ST 32] The number of commands received in queue 6 */
3908 #define XSDM_REG_NUM_OF_Q6_CMD 0x16625c
3909 /* [ST 32] The number of commands received in queue 7 */
3910 #define XSDM_REG_NUM_OF_Q7_CMD 0x166260
3911 /* [ST 32] The number of commands received in queue 8 */
3912 #define XSDM_REG_NUM_OF_Q8_CMD 0x166264
3913 /* [ST 32] The number of commands received in queue 9 */
3914 #define XSDM_REG_NUM_OF_Q9_CMD 0x166268
3915 /* [RW 13] The start address in the internal RAM for queue counters */
3916 #define XSDM_REG_Q_COUNTER_START_ADDR 0x166010
3917 /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
3918 #define XSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0x166548
3919 /* [R 1] parser fifo empty in sdm_sync block */
3920 #define XSDM_REG_SYNC_PARSER_EMPTY 0x166550
3921 /* [R 1] parser serial fifo empty in sdm_sync block */
3922 #define XSDM_REG_SYNC_SYNC_EMPTY 0x166558
3923 /* [RW 32] Tick for timer counter. Applicable only when
3924 ~xsdm_registers_timer_tick_enable.timer_tick_enable =1 */
3925 #define XSDM_REG_TIMER_TICK 0x166000
3926 /* [RW 32] Interrupt mask register #0 read/write */
3927 #define XSDM_REG_XSDM_INT_MASK_0 0x16629c
3928 #define XSDM_REG_XSDM_INT_MASK_1 0x1662ac
3929 /* [RW 11] Parity mask register #0 read/write */
3930 #define XSDM_REG_XSDM_PRTY_MASK 0x1662bc
3932 =======
3933 /* [R 11] Parity register #0 read */
3934 #define XSDM_REG_XSDM_PRTY_STS 0x1662b0
3936 /* [RW 5] The number of time_slots in the arbitration cycle */
3937 #define XSEM_REG_ARB_CYCLE_SIZE 0x280034
3938 /* [RW 3] The source that is associated with arbitration element 0. Source
3939 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3940 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
3941 #define XSEM_REG_ARB_ELEMENT0 0x280020
3942 /* [RW 3] The source that is associated with arbitration element 1. Source
3943 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3944 sleeping thread with priority 1; 4- sleeping thread with priority 2.
3945 Could not be equal to register ~xsem_registers_arb_element0.arb_element0 */
3946 #define XSEM_REG_ARB_ELEMENT1 0x280024
3947 /* [RW 3] The source that is associated with arbitration element 2. Source
3948 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3949 sleeping thread with priority 1; 4- sleeping thread with priority 2.
3950 Could not be equal to register ~xsem_registers_arb_element0.arb_element0
3951 and ~xsem_registers_arb_element1.arb_element1 */
3952 #define XSEM_REG_ARB_ELEMENT2 0x280028
3953 /* [RW 3] The source that is associated with arbitration element 3. Source
3954 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3955 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
3956 not be equal to register ~xsem_registers_arb_element0.arb_element0 and
3957 ~xsem_registers_arb_element1.arb_element1 and
3958 ~xsem_registers_arb_element2.arb_element2 */
3959 #define XSEM_REG_ARB_ELEMENT3 0x28002c
3960 /* [RW 3] The source that is associated with arbitration element 4. Source
3961 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3962 sleeping thread with priority 1; 4- sleeping thread with priority 2.
3963 Could not be equal to register ~xsem_registers_arb_element0.arb_element0
3964 and ~xsem_registers_arb_element1.arb_element1 and
3965 ~xsem_registers_arb_element2.arb_element2 and
3966 ~xsem_registers_arb_element3.arb_element3 */
3967 #define XSEM_REG_ARB_ELEMENT4 0x280030
3968 #define XSEM_REG_ENABLE_IN 0x2800a4
3969 #define XSEM_REG_ENABLE_OUT 0x2800a8
3970 /* [RW 32] This address space contains all registers and memories that are
3971 placed in SEM_FAST block. The SEM_FAST registers are described in
3972 appendix B. In order to access the SEM_FAST registers the base address
3973 XSEM_REGISTERS_FAST_MEMORY (Offset: 0x2a0000) should be added to each
3974 SEM_FAST register offset. */
3975 #define XSEM_REG_FAST_MEMORY 0x2a0000
3976 /* [RW 1] Disables input messages from FIC0 May be updated during run_time
3977 by the microcode */
3978 #define XSEM_REG_FIC0_DISABLE 0x280224
3979 /* [RW 1] Disables input messages from FIC1 May be updated during run_time
3980 by the microcode */
3981 #define XSEM_REG_FIC1_DISABLE 0x280234
3982 /* [RW 15] Interrupt table Read and write access to it is not possible in
3983 the middle of the work */
3984 #define XSEM_REG_INT_TABLE 0x280400
3985 /* [ST 24] Statistics register. The number of messages that entered through
3986 FIC0 */
3987 #define XSEM_REG_MSG_NUM_FIC0 0x280000
3988 /* [ST 24] Statistics register. The number of messages that entered through
3989 FIC1 */
3990 #define XSEM_REG_MSG_NUM_FIC1 0x280004
3991 /* [ST 24] Statistics register. The number of messages that were sent to
3992 FOC0 */
3993 #define XSEM_REG_MSG_NUM_FOC0 0x280008
3994 /* [ST 24] Statistics register. The number of messages that were sent to
3995 FOC1 */
3996 #define XSEM_REG_MSG_NUM_FOC1 0x28000c
3997 /* [ST 24] Statistics register. The number of messages that were sent to
3998 FOC2 */
3999 #define XSEM_REG_MSG_NUM_FOC2 0x280010
4000 /* [ST 24] Statistics register. The number of messages that were sent to
4001 FOC3 */
4002 #define XSEM_REG_MSG_NUM_FOC3 0x280014
4003 /* [RW 1] Disables input messages from the passive buffer May be updated
4004 during run_time by the microcode */
4005 #define XSEM_REG_PAS_DISABLE 0x28024c
4006 /* [WB 128] Debug only. Passive buffer memory */
4007 #define XSEM_REG_PASSIVE_BUFFER 0x282000
4008 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
4009 #define XSEM_REG_PRAM 0x2c0000
4010 /* [R 16] Valid sleeping threads indication have bit per thread */
4011 #define XSEM_REG_SLEEP_THREADS_VALID 0x28026c
4012 /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
4013 #define XSEM_REG_SLOW_EXT_STORE_EMPTY 0x2802a0
4014 /* [RW 16] List of free threads . There is a bit per thread. */
4015 #define XSEM_REG_THREADS_LIST 0x2802e4
4016 /* [RW 3] The arbitration scheme of time_slot 0 */
4017 #define XSEM_REG_TS_0_AS 0x280038
4018 /* [RW 3] The arbitration scheme of time_slot 10 */
4019 #define XSEM_REG_TS_10_AS 0x280060
4020 /* [RW 3] The arbitration scheme of time_slot 11 */
4021 #define XSEM_REG_TS_11_AS 0x280064
4022 /* [RW 3] The arbitration scheme of time_slot 12 */
4023 #define XSEM_REG_TS_12_AS 0x280068
4024 /* [RW 3] The arbitration scheme of time_slot 13 */
4025 #define XSEM_REG_TS_13_AS 0x28006c
4026 /* [RW 3] The arbitration scheme of time_slot 14 */
4027 #define XSEM_REG_TS_14_AS 0x280070
4028 /* [RW 3] The arbitration scheme of time_slot 15 */
4029 #define XSEM_REG_TS_15_AS 0x280074
4030 /* [RW 3] The arbitration scheme of time_slot 16 */
4031 #define XSEM_REG_TS_16_AS 0x280078
4032 /* [RW 3] The arbitration scheme of time_slot 17 */
4033 #define XSEM_REG_TS_17_AS 0x28007c
4034 /* [RW 3] The arbitration scheme of time_slot 18 */
4035 #define XSEM_REG_TS_18_AS 0x280080
4036 /* [RW 3] The arbitration scheme of time_slot 1 */
4037 #define XSEM_REG_TS_1_AS 0x28003c
4038 /* [RW 3] The arbitration scheme of time_slot 2 */
4039 #define XSEM_REG_TS_2_AS 0x280040
4040 /* [RW 3] The arbitration scheme of time_slot 3 */
4041 #define XSEM_REG_TS_3_AS 0x280044
4042 /* [RW 3] The arbitration scheme of time_slot 4 */
4043 #define XSEM_REG_TS_4_AS 0x280048
4044 /* [RW 3] The arbitration scheme of time_slot 5 */
4045 #define XSEM_REG_TS_5_AS 0x28004c
4046 /* [RW 3] The arbitration scheme of time_slot 6 */
4047 #define XSEM_REG_TS_6_AS 0x280050
4048 /* [RW 3] The arbitration scheme of time_slot 7 */
4049 #define XSEM_REG_TS_7_AS 0x280054
4050 /* [RW 3] The arbitration scheme of time_slot 8 */
4051 #define XSEM_REG_TS_8_AS 0x280058
4052 /* [RW 3] The arbitration scheme of time_slot 9 */
4053 #define XSEM_REG_TS_9_AS 0x28005c
4054 /* [RW 32] Interrupt mask register #0 read/write */
4055 #define XSEM_REG_XSEM_INT_MASK_0 0x280110
4056 #define XSEM_REG_XSEM_INT_MASK_1 0x280120
4057 /* [RW 32] Parity mask register #0 read/write */
4058 #define XSEM_REG_XSEM_PRTY_MASK_0 0x280130
4059 #define XSEM_REG_XSEM_PRTY_MASK_1 0x280140
4061 =======
4062 /* [R 32] Parity register #0 read */
4063 #define XSEM_REG_XSEM_PRTY_STS_0 0x280124
4064 #define XSEM_REG_XSEM_PRTY_STS_1 0x280134
4066 #define MCPR_NVM_ACCESS_ENABLE_EN (1L<<0)
4067 #define MCPR_NVM_ACCESS_ENABLE_WR_EN (1L<<1)
4068 #define MCPR_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL<<0)
4069 #define MCPR_NVM_CFG4_FLASH_SIZE (0x7L<<0)
4070 #define MCPR_NVM_COMMAND_DOIT (1L<<4)
4071 #define MCPR_NVM_COMMAND_DONE (1L<<3)
4072 #define MCPR_NVM_COMMAND_FIRST (1L<<7)
4073 #define MCPR_NVM_COMMAND_LAST (1L<<8)
4074 #define MCPR_NVM_COMMAND_WR (1L<<5)
4075 #define MCPR_NVM_COMMAND_WREN (1L<<16)
4076 #define MCPR_NVM_COMMAND_WREN_BITSHIFT 16
4077 #define MCPR_NVM_COMMAND_WRDI (1L<<17)
4078 #define MCPR_NVM_COMMAND_WRDI_BITSHIFT 17
4079 #define MCPR_NVM_SW_ARB_ARB_ARB1 (1L<<9)
4080 #define MCPR_NVM_SW_ARB_ARB_REQ_CLR1 (1L<<5)
4081 #define MCPR_NVM_SW_ARB_ARB_REQ_SET1 (1L<<1)
4082 #define BIGMAC_REGISTER_BMAC_CONTROL (0x00<<3)
4083 #define BIGMAC_REGISTER_BMAC_XGXS_CONTROL (0x01<<3)
4084 #define BIGMAC_REGISTER_CNT_MAX_SIZE (0x05<<3)
4085 #define BIGMAC_REGISTER_RX_CONTROL (0x21<<3)
4086 #define BIGMAC_REGISTER_RX_LLFC_MSG_FLDS (0x46<<3)
4087 #define BIGMAC_REGISTER_RX_MAX_SIZE (0x23<<3)
4088 #define BIGMAC_REGISTER_RX_STAT_GR64 (0x26<<3)
4089 #define BIGMAC_REGISTER_RX_STAT_GRIPJ (0x42<<3)
4090 #define BIGMAC_REGISTER_TX_CONTROL (0x07<<3)
4091 #define BIGMAC_REGISTER_TX_MAX_SIZE (0x09<<3)
4092 #define BIGMAC_REGISTER_TX_PAUSE_THRESHOLD (0x0A<<3)
4093 #define BIGMAC_REGISTER_TX_SOURCE_ADDR (0x08<<3)
4094 #define BIGMAC_REGISTER_TX_STAT_GTBYT (0x20<<3)
4095 #define BIGMAC_REGISTER_TX_STAT_GTPKT (0x0C<<3)
4096 #define EMAC_MDIO_COMM_COMMAND_ADDRESS (0L<<26)
4097 #define EMAC_MDIO_COMM_COMMAND_READ_22 (2L<<26)
4098 #define EMAC_MDIO_COMM_COMMAND_READ_45 (3L<<26)
4099 #define EMAC_MDIO_COMM_COMMAND_WRITE_22 (1L<<26)
4100 #define EMAC_MDIO_COMM_COMMAND_WRITE_45 (1L<<26)
4101 #define EMAC_MDIO_COMM_DATA (0xffffL<<0)
4102 #define EMAC_MDIO_COMM_START_BUSY (1L<<29)
4103 #define EMAC_MDIO_MODE_AUTO_POLL (1L<<4)
4104 #define EMAC_MDIO_MODE_CLAUSE_45 (1L<<31)
4106 =======
4107 #define EMAC_MDIO_MODE_CLOCK_CNT (0x3fL<<16)
4108 #define EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT 16
4110 #define EMAC_MODE_25G_MODE (1L<<5)
4111 #define EMAC_MODE_ACPI_RCVD (1L<<20)
4112 #define EMAC_MODE_HALF_DUPLEX (1L<<1)
4113 #define EMAC_MODE_MPKT (1L<<18)
4114 #define EMAC_MODE_MPKT_RCVD (1L<<19)
4115 #define EMAC_MODE_PORT_GMII (2L<<2)
4116 #define EMAC_MODE_PORT_MII (1L<<2)
4117 #define EMAC_MODE_PORT_MII_10M (3L<<2)
4118 #define EMAC_MODE_RESET (1L<<0)
4119 #define EMAC_REG_EMAC_MAC_MATCH 0x10
4120 #define EMAC_REG_EMAC_MDIO_COMM 0xac
4121 #define EMAC_REG_EMAC_MDIO_MODE 0xb4
4122 #define EMAC_REG_EMAC_MODE 0x0
4123 #define EMAC_REG_EMAC_RX_MODE 0xc8
4124 #define EMAC_REG_EMAC_RX_MTU_SIZE 0x9c
4125 #define EMAC_REG_EMAC_RX_STAT_AC 0x180
4126 #define EMAC_REG_EMAC_RX_STAT_AC_28 0x1f4
4127 #define EMAC_REG_EMAC_RX_STAT_AC_COUNT 23
4128 #define EMAC_REG_EMAC_TX_MODE 0xbc
4129 #define EMAC_REG_EMAC_TX_STAT_AC 0x280
4130 #define EMAC_REG_EMAC_TX_STAT_AC_COUNT 22
4131 #define EMAC_RX_MODE_FLOW_EN (1L<<2)
4132 #define EMAC_RX_MODE_KEEP_VLAN_TAG (1L<<10)
4133 #define EMAC_RX_MODE_PROMISCUOUS (1L<<8)
4134 #define EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31)
4135 #define EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3)
4136 #define EMAC_TX_MODE_RESET (1L<<0)
4138 =======
4139 #define MISC_REGISTERS_GPIO_1 1
4140 #define MISC_REGISTERS_GPIO_2 2
4141 #define MISC_REGISTERS_GPIO_3 3
4142 #define MISC_REGISTERS_GPIO_CLR_POS 16
4143 #define MISC_REGISTERS_GPIO_FLOAT (0xffL<<24)
4144 #define MISC_REGISTERS_GPIO_FLOAT_POS 24
4145 #define MISC_REGISTERS_GPIO_INPUT_HI_Z 2
4146 #define MISC_REGISTERS_GPIO_OUTPUT_HIGH 1
4147 #define MISC_REGISTERS_GPIO_OUTPUT_LOW 0
4148 #define MISC_REGISTERS_GPIO_PORT_SHIFT 4
4149 #define MISC_REGISTERS_GPIO_SET_POS 8
4151 #define MISC_REGISTERS_RESET_REG_1_CLEAR 0x588
4152 #define MISC_REGISTERS_RESET_REG_1_SET 0x584
4153 #define MISC_REGISTERS_RESET_REG_2_CLEAR 0x598
4154 #define MISC_REGISTERS_RESET_REG_2_RST_BMAC0 (0x1<<0)
4155 #define MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE (0x1<<14)
4156 #define MISC_REGISTERS_RESET_REG_2_SET 0x594
4157 #define MISC_REGISTERS_RESET_REG_3_CLEAR 0x5a8
4158 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ (0x1<<1)
4159 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN (0x1<<2)
4160 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD (0x1<<3)
4161 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW (0x1<<0)
4162 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ (0x1<<5)
4163 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN (0x1<<6)
4164 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD (0x1<<7)
4165 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW (0x1<<4)
4166 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB (0x1<<8)
4167 #define MISC_REGISTERS_RESET_REG_3_SET 0x5a4
4169 =======
4170 #define MISC_REGISTERS_SPIO_4 4
4171 #define MISC_REGISTERS_SPIO_5 5
4172 #define MISC_REGISTERS_SPIO_7 7
4173 #define MISC_REGISTERS_SPIO_CLR_POS 16
4174 #define MISC_REGISTERS_SPIO_FLOAT (0xffL<<24)
4175 #define GRC_MISC_REGISTERS_SPIO_FLOAT7 0x80000000
4176 #define GRC_MISC_REGISTERS_SPIO_FLOAT6 0x40000000
4177 #define GRC_MISC_REGISTERS_SPIO_FLOAT5 0x20000000
4178 #define GRC_MISC_REGISTERS_SPIO_FLOAT4 0x10000000
4179 #define MISC_REGISTERS_SPIO_FLOAT_POS 24
4180 #define MISC_REGISTERS_SPIO_INPUT_HI_Z 2
4181 #define MISC_REGISTERS_SPIO_INT_OLD_SET_POS 16
4182 #define MISC_REGISTERS_SPIO_OUTPUT_HIGH 1
4183 #define MISC_REGISTERS_SPIO_OUTPUT_LOW 0
4184 #define MISC_REGISTERS_SPIO_SET_POS 8
4185 #define HW_LOCK_MAX_RESOURCE_VALUE 31
4186 #define HW_LOCK_RESOURCE_8072_MDIO 0
4187 #define HW_LOCK_RESOURCE_GPIO 1
4188 #define HW_LOCK_RESOURCE_SPIO 2
4190 #define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR (1<<18)
4191 #define AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT (1<<31)
4192 #define AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT (1<<9)
4193 #define AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR (1<<8)
4194 #define AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT (1<<7)
4195 #define AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR (1<<6)
4196 #define AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT (1<<29)
4197 #define AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR (1<<28)
4198 #define AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT (1<<1)
4199 #define AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR (1<<0)
4200 #define AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR (1<<18)
4201 #define AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT (1<<11)
4202 #define AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT (1<<13)
4203 #define AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR (1<<12)
4204 #define AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR (1<<12)
4205 #define AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT (1<<15)
4206 #define AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR (1<<14)
4207 #define AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR (1<<20)
4208 #define AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR (1<<0)
4209 #define AEU_INPUTS_ATTN_BITS_PBF_HW_INTERRUPT (1<<31)
4210 #define AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT (1<<3)
4211 #define AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR (1<<2)
4212 #define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT (1<<5)
4213 #define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR (1<<4)
4214 #define AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT (1<<3)
4215 #define AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR (1<<2)
4216 #define AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR (1<<22)
4218 =======
4219 #define AEU_INPUTS_ATTN_BITS_SPIO5 (1<<15)
4221 #define AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT (1<<27)
4222 #define AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT (1<<5)
4223 #define AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT (1<<25)
4224 #define AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR (1<<24)
4225 #define AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT (1<<29)
4226 #define AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR (1<<28)
4227 #define AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT (1<<23)
4228 #define AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT (1<<27)
4229 #define AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR (1<<26)
4230 #define AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT (1<<21)
4231 #define AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR (1<<20)
4232 #define AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT (1<<25)
4233 #define AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR (1<<24)
4234 #define AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR (1<<16)
4235 #define AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT (1<<9)
4236 #define AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT (1<<7)
4237 #define AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR (1<<6)
4238 #define AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT (1<<11)
4239 #define AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR (1<<10)
4240 #define RESERVED_GENERAL_ATTENTION_BIT_0 0
4242 #define EVEREST_GEN_ATTN_IN_USE_MASK 0x3e0
4243 #define EVEREST_LATCHED_ATTN_IN_USE_MASK 0xffe00000
4245 #define RESERVED_GENERAL_ATTENTION_BIT_6 6
4246 #define RESERVED_GENERAL_ATTENTION_BIT_7 7
4247 #define RESERVED_GENERAL_ATTENTION_BIT_8 8
4248 #define RESERVED_GENERAL_ATTENTION_BIT_9 9
4249 #define RESERVED_GENERAL_ATTENTION_BIT_10 10
4250 #define RESERVED_GENERAL_ATTENTION_BIT_11 11
4251 #define RESERVED_GENERAL_ATTENTION_BIT_12 12
4252 #define RESERVED_GENERAL_ATTENTION_BIT_13 13
4253 #define RESERVED_GENERAL_ATTENTION_BIT_14 14
4254 #define RESERVED_GENERAL_ATTENTION_BIT_15 15
4255 #define RESERVED_GENERAL_ATTENTION_BIT_16 16
4256 #define RESERVED_GENERAL_ATTENTION_BIT_17 17
4257 #define RESERVED_GENERAL_ATTENTION_BIT_18 18
4258 #define RESERVED_GENERAL_ATTENTION_BIT_19 19
4259 #define RESERVED_GENERAL_ATTENTION_BIT_20 20
4260 #define RESERVED_GENERAL_ATTENTION_BIT_21 21
4262 /* storm asserts attention bits */
4263 #define TSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_7
4264 #define USTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_8
4265 #define CSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_9
4266 #define XSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_10
4268 /* mcp error attention bit */
4269 #define MCP_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_11
4271 #define LATCHED_ATTN_RBCR 23
4272 #define LATCHED_ATTN_RBCT 24
4273 #define LATCHED_ATTN_RBCN 25
4274 #define LATCHED_ATTN_RBCU 26
4275 #define LATCHED_ATTN_RBCP 27
4276 #define LATCHED_ATTN_TIMEOUT_GRC 28
4277 #define LATCHED_ATTN_RSVD_GRC 29
4278 #define LATCHED_ATTN_ROM_PARITY_MCP 30
4279 #define LATCHED_ATTN_UM_RX_PARITY_MCP 31
4280 #define LATCHED_ATTN_UM_TX_PARITY_MCP 32
4281 #define LATCHED_ATTN_SCPAD_PARITY_MCP 33
4283 #define GENERAL_ATTEN_WORD(atten_name) ((94 + atten_name) / 32)
4284 #define GENERAL_ATTEN_OFFSET(atten_name) (1 << ((94 + atten_name) % 32))
4285 /*
4286 * This file defines GRC base address for every block.
4287 * This file is included by chipsim, asm microcode and cpp microcode.
4288 * These values are used in Design.xml on regBase attribute
4289 * Use the base with the generated offsets of specific registers.
4290 */
4292 #define GRCBASE_PXPCS 0x000000
4293 #define GRCBASE_PCICONFIG 0x002000
4294 #define GRCBASE_PCIREG 0x002400
4295 #define GRCBASE_EMAC0 0x008000
4296 #define GRCBASE_EMAC1 0x008400
4297 #define GRCBASE_DBU 0x008800
4298 #define GRCBASE_MISC 0x00A000
4299 #define GRCBASE_DBG 0x00C000
4300 #define GRCBASE_NIG 0x010000
4301 #define GRCBASE_XCM 0x020000
4302 #define GRCBASE_PRS 0x040000
4303 #define GRCBASE_SRCH 0x040400
4304 #define GRCBASE_TSDM 0x042000
4305 #define GRCBASE_TCM 0x050000
4306 #define GRCBASE_BRB1 0x060000
4307 #define GRCBASE_MCP 0x080000
4308 #define GRCBASE_UPB 0x0C1000
4309 #define GRCBASE_CSDM 0x0C2000
4310 #define GRCBASE_USDM 0x0C4000
4311 #define GRCBASE_CCM 0x0D0000
4312 #define GRCBASE_UCM 0x0E0000
4313 #define GRCBASE_CDU 0x101000
4314 #define GRCBASE_DMAE 0x102000
4315 #define GRCBASE_PXP 0x103000
4316 #define GRCBASE_CFC 0x104000
4317 #define GRCBASE_HC 0x108000
4318 #define GRCBASE_PXP2 0x120000
4319 #define GRCBASE_PBF 0x140000
4320 #define GRCBASE_XPB 0x161000
4321 #define GRCBASE_TIMERS 0x164000
4322 #define GRCBASE_XSDM 0x166000
4323 #define GRCBASE_QM 0x168000
4324 #define GRCBASE_DQ 0x170000
4325 #define GRCBASE_TSEM 0x180000
4326 #define GRCBASE_CSEM 0x200000
4327 #define GRCBASE_XSEM 0x280000
4328 #define GRCBASE_USEM 0x300000
4329 #define GRCBASE_MISC_AEU GRCBASE_MISC
4332 /*the offset of the configuration space in the pci core register*/
4333 #define PCICFG_OFFSET 0x2000
4334 #define PCICFG_VENDOR_ID_OFFSET 0x00
4335 #define PCICFG_DEVICE_ID_OFFSET 0x02
4336 #define PCICFG_SUBSYSTEM_VENDOR_ID_OFFSET 0x2c
4337 #define PCICFG_SUBSYSTEM_ID_OFFSET 0x2e
4338 #define PCICFG_INT_LINE 0x3c
4339 #define PCICFG_INT_PIN 0x3d
4340 #define PCICFG_CACHE_LINE_SIZE 0x0c
4341 #define PCICFG_LATENCY_TIMER 0x0d
4342 #define PCICFG_REVESION_ID 0x08
4343 #define PCICFG_BAR_1_LOW 0x10
4344 #define PCICFG_BAR_1_HIGH 0x14
4345 #define PCICFG_BAR_2_LOW 0x18
4346 #define PCICFG_BAR_2_HIGH 0x1c
4347 #define PCICFG_GRC_ADDRESS 0x78
4348 #define PCICFG_GRC_DATA 0x80
4349 #define PCICFG_DEVICE_CONTROL 0xb4
4350 #define PCICFG_LINK_CONTROL 0xbc
4352 #define BAR_USTRORM_INTMEM 0x400000
4353 #define BAR_CSTRORM_INTMEM 0x410000
4354 #define BAR_XSTRORM_INTMEM 0x420000
4355 #define BAR_TSTRORM_INTMEM 0x430000
4357 #define BAR_IGU_INTMEM 0x440000
4359 #define BAR_DOORBELL_OFFSET 0x800000
4361 #define BAR_ME_REGISTER 0x450000
4365 #define PCI_CONFIG_2_BAR1_SIZE (0xfL<<0)
4366 #define PCI_CONFIG_2_BAR1_SIZE_DISABLED (0L<<0)
4367 #define PCI_CONFIG_2_BAR1_SIZE_64K (1L<<0)
4368 #define PCI_CONFIG_2_BAR1_SIZE_128K (2L<<0)
4369 #define PCI_CONFIG_2_BAR1_SIZE_256K (3L<<0)
4370 #define PCI_CONFIG_2_BAR1_SIZE_512K (4L<<0)
4371 #define PCI_CONFIG_2_BAR1_SIZE_1M (5L<<0)
4372 #define PCI_CONFIG_2_BAR1_SIZE_2M (6L<<0)
4373 #define PCI_CONFIG_2_BAR1_SIZE_4M (7L<<0)
4374 #define PCI_CONFIG_2_BAR1_SIZE_8M (8L<<0)
4375 #define PCI_CONFIG_2_BAR1_SIZE_16M (9L<<0)
4376 #define PCI_CONFIG_2_BAR1_SIZE_32M (10L<<0)
4377 #define PCI_CONFIG_2_BAR1_SIZE_64M (11L<<0)
4378 #define PCI_CONFIG_2_BAR1_SIZE_128M (12L<<0)
4379 #define PCI_CONFIG_2_BAR1_SIZE_256M (13L<<0)
4380 #define PCI_CONFIG_2_BAR1_SIZE_512M (14L<<0)
4381 #define PCI_CONFIG_2_BAR1_SIZE_1G (15L<<0)
4382 #define PCI_CONFIG_2_BAR1_64ENA (1L<<4)
4383 #define PCI_CONFIG_2_EXP_ROM_RETRY (1L<<5)
4384 #define PCI_CONFIG_2_CFG_CYCLE_RETRY (1L<<6)
4385 #define PCI_CONFIG_2_FIRST_CFG_DONE (1L<<7)
4386 #define PCI_CONFIG_2_EXP_ROM_SIZE (0xffL<<8)
4387 #define PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0L<<8)
4388 #define PCI_CONFIG_2_EXP_ROM_SIZE_2K (1L<<8)
4389 #define PCI_CONFIG_2_EXP_ROM_SIZE_4K (2L<<8)
4390 #define PCI_CONFIG_2_EXP_ROM_SIZE_8K (3L<<8)
4391 #define PCI_CONFIG_2_EXP_ROM_SIZE_16K (4L<<8)
4392 #define PCI_CONFIG_2_EXP_ROM_SIZE_32K (5L<<8)
4393 #define PCI_CONFIG_2_EXP_ROM_SIZE_64K (6L<<8)
4394 #define PCI_CONFIG_2_EXP_ROM_SIZE_128K (7L<<8)
4395 #define PCI_CONFIG_2_EXP_ROM_SIZE_256K (8L<<8)
4396 #define PCI_CONFIG_2_EXP_ROM_SIZE_512K (9L<<8)
4397 #define PCI_CONFIG_2_EXP_ROM_SIZE_1M (10L<<8)
4398 #define PCI_CONFIG_2_EXP_ROM_SIZE_2M (11L<<8)
4399 #define PCI_CONFIG_2_EXP_ROM_SIZE_4M (12L<<8)
4400 #define PCI_CONFIG_2_EXP_ROM_SIZE_8M (13L<<8)
4401 #define PCI_CONFIG_2_EXP_ROM_SIZE_16M (14L<<8)
4402 #define PCI_CONFIG_2_EXP_ROM_SIZE_32M (15L<<8)
4403 #define PCI_CONFIG_2_BAR_PREFETCH (1L<<16)
4404 #define PCI_CONFIG_2_RESERVED0 (0x7fffL<<17)
4406 /* config_3 offset */
4407 #define GRC_CONFIG_3_SIZE_REG (0x40c)
4408 #define PCI_CONFIG_3_STICKY_BYTE (0xffL<<0)
4409 #define PCI_CONFIG_3_FORCE_PME (1L<<24)
4410 #define PCI_CONFIG_3_PME_STATUS (1L<<25)
4411 #define PCI_CONFIG_3_PME_ENABLE (1L<<26)
4412 #define PCI_CONFIG_3_PM_STATE (0x3L<<27)
4413 #define PCI_CONFIG_3_VAUX_PRESET (1L<<30)
4414 #define PCI_CONFIG_3_PCI_POWER (1L<<31)
4416 /* config_2 offset */
4417 #define GRC_CONFIG_2_SIZE_REG 0x408
4419 #define GRC_BAR2_CONFIG 0x4e0
4420 #define PCI_CONFIG_2_BAR2_SIZE (0xfL<<0)
4421 #define PCI_CONFIG_2_BAR2_SIZE_DISABLED (0L<<0)
4422 #define PCI_CONFIG_2_BAR2_SIZE_64K (1L<<0)
4423 #define PCI_CONFIG_2_BAR2_SIZE_128K (2L<<0)
4424 #define PCI_CONFIG_2_BAR2_SIZE_256K (3L<<0)
4425 #define PCI_CONFIG_2_BAR2_SIZE_512K (4L<<0)
4426 #define PCI_CONFIG_2_BAR2_SIZE_1M (5L<<0)
4427 #define PCI_CONFIG_2_BAR2_SIZE_2M (6L<<0)
4428 #define PCI_CONFIG_2_BAR2_SIZE_4M (7L<<0)
4429 #define PCI_CONFIG_2_BAR2_SIZE_8M (8L<<0)
4430 #define PCI_CONFIG_2_BAR2_SIZE_16M (9L<<0)
4431 #define PCI_CONFIG_2_BAR2_SIZE_32M (10L<<0)
4432 #define PCI_CONFIG_2_BAR2_SIZE_64M (11L<<0)
4433 #define PCI_CONFIG_2_BAR2_SIZE_128M (12L<<0)
4434 #define PCI_CONFIG_2_BAR2_SIZE_256M (13L<<0)
4435 #define PCI_CONFIG_2_BAR2_SIZE_512M (14L<<0)
4436 #define PCI_CONFIG_2_BAR2_SIZE_1G (15L<<0)
4437 #define PCI_CONFIG_2_BAR2_64ENA (1L<<4)
4439 #define PCI_PM_DATA_A (0x410)
4440 #define PCI_PM_DATA_B (0x414)
4441 #define PCI_ID_VAL1 (0x434)
4442 #define PCI_ID_VAL2 (0x438)
4444 #define MDIO_REG_BANK_CL73_IEEEB0 0x0
4445 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL 0x0
4446 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN 0x0200
4447 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN 0x1000
4448 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST 0x8000
4450 #define MDIO_REG_BANK_CL73_IEEEB1 0x10
4451 #define MDIO_CL73_IEEEB1_AN_ADV2 0x01
4452 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M 0x0000
4453 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX 0x0020
4454 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 0x0040
4455 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR 0x0080
4457 #define MDIO_REG_BANK_RX0 0x80b0
4458 #define MDIO_RX0_RX_EQ_BOOST 0x1c
4459 #define MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
4460 #define MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL 0x10
4462 #define MDIO_REG_BANK_RX1 0x80c0
4463 #define MDIO_RX1_RX_EQ_BOOST 0x1c
4464 #define MDIO_RX1_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
4465 #define MDIO_RX1_RX_EQ_BOOST_OFFSET_CTRL 0x10
4467 #define MDIO_REG_BANK_RX2 0x80d0
4468 #define MDIO_RX2_RX_EQ_BOOST 0x1c
4469 #define MDIO_RX2_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
4470 #define MDIO_RX2_RX_EQ_BOOST_OFFSET_CTRL 0x10
4472 #define MDIO_REG_BANK_RX3 0x80e0
4473 #define MDIO_RX3_RX_EQ_BOOST 0x1c
4474 #define MDIO_RX3_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
4475 #define MDIO_RX3_RX_EQ_BOOST_OFFSET_CTRL 0x10
4477 #define MDIO_REG_BANK_RX_ALL 0x80f0
4478 #define MDIO_RX_ALL_RX_EQ_BOOST 0x1c
4479 #define MDIO_RX_ALL_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
4480 #define MDIO_RX_ALL_RX_EQ_BOOST_OFFSET_CTRL 0x10
4482 #define MDIO_REG_BANK_TX0 0x8060
4483 #define MDIO_TX0_TX_DRIVER 0x17
4484 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
4485 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
4486 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
4487 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
4488 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
4489 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
4490 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
4491 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
4492 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
4494 #define MDIO_REG_BANK_XGXS_BLOCK0 0x8000
4495 #define MDIO_BLOCK0_XGXS_CONTROL 0x10
4497 #define MDIO_REG_BANK_XGXS_BLOCK1 0x8010
4498 #define MDIO_BLOCK1_LANE_CTRL0 0x15
4499 #define MDIO_BLOCK1_LANE_CTRL1 0x16
4500 #define MDIO_BLOCK1_LANE_CTRL2 0x17
4501 #define MDIO_BLOCK1_LANE_PRBS 0x19
4503 #define MDIO_REG_BANK_XGXS_BLOCK2 0x8100
4504 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP 0x10
4505 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE 0x8000
4506 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE 0x4000
4507 #define MDIO_XGXS_BLOCK2_TX_LN_SWAP 0x11
4508 #define MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE 0x8000
4510 =======
4511 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G 0x14
4512 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS 0x0001
4513 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS 0x0010
4515 #define MDIO_XGXS_BLOCK2_TEST_MODE_LANE 0x15
4517 #define MDIO_REG_BANK_GP_STATUS 0x8120
4518 #define MDIO_GP_STATUS_TOP_AN_STATUS1 0x1B
4519 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE 0x0001
4520 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE 0x0002
4521 #define MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS 0x0004
4522 #define MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS 0x0008
4523 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE 0x0010
4524 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_LP_NP_BAM_ABLE 0x0020
4526 #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE 0x0040
4527 #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE 0x0080
4528 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK 0x3f00
4529 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M 0x0000
4530 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M 0x0100
4531 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G 0x0200
4532 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G 0x0300
4533 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G 0x0400
4534 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G 0x0500
4535 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG 0x0600
4536 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 0x0700
4537 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG 0x0800
4538 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G 0x0900
4539 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G 0x0A00
4540 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G 0x0B00
4541 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G 0x0C00
4542 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX 0x0D00
4543 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 0x0E00
4546 #define MDIO_REG_BANK_10G_PARALLEL_DETECT 0x8130
4547 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL 0x11
4548 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN 0x1
4549 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK 0x13
4550 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT (0xb71<<1)
4552 #define MDIO_REG_BANK_SERDES_DIGITAL 0x8300
4553 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1 0x10
4554 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE 0x0001
4555 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_TBI_IF 0x0002
4556 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN 0x0004
4557 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT 0x0008
4558 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET 0x0010
4559 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE 0x0020
4560 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2 0x11
4561 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN 0x0001
4562 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_AN_FST_TMR 0x0040
4563 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1 0x14
4564 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_DUPLEX 0x0004
4565 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_MASK 0x0018
4566 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_SHIFT 3
4567 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_2_5G 0x0018
4568 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_1G 0x0010
4569 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_100M 0x0008
4570 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_10M 0x0000
4571 #define MDIO_SERDES_DIGITAL_MISC1 0x18
4572 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_MASK 0xE000
4573 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_25M 0x0000
4574 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_100M 0x2000
4575 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_125M 0x4000
4576 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M 0x6000
4577 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_187_5M 0x8000
4578 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL 0x0010
4579 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK 0x000f
4580 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_2_5G 0x0000
4581 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_5G 0x0001
4582 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_6G 0x0002
4583 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_HIG 0x0003
4584 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4 0x0004
4585 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12G 0x0005
4586 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12_5G 0x0006
4587 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G 0x0007
4588 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_15G 0x0008
4589 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_16G 0x0009
4591 #define MDIO_REG_BANK_OVER_1G 0x8320
4592 #define MDIO_OVER_1G_DIGCTL_3_4 0x14
4593 #define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_MASK 0xffe0
4594 #define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_SHIFT 5
4595 #define MDIO_OVER_1G_UP1 0x19
4596 #define MDIO_OVER_1G_UP1_2_5G 0x0001
4597 #define MDIO_OVER_1G_UP1_5G 0x0002
4598 #define MDIO_OVER_1G_UP1_6G 0x0004
4599 #define MDIO_OVER_1G_UP1_10G 0x0010
4600 #define MDIO_OVER_1G_UP1_10GH 0x0008
4601 #define MDIO_OVER_1G_UP1_12G 0x0020
4602 #define MDIO_OVER_1G_UP1_12_5G 0x0040
4603 #define MDIO_OVER_1G_UP1_13G 0x0080
4604 #define MDIO_OVER_1G_UP1_15G 0x0100
4605 #define MDIO_OVER_1G_UP1_16G 0x0200
4606 #define MDIO_OVER_1G_UP2 0x1A
4607 #define MDIO_OVER_1G_UP2_IPREDRIVER_MASK 0x0007
4608 #define MDIO_OVER_1G_UP2_IDRIVER_MASK 0x0038
4609 #define MDIO_OVER_1G_UP2_PREEMPHASIS_MASK 0x03C0
4610 #define MDIO_OVER_1G_UP3 0x1B
4611 #define MDIO_OVER_1G_UP3_HIGIG2 0x0001
4612 #define MDIO_OVER_1G_LP_UP1 0x1C
4613 #define MDIO_OVER_1G_LP_UP2 0x1D
4614 #define MDIO_OVER_1G_LP_UP2_MR_ADV_OVER_1G_MASK 0x03ff
4615 #define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK 0x0780
4616 #define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT 7
4617 #define MDIO_OVER_1G_LP_UP3 0x1E
4619 #define MDIO_REG_BANK_BAM_NEXT_PAGE 0x8350
4620 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL 0x10
4621 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE 0x0001
4622 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN 0x0002
4624 #define MDIO_REG_BANK_CL73_USERB0 0x8370
4625 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1 0x12
4626 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN 0x8000
4627 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN 0x4000
4628 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN 0x2000
4629 #define MDIO_CL73_USERB0_CL73_BAM_CTRL3 0x14
4630 #define MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR 0x0001
4632 #define MDIO_REG_BANK_AER_BLOCK 0xFFD0
4633 #define MDIO_AER_BLOCK_AER_REG 0x1E
4635 #define MDIO_REG_BANK_COMBO_IEEE0 0xFFE0
4636 #define MDIO_COMBO_IEEE0_MII_CONTROL 0x10
4637 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK 0x2040
4638 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_10 0x0000
4639 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100 0x2000
4640 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000 0x0040
4641 #define MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX 0x0100
4642 #define MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN 0x0200
4643 #define MDIO_COMBO_IEEO_MII_CONTROL_AN_EN 0x1000
4644 #define MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK 0x4000
4645 #define MDIO_COMBO_IEEO_MII_CONTROL_RESET 0x8000
4646 #define MDIO_COMBO_IEEE0_MII_STATUS 0x11
4647 #define MDIO_COMBO_IEEE0_MII_STATUS_LINK_PASS 0x0004
4648 #define MDIO_COMBO_IEEE0_MII_STATUS_AUTONEG_COMPLETE 0x0020
4649 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV 0x14
4650 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX 0x0020
4651 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_HALF_DUPLEX 0x0040
4652 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK 0x0180
4653 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE 0x0000
4654 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC 0x0080
4655 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC 0x0100
4656 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH 0x0180
4657 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_NEXT_PAGE 0x8000
4658 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1 0x15
4659 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_NEXT_PAGE 0x8000
4660 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_ACK 0x4000
4661 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_MASK 0x0180
4662 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_NONE\
4663 0x0000
4664 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_BOTH\
4665 0x0180
4666 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_HALF_DUP_CAP 0x0040
4667 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_FULL_DUP_CAP 0x0020
4668 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_SGMII_MODE 0x0001
4672 =======
4673 #define EXT_PHY_AUTO_NEG_DEVAD 0x7
4675 #define EXT_PHY_OPT_PMA_PMD_DEVAD 0x1
4676 #define EXT_PHY_OPT_WIS_DEVAD 0x2
4677 #define EXT_PHY_OPT_PCS_DEVAD 0x3
4678 #define EXT_PHY_OPT_PHY_XS_DEVAD 0x4
4679 #define EXT_PHY_OPT_CNTL 0x0
4681 =======
4682 #define EXT_PHY_OPT_CNTL2 0x7
4684 #define EXT_PHY_OPT_PMD_RX_SD 0xa
4685 #define EXT_PHY_OPT_PMD_MISC_CNTL 0xca0a
4686 #define EXT_PHY_OPT_PHY_IDENTIFIER 0xc800
4687 #define EXT_PHY_OPT_PMD_DIGITAL_CNT 0xc808
4688 #define EXT_PHY_OPT_PMD_DIGITAL_SATUS 0xc809
4689 #define EXT_PHY_OPT_CMU_PLL_BYPASS 0xca09
4690 #define EXT_PHY_OPT_LASI_CNTL 0x9002
4691 #define EXT_PHY_OPT_RX_ALARM 0x9003
4692 #define EXT_PHY_OPT_LASI_STATUS 0x9005
4693 #define EXT_PHY_OPT_PCS_STATUS 0x0020
4694 #define EXT_PHY_OPT_XGXS_LANE_STATUS 0x0018
4696 =======
4697 #define EXT_PHY_OPT_AN_LINK_STATUS 0x8304
4698 #define EXT_PHY_OPT_AN_CL37_CL73 0x8370
4699 #define EXT_PHY_OPT_AN_CL37_FD 0xffe4
4700 #define EXT_PHY_OPT_AN_CL37_AN 0xffe0
4701 #define EXT_PHY_OPT_AN_ADV 0x11
4704 #define EXT_PHY_KR_PMA_PMD_DEVAD 0x1
4705 #define EXT_PHY_KR_PCS_DEVAD 0x3
4706 #define EXT_PHY_KR_AUTO_NEG_DEVAD 0x7
4707 #define EXT_PHY_KR_CTRL 0x0000
4709 =======
4710 #define EXT_PHY_KR_STATUS 0x0001
4711 #define EXT_PHY_KR_AUTO_NEG_COMPLETE 0x0020
4712 #define EXT_PHY_KR_AUTO_NEG_ADVERT 0x0010
4713 #define EXT_PHY_KR_AUTO_NEG_ADVERT_PAUSE 0x0400
4714 #define EXT_PHY_KR_AUTO_NEG_ADVERT_PAUSE_ASYMMETRIC 0x0800
4715 #define EXT_PHY_KR_AUTO_NEG_ADVERT_PAUSE_BOTH 0x0C00
4716 #define EXT_PHY_KR_AUTO_NEG_ADVERT_PAUSE_MASK 0x0C00
4717 #define EXT_PHY_KR_LP_AUTO_NEG 0x0013
4719 #define EXT_PHY_KR_CTRL2 0x0007
4720 #define EXT_PHY_KR_PCS_STATUS 0x0020
4721 #define EXT_PHY_KR_PMD_CTRL 0x0096
4722 #define EXT_PHY_KR_LASI_CNTL 0x9002
4723 #define EXT_PHY_KR_LASI_STATUS 0x9005
4724 #define EXT_PHY_KR_MISC_CTRL1 0xca85
4725 #define EXT_PHY_KR_GEN_CTRL 0xca10
4726 #define EXT_PHY_KR_ROM_CODE 0xca19
4728 =======
4729 #define EXT_PHY_KR_ROM_RESET_INTERNAL_MP 0x0188
4730 #define EXT_PHY_KR_ROM_MICRO_RESET 0x018a
4732 #define EXT_PHY_SFX7101_XGXS_TEST1 0xc00a