1 /*******************************************************************************
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2007 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
29 #include <linux/delay.h>
33 static s32
e1000_get_phy_cfg_done(struct e1000_hw
*hw
);
34 static s32
e1000_phy_force_speed_duplex(struct e1000_hw
*hw
);
35 static s32
e1000_set_d0_lplu_state(struct e1000_hw
*hw
, bool active
);
36 static s32
e1000_wait_autoneg(struct e1000_hw
*hw
);
38 /* Cable length tables */
39 static const u16 e1000_m88_cable_length_table
[] =
40 { 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED
};
42 static const u16 e1000_igp_2_cable_length_table
[] =
43 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,
44 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22,
45 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40,
46 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61,
47 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82,
48 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95,
49 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,
51 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
52 ARRAY_SIZE(e1000_igp_2_cable_length_table)
55 * e1000e_check_reset_block_generic - Check if PHY reset is blocked
56 * @hw: pointer to the HW structure
58 * Read the PHY management control register and check whether a PHY reset
59 * is blocked. If a reset is not blocked return 0, otherwise
60 * return E1000_BLK_PHY_RESET (12).
62 s32
e1000e_check_reset_block_generic(struct e1000_hw
*hw
)
68 return (manc
& E1000_MANC_BLK_PHY_RST_ON_IDE
) ?
69 E1000_BLK_PHY_RESET
: 0;
73 * e1000e_get_phy_id - Retrieve the PHY ID and revision
74 * @hw: pointer to the HW structure
76 * Reads the PHY registers and stores the PHY ID and possibly the PHY
77 * revision in the hardware structure.
79 s32
e1000e_get_phy_id(struct e1000_hw
*hw
)
81 struct e1000_phy_info
*phy
= &hw
->phy
;
85 ret_val
= e1e_rphy(hw
, PHY_ID1
, &phy_id
);
89 phy
->id
= (u32
)(phy_id
<< 16);
91 ret_val
= e1e_rphy(hw
, PHY_ID2
, &phy_id
);
95 phy
->id
|= (u32
)(phy_id
& PHY_REVISION_MASK
);
96 phy
->revision
= (u32
)(phy_id
& ~PHY_REVISION_MASK
);
102 * e1000e_phy_reset_dsp - Reset PHY DSP
103 * @hw: pointer to the HW structure
105 * Reset the digital signal processor.
107 s32
e1000e_phy_reset_dsp(struct e1000_hw
*hw
)
111 ret_val
= e1e_wphy(hw
, M88E1000_PHY_GEN_CONTROL
, 0xC1);
115 return e1e_wphy(hw
, M88E1000_PHY_GEN_CONTROL
, 0);
119 * e1000_read_phy_reg_mdic - Read MDI control register
120 * @hw: pointer to the HW structure
121 * @offset: register offset to be read
122 * @data: pointer to the read data
124 <<<<<<< HEAD:drivers/net/e1000e/phy.c
125 * Reads the MDI control regsiter in the PHY at offset and stores the
127 * Reads the MDI control register in the PHY at offset and stores the
128 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/net/e1000e/phy.c
129 * information read to data.
131 static s32
e1000_read_phy_reg_mdic(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
133 struct e1000_phy_info
*phy
= &hw
->phy
;
136 if (offset
> MAX_PHY_REG_ADDRESS
) {
137 hw_dbg(hw
, "PHY Address %d is out of range\n", offset
);
138 return -E1000_ERR_PARAM
;
141 /* Set up Op-code, Phy Address, and register offset in the MDI
142 * Control register. The MAC will take care of interfacing with the
143 * PHY to retrieve the desired data.
145 mdic
= ((offset
<< E1000_MDIC_REG_SHIFT
) |
146 (phy
->addr
<< E1000_MDIC_PHY_SHIFT
) |
147 (E1000_MDIC_OP_READ
));
151 /* Poll the ready bit to see if the MDI read completed */
152 for (i
= 0; i
< 64; i
++) {
155 if (mdic
& E1000_MDIC_READY
)
158 if (!(mdic
& E1000_MDIC_READY
)) {
159 hw_dbg(hw
, "MDI Read did not complete\n");
160 return -E1000_ERR_PHY
;
162 if (mdic
& E1000_MDIC_ERROR
) {
163 hw_dbg(hw
, "MDI Error\n");
164 return -E1000_ERR_PHY
;
172 * e1000_write_phy_reg_mdic - Write MDI control register
173 * @hw: pointer to the HW structure
174 * @offset: register offset to write to
175 * @data: data to write to register at offset
177 * Writes data to MDI control register in the PHY at offset.
179 static s32
e1000_write_phy_reg_mdic(struct e1000_hw
*hw
, u32 offset
, u16 data
)
181 struct e1000_phy_info
*phy
= &hw
->phy
;
184 if (offset
> MAX_PHY_REG_ADDRESS
) {
185 hw_dbg(hw
, "PHY Address %d is out of range\n", offset
);
186 return -E1000_ERR_PARAM
;
189 /* Set up Op-code, Phy Address, and register offset in the MDI
190 * Control register. The MAC will take care of interfacing with the
191 * PHY to retrieve the desired data.
193 mdic
= (((u32
)data
) |
194 (offset
<< E1000_MDIC_REG_SHIFT
) |
195 (phy
->addr
<< E1000_MDIC_PHY_SHIFT
) |
196 (E1000_MDIC_OP_WRITE
));
200 /* Poll the ready bit to see if the MDI read completed */
201 for (i
= 0; i
< E1000_GEN_POLL_TIMEOUT
; i
++) {
204 if (mdic
& E1000_MDIC_READY
)
207 if (!(mdic
& E1000_MDIC_READY
)) {
208 hw_dbg(hw
, "MDI Write did not complete\n");
209 return -E1000_ERR_PHY
;
216 * e1000e_read_phy_reg_m88 - Read m88 PHY register
217 * @hw: pointer to the HW structure
218 * @offset: register offset to be read
219 * @data: pointer to the read data
221 * Acquires semaphore, if necessary, then reads the PHY register at offset
222 * and storing the retrieved information in data. Release any acquired
223 * semaphores before exiting.
225 s32
e1000e_read_phy_reg_m88(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
229 ret_val
= hw
->phy
.ops
.acquire_phy(hw
);
233 ret_val
= e1000_read_phy_reg_mdic(hw
,
234 MAX_PHY_REG_ADDRESS
& offset
,
237 hw
->phy
.ops
.release_phy(hw
);
243 * e1000e_write_phy_reg_m88 - Write m88 PHY register
244 * @hw: pointer to the HW structure
245 * @offset: register offset to write to
246 * @data: data to write at register offset
248 * Acquires semaphore, if necessary, then writes the data to PHY register
249 * at the offset. Release any acquired semaphores before exiting.
251 s32
e1000e_write_phy_reg_m88(struct e1000_hw
*hw
, u32 offset
, u16 data
)
255 ret_val
= hw
->phy
.ops
.acquire_phy(hw
);
259 ret_val
= e1000_write_phy_reg_mdic(hw
,
260 MAX_PHY_REG_ADDRESS
& offset
,
263 hw
->phy
.ops
.release_phy(hw
);
269 * e1000e_read_phy_reg_igp - Read igp PHY register
270 * @hw: pointer to the HW structure
271 * @offset: register offset to be read
272 * @data: pointer to the read data
274 * Acquires semaphore, if necessary, then reads the PHY register at offset
275 * and storing the retrieved information in data. Release any acquired
276 * semaphores before exiting.
278 s32
e1000e_read_phy_reg_igp(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
282 ret_val
= hw
->phy
.ops
.acquire_phy(hw
);
286 if (offset
> MAX_PHY_MULTI_PAGE_REG
) {
287 ret_val
= e1000_write_phy_reg_mdic(hw
,
288 IGP01E1000_PHY_PAGE_SELECT
,
291 hw
->phy
.ops
.release_phy(hw
);
296 ret_val
= e1000_read_phy_reg_mdic(hw
,
297 MAX_PHY_REG_ADDRESS
& offset
,
300 hw
->phy
.ops
.release_phy(hw
);
306 * e1000e_write_phy_reg_igp - Write igp PHY register
307 * @hw: pointer to the HW structure
308 * @offset: register offset to write to
309 * @data: data to write at register offset
311 * Acquires semaphore, if necessary, then writes the data to PHY register
312 * at the offset. Release any acquired semaphores before exiting.
314 s32
e1000e_write_phy_reg_igp(struct e1000_hw
*hw
, u32 offset
, u16 data
)
318 ret_val
= hw
->phy
.ops
.acquire_phy(hw
);
322 if (offset
> MAX_PHY_MULTI_PAGE_REG
) {
323 ret_val
= e1000_write_phy_reg_mdic(hw
,
324 IGP01E1000_PHY_PAGE_SELECT
,
327 hw
->phy
.ops
.release_phy(hw
);
332 ret_val
= e1000_write_phy_reg_mdic(hw
,
333 MAX_PHY_REG_ADDRESS
& offset
,
336 hw
->phy
.ops
.release_phy(hw
);
342 * e1000e_read_kmrn_reg - Read kumeran register
343 * @hw: pointer to the HW structure
344 * @offset: register offset to be read
345 * @data: pointer to the read data
347 * Acquires semaphore, if necessary. Then reads the PHY register at offset
348 * using the kumeran interface. The information retrieved is stored in data.
349 * Release any acquired semaphores before exiting.
351 s32
e1000e_read_kmrn_reg(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
356 ret_val
= hw
->phy
.ops
.acquire_phy(hw
);
360 kmrnctrlsta
= ((offset
<< E1000_KMRNCTRLSTA_OFFSET_SHIFT
) &
361 E1000_KMRNCTRLSTA_OFFSET
) | E1000_KMRNCTRLSTA_REN
;
362 ew32(KMRNCTRLSTA
, kmrnctrlsta
);
366 kmrnctrlsta
= er32(KMRNCTRLSTA
);
367 *data
= (u16
)kmrnctrlsta
;
369 hw
->phy
.ops
.release_phy(hw
);
375 * e1000e_write_kmrn_reg - Write kumeran register
376 * @hw: pointer to the HW structure
377 * @offset: register offset to write to
378 * @data: data to write at register offset
380 * Acquires semaphore, if necessary. Then write the data to PHY register
381 * at the offset using the kumeran interface. Release any acquired semaphores
384 s32
e1000e_write_kmrn_reg(struct e1000_hw
*hw
, u32 offset
, u16 data
)
389 ret_val
= hw
->phy
.ops
.acquire_phy(hw
);
393 kmrnctrlsta
= ((offset
<< E1000_KMRNCTRLSTA_OFFSET_SHIFT
) &
394 E1000_KMRNCTRLSTA_OFFSET
) | data
;
395 ew32(KMRNCTRLSTA
, kmrnctrlsta
);
398 hw
->phy
.ops
.release_phy(hw
);
404 * e1000e_copper_link_setup_m88 - Setup m88 PHY's for copper link
405 * @hw: pointer to the HW structure
407 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
408 * and downshift values are set also.
410 s32
e1000e_copper_link_setup_m88(struct e1000_hw
*hw
)
412 struct e1000_phy_info
*phy
= &hw
->phy
;
416 /* Enable CRS on TX. This must be set for half-duplex operation. */
417 ret_val
= e1e_rphy(hw
, M88E1000_PHY_SPEC_CTRL
, &phy_data
);
421 phy_data
|= M88E1000_PSCR_ASSERT_CRS_ON_TX
;
424 * MDI/MDI-X = 0 (default)
425 * 0 - Auto for all speeds
428 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
430 phy_data
&= ~M88E1000_PSCR_AUTO_X_MODE
;
434 phy_data
|= M88E1000_PSCR_MDI_MANUAL_MODE
;
437 phy_data
|= M88E1000_PSCR_MDIX_MANUAL_MODE
;
440 phy_data
|= M88E1000_PSCR_AUTO_X_1000T
;
444 phy_data
|= M88E1000_PSCR_AUTO_X_MODE
;
449 * disable_polarity_correction = 0 (default)
450 * Automatic Correction for Reversed Cable Polarity
454 phy_data
&= ~M88E1000_PSCR_POLARITY_REVERSAL
;
455 if (phy
->disable_polarity_correction
== 1)
456 phy_data
|= M88E1000_PSCR_POLARITY_REVERSAL
;
458 ret_val
= e1e_wphy(hw
, M88E1000_PHY_SPEC_CTRL
, phy_data
);
462 if (phy
->revision
< 4) {
463 /* Force TX_CLK in the Extended PHY Specific Control Register
466 ret_val
= e1e_rphy(hw
, M88E1000_EXT_PHY_SPEC_CTRL
, &phy_data
);
470 phy_data
|= M88E1000_EPSCR_TX_CLK_25
;
472 if ((phy
->revision
== 2) &&
473 (phy
->id
== M88E1111_I_PHY_ID
)) {
474 /* 82573L PHY - set the downshift counter to 5x. */
475 phy_data
&= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK
;
476 phy_data
|= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X
;
478 /* Configure Master and Slave downshift values */
479 phy_data
&= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK
|
480 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK
);
481 phy_data
|= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X
|
482 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X
);
484 ret_val
= e1e_wphy(hw
, M88E1000_EXT_PHY_SPEC_CTRL
, phy_data
);
489 /* Commit the changes. */
490 ret_val
= e1000e_commit_phy(hw
);
492 hw_dbg(hw
, "Error committing the PHY changes\n");
498 * e1000e_copper_link_setup_igp - Setup igp PHY's for copper link
499 * @hw: pointer to the HW structure
501 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
504 s32
e1000e_copper_link_setup_igp(struct e1000_hw
*hw
)
506 struct e1000_phy_info
*phy
= &hw
->phy
;
510 ret_val
= e1000_phy_hw_reset(hw
);
512 hw_dbg(hw
, "Error resetting the PHY.\n");
516 /* Wait 15ms for MAC to configure PHY from NVM settings. */
519 /* disable lplu d0 during driver init */
520 ret_val
= e1000_set_d0_lplu_state(hw
, 0);
522 hw_dbg(hw
, "Error Disabling LPLU D0\n");
525 /* Configure mdi-mdix settings */
526 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CTRL
, &data
);
530 data
&= ~IGP01E1000_PSCR_AUTO_MDIX
;
534 data
&= ~IGP01E1000_PSCR_FORCE_MDI_MDIX
;
537 data
|= IGP01E1000_PSCR_FORCE_MDI_MDIX
;
541 data
|= IGP01E1000_PSCR_AUTO_MDIX
;
544 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CTRL
, data
);
548 /* set auto-master slave resolution settings */
549 if (hw
->mac
.autoneg
) {
550 /* when autonegotiation advertisement is only 1000Mbps then we
551 * should disable SmartSpeed and enable Auto MasterSlave
552 * resolution as hardware default. */
553 if (phy
->autoneg_advertised
== ADVERTISE_1000_FULL
) {
554 /* Disable SmartSpeed */
555 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
560 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
561 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
566 /* Set auto Master/Slave resolution process */
567 ret_val
= e1e_rphy(hw
, PHY_1000T_CTRL
, &data
);
571 data
&= ~CR_1000T_MS_ENABLE
;
572 ret_val
= e1e_wphy(hw
, PHY_1000T_CTRL
, data
);
577 ret_val
= e1e_rphy(hw
, PHY_1000T_CTRL
, &data
);
581 /* load defaults for future use */
582 phy
->original_ms_type
= (data
& CR_1000T_MS_ENABLE
) ?
583 ((data
& CR_1000T_MS_VALUE
) ?
584 e1000_ms_force_master
:
585 e1000_ms_force_slave
) :
588 switch (phy
->ms_type
) {
589 case e1000_ms_force_master
:
590 data
|= (CR_1000T_MS_ENABLE
| CR_1000T_MS_VALUE
);
592 case e1000_ms_force_slave
:
593 data
|= CR_1000T_MS_ENABLE
;
594 data
&= ~(CR_1000T_MS_VALUE
);
597 data
&= ~CR_1000T_MS_ENABLE
;
601 ret_val
= e1e_wphy(hw
, PHY_1000T_CTRL
, data
);
608 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
609 * @hw: pointer to the HW structure
611 * Reads the MII auto-neg advertisement register and/or the 1000T control
612 * register and if the PHY is already setup for auto-negotiation, then
613 * return successful. Otherwise, setup advertisement and flow control to
614 * the appropriate values for the wanted auto-negotiation.
616 static s32
e1000_phy_setup_autoneg(struct e1000_hw
*hw
)
618 struct e1000_phy_info
*phy
= &hw
->phy
;
620 u16 mii_autoneg_adv_reg
;
621 u16 mii_1000t_ctrl_reg
= 0;
623 phy
->autoneg_advertised
&= phy
->autoneg_mask
;
625 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
626 ret_val
= e1e_rphy(hw
, PHY_AUTONEG_ADV
, &mii_autoneg_adv_reg
);
630 if (phy
->autoneg_mask
& ADVERTISE_1000_FULL
) {
631 /* Read the MII 1000Base-T Control Register (Address 9). */
632 ret_val
= e1e_rphy(hw
, PHY_1000T_CTRL
, &mii_1000t_ctrl_reg
);
637 /* Need to parse both autoneg_advertised and fc and set up
638 * the appropriate PHY registers. First we will parse for
639 * autoneg_advertised software override. Since we can advertise
640 * a plethora of combinations, we need to check each bit
644 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
645 * Advertisement Register (Address 4) and the 1000 mb speed bits in
646 * the 1000Base-T Control Register (Address 9).
648 mii_autoneg_adv_reg
&= ~(NWAY_AR_100TX_FD_CAPS
|
649 NWAY_AR_100TX_HD_CAPS
|
650 NWAY_AR_10T_FD_CAPS
|
651 NWAY_AR_10T_HD_CAPS
);
652 mii_1000t_ctrl_reg
&= ~(CR_1000T_HD_CAPS
| CR_1000T_FD_CAPS
);
654 hw_dbg(hw
, "autoneg_advertised %x\n", phy
->autoneg_advertised
);
656 /* Do we want to advertise 10 Mb Half Duplex? */
657 if (phy
->autoneg_advertised
& ADVERTISE_10_HALF
) {
658 hw_dbg(hw
, "Advertise 10mb Half duplex\n");
659 mii_autoneg_adv_reg
|= NWAY_AR_10T_HD_CAPS
;
662 /* Do we want to advertise 10 Mb Full Duplex? */
663 if (phy
->autoneg_advertised
& ADVERTISE_10_FULL
) {
664 hw_dbg(hw
, "Advertise 10mb Full duplex\n");
665 mii_autoneg_adv_reg
|= NWAY_AR_10T_FD_CAPS
;
668 /* Do we want to advertise 100 Mb Half Duplex? */
669 if (phy
->autoneg_advertised
& ADVERTISE_100_HALF
) {
670 hw_dbg(hw
, "Advertise 100mb Half duplex\n");
671 mii_autoneg_adv_reg
|= NWAY_AR_100TX_HD_CAPS
;
674 /* Do we want to advertise 100 Mb Full Duplex? */
675 if (phy
->autoneg_advertised
& ADVERTISE_100_FULL
) {
676 hw_dbg(hw
, "Advertise 100mb Full duplex\n");
677 mii_autoneg_adv_reg
|= NWAY_AR_100TX_FD_CAPS
;
680 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
681 if (phy
->autoneg_advertised
& ADVERTISE_1000_HALF
)
682 hw_dbg(hw
, "Advertise 1000mb Half duplex request denied!\n");
684 /* Do we want to advertise 1000 Mb Full Duplex? */
685 if (phy
->autoneg_advertised
& ADVERTISE_1000_FULL
) {
686 hw_dbg(hw
, "Advertise 1000mb Full duplex\n");
687 mii_1000t_ctrl_reg
|= CR_1000T_FD_CAPS
;
690 /* Check for a software override of the flow control settings, and
691 * setup the PHY advertisement registers accordingly. If
692 * auto-negotiation is enabled, then software will have to set the
693 * "PAUSE" bits to the correct value in the Auto-Negotiation
694 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
697 * The possible values of the "fc" parameter are:
698 * 0: Flow control is completely disabled
699 * 1: Rx flow control is enabled (we can receive pause frames
700 * but not send pause frames).
701 * 2: Tx flow control is enabled (we can send pause frames
702 * but we do not support receiving pause frames).
703 * 3: Both Rx and TX flow control (symmetric) are enabled.
704 * other: No software override. The flow control configuration
705 * in the EEPROM is used.
707 switch (hw
->mac
.fc
) {
709 /* Flow control (RX & TX) is completely disabled by a
710 * software over-ride.
712 mii_autoneg_adv_reg
&= ~(NWAY_AR_ASM_DIR
| NWAY_AR_PAUSE
);
714 case e1000_fc_rx_pause
:
715 /* RX Flow control is enabled, and TX Flow control is
716 * disabled, by a software over-ride.
718 /* Since there really isn't a way to advertise that we are
719 * capable of RX Pause ONLY, we will advertise that we
720 * support both symmetric and asymmetric RX PAUSE. Later
721 * (in e1000e_config_fc_after_link_up) we will disable the
722 * hw's ability to send PAUSE frames.
724 mii_autoneg_adv_reg
|= (NWAY_AR_ASM_DIR
| NWAY_AR_PAUSE
);
726 case e1000_fc_tx_pause
:
727 /* TX Flow control is enabled, and RX Flow control is
728 * disabled, by a software over-ride.
730 mii_autoneg_adv_reg
|= NWAY_AR_ASM_DIR
;
731 mii_autoneg_adv_reg
&= ~NWAY_AR_PAUSE
;
734 /* Flow control (both RX and TX) is enabled by a software
737 mii_autoneg_adv_reg
|= (NWAY_AR_ASM_DIR
| NWAY_AR_PAUSE
);
740 hw_dbg(hw
, "Flow control param set incorrectly\n");
741 ret_val
= -E1000_ERR_CONFIG
;
745 ret_val
= e1e_wphy(hw
, PHY_AUTONEG_ADV
, mii_autoneg_adv_reg
);
749 hw_dbg(hw
, "Auto-Neg Advertising %x\n", mii_autoneg_adv_reg
);
751 if (phy
->autoneg_mask
& ADVERTISE_1000_FULL
) {
752 ret_val
= e1e_wphy(hw
, PHY_1000T_CTRL
, mii_1000t_ctrl_reg
);
759 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
760 * @hw: pointer to the HW structure
762 * Performs initial bounds checking on autoneg advertisement parameter, then
763 * configure to advertise the full capability. Setup the PHY to autoneg
764 * and restart the negotiation process between the link partner. If
765 * wait_for_link, then wait for autoneg to complete before exiting.
767 static s32
e1000_copper_link_autoneg(struct e1000_hw
*hw
)
769 struct e1000_phy_info
*phy
= &hw
->phy
;
773 /* Perform some bounds checking on the autoneg advertisement
776 phy
->autoneg_advertised
&= phy
->autoneg_mask
;
778 /* If autoneg_advertised is zero, we assume it was not defaulted
779 * by the calling code so we set to advertise full capability.
781 if (phy
->autoneg_advertised
== 0)
782 phy
->autoneg_advertised
= phy
->autoneg_mask
;
784 hw_dbg(hw
, "Reconfiguring auto-neg advertisement params\n");
785 ret_val
= e1000_phy_setup_autoneg(hw
);
787 hw_dbg(hw
, "Error Setting up Auto-Negotiation\n");
790 hw_dbg(hw
, "Restarting Auto-Neg\n");
792 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
793 * the Auto Neg Restart bit in the PHY control register.
795 ret_val
= e1e_rphy(hw
, PHY_CONTROL
, &phy_ctrl
);
799 phy_ctrl
|= (MII_CR_AUTO_NEG_EN
| MII_CR_RESTART_AUTO_NEG
);
800 ret_val
= e1e_wphy(hw
, PHY_CONTROL
, phy_ctrl
);
804 /* Does the user want to wait for Auto-Neg to complete here, or
805 * check at a later time (for example, callback routine).
807 if (phy
->wait_for_link
) {
808 ret_val
= e1000_wait_autoneg(hw
);
810 hw_dbg(hw
, "Error while waiting for "
811 "autoneg to complete\n");
816 hw
->mac
.get_link_status
= 1;
822 * e1000e_setup_copper_link - Configure copper link settings
823 * @hw: pointer to the HW structure
825 * Calls the appropriate function to configure the link for auto-neg or forced
826 * speed and duplex. Then we check for link, once link is established calls
827 * to configure collision distance and flow control are called. If link is
828 * not established, we return -E1000_ERR_PHY (-2).
830 s32
e1000e_setup_copper_link(struct e1000_hw
*hw
)
835 if (hw
->mac
.autoneg
) {
836 /* Setup autoneg and flow control advertisement and perform
837 * autonegotiation. */
838 ret_val
= e1000_copper_link_autoneg(hw
);
842 /* PHY will be set to 10H, 10F, 100H or 100F
843 * depending on user settings. */
844 hw_dbg(hw
, "Forcing Speed and Duplex\n");
845 ret_val
= e1000_phy_force_speed_duplex(hw
);
847 hw_dbg(hw
, "Error Forcing Speed and Duplex\n");
852 /* Check link status. Wait up to 100 microseconds for link to become
855 ret_val
= e1000e_phy_has_link_generic(hw
,
856 COPPER_LINK_UP_LIMIT
,
863 hw_dbg(hw
, "Valid link established!!!\n");
864 e1000e_config_collision_dist(hw
);
865 ret_val
= e1000e_config_fc_after_link_up(hw
);
867 hw_dbg(hw
, "Unable to establish link!!!\n");
874 * e1000e_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
875 * @hw: pointer to the HW structure
877 * Calls the PHY setup function to force speed and duplex. Clears the
878 * auto-crossover to force MDI manually. Waits for link and returns
879 * successful if link up is successful, else -E1000_ERR_PHY (-2).
881 s32
e1000e_phy_force_speed_duplex_igp(struct e1000_hw
*hw
)
883 struct e1000_phy_info
*phy
= &hw
->phy
;
888 ret_val
= e1e_rphy(hw
, PHY_CONTROL
, &phy_data
);
892 e1000e_phy_force_speed_duplex_setup(hw
, &phy_data
);
894 ret_val
= e1e_wphy(hw
, PHY_CONTROL
, phy_data
);
898 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
899 * forced whenever speed and duplex are forced.
901 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CTRL
, &phy_data
);
905 phy_data
&= ~IGP01E1000_PSCR_AUTO_MDIX
;
906 phy_data
&= ~IGP01E1000_PSCR_FORCE_MDI_MDIX
;
908 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CTRL
, phy_data
);
912 hw_dbg(hw
, "IGP PSCR: %X\n", phy_data
);
916 if (phy
->wait_for_link
) {
917 hw_dbg(hw
, "Waiting for forced speed/duplex link on IGP phy.\n");
919 ret_val
= e1000e_phy_has_link_generic(hw
,
927 hw_dbg(hw
, "Link taking longer than expected.\n");
930 ret_val
= e1000e_phy_has_link_generic(hw
,
942 * e1000e_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
943 * @hw: pointer to the HW structure
945 * Calls the PHY setup function to force speed and duplex. Clears the
946 * auto-crossover to force MDI manually. Resets the PHY to commit the
947 * changes. If time expires while waiting for link up, we reset the DSP.
948 * After reset, TX_CLK and CRS on TX must be set. Return successful upon
949 * successful completion, else return corresponding error code.
951 s32
e1000e_phy_force_speed_duplex_m88(struct e1000_hw
*hw
)
953 struct e1000_phy_info
*phy
= &hw
->phy
;
958 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
959 * forced whenever speed and duplex are forced.
961 ret_val
= e1e_rphy(hw
, M88E1000_PHY_SPEC_CTRL
, &phy_data
);
965 phy_data
&= ~M88E1000_PSCR_AUTO_X_MODE
;
966 ret_val
= e1e_wphy(hw
, M88E1000_PHY_SPEC_CTRL
, phy_data
);
970 hw_dbg(hw
, "M88E1000 PSCR: %X\n", phy_data
);
972 ret_val
= e1e_rphy(hw
, PHY_CONTROL
, &phy_data
);
976 e1000e_phy_force_speed_duplex_setup(hw
, &phy_data
);
978 /* Reset the phy to commit changes. */
979 phy_data
|= MII_CR_RESET
;
981 ret_val
= e1e_wphy(hw
, PHY_CONTROL
, phy_data
);
987 if (phy
->wait_for_link
) {
988 hw_dbg(hw
, "Waiting for forced speed/duplex link on M88 phy.\n");
990 ret_val
= e1000e_phy_has_link_generic(hw
, PHY_FORCE_LIMIT
,
996 /* We didn't get link.
997 * Reset the DSP and cross our fingers.
999 ret_val
= e1e_wphy(hw
, M88E1000_PHY_PAGE_SELECT
, 0x001d);
1002 ret_val
= e1000e_phy_reset_dsp(hw
);
1008 ret_val
= e1000e_phy_has_link_generic(hw
, PHY_FORCE_LIMIT
,
1014 ret_val
= e1e_rphy(hw
, M88E1000_EXT_PHY_SPEC_CTRL
, &phy_data
);
1018 /* Resetting the phy means we need to re-force TX_CLK in the
1019 * Extended PHY Specific Control Register to 25MHz clock from
1020 * the reset value of 2.5MHz.
1022 phy_data
|= M88E1000_EPSCR_TX_CLK_25
;
1023 ret_val
= e1e_wphy(hw
, M88E1000_EXT_PHY_SPEC_CTRL
, phy_data
);
1027 /* In addition, we must re-enable CRS on Tx for both half and full
1030 ret_val
= e1e_rphy(hw
, M88E1000_PHY_SPEC_CTRL
, &phy_data
);
1034 phy_data
|= M88E1000_PSCR_ASSERT_CRS_ON_TX
;
1035 ret_val
= e1e_wphy(hw
, M88E1000_PHY_SPEC_CTRL
, phy_data
);
1041 * e1000e_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
1042 * @hw: pointer to the HW structure
1043 * @phy_ctrl: pointer to current value of PHY_CONTROL
1045 * Forces speed and duplex on the PHY by doing the following: disable flow
1046 * control, force speed/duplex on the MAC, disable auto speed detection,
1047 * disable auto-negotiation, configure duplex, configure speed, configure
1048 * the collision distance, write configuration to CTRL register. The
1049 * caller must write to the PHY_CONTROL register for these settings to
1052 void e1000e_phy_force_speed_duplex_setup(struct e1000_hw
*hw
, u16
*phy_ctrl
)
1054 struct e1000_mac_info
*mac
= &hw
->mac
;
1057 /* Turn off flow control when forcing speed/duplex */
1058 mac
->fc
= e1000_fc_none
;
1060 /* Force speed/duplex on the mac */
1062 ctrl
|= (E1000_CTRL_FRCSPD
| E1000_CTRL_FRCDPX
);
1063 ctrl
&= ~E1000_CTRL_SPD_SEL
;
1065 /* Disable Auto Speed Detection */
1066 ctrl
&= ~E1000_CTRL_ASDE
;
1068 /* Disable autoneg on the phy */
1069 *phy_ctrl
&= ~MII_CR_AUTO_NEG_EN
;
1071 /* Forcing Full or Half Duplex? */
1072 if (mac
->forced_speed_duplex
& E1000_ALL_HALF_DUPLEX
) {
1073 ctrl
&= ~E1000_CTRL_FD
;
1074 *phy_ctrl
&= ~MII_CR_FULL_DUPLEX
;
1075 hw_dbg(hw
, "Half Duplex\n");
1077 ctrl
|= E1000_CTRL_FD
;
1078 *phy_ctrl
|= MII_CR_FULL_DUPLEX
;
1079 hw_dbg(hw
, "Full Duplex\n");
1082 /* Forcing 10mb or 100mb? */
1083 if (mac
->forced_speed_duplex
& E1000_ALL_100_SPEED
) {
1084 ctrl
|= E1000_CTRL_SPD_100
;
1085 *phy_ctrl
|= MII_CR_SPEED_100
;
1086 *phy_ctrl
&= ~(MII_CR_SPEED_1000
| MII_CR_SPEED_10
);
1087 hw_dbg(hw
, "Forcing 100mb\n");
1089 ctrl
&= ~(E1000_CTRL_SPD_1000
| E1000_CTRL_SPD_100
);
1090 *phy_ctrl
|= MII_CR_SPEED_10
;
1091 *phy_ctrl
&= ~(MII_CR_SPEED_1000
| MII_CR_SPEED_100
);
1092 hw_dbg(hw
, "Forcing 10mb\n");
1095 e1000e_config_collision_dist(hw
);
1101 * e1000e_set_d3_lplu_state - Sets low power link up state for D3
1102 * @hw: pointer to the HW structure
1103 * @active: boolean used to enable/disable lplu
1105 * Success returns 0, Failure returns 1
1107 * The low power link up (lplu) state is set to the power management level D3
1108 * and SmartSpeed is disabled when active is true, else clear lplu for D3
1109 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1110 * is used during Dx states where the power conservation is most important.
1111 * During driver activity, SmartSpeed should be enabled so performance is
1114 s32
e1000e_set_d3_lplu_state(struct e1000_hw
*hw
, bool active
)
1116 struct e1000_phy_info
*phy
= &hw
->phy
;
1120 ret_val
= e1e_rphy(hw
, IGP02E1000_PHY_POWER_MGMT
, &data
);
1125 data
&= ~IGP02E1000_PM_D3_LPLU
;
1126 ret_val
= e1e_wphy(hw
,
1127 IGP02E1000_PHY_POWER_MGMT
,
1131 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
1132 * during Dx states where the power conservation is most
1133 * important. During driver activity we should enable
1134 * SmartSpeed, so performance is maintained. */
1135 if (phy
->smart_speed
== e1000_smart_speed_on
) {
1136 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
1141 data
|= IGP01E1000_PSCFR_SMART_SPEED
;
1142 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
1146 } else if (phy
->smart_speed
== e1000_smart_speed_off
) {
1147 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
1152 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
1153 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
1158 } else if ((phy
->autoneg_advertised
== E1000_ALL_SPEED_DUPLEX
) ||
1159 (phy
->autoneg_advertised
== E1000_ALL_NOT_GIG
) ||
1160 (phy
->autoneg_advertised
== E1000_ALL_10_SPEED
)) {
1161 data
|= IGP02E1000_PM_D3_LPLU
;
1162 ret_val
= e1e_wphy(hw
, IGP02E1000_PHY_POWER_MGMT
, data
);
1166 /* When LPLU is enabled, we should disable SmartSpeed */
1167 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
, &data
);
1171 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
1172 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
, data
);
1179 <<<<<<< HEAD:drivers/net/e1000e/phy.c
1180 * e1000e_check_downshift - Checks whether a downshift in speed occured
1182 * e1000e_check_downshift - Checks whether a downshift in speed occurred
1183 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/net/e1000e/phy.c
1184 * @hw: pointer to the HW structure
1186 * Success returns 0, Failure returns 1
1188 * A downshift is detected by querying the PHY link health.
1190 s32
e1000e_check_downshift(struct e1000_hw
*hw
)
1192 struct e1000_phy_info
*phy
= &hw
->phy
;
1194 u16 phy_data
, offset
, mask
;
1196 switch (phy
->type
) {
1198 case e1000_phy_gg82563
:
1199 offset
= M88E1000_PHY_SPEC_STATUS
;
1200 mask
= M88E1000_PSSR_DOWNSHIFT
;
1202 case e1000_phy_igp_2
:
1203 case e1000_phy_igp_3
:
1204 offset
= IGP01E1000_PHY_LINK_HEALTH
;
1205 mask
= IGP01E1000_PLHR_SS_DOWNGRADE
;
1208 /* speed downshift not supported */
1209 phy
->speed_downgraded
= 0;
1213 ret_val
= e1e_rphy(hw
, offset
, &phy_data
);
1216 phy
->speed_downgraded
= (phy_data
& mask
);
1222 * e1000_check_polarity_m88 - Checks the polarity.
1223 * @hw: pointer to the HW structure
1225 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1227 * Polarity is determined based on the PHY specific status register.
1229 static s32
e1000_check_polarity_m88(struct e1000_hw
*hw
)
1231 struct e1000_phy_info
*phy
= &hw
->phy
;
1235 ret_val
= e1e_rphy(hw
, M88E1000_PHY_SPEC_STATUS
, &data
);
1238 phy
->cable_polarity
= (data
& M88E1000_PSSR_REV_POLARITY
)
1239 ? e1000_rev_polarity_reversed
1240 : e1000_rev_polarity_normal
;
1246 * e1000_check_polarity_igp - Checks the polarity.
1247 * @hw: pointer to the HW structure
1249 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1251 * Polarity is determined based on the PHY port status register, and the
1252 * current speed (since there is no polarity at 100Mbps).
1254 static s32
e1000_check_polarity_igp(struct e1000_hw
*hw
)
1256 struct e1000_phy_info
*phy
= &hw
->phy
;
1258 u16 data
, offset
, mask
;
1260 /* Polarity is determined based on the speed of
1261 * our connection. */
1262 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_STATUS
, &data
);
1266 if ((data
& IGP01E1000_PSSR_SPEED_MASK
) ==
1267 IGP01E1000_PSSR_SPEED_1000MBPS
) {
1268 offset
= IGP01E1000_PHY_PCS_INIT_REG
;
1269 mask
= IGP01E1000_PHY_POLARITY_MASK
;
1271 /* This really only applies to 10Mbps since
1272 * there is no polarity for 100Mbps (always 0).
1274 offset
= IGP01E1000_PHY_PORT_STATUS
;
1275 mask
= IGP01E1000_PSSR_POLARITY_REVERSED
;
1278 ret_val
= e1e_rphy(hw
, offset
, &data
);
1281 phy
->cable_polarity
= (data
& mask
)
1282 ? e1000_rev_polarity_reversed
1283 : e1000_rev_polarity_normal
;
1289 * e1000_wait_autoneg - Wait for auto-neg compeletion
1290 * @hw: pointer to the HW structure
1292 * Waits for auto-negotiation to complete or for the auto-negotiation time
1293 * limit to expire, which ever happens first.
1295 static s32
e1000_wait_autoneg(struct e1000_hw
*hw
)
1300 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
1301 for (i
= PHY_AUTO_NEG_LIMIT
; i
> 0; i
--) {
1302 ret_val
= e1e_rphy(hw
, PHY_STATUS
, &phy_status
);
1305 ret_val
= e1e_rphy(hw
, PHY_STATUS
, &phy_status
);
1308 if (phy_status
& MII_SR_AUTONEG_COMPLETE
)
1313 /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
1320 * e1000e_phy_has_link_generic - Polls PHY for link
1321 * @hw: pointer to the HW structure
1322 * @iterations: number of times to poll for link
1323 * @usec_interval: delay between polling attempts
1324 * @success: pointer to whether polling was successful or not
1326 * Polls the PHY status register for link, 'iterations' number of times.
1328 s32
e1000e_phy_has_link_generic(struct e1000_hw
*hw
, u32 iterations
,
1329 u32 usec_interval
, bool *success
)
1334 for (i
= 0; i
< iterations
; i
++) {
1335 /* Some PHYs require the PHY_STATUS register to be read
1336 * twice due to the link bit being sticky. No harm doing
1337 * it across the board.
1339 ret_val
= e1e_rphy(hw
, PHY_STATUS
, &phy_status
);
1342 ret_val
= e1e_rphy(hw
, PHY_STATUS
, &phy_status
);
1345 if (phy_status
& MII_SR_LINK_STATUS
)
1347 if (usec_interval
>= 1000)
1348 mdelay(usec_interval
/1000);
1350 udelay(usec_interval
);
1353 *success
= (i
< iterations
);
1359 * e1000e_get_cable_length_m88 - Determine cable length for m88 PHY
1360 * @hw: pointer to the HW structure
1362 * Reads the PHY specific status register to retrieve the cable length
1363 * information. The cable length is determined by averaging the minimum and
1364 * maximum values to get the "average" cable length. The m88 PHY has four
1365 * possible cable length values, which are:
1366 * Register Value Cable Length
1370 * 3 110 - 140 meters
1373 s32
e1000e_get_cable_length_m88(struct e1000_hw
*hw
)
1375 struct e1000_phy_info
*phy
= &hw
->phy
;
1377 u16 phy_data
, index
;
1379 ret_val
= e1e_rphy(hw
, M88E1000_PHY_SPEC_STATUS
, &phy_data
);
1383 index
= (phy_data
& M88E1000_PSSR_CABLE_LENGTH
) >>
1384 M88E1000_PSSR_CABLE_LENGTH_SHIFT
;
1385 phy
->min_cable_length
= e1000_m88_cable_length_table
[index
];
1386 phy
->max_cable_length
= e1000_m88_cable_length_table
[index
+1];
1388 phy
->cable_length
= (phy
->min_cable_length
+ phy
->max_cable_length
) / 2;
1394 * e1000e_get_cable_length_igp_2 - Determine cable length for igp2 PHY
1395 * @hw: pointer to the HW structure
1397 * The automatic gain control (agc) normalizes the amplitude of the
1398 * received signal, adjusting for the attenuation produced by the
1399 <<<<<<< HEAD:drivers/net/e1000e/phy.c
1400 * cable. By reading the AGC registers, which reperesent the
1401 * cobination of course and fine gain value, the value can be put
1403 * cable. By reading the AGC registers, which represent the
1404 * combination of course and fine gain value, the value can be put
1405 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/net/e1000e/phy.c
1406 * into a lookup table to obtain the approximate cable length
1409 s32
e1000e_get_cable_length_igp_2(struct e1000_hw
*hw
)
1411 struct e1000_phy_info
*phy
= &hw
->phy
;
1413 u16 phy_data
, i
, agc_value
= 0;
1414 u16 cur_agc_index
, max_agc_index
= 0;
1415 u16 min_agc_index
= IGP02E1000_CABLE_LENGTH_TABLE_SIZE
- 1;
1416 u16 agc_reg_array
[IGP02E1000_PHY_CHANNEL_NUM
] =
1417 {IGP02E1000_PHY_AGC_A
,
1418 IGP02E1000_PHY_AGC_B
,
1419 IGP02E1000_PHY_AGC_C
,
1420 IGP02E1000_PHY_AGC_D
};
1422 /* Read the AGC registers for all channels */
1423 for (i
= 0; i
< IGP02E1000_PHY_CHANNEL_NUM
; i
++) {
1424 ret_val
= e1e_rphy(hw
, agc_reg_array
[i
], &phy_data
);
1428 /* Getting bits 15:9, which represent the combination of
1429 * course and fine gain values. The result is a number
1430 * that can be put into the lookup table to obtain the
1431 * approximate cable length. */
1432 cur_agc_index
= (phy_data
>> IGP02E1000_AGC_LENGTH_SHIFT
) &
1433 IGP02E1000_AGC_LENGTH_MASK
;
1435 /* Array index bound check. */
1436 if ((cur_agc_index
>= IGP02E1000_CABLE_LENGTH_TABLE_SIZE
) ||
1437 (cur_agc_index
== 0))
1438 return -E1000_ERR_PHY
;
1440 /* Remove min & max AGC values from calculation. */
1441 if (e1000_igp_2_cable_length_table
[min_agc_index
] >
1442 e1000_igp_2_cable_length_table
[cur_agc_index
])
1443 min_agc_index
= cur_agc_index
;
1444 if (e1000_igp_2_cable_length_table
[max_agc_index
] <
1445 e1000_igp_2_cable_length_table
[cur_agc_index
])
1446 max_agc_index
= cur_agc_index
;
1448 agc_value
+= e1000_igp_2_cable_length_table
[cur_agc_index
];
1451 agc_value
-= (e1000_igp_2_cable_length_table
[min_agc_index
] +
1452 e1000_igp_2_cable_length_table
[max_agc_index
]);
1453 agc_value
/= (IGP02E1000_PHY_CHANNEL_NUM
- 2);
1455 /* Calculate cable length with the error range of +/- 10 meters. */
1456 phy
->min_cable_length
= ((agc_value
- IGP02E1000_AGC_RANGE
) > 0) ?
1457 (agc_value
- IGP02E1000_AGC_RANGE
) : 0;
1458 phy
->max_cable_length
= agc_value
+ IGP02E1000_AGC_RANGE
;
1460 phy
->cable_length
= (phy
->min_cable_length
+ phy
->max_cable_length
) / 2;
1466 * e1000e_get_phy_info_m88 - Retrieve PHY information
1467 * @hw: pointer to the HW structure
1469 * Valid for only copper links. Read the PHY status register (sticky read)
1470 * to verify that link is up. Read the PHY special control register to
1471 * determine the polarity and 10base-T extended distance. Read the PHY
1472 * special status register to determine MDI/MDIx and current speed. If
1473 * speed is 1000, then determine cable length, local and remote receiver.
1475 s32
e1000e_get_phy_info_m88(struct e1000_hw
*hw
)
1477 struct e1000_phy_info
*phy
= &hw
->phy
;
1482 if (hw
->media_type
!= e1000_media_type_copper
) {
1483 hw_dbg(hw
, "Phy info is only valid for copper media\n");
1484 return -E1000_ERR_CONFIG
;
1487 ret_val
= e1000e_phy_has_link_generic(hw
, 1, 0, &link
);
1492 hw_dbg(hw
, "Phy info is only valid if link is up\n");
1493 return -E1000_ERR_CONFIG
;
1496 ret_val
= e1e_rphy(hw
, M88E1000_PHY_SPEC_CTRL
, &phy_data
);
1500 phy
->polarity_correction
= (phy_data
&
1501 M88E1000_PSCR_POLARITY_REVERSAL
);
1503 ret_val
= e1000_check_polarity_m88(hw
);
1507 ret_val
= e1e_rphy(hw
, M88E1000_PHY_SPEC_STATUS
, &phy_data
);
1511 phy
->is_mdix
= (phy_data
& M88E1000_PSSR_MDIX
);
1513 if ((phy_data
& M88E1000_PSSR_SPEED
) == M88E1000_PSSR_1000MBS
) {
1514 ret_val
= e1000_get_cable_length(hw
);
1518 ret_val
= e1e_rphy(hw
, PHY_1000T_STATUS
, &phy_data
);
1522 phy
->local_rx
= (phy_data
& SR_1000T_LOCAL_RX_STATUS
)
1523 ? e1000_1000t_rx_status_ok
1524 : e1000_1000t_rx_status_not_ok
;
1526 phy
->remote_rx
= (phy_data
& SR_1000T_REMOTE_RX_STATUS
)
1527 ? e1000_1000t_rx_status_ok
1528 : e1000_1000t_rx_status_not_ok
;
1530 /* Set values to "undefined" */
1531 phy
->cable_length
= E1000_CABLE_LENGTH_UNDEFINED
;
1532 phy
->local_rx
= e1000_1000t_rx_status_undefined
;
1533 phy
->remote_rx
= e1000_1000t_rx_status_undefined
;
1540 * e1000e_get_phy_info_igp - Retrieve igp PHY information
1541 * @hw: pointer to the HW structure
1543 * Read PHY status to determine if link is up. If link is up, then
1544 * set/determine 10base-T extended distance and polarity correction. Read
1545 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
1546 * determine on the cable length, local and remote receiver.
1548 s32
e1000e_get_phy_info_igp(struct e1000_hw
*hw
)
1550 struct e1000_phy_info
*phy
= &hw
->phy
;
1555 ret_val
= e1000e_phy_has_link_generic(hw
, 1, 0, &link
);
1560 hw_dbg(hw
, "Phy info is only valid if link is up\n");
1561 return -E1000_ERR_CONFIG
;
1564 phy
->polarity_correction
= 1;
1566 ret_val
= e1000_check_polarity_igp(hw
);
1570 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_STATUS
, &data
);
1574 phy
->is_mdix
= (data
& IGP01E1000_PSSR_MDIX
);
1576 if ((data
& IGP01E1000_PSSR_SPEED_MASK
) ==
1577 IGP01E1000_PSSR_SPEED_1000MBPS
) {
1578 ret_val
= e1000_get_cable_length(hw
);
1582 ret_val
= e1e_rphy(hw
, PHY_1000T_STATUS
, &data
);
1586 phy
->local_rx
= (data
& SR_1000T_LOCAL_RX_STATUS
)
1587 ? e1000_1000t_rx_status_ok
1588 : e1000_1000t_rx_status_not_ok
;
1590 phy
->remote_rx
= (data
& SR_1000T_REMOTE_RX_STATUS
)
1591 ? e1000_1000t_rx_status_ok
1592 : e1000_1000t_rx_status_not_ok
;
1594 phy
->cable_length
= E1000_CABLE_LENGTH_UNDEFINED
;
1595 phy
->local_rx
= e1000_1000t_rx_status_undefined
;
1596 phy
->remote_rx
= e1000_1000t_rx_status_undefined
;
1603 * e1000e_phy_sw_reset - PHY software reset
1604 * @hw: pointer to the HW structure
1606 * Does a software reset of the PHY by reading the PHY control register and
1607 * setting/write the control register reset bit to the PHY.
1609 s32
e1000e_phy_sw_reset(struct e1000_hw
*hw
)
1614 ret_val
= e1e_rphy(hw
, PHY_CONTROL
, &phy_ctrl
);
1618 phy_ctrl
|= MII_CR_RESET
;
1619 ret_val
= e1e_wphy(hw
, PHY_CONTROL
, phy_ctrl
);
1629 * e1000e_phy_hw_reset_generic - PHY hardware reset
1630 * @hw: pointer to the HW structure
1632 * Verify the reset block is not blocking us from resetting. Acquire
1633 * semaphore (if necessary) and read/set/write the device control reset
1634 * bit in the PHY. Wait the appropriate delay time for the device to
1635 <<<<<<< HEAD:drivers/net/e1000e/phy.c
1636 * reset and relase the semaphore (if necessary).
1638 * reset and release the semaphore (if necessary).
1639 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/net/e1000e/phy.c
1641 s32
e1000e_phy_hw_reset_generic(struct e1000_hw
*hw
)
1643 struct e1000_phy_info
*phy
= &hw
->phy
;
1647 ret_val
= e1000_check_reset_block(hw
);
1651 ret_val
= phy
->ops
.acquire_phy(hw
);
1656 ew32(CTRL
, ctrl
| E1000_CTRL_PHY_RST
);
1659 udelay(phy
->reset_delay_us
);
1666 phy
->ops
.release_phy(hw
);
1668 return e1000_get_phy_cfg_done(hw
);
1672 * e1000e_get_cfg_done - Generic configuration done
1673 * @hw: pointer to the HW structure
1675 * Generic function to wait 10 milli-seconds for configuration to complete
1676 * and return success.
1678 s32
e1000e_get_cfg_done(struct e1000_hw
*hw
)
1684 /* Internal function pointers */
1687 * e1000_get_phy_cfg_done - Generic PHY configuration done
1688 * @hw: pointer to the HW structure
1690 * Return success if silicon family did not implement a family specific
1691 * get_cfg_done function.
1693 static s32
e1000_get_phy_cfg_done(struct e1000_hw
*hw
)
1695 if (hw
->phy
.ops
.get_cfg_done
)
1696 return hw
->phy
.ops
.get_cfg_done(hw
);
1702 * e1000_phy_force_speed_duplex - Generic force PHY speed/duplex
1703 * @hw: pointer to the HW structure
1705 * When the silicon family has not implemented a forced speed/duplex
1706 * function for the PHY, simply return 0.
1708 static s32
e1000_phy_force_speed_duplex(struct e1000_hw
*hw
)
1710 if (hw
->phy
.ops
.force_speed_duplex
)
1711 return hw
->phy
.ops
.force_speed_duplex(hw
);
1717 * e1000e_get_phy_type_from_id - Get PHY type from id
1718 * @phy_id: phy_id read from the phy
1720 * Returns the phy type from the id.
1722 enum e1000_phy_type
e1000e_get_phy_type_from_id(u32 phy_id
)
1724 enum e1000_phy_type phy_type
= e1000_phy_unknown
;
1727 case M88E1000_I_PHY_ID
:
1728 case M88E1000_E_PHY_ID
:
1729 case M88E1111_I_PHY_ID
:
1730 case M88E1011_I_PHY_ID
:
1731 phy_type
= e1000_phy_m88
;
1733 case IGP01E1000_I_PHY_ID
: /* IGP 1 & 2 share this */
1734 phy_type
= e1000_phy_igp_2
;
1736 case GG82563_E_PHY_ID
:
1737 phy_type
= e1000_phy_gg82563
;
1739 case IGP03E1000_E_PHY_ID
:
1740 phy_type
= e1000_phy_igp_3
;
1743 case IFE_PLUS_E_PHY_ID
:
1744 case IFE_C_E_PHY_ID
:
1745 phy_type
= e1000_phy_ife
;
1748 phy_type
= e1000_phy_unknown
;
1755 * e1000e_commit_phy - Soft PHY reset
1756 * @hw: pointer to the HW structure
1758 * Performs a soft PHY reset on those that apply. This is a function pointer
1759 * entry point called by drivers.
1761 s32
e1000e_commit_phy(struct e1000_hw
*hw
)
1763 if (hw
->phy
.ops
.commit_phy
)
1764 return hw
->phy
.ops
.commit_phy(hw
);
1770 * e1000_set_d0_lplu_state - Sets low power link up state for D0
1771 * @hw: pointer to the HW structure
1772 * @active: boolean used to enable/disable lplu
1774 * Success returns 0, Failure returns 1
1776 * The low power link up (lplu) state is set to the power management level D0
1777 * and SmartSpeed is disabled when active is true, else clear lplu for D0
1778 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1779 * is used during Dx states where the power conservation is most important.
1780 * During driver activity, SmartSpeed should be enabled so performance is
1781 * maintained. This is a function pointer entry point called by drivers.
1783 static s32
e1000_set_d0_lplu_state(struct e1000_hw
*hw
, bool active
)
1785 if (hw
->phy
.ops
.set_d0_lplu_state
)
1786 return hw
->phy
.ops
.set_d0_lplu_state(hw
, active
);