?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Merge git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
[wrt350n-kernel.git] / drivers / net / igb / igb_ethtool.c
blobbcd3fd7ef04fb05f049139625fdc1bea79d687da
1 /*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 /* ethtool support for igb */
29
30 #include <linux/vmalloc.h>
31 #include <linux/netdevice.h>
32 #include <linux/pci.h>
33 #include <linux/delay.h>
34 #include <linux/interrupt.h>
35 #include <linux/if_ether.h>
36 #include <linux/ethtool.h>
37
38 #include "igb.h"
39
40 struct igb_stats {
41 char stat_string[ETH_GSTRING_LEN];
42 int sizeof_stat;
43 int stat_offset;
44 };
45
46 <<<<<<< HEAD:drivers/net/igb/igb_ethtool.c
47 #define IGB_STAT(m) sizeof(((struct igb_adapter *)0)->m), \
48 =======
49 #define IGB_STAT(m) FIELD_SIZEOF(struct igb_adapter, m), \
50 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/net/igb/igb_ethtool.c
51 offsetof(struct igb_adapter, m)
52 static const struct igb_stats igb_gstrings_stats[] = {
53 { "rx_packets", IGB_STAT(stats.gprc) },
54 { "tx_packets", IGB_STAT(stats.gptc) },
55 { "rx_bytes", IGB_STAT(stats.gorc) },
56 { "tx_bytes", IGB_STAT(stats.gotc) },
57 { "rx_broadcast", IGB_STAT(stats.bprc) },
58 { "tx_broadcast", IGB_STAT(stats.bptc) },
59 { "rx_multicast", IGB_STAT(stats.mprc) },
60 { "tx_multicast", IGB_STAT(stats.mptc) },
61 { "rx_errors", IGB_STAT(net_stats.rx_errors) },
62 { "tx_errors", IGB_STAT(net_stats.tx_errors) },
63 { "tx_dropped", IGB_STAT(net_stats.tx_dropped) },
64 { "multicast", IGB_STAT(stats.mprc) },
65 { "collisions", IGB_STAT(stats.colc) },
66 { "rx_length_errors", IGB_STAT(net_stats.rx_length_errors) },
67 { "rx_over_errors", IGB_STAT(net_stats.rx_over_errors) },
68 { "rx_crc_errors", IGB_STAT(stats.crcerrs) },
69 { "rx_frame_errors", IGB_STAT(net_stats.rx_frame_errors) },
70 { "rx_no_buffer_count", IGB_STAT(stats.rnbc) },
71 { "rx_missed_errors", IGB_STAT(stats.mpc) },
72 { "tx_aborted_errors", IGB_STAT(stats.ecol) },
73 { "tx_carrier_errors", IGB_STAT(stats.tncrs) },
74 { "tx_fifo_errors", IGB_STAT(net_stats.tx_fifo_errors) },
75 { "tx_heartbeat_errors", IGB_STAT(net_stats.tx_heartbeat_errors) },
76 { "tx_window_errors", IGB_STAT(stats.latecol) },
77 { "tx_abort_late_coll", IGB_STAT(stats.latecol) },
78 { "tx_deferred_ok", IGB_STAT(stats.dc) },
79 { "tx_single_coll_ok", IGB_STAT(stats.scc) },
80 { "tx_multi_coll_ok", IGB_STAT(stats.mcc) },
81 { "tx_timeout_count", IGB_STAT(tx_timeout_count) },
82 { "tx_restart_queue", IGB_STAT(restart_queue) },
83 { "rx_long_length_errors", IGB_STAT(stats.roc) },
84 { "rx_short_length_errors", IGB_STAT(stats.ruc) },
85 { "rx_align_errors", IGB_STAT(stats.algnerrc) },
86 { "tx_tcp_seg_good", IGB_STAT(stats.tsctc) },
87 { "tx_tcp_seg_failed", IGB_STAT(stats.tsctfc) },
88 { "rx_flow_control_xon", IGB_STAT(stats.xonrxc) },
89 { "rx_flow_control_xoff", IGB_STAT(stats.xoffrxc) },
90 { "tx_flow_control_xon", IGB_STAT(stats.xontxc) },
91 { "tx_flow_control_xoff", IGB_STAT(stats.xofftxc) },
92 { "rx_long_byte_count", IGB_STAT(stats.gorc) },
93 { "rx_csum_offload_good", IGB_STAT(hw_csum_good) },
94 { "rx_csum_offload_errors", IGB_STAT(hw_csum_err) },
95 { "rx_header_split", IGB_STAT(rx_hdr_split) },
96 { "alloc_rx_buff_failed", IGB_STAT(alloc_rx_buff_failed) },
97 { "tx_smbus", IGB_STAT(stats.mgptc) },
98 { "rx_smbus", IGB_STAT(stats.mgprc) },
99 { "dropped_smbus", IGB_STAT(stats.mgpdc) },
100 };
101
102 #define IGB_QUEUE_STATS_LEN \
103 ((((((struct igb_adapter *)netdev->priv)->num_rx_queues > 1) ? \
104 ((struct igb_adapter *)netdev->priv)->num_rx_queues : 0) + \
105 (((((struct igb_adapter *)netdev->priv)->num_tx_queues > 1) ? \
106 ((struct igb_adapter *)netdev->priv)->num_tx_queues : 0))) * \
107 (sizeof(struct igb_queue_stats) / sizeof(u64)))
108 #define IGB_GLOBAL_STATS_LEN \
109 sizeof(igb_gstrings_stats) / sizeof(struct igb_stats)
110 #define IGB_STATS_LEN (IGB_GLOBAL_STATS_LEN + IGB_QUEUE_STATS_LEN)
111 static const char igb_gstrings_test[][ETH_GSTRING_LEN] = {
112 "Register test (offline)", "Eeprom test (offline)",
113 "Interrupt test (offline)", "Loopback test (offline)",
114 "Link test (on/offline)"
115 };
116 #define IGB_TEST_LEN sizeof(igb_gstrings_test) / ETH_GSTRING_LEN
117
118 static int igb_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
119 {
120 struct igb_adapter *adapter = netdev_priv(netdev);
121 struct e1000_hw *hw = &adapter->hw;
122
123 if (hw->phy.media_type == e1000_media_type_copper) {
124
125 ecmd->supported = (SUPPORTED_10baseT_Half |
126 SUPPORTED_10baseT_Full |
127 SUPPORTED_100baseT_Half |
128 SUPPORTED_100baseT_Full |
129 SUPPORTED_1000baseT_Full|
130 SUPPORTED_Autoneg |
131 SUPPORTED_TP);
132 ecmd->advertising = ADVERTISED_TP;
133
134 if (hw->mac.autoneg == 1) {
135 ecmd->advertising |= ADVERTISED_Autoneg;
136 /* the e1000 autoneg seems to match ethtool nicely */
137 ecmd->advertising |= hw->phy.autoneg_advertised;
138 }
139
140 ecmd->port = PORT_TP;
141 ecmd->phy_address = hw->phy.addr;
142 } else {
143 ecmd->supported = (SUPPORTED_1000baseT_Full |
144 SUPPORTED_FIBRE |
145 SUPPORTED_Autoneg);
146
147 ecmd->advertising = (ADVERTISED_1000baseT_Full |
148 ADVERTISED_FIBRE |
149 ADVERTISED_Autoneg);
150
151 ecmd->port = PORT_FIBRE;
152 }
153
154 ecmd->transceiver = XCVR_INTERNAL;
155
156 if (rd32(E1000_STATUS) & E1000_STATUS_LU) {
157
158 adapter->hw.mac.ops.get_speed_and_duplex(hw,
159 &adapter->link_speed,
160 &adapter->link_duplex);
161 ecmd->speed = adapter->link_speed;
162
163 /* unfortunately FULL_DUPLEX != DUPLEX_FULL
164 * and HALF_DUPLEX != DUPLEX_HALF */
165
166 if (adapter->link_duplex == FULL_DUPLEX)
167 ecmd->duplex = DUPLEX_FULL;
168 else
169 ecmd->duplex = DUPLEX_HALF;
170 } else {
171 ecmd->speed = -1;
172 ecmd->duplex = -1;
173 }
174
175 ecmd->autoneg = ((hw->phy.media_type == e1000_media_type_fiber) ||
176 hw->mac.autoneg) ? AUTONEG_ENABLE : AUTONEG_DISABLE;
177 return 0;
178 }
179
180 static int igb_set_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
181 {
182 struct igb_adapter *adapter = netdev_priv(netdev);
183 struct e1000_hw *hw = &adapter->hw;
184
185 /* When SoL/IDER sessions are active, autoneg/speed/duplex
186 * cannot be changed */
187 if (igb_check_reset_block(hw)) {
188 dev_err(&adapter->pdev->dev, "Cannot change link "
189 "characteristics when SoL/IDER is active.\n");
190 return -EINVAL;
191 }
192
193 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
194 msleep(1);
195
196 if (ecmd->autoneg == AUTONEG_ENABLE) {
197 hw->mac.autoneg = 1;
198 if (hw->phy.media_type == e1000_media_type_fiber)
199 hw->phy.autoneg_advertised = ADVERTISED_1000baseT_Full |
200 ADVERTISED_FIBRE |
201 ADVERTISED_Autoneg;
202 else
203 hw->phy.autoneg_advertised = ecmd->advertising |
204 ADVERTISED_TP |
205 ADVERTISED_Autoneg;
206 ecmd->advertising = hw->phy.autoneg_advertised;
207 } else
208 if (igb_set_spd_dplx(adapter, ecmd->speed + ecmd->duplex)) {
209 clear_bit(__IGB_RESETTING, &adapter->state);
210 return -EINVAL;
211 }
212
213 /* reset the link */
214
215 if (netif_running(adapter->netdev)) {
216 igb_down(adapter);
217 igb_up(adapter);
218 } else
219 igb_reset(adapter);
220
221 clear_bit(__IGB_RESETTING, &adapter->state);
222 return 0;
223 }
224
225 static void igb_get_pauseparam(struct net_device *netdev,
226 struct ethtool_pauseparam *pause)
227 {
228 struct igb_adapter *adapter = netdev_priv(netdev);
229 struct e1000_hw *hw = &adapter->hw;
230
231 pause->autoneg =
232 (adapter->fc_autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE);
233
234 if (hw->fc.type == e1000_fc_rx_pause)
235 pause->rx_pause = 1;
236 else if (hw->fc.type == e1000_fc_tx_pause)
237 pause->tx_pause = 1;
238 else if (hw->fc.type == e1000_fc_full) {
239 pause->rx_pause = 1;
240 pause->tx_pause = 1;
241 }
242 }
243
244 static int igb_set_pauseparam(struct net_device *netdev,
245 struct ethtool_pauseparam *pause)
246 {
247 struct igb_adapter *adapter = netdev_priv(netdev);
248 struct e1000_hw *hw = &adapter->hw;
249 int retval = 0;
250
251 adapter->fc_autoneg = pause->autoneg;
252
253 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
254 msleep(1);
255
256 if (pause->rx_pause && pause->tx_pause)
257 hw->fc.type = e1000_fc_full;
258 else if (pause->rx_pause && !pause->tx_pause)
259 hw->fc.type = e1000_fc_rx_pause;
260 else if (!pause->rx_pause && pause->tx_pause)
261 hw->fc.type = e1000_fc_tx_pause;
262 else if (!pause->rx_pause && !pause->tx_pause)
263 hw->fc.type = e1000_fc_none;
264
265 hw->fc.original_type = hw->fc.type;
266
267 if (adapter->fc_autoneg == AUTONEG_ENABLE) {
268 if (netif_running(adapter->netdev)) {
269 igb_down(adapter);
270 igb_up(adapter);
271 } else
272 igb_reset(adapter);
273 } else
274 retval = ((hw->phy.media_type == e1000_media_type_fiber) ?
275 igb_setup_link(hw) : igb_force_mac_fc(hw));
276
277 clear_bit(__IGB_RESETTING, &adapter->state);
278 return retval;
279 }
280
281 static u32 igb_get_rx_csum(struct net_device *netdev)
282 {
283 struct igb_adapter *adapter = netdev_priv(netdev);
284 return adapter->rx_csum;
285 }
286
287 static int igb_set_rx_csum(struct net_device *netdev, u32 data)
288 {
289 struct igb_adapter *adapter = netdev_priv(netdev);
290 adapter->rx_csum = data;
291
292 return 0;
293 }
294
295 static u32 igb_get_tx_csum(struct net_device *netdev)
296 {
297 return (netdev->features & NETIF_F_HW_CSUM) != 0;
298 }
299
300 static int igb_set_tx_csum(struct net_device *netdev, u32 data)
301 {
302 if (data)
303 netdev->features |= NETIF_F_HW_CSUM;
304 else
305 netdev->features &= ~NETIF_F_HW_CSUM;
306
307 return 0;
308 }
309
310 static int igb_set_tso(struct net_device *netdev, u32 data)
311 {
312 struct igb_adapter *adapter = netdev_priv(netdev);
313
314 if (data)
315 netdev->features |= NETIF_F_TSO;
316 else
317 netdev->features &= ~NETIF_F_TSO;
318
319 if (data)
320 netdev->features |= NETIF_F_TSO6;
321 else
322 netdev->features &= ~NETIF_F_TSO6;
323
324 dev_info(&adapter->pdev->dev, "TSO is %s\n",
325 data ? "Enabled" : "Disabled");
326 return 0;
327 }
328
329 static u32 igb_get_msglevel(struct net_device *netdev)
330 {
331 struct igb_adapter *adapter = netdev_priv(netdev);
332 return adapter->msg_enable;
333 }
334
335 static void igb_set_msglevel(struct net_device *netdev, u32 data)
336 {
337 struct igb_adapter *adapter = netdev_priv(netdev);
338 adapter->msg_enable = data;
339 }
340
341 static int igb_get_regs_len(struct net_device *netdev)
342 {
343 #define IGB_REGS_LEN 551
344 return IGB_REGS_LEN * sizeof(u32);
345 }
346
347 static void igb_get_regs(struct net_device *netdev,
348 struct ethtool_regs *regs, void *p)
349 {
350 struct igb_adapter *adapter = netdev_priv(netdev);
351 struct e1000_hw *hw = &adapter->hw;
352 u32 *regs_buff = p;
353 u8 i;
354
355 memset(p, 0, IGB_REGS_LEN * sizeof(u32));
356
357 regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id;
358
359 /* General Registers */
360 regs_buff[0] = rd32(E1000_CTRL);
361 regs_buff[1] = rd32(E1000_STATUS);
362 regs_buff[2] = rd32(E1000_CTRL_EXT);
363 regs_buff[3] = rd32(E1000_MDIC);
364 regs_buff[4] = rd32(E1000_SCTL);
365 regs_buff[5] = rd32(E1000_CONNSW);
366 regs_buff[6] = rd32(E1000_VET);
367 regs_buff[7] = rd32(E1000_LEDCTL);
368 regs_buff[8] = rd32(E1000_PBA);
369 regs_buff[9] = rd32(E1000_PBS);
370 regs_buff[10] = rd32(E1000_FRTIMER);
371 regs_buff[11] = rd32(E1000_TCPTIMER);
372
373 /* NVM Register */
374 regs_buff[12] = rd32(E1000_EECD);
375
376 /* Interrupt */
377 regs_buff[13] = rd32(E1000_EICR);
378 regs_buff[14] = rd32(E1000_EICS);
379 regs_buff[15] = rd32(E1000_EIMS);
380 regs_buff[16] = rd32(E1000_EIMC);
381 regs_buff[17] = rd32(E1000_EIAC);
382 regs_buff[18] = rd32(E1000_EIAM);
383 regs_buff[19] = rd32(E1000_ICR);
384 regs_buff[20] = rd32(E1000_ICS);
385 regs_buff[21] = rd32(E1000_IMS);
386 regs_buff[22] = rd32(E1000_IMC);
387 regs_buff[23] = rd32(E1000_IAC);
388 regs_buff[24] = rd32(E1000_IAM);
389 regs_buff[25] = rd32(E1000_IMIRVP);
390
391 /* Flow Control */
392 regs_buff[26] = rd32(E1000_FCAL);
393 regs_buff[27] = rd32(E1000_FCAH);
394 regs_buff[28] = rd32(E1000_FCTTV);
395 regs_buff[29] = rd32(E1000_FCRTL);
396 regs_buff[30] = rd32(E1000_FCRTH);
397 regs_buff[31] = rd32(E1000_FCRTV);
398
399 /* Receive */
400 regs_buff[32] = rd32(E1000_RCTL);
401 regs_buff[33] = rd32(E1000_RXCSUM);
402 regs_buff[34] = rd32(E1000_RLPML);
403 regs_buff[35] = rd32(E1000_RFCTL);
404 regs_buff[36] = rd32(E1000_MRQC);
405 regs_buff[37] = rd32(E1000_VMD_CTL);
406
407 /* Transmit */
408 regs_buff[38] = rd32(E1000_TCTL);
409 regs_buff[39] = rd32(E1000_TCTL_EXT);
410 regs_buff[40] = rd32(E1000_TIPG);
411 regs_buff[41] = rd32(E1000_DTXCTL);
412
413 /* Wake Up */
414 regs_buff[42] = rd32(E1000_WUC);
415 regs_buff[43] = rd32(E1000_WUFC);
416 regs_buff[44] = rd32(E1000_WUS);
417 regs_buff[45] = rd32(E1000_IPAV);
418 regs_buff[46] = rd32(E1000_WUPL);
419
420 /* MAC */
421 regs_buff[47] = rd32(E1000_PCS_CFG0);
422 regs_buff[48] = rd32(E1000_PCS_LCTL);
423 regs_buff[49] = rd32(E1000_PCS_LSTAT);
424 regs_buff[50] = rd32(E1000_PCS_ANADV);
425 regs_buff[51] = rd32(E1000_PCS_LPAB);
426 regs_buff[52] = rd32(E1000_PCS_NPTX);
427 regs_buff[53] = rd32(E1000_PCS_LPABNP);
428
429 /* Statistics */
430 regs_buff[54] = adapter->stats.crcerrs;
431 regs_buff[55] = adapter->stats.algnerrc;
432 regs_buff[56] = adapter->stats.symerrs;
433 regs_buff[57] = adapter->stats.rxerrc;
434 regs_buff[58] = adapter->stats.mpc;
435 regs_buff[59] = adapter->stats.scc;
436 regs_buff[60] = adapter->stats.ecol;
437 regs_buff[61] = adapter->stats.mcc;
438 regs_buff[62] = adapter->stats.latecol;
439 regs_buff[63] = adapter->stats.colc;
440 regs_buff[64] = adapter->stats.dc;
441 regs_buff[65] = adapter->stats.tncrs;
442 regs_buff[66] = adapter->stats.sec;
443 regs_buff[67] = adapter->stats.htdpmc;
444 regs_buff[68] = adapter->stats.rlec;
445 regs_buff[69] = adapter->stats.xonrxc;
446 regs_buff[70] = adapter->stats.xontxc;
447 regs_buff[71] = adapter->stats.xoffrxc;
448 regs_buff[72] = adapter->stats.xofftxc;
449 regs_buff[73] = adapter->stats.fcruc;
450 regs_buff[74] = adapter->stats.prc64;
451 regs_buff[75] = adapter->stats.prc127;
452 regs_buff[76] = adapter->stats.prc255;
453 regs_buff[77] = adapter->stats.prc511;
454 regs_buff[78] = adapter->stats.prc1023;
455 regs_buff[79] = adapter->stats.prc1522;
456 regs_buff[80] = adapter->stats.gprc;
457 regs_buff[81] = adapter->stats.bprc;
458 regs_buff[82] = adapter->stats.mprc;
459 regs_buff[83] = adapter->stats.gptc;
460 regs_buff[84] = adapter->stats.gorc;
461 regs_buff[86] = adapter->stats.gotc;
462 regs_buff[88] = adapter->stats.rnbc;
463 regs_buff[89] = adapter->stats.ruc;
464 regs_buff[90] = adapter->stats.rfc;
465 regs_buff[91] = adapter->stats.roc;
466 regs_buff[92] = adapter->stats.rjc;
467 regs_buff[93] = adapter->stats.mgprc;
468 regs_buff[94] = adapter->stats.mgpdc;
469 regs_buff[95] = adapter->stats.mgptc;
470 regs_buff[96] = adapter->stats.tor;
471 regs_buff[98] = adapter->stats.tot;
472 regs_buff[100] = adapter->stats.tpr;
473 regs_buff[101] = adapter->stats.tpt;
474 regs_buff[102] = adapter->stats.ptc64;
475 regs_buff[103] = adapter->stats.ptc127;
476 regs_buff[104] = adapter->stats.ptc255;
477 regs_buff[105] = adapter->stats.ptc511;
478 regs_buff[106] = adapter->stats.ptc1023;
479 regs_buff[107] = adapter->stats.ptc1522;
480 regs_buff[108] = adapter->stats.mptc;
481 regs_buff[109] = adapter->stats.bptc;
482 regs_buff[110] = adapter->stats.tsctc;
483 regs_buff[111] = adapter->stats.iac;
484 regs_buff[112] = adapter->stats.rpthc;
485 regs_buff[113] = adapter->stats.hgptc;
486 regs_buff[114] = adapter->stats.hgorc;
487 regs_buff[116] = adapter->stats.hgotc;
488 regs_buff[118] = adapter->stats.lenerrs;
489 regs_buff[119] = adapter->stats.scvpc;
490 regs_buff[120] = adapter->stats.hrmpc;
491
492 /* These should probably be added to e1000_regs.h instead */
493 #define E1000_PSRTYPE_REG(_i) (0x05480 + ((_i) * 4))
494 #define E1000_RAL(_i) (0x05400 + ((_i) * 8))
495 #define E1000_RAH(_i) (0x05404 + ((_i) * 8))
496 #define E1000_IP4AT_REG(_i) (0x05840 + ((_i) * 8))
497 #define E1000_IP6AT_REG(_i) (0x05880 + ((_i) * 4))
498 #define E1000_WUPM_REG(_i) (0x05A00 + ((_i) * 4))
499 #define E1000_FFMT_REG(_i) (0x09000 + ((_i) * 8))
500 #define E1000_FFVT_REG(_i) (0x09800 + ((_i) * 8))
501 #define E1000_FFLT_REG(_i) (0x05F00 + ((_i) * 8))
502
503 for (i = 0; i < 4; i++)
504 regs_buff[121 + i] = rd32(E1000_SRRCTL(i));
505 for (i = 0; i < 4; i++)
506 regs_buff[125 + i] = rd32(E1000_PSRTYPE_REG(i));
507 for (i = 0; i < 4; i++)
508 regs_buff[129 + i] = rd32(E1000_RDBAL(i));
509 for (i = 0; i < 4; i++)
510 regs_buff[133 + i] = rd32(E1000_RDBAH(i));
511 for (i = 0; i < 4; i++)
512 regs_buff[137 + i] = rd32(E1000_RDLEN(i));
513 for (i = 0; i < 4; i++)
514 regs_buff[141 + i] = rd32(E1000_RDH(i));
515 for (i = 0; i < 4; i++)
516 regs_buff[145 + i] = rd32(E1000_RDT(i));
517 for (i = 0; i < 4; i++)
518 regs_buff[149 + i] = rd32(E1000_RXDCTL(i));
519
520 for (i = 0; i < 10; i++)
521 regs_buff[153 + i] = rd32(E1000_EITR(i));
522 for (i = 0; i < 8; i++)
523 regs_buff[163 + i] = rd32(E1000_IMIR(i));
524 for (i = 0; i < 8; i++)
525 regs_buff[171 + i] = rd32(E1000_IMIREXT(i));
526 for (i = 0; i < 16; i++)
527 regs_buff[179 + i] = rd32(E1000_RAL(i));
528 for (i = 0; i < 16; i++)
529 regs_buff[195 + i] = rd32(E1000_RAH(i));
530
531 for (i = 0; i < 4; i++)
532 regs_buff[211 + i] = rd32(E1000_TDBAL(i));
533 for (i = 0; i < 4; i++)
534 regs_buff[215 + i] = rd32(E1000_TDBAH(i));
535 for (i = 0; i < 4; i++)
536 regs_buff[219 + i] = rd32(E1000_TDLEN(i));
537 for (i = 0; i < 4; i++)
538 regs_buff[223 + i] = rd32(E1000_TDH(i));
539 for (i = 0; i < 4; i++)
540 regs_buff[227 + i] = rd32(E1000_TDT(i));
541 for (i = 0; i < 4; i++)
542 regs_buff[231 + i] = rd32(E1000_TXDCTL(i));
543 for (i = 0; i < 4; i++)
544 regs_buff[235 + i] = rd32(E1000_TDWBAL(i));
545 for (i = 0; i < 4; i++)
546 regs_buff[239 + i] = rd32(E1000_TDWBAH(i));
547 for (i = 0; i < 4; i++)
548 regs_buff[243 + i] = rd32(E1000_DCA_TXCTRL(i));
549
550 for (i = 0; i < 4; i++)
551 regs_buff[247 + i] = rd32(E1000_IP4AT_REG(i));
552 for (i = 0; i < 4; i++)
553 regs_buff[251 + i] = rd32(E1000_IP6AT_REG(i));
554 for (i = 0; i < 32; i++)
555 regs_buff[255 + i] = rd32(E1000_WUPM_REG(i));
556 for (i = 0; i < 128; i++)
557 regs_buff[287 + i] = rd32(E1000_FFMT_REG(i));
558 for (i = 0; i < 128; i++)
559 regs_buff[415 + i] = rd32(E1000_FFVT_REG(i));
560 for (i = 0; i < 4; i++)
561 regs_buff[543 + i] = rd32(E1000_FFLT_REG(i));
562
563 regs_buff[547] = rd32(E1000_TDFH);
564 regs_buff[548] = rd32(E1000_TDFT);
565 regs_buff[549] = rd32(E1000_TDFHS);
566 regs_buff[550] = rd32(E1000_TDFPC);
567
568 }
569
570 static int igb_get_eeprom_len(struct net_device *netdev)
571 {
572 struct igb_adapter *adapter = netdev_priv(netdev);
573 return adapter->hw.nvm.word_size * 2;
574 }
575
576 static int igb_get_eeprom(struct net_device *netdev,
577 struct ethtool_eeprom *eeprom, u8 *bytes)
578 {
579 struct igb_adapter *adapter = netdev_priv(netdev);
580 struct e1000_hw *hw = &adapter->hw;
581 u16 *eeprom_buff;
582 int first_word, last_word;
583 int ret_val = 0;
584 u16 i;
585
586 if (eeprom->len == 0)
587 return -EINVAL;
588
589 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
590
591 first_word = eeprom->offset >> 1;
592 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
593
594 eeprom_buff = kmalloc(sizeof(u16) *
595 (last_word - first_word + 1), GFP_KERNEL);
596 if (!eeprom_buff)
597 return -ENOMEM;
598
599 if (hw->nvm.type == e1000_nvm_eeprom_spi)
600 ret_val = hw->nvm.ops.read_nvm(hw, first_word,
601 last_word - first_word + 1,
602 eeprom_buff);
603 else {
604 for (i = 0; i < last_word - first_word + 1; i++) {
605 ret_val = hw->nvm.ops.read_nvm(hw, first_word + i, 1,
606 &eeprom_buff[i]);
607 if (ret_val)
608 break;
609 }
610 }
611
612 /* Device's eeprom is always little-endian, word addressable */
613 for (i = 0; i < last_word - first_word + 1; i++)
614 le16_to_cpus(&eeprom_buff[i]);
615
616 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1),
617 eeprom->len);
618 kfree(eeprom_buff);
619
620 return ret_val;
621 }
622
623 static int igb_set_eeprom(struct net_device *netdev,
624 struct ethtool_eeprom *eeprom, u8 *bytes)
625 {
626 struct igb_adapter *adapter = netdev_priv(netdev);
627 struct e1000_hw *hw = &adapter->hw;
628 u16 *eeprom_buff;
629 void *ptr;
630 int max_len, first_word, last_word, ret_val = 0;
631 u16 i;
632
633 if (eeprom->len == 0)
634 return -EOPNOTSUPP;
635
636 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
637 return -EFAULT;
638
639 max_len = hw->nvm.word_size * 2;
640
641 first_word = eeprom->offset >> 1;
642 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
643 eeprom_buff = kmalloc(max_len, GFP_KERNEL);
644 if (!eeprom_buff)
645 return -ENOMEM;
646
647 ptr = (void *)eeprom_buff;
648
649 if (eeprom->offset & 1) {
650 /* need read/modify/write of first changed EEPROM word */
651 /* only the second byte of the word is being modified */
652 ret_val = hw->nvm.ops.read_nvm(hw, first_word, 1,
653 &eeprom_buff[0]);
654 ptr++;
655 }
656 if (((eeprom->offset + eeprom->len) & 1) && (ret_val == 0)) {
657 /* need read/modify/write of last changed EEPROM word */
658 /* only the first byte of the word is being modified */
659 ret_val = hw->nvm.ops.read_nvm(hw, last_word, 1,
660 &eeprom_buff[last_word - first_word]);
661 }
662
663 /* Device's eeprom is always little-endian, word addressable */
664 for (i = 0; i < last_word - first_word + 1; i++)
665 le16_to_cpus(&eeprom_buff[i]);
666
667 memcpy(ptr, bytes, eeprom->len);
668
669 for (i = 0; i < last_word - first_word + 1; i++)
670 eeprom_buff[i] = cpu_to_le16(eeprom_buff[i]);
671
672 ret_val = hw->nvm.ops.write_nvm(hw, first_word,
673 last_word - first_word + 1, eeprom_buff);
674
675 /* Update the checksum over the first part of the EEPROM if needed
676 * and flush shadow RAM for 82573 controllers */
677 if ((ret_val == 0) && ((first_word <= NVM_CHECKSUM_REG)))
678 igb_update_nvm_checksum(hw);
679
680 kfree(eeprom_buff);
681 return ret_val;
682 }
683
684 static void igb_get_drvinfo(struct net_device *netdev,
685 struct ethtool_drvinfo *drvinfo)
686 {
687 struct igb_adapter *adapter = netdev_priv(netdev);
688 char firmware_version[32];
689 u16 eeprom_data;
690
691 strncpy(drvinfo->driver, igb_driver_name, 32);
692 strncpy(drvinfo->version, igb_driver_version, 32);
693
694 /* EEPROM image version # is reported as firmware version # for
695 * 82575 controllers */
696 adapter->hw.nvm.ops.read_nvm(&adapter->hw, 5, 1, &eeprom_data);
697 sprintf(firmware_version, "%d.%d-%d",
698 (eeprom_data & 0xF000) >> 12,
699 (eeprom_data & 0x0FF0) >> 4,
700 eeprom_data & 0x000F);
701
702 strncpy(drvinfo->fw_version, firmware_version, 32);
703 strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32);
704 drvinfo->n_stats = IGB_STATS_LEN;
705 drvinfo->testinfo_len = IGB_TEST_LEN;
706 drvinfo->regdump_len = igb_get_regs_len(netdev);
707 drvinfo->eedump_len = igb_get_eeprom_len(netdev);
708 }
709
710 static void igb_get_ringparam(struct net_device *netdev,
711 struct ethtool_ringparam *ring)
712 {
713 struct igb_adapter *adapter = netdev_priv(netdev);
714 struct igb_ring *tx_ring = adapter->tx_ring;
715 struct igb_ring *rx_ring = adapter->rx_ring;
716
717 ring->rx_max_pending = IGB_MAX_RXD;
718 ring->tx_max_pending = IGB_MAX_TXD;
719 ring->rx_mini_max_pending = 0;
720 ring->rx_jumbo_max_pending = 0;
721 ring->rx_pending = rx_ring->count;
722 ring->tx_pending = tx_ring->count;
723 ring->rx_mini_pending = 0;
724 ring->rx_jumbo_pending = 0;
725 }
726
727 static int igb_set_ringparam(struct net_device *netdev,
728 struct ethtool_ringparam *ring)
729 {
730 struct igb_adapter *adapter = netdev_priv(netdev);
731 struct igb_buffer *old_buf;
732 struct igb_buffer *old_rx_buf;
733 void *old_desc;
734 int i, err;
735 u32 new_rx_count, new_tx_count, old_size;
736 dma_addr_t old_dma;
737
738 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
739 return -EINVAL;
740
741 new_rx_count = max(ring->rx_pending, (u32)IGB_MIN_RXD);
742 new_rx_count = min(new_rx_count, (u32)IGB_MAX_RXD);
743 new_rx_count = ALIGN(new_rx_count, REQ_RX_DESCRIPTOR_MULTIPLE);
744
745 new_tx_count = max(ring->tx_pending, (u32)IGB_MIN_TXD);
746 new_tx_count = min(new_tx_count, (u32)IGB_MAX_TXD);
747 new_tx_count = ALIGN(new_tx_count, REQ_TX_DESCRIPTOR_MULTIPLE);
748
749 if ((new_tx_count == adapter->tx_ring->count) &&
750 (new_rx_count == adapter->rx_ring->count)) {
751 /* nothing to do */
752 return 0;
753 }
754
755 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
756 msleep(1);
757
758 if (netif_running(adapter->netdev))
759 igb_down(adapter);
760
761 /*
762 * We can't just free everything and then setup again,
763 * because the ISRs in MSI-X mode get passed pointers
764 * to the tx and rx ring structs.
765 */
766 if (new_tx_count != adapter->tx_ring->count) {
767 for (i = 0; i < adapter->num_tx_queues; i++) {
768 /* Save existing descriptor ring */
769 old_buf = adapter->tx_ring[i].buffer_info;
770 old_desc = adapter->tx_ring[i].desc;
771 old_size = adapter->tx_ring[i].size;
772 old_dma = adapter->tx_ring[i].dma;
773 /* Try to allocate a new one */
774 adapter->tx_ring[i].buffer_info = NULL;
775 adapter->tx_ring[i].desc = NULL;
776 adapter->tx_ring[i].count = new_tx_count;
777 err = igb_setup_tx_resources(adapter,
778 &adapter->tx_ring[i]);
779 if (err) {
780 /* Restore the old one so at least
781 the adapter still works, even if
782 we failed the request */
783 adapter->tx_ring[i].buffer_info = old_buf;
784 adapter->tx_ring[i].desc = old_desc;
785 adapter->tx_ring[i].size = old_size;
786 adapter->tx_ring[i].dma = old_dma;
787 goto err_setup;
788 }
789 /* Free the old buffer manually */
790 vfree(old_buf);
791 pci_free_consistent(adapter->pdev, old_size,
792 old_desc, old_dma);
793 }
794 }
795
796 if (new_rx_count != adapter->rx_ring->count) {
797 for (i = 0; i < adapter->num_rx_queues; i++) {
798
799 old_rx_buf = adapter->rx_ring[i].buffer_info;
800 old_desc = adapter->rx_ring[i].desc;
801 old_size = adapter->rx_ring[i].size;
802 old_dma = adapter->rx_ring[i].dma;
803
804 adapter->rx_ring[i].buffer_info = NULL;
805 adapter->rx_ring[i].desc = NULL;
806 adapter->rx_ring[i].dma = 0;
807 adapter->rx_ring[i].count = new_rx_count;
808 err = igb_setup_rx_resources(adapter,
809 &adapter->rx_ring[i]);
810 if (err) {
811 adapter->rx_ring[i].buffer_info = old_rx_buf;
812 adapter->rx_ring[i].desc = old_desc;
813 adapter->rx_ring[i].size = old_size;
814 adapter->rx_ring[i].dma = old_dma;
815 goto err_setup;
816 }
817
818 vfree(old_rx_buf);
819 pci_free_consistent(adapter->pdev, old_size, old_desc,
820 old_dma);
821 }
822 }
823
824 err = 0;
825 err_setup:
826 if (netif_running(adapter->netdev))
827 igb_up(adapter);
828
829 clear_bit(__IGB_RESETTING, &adapter->state);
830 return err;
831 }
832
833 /* ethtool register test data */
834 struct igb_reg_test {
835 u16 reg;
836 u8 array_len;
837 u8 test_type;
838 u32 mask;
839 u32 write;
840 };
841
842 /* In the hardware, registers are laid out either singly, in arrays
843 * spaced 0x100 bytes apart, or in contiguous tables. We assume
844 * most tests take place on arrays or single registers (handled
845 * as a single-element array) and special-case the tables.
846 * Table tests are always pattern tests.
847 *
848 * We also make provision for some required setup steps by specifying
849 * registers to be written without any read-back testing.
850 */
851
852 #define PATTERN_TEST 1
853 #define SET_READ_TEST 2
854 #define WRITE_NO_TEST 3
855 #define TABLE32_TEST 4
856 #define TABLE64_TEST_LO 5
857 #define TABLE64_TEST_HI 6
858
859 /* default register test */
860 static struct igb_reg_test reg_test_82575[] = {
861 { E1000_FCAL, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
862 { E1000_FCAH, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
863 { E1000_FCT, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
864 { E1000_VET, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
865 { E1000_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
866 { E1000_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
867 { E1000_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
868 /* Enable all four RX queues before testing. */
869 { E1000_RXDCTL(0), 4, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
870 /* RDH is read-only for 82575, only test RDT. */
871 { E1000_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
872 { E1000_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
873 { E1000_FCRTH, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
874 { E1000_FCTTV, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
875 { E1000_TIPG, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
876 { E1000_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
877 { E1000_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
878 { E1000_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
879 { E1000_RCTL, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
880 { E1000_RCTL, 1, SET_READ_TEST, 0x04CFB3FE, 0x003FFFFB },
881 { E1000_RCTL, 1, SET_READ_TEST, 0x04CFB3FE, 0xFFFFFFFF },
882 { E1000_TCTL, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
883 { E1000_TXCW, 1, PATTERN_TEST, 0xC000FFFF, 0x0000FFFF },
884 { E1000_RA, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
885 { E1000_RA, 16, TABLE64_TEST_HI, 0x800FFFFF, 0xFFFFFFFF },
886 { E1000_MTA, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
887 { 0, 0, 0, 0 }
888 };
889
890 static bool reg_pattern_test(struct igb_adapter *adapter, u64 *data,
891 int reg, u32 mask, u32 write)
892 {
893 u32 pat, val;
894 u32 _test[] =
895 {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
896 for (pat = 0; pat < ARRAY_SIZE(_test); pat++) {
897 writel((_test[pat] & write), (adapter->hw.hw_addr + reg));
898 val = readl(adapter->hw.hw_addr + reg);
899 if (val != (_test[pat] & write & mask)) {
900 dev_err(&adapter->pdev->dev, "pattern test reg %04X "
901 "failed: got 0x%08X expected 0x%08X\n",
902 reg, val, (_test[pat] & write & mask));
903 *data = reg;
904 return 1;
905 }
906 }
907 return 0;
908 }
909
910 static bool reg_set_and_check(struct igb_adapter *adapter, u64 *data,
911 int reg, u32 mask, u32 write)
912 {
913 u32 val;
914 writel((write & mask), (adapter->hw.hw_addr + reg));
915 val = readl(adapter->hw.hw_addr + reg);
916 if ((write & mask) != (val & mask)) {
917 dev_err(&adapter->pdev->dev, "set/check reg %04X test failed:"
918 " got 0x%08X expected 0x%08X\n", reg,
919 (val & mask), (write & mask));
920 *data = reg;
921 return 1;
922 }
923 return 0;
924 }
925
926 #define REG_PATTERN_TEST(reg, mask, write) \
927 do { \
928 if (reg_pattern_test(adapter, data, reg, mask, write)) \
929 return 1; \
930 } while (0)
931
932 #define REG_SET_AND_CHECK(reg, mask, write) \
933 do { \
934 if (reg_set_and_check(adapter, data, reg, mask, write)) \
935 return 1; \
936 } while (0)
937
938 static int igb_reg_test(struct igb_adapter *adapter, u64 *data)
939 {
940 struct e1000_hw *hw = &adapter->hw;
941 struct igb_reg_test *test;
942 u32 value, before, after;
943 u32 i, toggle;
944
945 toggle = 0x7FFFF3FF;
946 test = reg_test_82575;
947
948 /* Because the status register is such a special case,
949 * we handle it separately from the rest of the register
950 * tests. Some bits are read-only, some toggle, and some
951 * are writable on newer MACs.
952 */
953 before = rd32(E1000_STATUS);
954 value = (rd32(E1000_STATUS) & toggle);
955 wr32(E1000_STATUS, toggle);
956 after = rd32(E1000_STATUS) & toggle;
957 if (value != after) {
958 dev_err(&adapter->pdev->dev, "failed STATUS register test "
959 "got: 0x%08X expected: 0x%08X\n", after, value);
960 *data = 1;
961 return 1;
962 }
963 /* restore previous status */
964 wr32(E1000_STATUS, before);
965
966 /* Perform the remainder of the register test, looping through
967 * the test table until we either fail or reach the null entry.
968 */
969 while (test->reg) {
970 for (i = 0; i < test->array_len; i++) {
971 switch (test->test_type) {
972 case PATTERN_TEST:
973 REG_PATTERN_TEST(test->reg + (i * 0x100),
974 test->mask,
975 test->write);
976 break;
977 case SET_READ_TEST:
978 REG_SET_AND_CHECK(test->reg + (i * 0x100),
979 test->mask,
980 test->write);
981 break;
982 case WRITE_NO_TEST:
983 writel(test->write,
984 (adapter->hw.hw_addr + test->reg)
985 + (i * 0x100));
986 break;
987 case TABLE32_TEST:
988 REG_PATTERN_TEST(test->reg + (i * 4),
989 test->mask,
990 test->write);
991 break;
992 case TABLE64_TEST_LO:
993 REG_PATTERN_TEST(test->reg + (i * 8),
994 test->mask,
995 test->write);
996 break;
997 case TABLE64_TEST_HI:
998 REG_PATTERN_TEST((test->reg + 4) + (i * 8),
999 test->mask,
1000 test->write);
1001 break;
1002 }
1003 }
1004 test++;
1005 }
1006
1007 *data = 0;
1008 return 0;
1009 }
1010
1011 static int igb_eeprom_test(struct igb_adapter *adapter, u64 *data)
1012 {
1013 u16 temp;
1014 u16 checksum = 0;
1015 u16 i;
1016
1017 *data = 0;
1018 /* Read and add up the contents of the EEPROM */
1019 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
1020 if ((adapter->hw.nvm.ops.read_nvm(&adapter->hw, i, 1, &temp))
1021 < 0) {
1022 *data = 1;
1023 break;
1024 }
1025 checksum += temp;
1026 }
1027
1028 /* If Checksum is not Correct return error else test passed */
1029 if ((checksum != (u16) NVM_SUM) && !(*data))
1030 *data = 2;
1031
1032 return *data;
1033 }
1034
1035 static irqreturn_t igb_test_intr(int irq, void *data)
1036 {
1037 struct net_device *netdev = (struct net_device *) data;
1038 struct igb_adapter *adapter = netdev_priv(netdev);
1039 struct e1000_hw *hw = &adapter->hw;
1040
1041 adapter->test_icr |= rd32(E1000_ICR);
1042
1043 return IRQ_HANDLED;
1044 }
1045
1046 static int igb_intr_test(struct igb_adapter *adapter, u64 *data)
1047 {
1048 struct e1000_hw *hw = &adapter->hw;
1049 struct net_device *netdev = adapter->netdev;
1050 u32 mask, i = 0, shared_int = true;
1051 u32 irq = adapter->pdev->irq;
1052
1053 *data = 0;
1054
1055 /* Hook up test interrupt handler just for this test */
1056 if (adapter->msix_entries) {
1057 /* NOTE: we don't test MSI-X interrupts here, yet */
1058 return 0;
1059 } else if (adapter->msi_enabled) {
1060 shared_int = false;
1061 if (request_irq(irq, &igb_test_intr, 0, netdev->name, netdev)) {
1062 *data = 1;
1063 return -1;
1064 }
1065 } else if (!request_irq(irq, &igb_test_intr, IRQF_PROBE_SHARED,
1066 netdev->name, netdev)) {
1067 shared_int = false;
1068 } else if (request_irq(irq, &igb_test_intr, IRQF_SHARED,
1069 netdev->name, netdev)) {
1070 *data = 1;
1071 return -1;
1072 }
1073 dev_info(&adapter->pdev->dev, "testing %s interrupt\n",
1074 (shared_int ? "shared" : "unshared"));
1075
1076 /* Disable all the interrupts */
1077 wr32(E1000_IMC, 0xFFFFFFFF);
1078 msleep(10);
1079
1080 /* Test each interrupt */
1081 for (; i < 10; i++) {
1082 /* Interrupt to test */
1083 mask = 1 << i;
1084
1085 if (!shared_int) {
1086 /* Disable the interrupt to be reported in
1087 * the cause register and then force the same
1088 * interrupt and see if one gets posted. If
1089 * an interrupt was posted to the bus, the
1090 * test failed.
1091 */
1092 adapter->test_icr = 0;
1093 wr32(E1000_IMC, ~mask & 0x00007FFF);
1094 wr32(E1000_ICS, ~mask & 0x00007FFF);
1095 msleep(10);
1096
1097 if (adapter->test_icr & mask) {
1098 *data = 3;
1099 break;
1100 }
1101 }
1102
1103 /* Enable the interrupt to be reported in
1104 * the cause register and then force the same
1105 * interrupt and see if one gets posted. If
1106 * an interrupt was not posted to the bus, the
1107 * test failed.
1108 */
1109 adapter->test_icr = 0;
1110 wr32(E1000_IMS, mask);
1111 wr32(E1000_ICS, mask);
1112 msleep(10);
1113
1114 if (!(adapter->test_icr & mask)) {
1115 *data = 4;
1116 break;
1117 }
1118
1119 if (!shared_int) {
1120 /* Disable the other interrupts to be reported in
1121 * the cause register and then force the other
1122 * interrupts and see if any get posted. If
1123 * an interrupt was posted to the bus, the
1124 * test failed.
1125 */
1126 adapter->test_icr = 0;
1127 wr32(E1000_IMC, ~mask & 0x00007FFF);
1128 wr32(E1000_ICS, ~mask & 0x00007FFF);
1129 msleep(10);
1130
1131 if (adapter->test_icr) {
1132 *data = 5;
1133 break;
1134 }
1135 }
1136 }
1137
1138 /* Disable all the interrupts */
1139 wr32(E1000_IMC, 0xFFFFFFFF);
1140 msleep(10);
1141
1142 /* Unhook test interrupt handler */
1143 free_irq(irq, netdev);
1144
1145 return *data;
1146 }
1147
1148 static void igb_free_desc_rings(struct igb_adapter *adapter)
1149 {
1150 struct igb_ring *tx_ring = &adapter->test_tx_ring;
1151 struct igb_ring *rx_ring = &adapter->test_rx_ring;
1152 struct pci_dev *pdev = adapter->pdev;
1153 int i;
1154
1155 if (tx_ring->desc && tx_ring->buffer_info) {
1156 for (i = 0; i < tx_ring->count; i++) {
1157 struct igb_buffer *buf = &(tx_ring->buffer_info[i]);
1158 if (buf->dma)
1159 pci_unmap_single(pdev, buf->dma, buf->length,
1160 PCI_DMA_TODEVICE);
1161 if (buf->skb)
1162 dev_kfree_skb(buf->skb);
1163 }
1164 }
1165
1166 if (rx_ring->desc && rx_ring->buffer_info) {
1167 for (i = 0; i < rx_ring->count; i++) {
1168 struct igb_buffer *buf = &(rx_ring->buffer_info[i]);
1169 if (buf->dma)
1170 pci_unmap_single(pdev, buf->dma,
1171 IGB_RXBUFFER_2048,
1172 PCI_DMA_FROMDEVICE);
1173 if (buf->skb)
1174 dev_kfree_skb(buf->skb);
1175 }
1176 }
1177
1178 if (tx_ring->desc) {
1179 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc,
1180 tx_ring->dma);
1181 tx_ring->desc = NULL;
1182 }
1183 if (rx_ring->desc) {
1184 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc,
1185 rx_ring->dma);
1186 rx_ring->desc = NULL;
1187 }
1188
1189 kfree(tx_ring->buffer_info);
1190 tx_ring->buffer_info = NULL;
1191 kfree(rx_ring->buffer_info);
1192 rx_ring->buffer_info = NULL;
1193
1194 return;
1195 }
1196
1197 static int igb_setup_desc_rings(struct igb_adapter *adapter)
1198 {
1199 struct e1000_hw *hw = &adapter->hw;
1200 struct igb_ring *tx_ring = &adapter->test_tx_ring;
1201 struct igb_ring *rx_ring = &adapter->test_rx_ring;
1202 struct pci_dev *pdev = adapter->pdev;
1203 u32 rctl;
1204 int i, ret_val;
1205
1206 /* Setup Tx descriptor ring and Tx buffers */
1207
1208 if (!tx_ring->count)
1209 tx_ring->count = IGB_DEFAULT_TXD;
1210
1211 tx_ring->buffer_info = kcalloc(tx_ring->count,
1212 sizeof(struct igb_buffer),
1213 GFP_KERNEL);
1214 if (!tx_ring->buffer_info) {
1215 ret_val = 1;
1216 goto err_nomem;
1217 }
1218
1219 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc);
1220 tx_ring->size = ALIGN(tx_ring->size, 4096);
1221 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1222 &tx_ring->dma);
1223 if (!tx_ring->desc) {
1224 ret_val = 2;
1225 goto err_nomem;
1226 }
1227 tx_ring->next_to_use = tx_ring->next_to_clean = 0;
1228
1229 wr32(E1000_TDBAL(0),
1230 ((u64) tx_ring->dma & 0x00000000FFFFFFFF));
1231 wr32(E1000_TDBAH(0), ((u64) tx_ring->dma >> 32));
1232 wr32(E1000_TDLEN(0),
1233 tx_ring->count * sizeof(struct e1000_tx_desc));
1234 wr32(E1000_TDH(0), 0);
1235 wr32(E1000_TDT(0), 0);
1236 wr32(E1000_TCTL,
1237 E1000_TCTL_PSP | E1000_TCTL_EN |
1238 E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT |
1239 E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT);
1240
1241 for (i = 0; i < tx_ring->count; i++) {
1242 struct e1000_tx_desc *tx_desc = E1000_TX_DESC(*tx_ring, i);
1243 struct sk_buff *skb;
1244 unsigned int size = 1024;
1245
1246 skb = alloc_skb(size, GFP_KERNEL);
1247 if (!skb) {
1248 ret_val = 3;
1249 goto err_nomem;
1250 }
1251 skb_put(skb, size);
1252 tx_ring->buffer_info[i].skb = skb;
1253 tx_ring->buffer_info[i].length = skb->len;
1254 tx_ring->buffer_info[i].dma =
1255 pci_map_single(pdev, skb->data, skb->len,
1256 PCI_DMA_TODEVICE);
1257 tx_desc->buffer_addr = cpu_to_le64(tx_ring->buffer_info[i].dma);
1258 tx_desc->lower.data = cpu_to_le32(skb->len);
1259 tx_desc->lower.data |= cpu_to_le32(E1000_TXD_CMD_EOP |
1260 E1000_TXD_CMD_IFCS |
1261 E1000_TXD_CMD_RS);
1262 tx_desc->upper.data = 0;
1263 }
1264
1265 /* Setup Rx descriptor ring and Rx buffers */
1266
1267 if (!rx_ring->count)
1268 rx_ring->count = IGB_DEFAULT_RXD;
1269
1270 rx_ring->buffer_info = kcalloc(rx_ring->count,
1271 sizeof(struct igb_buffer),
1272 GFP_KERNEL);
1273 if (!rx_ring->buffer_info) {
1274 ret_val = 4;
1275 goto err_nomem;
1276 }
1277
1278 rx_ring->size = rx_ring->count * sizeof(struct e1000_rx_desc);
1279 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1280 &rx_ring->dma);
1281 if (!rx_ring->desc) {
1282 ret_val = 5;
1283 goto err_nomem;
1284 }
1285 rx_ring->next_to_use = rx_ring->next_to_clean = 0;
1286
1287 rctl = rd32(E1000_RCTL);
1288 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1289 wr32(E1000_RDBAL(0),
1290 ((u64) rx_ring->dma & 0xFFFFFFFF));
1291 wr32(E1000_RDBAH(0),
1292 ((u64) rx_ring->dma >> 32));
1293 wr32(E1000_RDLEN(0), rx_ring->size);
1294 wr32(E1000_RDH(0), 0);
1295 wr32(E1000_RDT(0), 0);
1296 rctl = E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_SZ_2048 |
1297 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
1298 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
1299 wr32(E1000_RCTL, rctl);
1300 wr32(E1000_SRRCTL(0), 0);
1301
1302 for (i = 0; i < rx_ring->count; i++) {
1303 struct e1000_rx_desc *rx_desc = E1000_RX_DESC(*rx_ring, i);
1304 struct sk_buff *skb;
1305
1306 skb = alloc_skb(IGB_RXBUFFER_2048 + NET_IP_ALIGN,
1307 GFP_KERNEL);
1308 if (!skb) {
1309 ret_val = 6;
1310 goto err_nomem;
1311 }
1312 skb_reserve(skb, NET_IP_ALIGN);
1313 rx_ring->buffer_info[i].skb = skb;
1314 rx_ring->buffer_info[i].dma =
1315 pci_map_single(pdev, skb->data, IGB_RXBUFFER_2048,
1316 PCI_DMA_FROMDEVICE);
1317 rx_desc->buffer_addr = cpu_to_le64(rx_ring->buffer_info[i].dma);
1318 memset(skb->data, 0x00, skb->len);
1319 }
1320
1321 return 0;
1322
1323 err_nomem:
1324 igb_free_desc_rings(adapter);
1325 return ret_val;
1326 }
1327
1328 static void igb_phy_disable_receiver(struct igb_adapter *adapter)
1329 {
1330 struct e1000_hw *hw = &adapter->hw;
1331
1332 /* Write out to PHY registers 29 and 30 to disable the Receiver. */
1333 hw->phy.ops.write_phy_reg(hw, 29, 0x001F);
1334 hw->phy.ops.write_phy_reg(hw, 30, 0x8FFC);
1335 hw->phy.ops.write_phy_reg(hw, 29, 0x001A);
1336 hw->phy.ops.write_phy_reg(hw, 30, 0x8FF0);
1337 }
1338
1339 static int igb_integrated_phy_loopback(struct igb_adapter *adapter)
1340 {
1341 struct e1000_hw *hw = &adapter->hw;
1342 u32 ctrl_reg = 0;
1343 u32 stat_reg = 0;
1344
1345 hw->mac.autoneg = false;
1346
1347 if (hw->phy.type == e1000_phy_m88) {
1348 /* Auto-MDI/MDIX Off */
1349 hw->phy.ops.write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808);
1350 /* reset to update Auto-MDI/MDIX */
1351 hw->phy.ops.write_phy_reg(hw, PHY_CONTROL, 0x9140);
1352 /* autoneg off */
1353 hw->phy.ops.write_phy_reg(hw, PHY_CONTROL, 0x8140);
1354 }
1355
1356 ctrl_reg = rd32(E1000_CTRL);
1357
1358 /* force 1000, set loopback */
1359 hw->phy.ops.write_phy_reg(hw, PHY_CONTROL, 0x4140);
1360
1361 /* Now set up the MAC to the same speed/duplex as the PHY. */
1362 ctrl_reg = rd32(E1000_CTRL);
1363 ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
1364 ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
1365 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
1366 E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */
1367 E1000_CTRL_FD); /* Force Duplex to FULL */
1368
1369 if (hw->phy.media_type == e1000_media_type_copper &&
1370 hw->phy.type == e1000_phy_m88)
1371 ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */
1372 else {
1373 /* Set the ILOS bit on the fiber Nic if half duplex link is
1374 * detected. */
1375 stat_reg = rd32(E1000_STATUS);
1376 if ((stat_reg & E1000_STATUS_FD) == 0)
1377 ctrl_reg |= (E1000_CTRL_ILOS | E1000_CTRL_SLU);
1378 }
1379
1380 wr32(E1000_CTRL, ctrl_reg);
1381
1382 /* Disable the receiver on the PHY so when a cable is plugged in, the
1383 * PHY does not begin to autoneg when a cable is reconnected to the NIC.
1384 */
1385 if (hw->phy.type == e1000_phy_m88)
1386 igb_phy_disable_receiver(adapter);
1387
1388 udelay(500);
1389
1390 return 0;
1391 }
1392
1393 static int igb_set_phy_loopback(struct igb_adapter *adapter)
1394 {
1395 return igb_integrated_phy_loopback(adapter);
1396 }
1397
1398 static int igb_setup_loopback_test(struct igb_adapter *adapter)
1399 {
1400 struct e1000_hw *hw = &adapter->hw;
1401 u32 rctl;
1402
1403 if (hw->phy.media_type == e1000_media_type_fiber ||
1404 hw->phy.media_type == e1000_media_type_internal_serdes) {
1405 rctl = rd32(E1000_RCTL);
1406 rctl |= E1000_RCTL_LBM_TCVR;
1407 wr32(E1000_RCTL, rctl);
1408 return 0;
1409 } else if (hw->phy.media_type == e1000_media_type_copper) {
1410 return igb_set_phy_loopback(adapter);
1411 }
1412
1413 return 7;
1414 }
1415
1416 static void igb_loopback_cleanup(struct igb_adapter *adapter)
1417 {
1418 struct e1000_hw *hw = &adapter->hw;
1419 u32 rctl;
1420 u16 phy_reg;
1421
1422 rctl = rd32(E1000_RCTL);
1423 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
1424 wr32(E1000_RCTL, rctl);
1425
1426 hw->mac.autoneg = true;
1427 hw->phy.ops.read_phy_reg(hw, PHY_CONTROL, &phy_reg);
1428 if (phy_reg & MII_CR_LOOPBACK) {
1429 phy_reg &= ~MII_CR_LOOPBACK;
1430 hw->phy.ops.write_phy_reg(hw, PHY_CONTROL, phy_reg);
1431 igb_phy_sw_reset(hw);
1432 }
1433 }
1434
1435 static void igb_create_lbtest_frame(struct sk_buff *skb,
1436 unsigned int frame_size)
1437 {
1438 memset(skb->data, 0xFF, frame_size);
1439 frame_size &= ~1;
1440 memset(&skb->data[frame_size / 2], 0xAA, frame_size / 2 - 1);
1441 memset(&skb->data[frame_size / 2 + 10], 0xBE, 1);
1442 memset(&skb->data[frame_size / 2 + 12], 0xAF, 1);
1443 }
1444
1445 static int igb_check_lbtest_frame(struct sk_buff *skb, unsigned int frame_size)
1446 {
1447 frame_size &= ~1;
1448 if (*(skb->data + 3) == 0xFF)
1449 if ((*(skb->data + frame_size / 2 + 10) == 0xBE) &&
1450 (*(skb->data + frame_size / 2 + 12) == 0xAF))
1451 return 0;
1452 return 13;
1453 }
1454
1455 static int igb_run_loopback_test(struct igb_adapter *adapter)
1456 {
1457 struct e1000_hw *hw = &adapter->hw;
1458 struct igb_ring *tx_ring = &adapter->test_tx_ring;
1459 struct igb_ring *rx_ring = &adapter->test_rx_ring;
1460 struct pci_dev *pdev = adapter->pdev;
1461 int i, j, k, l, lc, good_cnt;
1462 int ret_val = 0;
1463 unsigned long time;
1464
1465 wr32(E1000_RDT(0), rx_ring->count - 1);
1466
1467 /* Calculate the loop count based on the largest descriptor ring
1468 * The idea is to wrap the largest ring a number of times using 64
1469 * send/receive pairs during each loop
1470 */
1471
1472 if (rx_ring->count <= tx_ring->count)
1473 lc = ((tx_ring->count / 64) * 2) + 1;
1474 else
1475 lc = ((rx_ring->count / 64) * 2) + 1;
1476
1477 k = l = 0;
1478 for (j = 0; j <= lc; j++) { /* loop count loop */
1479 for (i = 0; i < 64; i++) { /* send the packets */
1480 igb_create_lbtest_frame(tx_ring->buffer_info[k].skb,
1481 1024);
1482 pci_dma_sync_single_for_device(pdev,
1483 tx_ring->buffer_info[k].dma,
1484 tx_ring->buffer_info[k].length,
1485 PCI_DMA_TODEVICE);
1486 k++;
1487 if (k == tx_ring->count)
1488 k = 0;
1489 }
1490 wr32(E1000_TDT(0), k);
1491 msleep(200);
1492 time = jiffies; /* set the start time for the receive */
1493 good_cnt = 0;
1494 do { /* receive the sent packets */
1495 pci_dma_sync_single_for_cpu(pdev,
1496 rx_ring->buffer_info[l].dma,
1497 IGB_RXBUFFER_2048,
1498 PCI_DMA_FROMDEVICE);
1499
1500 ret_val = igb_check_lbtest_frame(
1501 rx_ring->buffer_info[l].skb, 1024);
1502 if (!ret_val)
1503 good_cnt++;
1504 l++;
1505 if (l == rx_ring->count)
1506 l = 0;
1507 /* time + 20 msecs (200 msecs on 2.4) is more than
1508 * enough time to complete the receives, if it's
1509 * exceeded, break and error off
1510 */
1511 } while (good_cnt < 64 && jiffies < (time + 20));
1512 if (good_cnt != 64) {
1513 ret_val = 13; /* ret_val is the same as mis-compare */
1514 break;
1515 }
1516 if (jiffies >= (time + 20)) {
1517 ret_val = 14; /* error code for time out error */
1518 break;
1519 }
1520 } /* end loop count loop */
1521 return ret_val;
1522 }
1523
1524 static int igb_loopback_test(struct igb_adapter *adapter, u64 *data)
1525 {
1526 /* PHY loopback cannot be performed if SoL/IDER
1527 * sessions are active */
1528 if (igb_check_reset_block(&adapter->hw)) {
1529 dev_err(&adapter->pdev->dev,
1530 "Cannot do PHY loopback test "
1531 "when SoL/IDER is active.\n");
1532 *data = 0;
1533 goto out;
1534 }
1535 *data = igb_setup_desc_rings(adapter);
1536 if (*data)
1537 goto out;
1538 *data = igb_setup_loopback_test(adapter);
1539 if (*data)
1540 goto err_loopback;
1541 *data = igb_run_loopback_test(adapter);
1542 igb_loopback_cleanup(adapter);
1543
1544 err_loopback:
1545 igb_free_desc_rings(adapter);
1546 out:
1547 return *data;
1548 }
1549
1550 static int igb_link_test(struct igb_adapter *adapter, u64 *data)
1551 {
1552 struct e1000_hw *hw = &adapter->hw;
1553 *data = 0;
1554 if (hw->phy.media_type == e1000_media_type_internal_serdes) {
1555 int i = 0;
1556 hw->mac.serdes_has_link = false;
1557
1558 /* On some blade server designs, link establishment
1559 * could take as long as 2-3 minutes */
1560 do {
1561 hw->mac.ops.check_for_link(&adapter->hw);
1562 if (hw->mac.serdes_has_link)
1563 return *data;
1564 msleep(20);
1565 } while (i++ < 3750);
1566
1567 *data = 1;
1568 } else {
1569 hw->mac.ops.check_for_link(&adapter->hw);
1570 if (hw->mac.autoneg)
1571 msleep(4000);
1572
1573 if (!(rd32(E1000_STATUS) &
1574 E1000_STATUS_LU))
1575 *data = 1;
1576 }
1577 return *data;
1578 }
1579
1580 static void igb_diag_test(struct net_device *netdev,
1581 struct ethtool_test *eth_test, u64 *data)
1582 {
1583 struct igb_adapter *adapter = netdev_priv(netdev);
1584 u16 autoneg_advertised;
1585 u8 forced_speed_duplex, autoneg;
1586 bool if_running = netif_running(netdev);
1587
1588 set_bit(__IGB_TESTING, &adapter->state);
1589 if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
1590 /* Offline tests */
1591
1592 /* save speed, duplex, autoneg settings */
1593 autoneg_advertised = adapter->hw.phy.autoneg_advertised;
1594 forced_speed_duplex = adapter->hw.mac.forced_speed_duplex;
1595 autoneg = adapter->hw.mac.autoneg;
1596
1597 dev_info(&adapter->pdev->dev, "offline testing starting\n");
1598
1599 /* Link test performed before hardware reset so autoneg doesn't
1600 * interfere with test result */
1601 if (igb_link_test(adapter, &data[4]))
1602 eth_test->flags |= ETH_TEST_FL_FAILED;
1603
1604 if (if_running)
1605 /* indicate we're in test mode */
1606 dev_close(netdev);
1607 else
1608 igb_reset(adapter);
1609
1610 if (igb_reg_test(adapter, &data[0]))
1611 eth_test->flags |= ETH_TEST_FL_FAILED;
1612
1613 igb_reset(adapter);
1614 if (igb_eeprom_test(adapter, &data[1]))
1615 eth_test->flags |= ETH_TEST_FL_FAILED;
1616
1617 igb_reset(adapter);
1618 if (igb_intr_test(adapter, &data[2]))
1619 eth_test->flags |= ETH_TEST_FL_FAILED;
1620
1621 igb_reset(adapter);
1622 if (igb_loopback_test(adapter, &data[3]))
1623 eth_test->flags |= ETH_TEST_FL_FAILED;
1624
1625 /* restore speed, duplex, autoneg settings */
1626 adapter->hw.phy.autoneg_advertised = autoneg_advertised;
1627 adapter->hw.mac.forced_speed_duplex = forced_speed_duplex;
1628 adapter->hw.mac.autoneg = autoneg;
1629
1630 /* force this routine to wait until autoneg complete/timeout */
1631 adapter->hw.phy.autoneg_wait_to_complete = true;
1632 igb_reset(adapter);
1633 adapter->hw.phy.autoneg_wait_to_complete = false;
1634
1635 clear_bit(__IGB_TESTING, &adapter->state);
1636 if (if_running)
1637 dev_open(netdev);
1638 } else {
1639 dev_info(&adapter->pdev->dev, "online testing starting\n");
1640 /* Online tests */
1641 if (igb_link_test(adapter, &data[4]))
1642 eth_test->flags |= ETH_TEST_FL_FAILED;
1643
1644 /* Online tests aren't run; pass by default */
1645 data[0] = 0;
1646 data[1] = 0;
1647 data[2] = 0;
1648 data[3] = 0;
1649
1650 clear_bit(__IGB_TESTING, &adapter->state);
1651 }
1652 msleep_interruptible(4 * 1000);
1653 }
1654
1655 static int igb_wol_exclusion(struct igb_adapter *adapter,
1656 struct ethtool_wolinfo *wol)
1657 {
1658 struct e1000_hw *hw = &adapter->hw;
1659 int retval = 1; /* fail by default */
1660
1661 switch (hw->device_id) {
1662 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1663 /* WoL not supported */
1664 wol->supported = 0;
1665 break;
1666 case E1000_DEV_ID_82575EB_FIBER_SERDES:
1667 /* Wake events not supported on port B */
1668 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) {
1669 wol->supported = 0;
1670 break;
1671 }
1672 /* return success for non excluded adapter ports */
1673 retval = 0;
1674 break;
1675 default:
1676 /* dual port cards only support WoL on port A from now on
1677 * unless it was enabled in the eeprom for port B
1678 * so exclude FUNC_1 ports from having WoL enabled */
1679 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1 &&
1680 !adapter->eeprom_wol) {
1681 wol->supported = 0;
1682 break;
1683 }
1684
1685 retval = 0;
1686 }
1687
1688 return retval;
1689 }
1690
1691 static void igb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1692 {
1693 struct igb_adapter *adapter = netdev_priv(netdev);
1694
1695 wol->supported = WAKE_UCAST | WAKE_MCAST |
1696 WAKE_BCAST | WAKE_MAGIC;
1697 wol->wolopts = 0;
1698
1699 /* this function will set ->supported = 0 and return 1 if wol is not
1700 * supported by this hardware */
1701 if (igb_wol_exclusion(adapter, wol))
1702 return;
1703
1704 /* apply any specific unsupported masks here */
1705 switch (adapter->hw.device_id) {
1706 default:
1707 break;
1708 }
1709
1710 if (adapter->wol & E1000_WUFC_EX)
1711 wol->wolopts |= WAKE_UCAST;
1712 if (adapter->wol & E1000_WUFC_MC)
1713 wol->wolopts |= WAKE_MCAST;
1714 if (adapter->wol & E1000_WUFC_BC)
1715 wol->wolopts |= WAKE_BCAST;
1716 if (adapter->wol & E1000_WUFC_MAG)
1717 wol->wolopts |= WAKE_MAGIC;
1718
1719 return;
1720 }
1721
1722 static int igb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1723 {
1724 struct igb_adapter *adapter = netdev_priv(netdev);
1725 struct e1000_hw *hw = &adapter->hw;
1726
1727 if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE))
1728 return -EOPNOTSUPP;
1729
1730 if (igb_wol_exclusion(adapter, wol))
1731 return wol->wolopts ? -EOPNOTSUPP : 0;
1732
1733 switch (hw->device_id) {
1734 default:
1735 break;
1736 }
1737
1738 /* these settings will always override what we currently have */
1739 adapter->wol = 0;
1740
1741 if (wol->wolopts & WAKE_UCAST)
1742 adapter->wol |= E1000_WUFC_EX;
1743 if (wol->wolopts & WAKE_MCAST)
1744 adapter->wol |= E1000_WUFC_MC;
1745 if (wol->wolopts & WAKE_BCAST)
1746 adapter->wol |= E1000_WUFC_BC;
1747 if (wol->wolopts & WAKE_MAGIC)
1748 adapter->wol |= E1000_WUFC_MAG;
1749
1750 return 0;
1751 }
1752
1753 /* toggle LED 4 times per second = 2 "blinks" per second */
1754 #define IGB_ID_INTERVAL (HZ/4)
1755
1756 /* bit defines for adapter->led_status */
1757 #define IGB_LED_ON 0
1758
1759 static int igb_phys_id(struct net_device *netdev, u32 data)
1760 {
1761 struct igb_adapter *adapter = netdev_priv(netdev);
1762 struct e1000_hw *hw = &adapter->hw;
1763
1764 if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
1765 data = (u32)(MAX_SCHEDULE_TIMEOUT / HZ);
1766
1767 igb_blink_led(hw);
1768 msleep_interruptible(data * 1000);
1769
1770 igb_led_off(hw);
1771 clear_bit(IGB_LED_ON, &adapter->led_status);
1772 igb_cleanup_led(hw);
1773
1774 return 0;
1775 }
1776
1777 static int igb_set_coalesce(struct net_device *netdev,
1778 struct ethtool_coalesce *ec)
1779 {
1780 struct igb_adapter *adapter = netdev_priv(netdev);
1781
1782 if ((ec->rx_coalesce_usecs > IGB_MAX_ITR_USECS) ||
1783 ((ec->rx_coalesce_usecs > 3) &&
1784 (ec->rx_coalesce_usecs < IGB_MIN_ITR_USECS)) ||
1785 (ec->rx_coalesce_usecs == 2))
1786 return -EINVAL;
1787
1788 /* convert to rate of irq's per second */
1789 if (ec->rx_coalesce_usecs <= 3)
1790 adapter->itr_setting = ec->rx_coalesce_usecs;
1791 else
1792 adapter->itr_setting = (1000000 / ec->rx_coalesce_usecs);
1793
1794 if (netif_running(netdev))
1795 igb_reinit_locked(adapter);
1796
1797 return 0;
1798 }
1799
1800 static int igb_get_coalesce(struct net_device *netdev,
1801 struct ethtool_coalesce *ec)
1802 {
1803 struct igb_adapter *adapter = netdev_priv(netdev);
1804
1805 if (adapter->itr_setting <= 3)
1806 ec->rx_coalesce_usecs = adapter->itr_setting;
1807 else
1808 ec->rx_coalesce_usecs = 1000000 / adapter->itr_setting;
1809
1810 return 0;
1811 }
1812
1813
1814 static int igb_nway_reset(struct net_device *netdev)
1815 {
1816 struct igb_adapter *adapter = netdev_priv(netdev);
1817 if (netif_running(netdev))
1818 igb_reinit_locked(adapter);
1819 return 0;
1820 }
1821
1822 static int igb_get_sset_count(struct net_device *netdev, int sset)
1823 {
1824 switch (sset) {
1825 case ETH_SS_STATS:
1826 return IGB_STATS_LEN;
1827 case ETH_SS_TEST:
1828 return IGB_TEST_LEN;
1829 default:
1830 return -ENOTSUPP;
1831 }
1832 }
1833
1834 static void igb_get_ethtool_stats(struct net_device *netdev,
1835 struct ethtool_stats *stats, u64 *data)
1836 {
1837 struct igb_adapter *adapter = netdev_priv(netdev);
1838 u64 *queue_stat;
1839 int stat_count = sizeof(struct igb_queue_stats) / sizeof(u64);
1840 int j;
1841 int i;
1842
1843 igb_update_stats(adapter);
1844 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
1845 char *p = (char *)adapter+igb_gstrings_stats[i].stat_offset;
1846 data[i] = (igb_gstrings_stats[i].sizeof_stat ==
1847 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
1848 }
1849 for (j = 0; j < adapter->num_rx_queues; j++) {
1850 int k;
1851 queue_stat = (u64 *)&adapter->rx_ring[j].rx_stats;
1852 for (k = 0; k < stat_count; k++)
1853 data[i + k] = queue_stat[k];
1854 i += k;
1855 }
1856 }
1857
1858 static void igb_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
1859 {
1860 struct igb_adapter *adapter = netdev_priv(netdev);
1861 u8 *p = data;
1862 int i;
1863
1864 switch (stringset) {
1865 case ETH_SS_TEST:
1866 memcpy(data, *igb_gstrings_test,
1867 IGB_TEST_LEN*ETH_GSTRING_LEN);
1868 break;
1869 case ETH_SS_STATS:
1870 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
1871 memcpy(p, igb_gstrings_stats[i].stat_string,
1872 ETH_GSTRING_LEN);
1873 p += ETH_GSTRING_LEN;
1874 }
1875 for (i = 0; i < adapter->num_tx_queues; i++) {
1876 sprintf(p, "tx_queue_%u_packets", i);
1877 p += ETH_GSTRING_LEN;
1878 sprintf(p, "tx_queue_%u_bytes", i);
1879 p += ETH_GSTRING_LEN;
1880 }
1881 for (i = 0; i < adapter->num_rx_queues; i++) {
1882 sprintf(p, "rx_queue_%u_packets", i);
1883 p += ETH_GSTRING_LEN;
1884 sprintf(p, "rx_queue_%u_bytes", i);
1885 p += ETH_GSTRING_LEN;
1886 }
1887 /* BUG_ON(p - data != IGB_STATS_LEN * ETH_GSTRING_LEN); */
1888 break;
1889 }
1890 }
1891
1892 static struct ethtool_ops igb_ethtool_ops = {
1893 .get_settings = igb_get_settings,
1894 .set_settings = igb_set_settings,
1895 .get_drvinfo = igb_get_drvinfo,
1896 .get_regs_len = igb_get_regs_len,
1897 .get_regs = igb_get_regs,
1898 .get_wol = igb_get_wol,
1899 .set_wol = igb_set_wol,
1900 .get_msglevel = igb_get_msglevel,
1901 .set_msglevel = igb_set_msglevel,
1902 .nway_reset = igb_nway_reset,
1903 .get_link = ethtool_op_get_link,
1904 .get_eeprom_len = igb_get_eeprom_len,
1905 .get_eeprom = igb_get_eeprom,
1906 .set_eeprom = igb_set_eeprom,
1907 .get_ringparam = igb_get_ringparam,
1908 .set_ringparam = igb_set_ringparam,
1909 .get_pauseparam = igb_get_pauseparam,
1910 .set_pauseparam = igb_set_pauseparam,
1911 .get_rx_csum = igb_get_rx_csum,
1912 .set_rx_csum = igb_set_rx_csum,
1913 .get_tx_csum = igb_get_tx_csum,
1914 .set_tx_csum = igb_set_tx_csum,
1915 .get_sg = ethtool_op_get_sg,
1916 .set_sg = ethtool_op_set_sg,
1917 .get_tso = ethtool_op_get_tso,
1918 .set_tso = igb_set_tso,
1919 .self_test = igb_diag_test,
1920 .get_strings = igb_get_strings,
1921 .phys_id = igb_phys_id,
1922 .get_sset_count = igb_get_sset_count,
1923 .get_ethtool_stats = igb_get_ethtool_stats,
1924 .get_coalesce = igb_get_coalesce,
1925 .set_coalesce = igb_set_coalesce,
1926 };
1927
1928 void igb_set_ethtool_ops(struct net_device *netdev)
1929 {
1930 SET_ETHTOOL_OPS(netdev, &igb_ethtool_ops);
1931 }
WRT350N Kernel Patches