?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Merge git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
[wrt350n-kernel.git] / drivers / net / wireless / ath5k / hw.c
blob1cb7f5d04f07c95820a7f9995bb5f8bab58ff095
1 /*
2 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2007 Nick Kossifidis <mickflemm@gmail.com>
4 * Copyright (c) 2007 Matthew W. S. Bell <mentor@madwifi.org>
5 * Copyright (c) 2007 Luis Rodriguez <mcgrof@winlab.rutgers.edu>
6 * Copyright (c) 2007 Pavel Roskin <proski@gnu.org>
7 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
8 *
9 * Permission to use, copy, modify, and distribute this software for any
10 * purpose with or without fee is hereby granted, provided that the above
11 * copyright notice and this permission notice appear in all copies.
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 *
21 */
22
23 /*
24 * HW related functions for Atheros Wireless LAN devices.
25 */
26
27 #include <linux/pci.h>
28 #include <linux/delay.h>
29
30 #include "reg.h"
31 #include "base.h"
32 #include "debug.h"
33
34 /*Rate tables*/
35 static const struct ath5k_rate_table ath5k_rt_11a = AR5K_RATES_11A;
36 static const struct ath5k_rate_table ath5k_rt_11b = AR5K_RATES_11B;
37 static const struct ath5k_rate_table ath5k_rt_11g = AR5K_RATES_11G;
38 static const struct ath5k_rate_table ath5k_rt_turbo = AR5K_RATES_TURBO;
39 static const struct ath5k_rate_table ath5k_rt_xr = AR5K_RATES_XR;
40
41 /*Prototypes*/
42 static int ath5k_hw_nic_reset(struct ath5k_hw *, u32);
43 static int ath5k_hw_nic_wakeup(struct ath5k_hw *, int, bool);
44 static int ath5k_hw_setup_4word_tx_desc(struct ath5k_hw *, struct ath5k_desc *,
45 unsigned int, unsigned int, enum ath5k_pkt_type, unsigned int,
46 unsigned int, unsigned int, unsigned int, unsigned int, unsigned int,
47 unsigned int, unsigned int);
48 <<<<<<< HEAD:drivers/net/wireless/ath5k/hw.c
49 static bool ath5k_hw_setup_xr_tx_desc(struct ath5k_hw *, struct ath5k_desc *,
50 =======
51 static int ath5k_hw_setup_xr_tx_desc(struct ath5k_hw *, struct ath5k_desc *,
52 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/net/wireless/ath5k/hw.c
53 unsigned int, unsigned int, unsigned int, unsigned int, unsigned int,
54 unsigned int);
55 static int ath5k_hw_proc_4word_tx_status(struct ath5k_hw *, struct ath5k_desc *);
56 static int ath5k_hw_setup_2word_tx_desc(struct ath5k_hw *, struct ath5k_desc *,
57 unsigned int, unsigned int, enum ath5k_pkt_type, unsigned int,
58 unsigned int, unsigned int, unsigned int, unsigned int, unsigned int,
59 unsigned int, unsigned int);
60 static int ath5k_hw_proc_2word_tx_status(struct ath5k_hw *, struct ath5k_desc *);
61 static int ath5k_hw_proc_new_rx_status(struct ath5k_hw *, struct ath5k_desc *);
62 static int ath5k_hw_proc_old_rx_status(struct ath5k_hw *, struct ath5k_desc *);
63 static int ath5k_hw_get_capabilities(struct ath5k_hw *);
64
65 static int ath5k_eeprom_init(struct ath5k_hw *);
66 static int ath5k_eeprom_read_mac(struct ath5k_hw *, u8 *);
67
68 static int ath5k_hw_enable_pspoll(struct ath5k_hw *, u8 *, u16);
69 static int ath5k_hw_disable_pspoll(struct ath5k_hw *);
70
71 /*
72 * Enable to overwrite the country code (use "00" for debug)
73 */
74 #if 0
75 #define COUNTRYCODE "00"
76 #endif
77
78 /*******************\
79 General Functions
80 \*******************/
81
82 /*
83 * Functions used internaly
84 */
85
86 static inline unsigned int ath5k_hw_htoclock(unsigned int usec, bool turbo)
87 {
88 return turbo == true ? (usec * 80) : (usec * 40);
89 }
90
91 static inline unsigned int ath5k_hw_clocktoh(unsigned int clock, bool turbo)
92 {
93 return turbo == true ? (clock / 80) : (clock / 40);
94 }
95
96 /*
97 * Check if a register write has been completed
98 */
99 int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val,
100 bool is_set)
101 {
102 int i;
103 u32 data;
104
105 for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) {
106 data = ath5k_hw_reg_read(ah, reg);
107 if ((is_set == true) && (data & flag))
108 break;
109 else if ((data & flag) == val)
110 break;
111 udelay(15);
112 }
113
114 return (i <= 0) ? -EAGAIN : 0;
115 }
116
117
118 /***************************************\
119 Attach/Detach Functions
120 \***************************************/
121
122 /*
123 * Check if the device is supported and initialize the needed structs
124 */
125 struct ath5k_hw *ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version)
126 {
127 struct ath5k_hw *ah;
128 u8 mac[ETH_ALEN];
129 int ret;
130 u32 srev;
131
132 /*If we passed the test malloc a ath5k_hw struct*/
133 ah = kzalloc(sizeof(struct ath5k_hw), GFP_KERNEL);
134 if (ah == NULL) {
135 ret = -ENOMEM;
136 ATH5K_ERR(sc, "out of memory\n");
137 goto err;
138 }
139
140 ah->ah_sc = sc;
141 ah->ah_iobase = sc->iobase;
142
143 /*
144 * HW information
145 */
146
147 /* Get reg domain from eeprom */
148 ath5k_get_regdomain(ah);
149
150 ah->ah_op_mode = IEEE80211_IF_TYPE_STA;
151 ah->ah_radar.r_enabled = AR5K_TUNE_RADAR_ALERT;
152 ah->ah_turbo = false;
153 ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER;
154 ah->ah_imr = 0;
155 ah->ah_atim_window = 0;
156 ah->ah_aifs = AR5K_TUNE_AIFS;
157 ah->ah_cw_min = AR5K_TUNE_CWMIN;
158 ah->ah_limit_tx_retries = AR5K_INIT_TX_RETRY;
159 ah->ah_software_retry = false;
160 ah->ah_ant_diversity = AR5K_TUNE_ANT_DIVERSITY;
161
162 /*
163 * Set the mac revision based on the pci id
164 */
165 ah->ah_version = mac_version;
166
167 /*Fill the ath5k_hw struct with the needed functions*/
168 if (ah->ah_version == AR5K_AR5212)
169 ah->ah_magic = AR5K_EEPROM_MAGIC_5212;
170 else if (ah->ah_version == AR5K_AR5211)
171 ah->ah_magic = AR5K_EEPROM_MAGIC_5211;
172
173 if (ah->ah_version == AR5K_AR5212) {
174 ah->ah_setup_tx_desc = ath5k_hw_setup_4word_tx_desc;
175 ah->ah_setup_xtx_desc = ath5k_hw_setup_xr_tx_desc;
176 ah->ah_proc_tx_desc = ath5k_hw_proc_4word_tx_status;
177 } else {
178 ah->ah_setup_tx_desc = ath5k_hw_setup_2word_tx_desc;
179 ah->ah_setup_xtx_desc = ath5k_hw_setup_xr_tx_desc;
180 ah->ah_proc_tx_desc = ath5k_hw_proc_2word_tx_status;
181 }
182
183 if (ah->ah_version == AR5K_AR5212)
184 ah->ah_proc_rx_desc = ath5k_hw_proc_new_rx_status;
185 else if (ah->ah_version <= AR5K_AR5211)
186 ah->ah_proc_rx_desc = ath5k_hw_proc_old_rx_status;
187
188 /* Bring device out of sleep and reset it's units */
189 ret = ath5k_hw_nic_wakeup(ah, AR5K_INIT_MODE, true);
190 if (ret)
191 goto err_free;
192
193 /* Get MAC, PHY and RADIO revisions */
194 srev = ath5k_hw_reg_read(ah, AR5K_SREV);
195 ah->ah_mac_srev = srev;
196 ah->ah_mac_version = AR5K_REG_MS(srev, AR5K_SREV_VER);
197 ah->ah_mac_revision = AR5K_REG_MS(srev, AR5K_SREV_REV);
198 ah->ah_phy_revision = ath5k_hw_reg_read(ah, AR5K_PHY_CHIP_ID) &
199 0xffffffff;
200 ah->ah_radio_5ghz_revision = ath5k_hw_radio_revision(ah,
201 CHANNEL_5GHZ);
202
203 if (ah->ah_version == AR5K_AR5210)
204 ah->ah_radio_2ghz_revision = 0;
205 else
206 ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
207 CHANNEL_2GHZ);
208
209 /* Return on unsuported chips (unsupported eeprom etc) */
210 if(srev >= AR5K_SREV_VER_AR5416){
211 ATH5K_ERR(sc, "Device not yet supported.\n");
212 ret = -ENODEV;
213 goto err_free;
214 }
215
216 /* Identify single chip solutions */
217 if((srev <= AR5K_SREV_VER_AR5414) &&
218 (srev >= AR5K_SREV_VER_AR2424)) {
219 ah->ah_single_chip = true;
220 } else {
221 ah->ah_single_chip = false;
222 }
223
224 /* Single chip radio */
225 if (ah->ah_radio_2ghz_revision == ah->ah_radio_5ghz_revision)
226 ah->ah_radio_2ghz_revision = 0;
227
228 /* Identify the radio chip*/
229 if (ah->ah_version == AR5K_AR5210) {
230 ah->ah_radio = AR5K_RF5110;
231 } else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112) {
232 ah->ah_radio = AR5K_RF5111;
233 } else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_SC1) {
234 ah->ah_radio = AR5K_RF5112;
235 } else {
236 ah->ah_radio = AR5K_RF5413;
237 }
238
239 ah->ah_phy = AR5K_PHY(0);
240
241 /*
242 * Get card capabilities, values, ...
243 */
244
245 ret = ath5k_eeprom_init(ah);
246 if (ret) {
247 ATH5K_ERR(sc, "unable to init EEPROM\n");
248 goto err_free;
249 }
250
251 /* Get misc capabilities */
252 ret = ath5k_hw_get_capabilities(ah);
253 if (ret) {
254 ATH5K_ERR(sc, "unable to get device capabilities: 0x%04x\n",
255 sc->pdev->device);
256 goto err_free;
257 }
258
259 /* Get MAC address */
260 ret = ath5k_eeprom_read_mac(ah, mac);
261 if (ret) {
262 ATH5K_ERR(sc, "unable to read address from EEPROM: 0x%04x\n",
263 sc->pdev->device);
264 goto err_free;
265 }
266
267 ath5k_hw_set_lladdr(ah, mac);
268 /* Set BSSID to bcast address: ff:ff:ff:ff:ff:ff for now */
269 memset(ah->ah_bssid, 0xff, ETH_ALEN);
270 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
271 ath5k_hw_set_opmode(ah);
272
273 ath5k_hw_set_rfgain_opt(ah);
274
275 return ah;
276 err_free:
277 kfree(ah);
278 err:
279 return ERR_PTR(ret);
280 }
281
282 /*
283 * Bring up MAC + PHY Chips
284 */
285 static int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial)
286 {
287 u32 turbo, mode, clock;
288 int ret;
289
290 turbo = 0;
291 mode = 0;
292 clock = 0;
293
294 ATH5K_TRACE(ah->ah_sc);
295
296 /* Wakeup the device */
297 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
298 if (ret) {
299 ATH5K_ERR(ah->ah_sc, "failed to wakeup the MAC Chip\n");
300 return ret;
301 }
302
303 if (ah->ah_version != AR5K_AR5210) {
304 /*
305 * Get channel mode flags
306 */
307
308 if (ah->ah_radio >= AR5K_RF5112) {
309 mode = AR5K_PHY_MODE_RAD_RF5112;
310 clock = AR5K_PHY_PLL_RF5112;
311 } else {
312 mode = AR5K_PHY_MODE_RAD_RF5111; /*Zero*/
313 clock = AR5K_PHY_PLL_RF5111; /*Zero*/
314 }
315
316 if (flags & CHANNEL_2GHZ) {
317 mode |= AR5K_PHY_MODE_FREQ_2GHZ;
318 clock |= AR5K_PHY_PLL_44MHZ;
319
320 if (flags & CHANNEL_CCK) {
321 mode |= AR5K_PHY_MODE_MOD_CCK;
322 } else if (flags & CHANNEL_OFDM) {
323 /* XXX Dynamic OFDM/CCK is not supported by the
324 * AR5211 so we set MOD_OFDM for plain g (no
325 * CCK headers) operation. We need to test
326 * this, 5211 might support ofdm-only g after
327 * all, there are also initial register values
328 * in the code for g mode (see initvals.c). */
329 if (ah->ah_version == AR5K_AR5211)
330 mode |= AR5K_PHY_MODE_MOD_OFDM;
331 else
332 mode |= AR5K_PHY_MODE_MOD_DYN;
333 } else {
334 ATH5K_ERR(ah->ah_sc,
335 "invalid radio modulation mode\n");
336 return -EINVAL;
337 }
338 } else if (flags & CHANNEL_5GHZ) {
339 mode |= AR5K_PHY_MODE_FREQ_5GHZ;
340 clock |= AR5K_PHY_PLL_40MHZ;
341
342 if (flags & CHANNEL_OFDM)
343 mode |= AR5K_PHY_MODE_MOD_OFDM;
344 else {
345 ATH5K_ERR(ah->ah_sc,
346 "invalid radio modulation mode\n");
347 return -EINVAL;
348 }
349 } else {
350 ATH5K_ERR(ah->ah_sc, "invalid radio frequency mode\n");
351 return -EINVAL;
352 }
353
354 if (flags & CHANNEL_TURBO)
355 turbo = AR5K_PHY_TURBO_MODE | AR5K_PHY_TURBO_SHORT;
356 } else { /* Reset the device */
357
358 /* ...enable Atheros turbo mode if requested */
359 if (flags & CHANNEL_TURBO)
360 ath5k_hw_reg_write(ah, AR5K_PHY_TURBO_MODE,
361 AR5K_PHY_TURBO);
362 }
363
364 /* ...reset chipset and PCI device */
365 if (ah->ah_single_chip == false && ath5k_hw_nic_reset(ah,
366 AR5K_RESET_CTL_CHIP | AR5K_RESET_CTL_PCI)) {
367 ATH5K_ERR(ah->ah_sc, "failed to reset the MAC Chip + PCI\n");
368 return -EIO;
369 }
370
371 if (ah->ah_version == AR5K_AR5210)
372 udelay(2300);
373
374 /* ...wakeup again!*/
375 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
376 if (ret) {
377 ATH5K_ERR(ah->ah_sc, "failed to resume the MAC Chip\n");
378 return ret;
379 }
380
381 /* ...final warm reset */
382 if (ath5k_hw_nic_reset(ah, 0)) {
383 ATH5K_ERR(ah->ah_sc, "failed to warm reset the MAC Chip\n");
384 return -EIO;
385 }
386
387 if (ah->ah_version != AR5K_AR5210) {
388 /* ...set the PHY operating mode */
389 ath5k_hw_reg_write(ah, clock, AR5K_PHY_PLL);
390 udelay(300);
391
392 ath5k_hw_reg_write(ah, mode, AR5K_PHY_MODE);
393 ath5k_hw_reg_write(ah, turbo, AR5K_PHY_TURBO);
394 }
395
396 return 0;
397 }
398
399 /*
400 * Get the rate table for a specific operation mode
401 */
402 const struct ath5k_rate_table *ath5k_hw_get_rate_table(struct ath5k_hw *ah,
403 unsigned int mode)
404 {
405 ATH5K_TRACE(ah->ah_sc);
406
407 if (!test_bit(mode, ah->ah_capabilities.cap_mode))
408 return NULL;
409
410 /* Get rate tables */
411 switch (mode) {
412 case MODE_IEEE80211A:
413 return &ath5k_rt_11a;
414 case MODE_ATHEROS_TURBO:
415 return &ath5k_rt_turbo;
416 case MODE_IEEE80211B:
417 return &ath5k_rt_11b;
418 case MODE_IEEE80211G:
419 return &ath5k_rt_11g;
420 case MODE_ATHEROS_TURBOG:
421 return &ath5k_rt_xr;
422 }
423
424 return NULL;
425 }
426
427 /*
428 * Free the ath5k_hw struct
429 */
430 void ath5k_hw_detach(struct ath5k_hw *ah)
431 {
432 ATH5K_TRACE(ah->ah_sc);
433
434 if (ah->ah_rf_banks != NULL)
435 kfree(ah->ah_rf_banks);
436
437 /* assume interrupts are down */
438 kfree(ah);
439 }
440
441 /****************************\
442 Reset function and helpers
443 \****************************/
444
445 /**
446 * ath5k_hw_write_ofdm_timings - set OFDM timings on AR5212
447 *
448 * @ah: the &struct ath5k_hw
449 * @channel: the currently set channel upon reset
450 *
451 * Write the OFDM timings for the AR5212 upon reset. This is a helper for
452 * ath5k_hw_reset(). This seems to tune the PLL a specified frequency
453 * depending on the bandwidth of the channel.
454 *
455 */
456 static inline int ath5k_hw_write_ofdm_timings(struct ath5k_hw *ah,
457 struct ieee80211_channel *channel)
458 {
459 /* Get exponent and mantissa and set it */
460 u32 coef_scaled, coef_exp, coef_man,
461 ds_coef_exp, ds_coef_man, clock;
462
463 if (!(ah->ah_version == AR5K_AR5212) ||
464 !(channel->val & CHANNEL_OFDM))
465 BUG();
466
467 /* Seems there are two PLLs, one for baseband sampling and one
468 * for tuning. Tuning basebands are 40 MHz or 80MHz when in
469 * turbo. */
470 clock = channel->val & CHANNEL_TURBO ? 80 : 40;
471 coef_scaled = ((5 * (clock << 24)) / 2) /
472 channel->freq;
473
474 for (coef_exp = 31; coef_exp > 0; coef_exp--)
475 if ((coef_scaled >> coef_exp) & 0x1)
476 break;
477
478 if (!coef_exp)
479 return -EINVAL;
480
481 coef_exp = 14 - (coef_exp - 24);
482 coef_man = coef_scaled +
483 (1 << (24 - coef_exp - 1));
484 ds_coef_man = coef_man >> (24 - coef_exp);
485 ds_coef_exp = coef_exp - 16;
486
487 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3,
488 AR5K_PHY_TIMING_3_DSC_MAN, ds_coef_man);
489 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3,
490 AR5K_PHY_TIMING_3_DSC_EXP, ds_coef_exp);
491
492 return 0;
493 }
494
495 /**
496 * ath5k_hw_write_rate_duration - set rate duration during hw resets
497 *
498 * @ah: the &struct ath5k_hw
499 * @driver_mode: one of enum ieee80211_phymode or our one of our own
500 * vendor modes
501 *
502 * Write the rate duration table for the current mode upon hw reset. This
503 * is a helper for ath5k_hw_reset(). It seems all this is doing is setting
504 * an ACK timeout for the hardware for the current mode for each rate. The
505 * rates which are capable of short preamble (802.11b rates 2Mbps, 5.5Mbps,
506 * and 11Mbps) have another register for the short preamble ACK timeout
507 * calculation.
508 *
509 */
510 static inline void ath5k_hw_write_rate_duration(struct ath5k_hw *ah,
511 unsigned int driver_mode)
512 {
513 struct ath5k_softc *sc = ah->ah_sc;
514 const struct ath5k_rate_table *rt;
515 unsigned int i;
516
517 /* Get rate table for the current operating mode */
518 rt = ath5k_hw_get_rate_table(ah,
519 driver_mode);
520
521 /* Write rate duration table */
522 for (i = 0; i < rt->rate_count; i++) {
523 const struct ath5k_rate *rate, *control_rate;
524 u32 reg;
525 u16 tx_time;
526
527 rate = &rt->rates[i];
528 control_rate = &rt->rates[rate->control_rate];
529
530 /* Set ACK timeout */
531 reg = AR5K_RATE_DUR(rate->rate_code);
532
533 /* An ACK frame consists of 10 bytes. If you add the FCS,
534 * which ieee80211_generic_frame_duration() adds,
535 * its 14 bytes. Note we use the control rate and not the
536 * actual rate for this rate. See mac80211 tx.c
537 * ieee80211_duration() for a brief description of
538 * what rate we should choose to TX ACKs. */
539 tx_time = ieee80211_generic_frame_duration(sc->hw,
540 sc->vif, 10, control_rate->rate_kbps/100);
541
542 ath5k_hw_reg_write(ah, tx_time, reg);
543
544 if (!HAS_SHPREAMBLE(i))
545 continue;
546
547 /*
548 * We're not distinguishing short preamble here,
549 * This is true, all we'll get is a longer value here
550 * which is not necessarilly bad. We could use
551 * export ieee80211_frame_duration() but that needs to be
552 * fixed first to be properly used by mac802111 drivers:
553 *
554 * - remove erp stuff and let the routine figure ofdm
555 * erp rates
556 * - remove passing argument ieee80211_local as
557 * drivers don't have access to it
558 * - move drivers using ieee80211_generic_frame_duration()
559 * to this
560 */
561 ath5k_hw_reg_write(ah, tx_time,
562 reg + (AR5K_SET_SHORT_PREAMBLE << 2));
563 }
564 }
565
566 /*
567 * Main reset function
568 */
569 int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode,
570 struct ieee80211_channel *channel, bool change_channel)
571 {
572 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
573 u32 data, s_seq, s_ant, s_led[3];
574 unsigned int i, mode, freq, ee_mode, ant[2], driver_mode = -1;
575 int ret;
576
577 ATH5K_TRACE(ah->ah_sc);
578
579 s_seq = 0;
580 s_ant = 0;
581 ee_mode = 0;
582 freq = 0;
583 mode = 0;
584
585 /*
586 * Save some registers before a reset
587 */
588 /*DCU/Antenna selection not available on 5210*/
589 if (ah->ah_version != AR5K_AR5210) {
590 if (change_channel == true) {
591 /* Seq number for queue 0 -do this for all queues ? */
592 s_seq = ath5k_hw_reg_read(ah,
593 AR5K_QUEUE_DFS_SEQNUM(0));
594 /*Default antenna*/
595 s_ant = ath5k_hw_reg_read(ah, AR5K_DEFAULT_ANTENNA);
596 }
597 }
598
599 /*GPIOs*/
600 s_led[0] = ath5k_hw_reg_read(ah, AR5K_PCICFG) & AR5K_PCICFG_LEDSTATE;
601 s_led[1] = ath5k_hw_reg_read(ah, AR5K_GPIOCR);
602 s_led[2] = ath5k_hw_reg_read(ah, AR5K_GPIODO);
603
604 if (change_channel == true && ah->ah_rf_banks != NULL)
605 ath5k_hw_get_rf_gain(ah);
606
607
608 /*Wakeup the device*/
609 ret = ath5k_hw_nic_wakeup(ah, channel->val, false);
610 if (ret)
611 return ret;
612
613 /*
614 * Initialize operating mode
615 */
616 ah->ah_op_mode = op_mode;
617
618 /*
619 * 5111/5112 Settings
620 * 5210 only comes with RF5110
621 */
622 if (ah->ah_version != AR5K_AR5210) {
623 if (ah->ah_radio != AR5K_RF5111 &&
624 ah->ah_radio != AR5K_RF5112 &&
625 ah->ah_radio != AR5K_RF5413) {
626 ATH5K_ERR(ah->ah_sc,
627 "invalid phy radio: %u\n", ah->ah_radio);
628 return -EINVAL;
629 }
630
631 switch (channel->val & CHANNEL_MODES) {
632 case CHANNEL_A:
633 mode = AR5K_INI_VAL_11A;
634 freq = AR5K_INI_RFGAIN_5GHZ;
635 ee_mode = AR5K_EEPROM_MODE_11A;
636 driver_mode = MODE_IEEE80211A;
637 break;
638 case CHANNEL_G:
639 mode = AR5K_INI_VAL_11G;
640 freq = AR5K_INI_RFGAIN_2GHZ;
641 ee_mode = AR5K_EEPROM_MODE_11G;
642 driver_mode = MODE_IEEE80211G;
643 break;
644 case CHANNEL_B:
645 mode = AR5K_INI_VAL_11B;
646 freq = AR5K_INI_RFGAIN_2GHZ;
647 ee_mode = AR5K_EEPROM_MODE_11B;
648 driver_mode = MODE_IEEE80211B;
649 break;
650 case CHANNEL_T:
651 mode = AR5K_INI_VAL_11A_TURBO;
652 freq = AR5K_INI_RFGAIN_5GHZ;
653 ee_mode = AR5K_EEPROM_MODE_11A;
654 driver_mode = MODE_ATHEROS_TURBO;
655 break;
656 /*Is this ok on 5211 too ?*/
657 case CHANNEL_TG:
658 mode = AR5K_INI_VAL_11G_TURBO;
659 freq = AR5K_INI_RFGAIN_2GHZ;
660 ee_mode = AR5K_EEPROM_MODE_11G;
661 driver_mode = MODE_ATHEROS_TURBOG;
662 break;
663 case CHANNEL_XR:
664 if (ah->ah_version == AR5K_AR5211) {
665 ATH5K_ERR(ah->ah_sc,
666 "XR mode not available on 5211");
667 return -EINVAL;
668 }
669 mode = AR5K_INI_VAL_XR;
670 freq = AR5K_INI_RFGAIN_5GHZ;
671 ee_mode = AR5K_EEPROM_MODE_11A;
672 driver_mode = MODE_IEEE80211A;
673 break;
674 default:
675 ATH5K_ERR(ah->ah_sc,
676 "invalid channel: %d\n", channel->freq);
677 return -EINVAL;
678 }
679
680 /* PHY access enable */
681 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
682
683 }
684
685 ret = ath5k_hw_write_initvals(ah, mode, change_channel);
686 if (ret)
687 return ret;
688
689 /*
690 * 5211/5212 Specific
691 */
692 if (ah->ah_version != AR5K_AR5210) {
693 /*
694 * Write initial RF gain settings
695 * This should work for both 5111/5112
696 */
697 ret = ath5k_hw_rfgain(ah, freq);
698 if (ret)
699 return ret;
700
701 mdelay(1);
702
703 /*
704 * Write some more initial register settings
705 */
706 if (ah->ah_version > AR5K_AR5211){ /* found on 5213+ */
707 ath5k_hw_reg_write(ah, 0x0002a002, AR5K_PHY(11));
708
709 if (channel->val == CHANNEL_G)
710 ath5k_hw_reg_write(ah, 0x00f80d80, AR5K_PHY(83)); /* 0x00fc0ec0 */
711 else
712 ath5k_hw_reg_write(ah, 0x00000000, AR5K_PHY(83));
713
714 ath5k_hw_reg_write(ah, 0x000001b5, 0xa228); /* 0x000009b5 */
715 ath5k_hw_reg_write(ah, 0x000009b5, 0xa228);
716 ath5k_hw_reg_write(ah, 0x0000000f, 0x8060);
717 ath5k_hw_reg_write(ah, 0x00000000, 0xa254);
718 ath5k_hw_reg_write(ah, 0x0000000e, AR5K_PHY_SCAL);
719 }
720
721 /* Fix for first revision of the RF5112 RF chipset */
722 if (ah->ah_radio >= AR5K_RF5112 &&
723 ah->ah_radio_5ghz_revision <
724 AR5K_SREV_RAD_5112A) {
725 ath5k_hw_reg_write(ah, AR5K_PHY_CCKTXCTL_WORLD,
726 AR5K_PHY_CCKTXCTL);
727 if (channel->val & CHANNEL_5GHZ)
728 data = 0xffb81020;
729 else
730 data = 0xffb80d20;
731 ath5k_hw_reg_write(ah, data, AR5K_PHY_FRAME_CTL);
732 }
733
734 /*
735 * Set TX power (FIXME)
736 */
737 ret = ath5k_hw_txpower(ah, channel, AR5K_TUNE_DEFAULT_TXPOWER);
738 if (ret)
739 return ret;
740
741 /* Write rate duration table only on AR5212 and if
742 * virtual interface has already been brought up
743 * XXX: rethink this after new mode changes to
744 * mac80211 are integrated */
745 if (ah->ah_version == AR5K_AR5212 &&
746 ah->ah_sc->vif != NULL)
747 ath5k_hw_write_rate_duration(ah, driver_mode);
748
749 /*
750 * Write RF registers
751 * TODO:Does this work on 5211 (5111) ?
752 */
753 ret = ath5k_hw_rfregs(ah, channel, mode);
754 if (ret)
755 return ret;
756
757 /*
758 * Configure additional registers
759 */
760
761 /* Write OFDM timings on 5212*/
762 if (ah->ah_version == AR5K_AR5212 &&
763 channel->val & CHANNEL_OFDM) {
764 ret = ath5k_hw_write_ofdm_timings(ah, channel);
765 if (ret)
766 return ret;
767 }
768
769 /*Enable/disable 802.11b mode on 5111
770 (enable 2111 frequency converter + CCK)*/
771 if (ah->ah_radio == AR5K_RF5111) {
772 if (driver_mode == MODE_IEEE80211B)
773 AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG,
774 AR5K_TXCFG_B_MODE);
775 else
776 AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG,
777 AR5K_TXCFG_B_MODE);
778 }
779
780 /*
781 * Set channel and calibrate the PHY
782 */
783 ret = ath5k_hw_channel(ah, channel);
784 if (ret)
785 return ret;
786
787 /* Set antenna mode */
788 AR5K_REG_MASKED_BITS(ah, AR5K_PHY(0x44),
789 ah->ah_antenna[ee_mode][0], 0xfffffc06);
790
791 /*
792 * In case a fixed antenna was set as default
793 * write the same settings on both AR5K_PHY_ANT_SWITCH_TABLE
794 * registers.
795 */
796 if (s_ant != 0){
797 if (s_ant == AR5K_ANT_FIXED_A) /* 1 - Main */
798 ant[0] = ant[1] = AR5K_ANT_FIXED_A;
799 else /* 2 - Aux */
800 ant[0] = ant[1] = AR5K_ANT_FIXED_B;
801 } else {
802 ant[0] = AR5K_ANT_FIXED_A;
803 ant[1] = AR5K_ANT_FIXED_B;
804 }
805
806 ath5k_hw_reg_write(ah, ah->ah_antenna[ee_mode][ant[0]],
807 AR5K_PHY_ANT_SWITCH_TABLE_0);
808 ath5k_hw_reg_write(ah, ah->ah_antenna[ee_mode][ant[1]],
809 AR5K_PHY_ANT_SWITCH_TABLE_1);
810
811 /* Commit values from EEPROM */
812 if (ah->ah_radio == AR5K_RF5111)
813 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_FRAME_CTL,
814 AR5K_PHY_FRAME_CTL_TX_CLIP, ee->ee_tx_clip);
815
816 ath5k_hw_reg_write(ah,
817 AR5K_PHY_NF_SVAL(ee->ee_noise_floor_thr[ee_mode]),
818 AR5K_PHY(0x5a));
819
820 AR5K_REG_MASKED_BITS(ah, AR5K_PHY(0x11),
821 (ee->ee_switch_settling[ee_mode] << 7) & 0x3f80,
822 0xffffc07f);
823 AR5K_REG_MASKED_BITS(ah, AR5K_PHY(0x12),
824 (ee->ee_ant_tx_rx[ee_mode] << 12) & 0x3f000,
825 0xfffc0fff);
826 AR5K_REG_MASKED_BITS(ah, AR5K_PHY(0x14),
827 (ee->ee_adc_desired_size[ee_mode] & 0x00ff) |
828 ((ee->ee_pga_desired_size[ee_mode] << 8) & 0xff00),
829 0xffff0000);
830
831 ath5k_hw_reg_write(ah,
832 (ee->ee_tx_end2xpa_disable[ee_mode] << 24) |
833 (ee->ee_tx_end2xpa_disable[ee_mode] << 16) |
834 (ee->ee_tx_frm2xpa_enable[ee_mode] << 8) |
835 (ee->ee_tx_frm2xpa_enable[ee_mode]), AR5K_PHY(0x0d));
836
837 AR5K_REG_MASKED_BITS(ah, AR5K_PHY(0x0a),
838 ee->ee_tx_end2xlna_enable[ee_mode] << 8, 0xffff00ff);
839 AR5K_REG_MASKED_BITS(ah, AR5K_PHY(0x19),
840 (ee->ee_thr_62[ee_mode] << 12) & 0x7f000, 0xfff80fff);
841 AR5K_REG_MASKED_BITS(ah, AR5K_PHY(0x49), 4, 0xffffff01);
842
843 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ,
844 AR5K_PHY_IQ_CORR_ENABLE |
845 (ee->ee_i_cal[ee_mode] << AR5K_PHY_IQ_CORR_Q_I_COFF_S) |
846 ee->ee_q_cal[ee_mode]);
847
848 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1)
849 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN_2GHZ,
850 AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX,
851 ee->ee_margin_tx_rx[ee_mode]);
852
853 } else {
854 mdelay(1);
855 /* Disable phy and wait */
856 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
857 mdelay(1);
858 }
859
860 /*
861 * Restore saved values
862 */
863 /*DCU/Antenna selection not available on 5210*/
864 if (ah->ah_version != AR5K_AR5210) {
865 ath5k_hw_reg_write(ah, s_seq, AR5K_QUEUE_DFS_SEQNUM(0));
866 ath5k_hw_reg_write(ah, s_ant, AR5K_DEFAULT_ANTENNA);
867 }
868 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, s_led[0]);
869 ath5k_hw_reg_write(ah, s_led[1], AR5K_GPIOCR);
870 ath5k_hw_reg_write(ah, s_led[2], AR5K_GPIODO);
871
872 /*
873 * Misc
874 */
875 /* XXX: add ah->aid once mac80211 gives this to us */
876 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
877
878 ath5k_hw_set_opmode(ah);
879 /*PISR/SISR Not available on 5210*/
880 if (ah->ah_version != AR5K_AR5210) {
881 ath5k_hw_reg_write(ah, 0xffffffff, AR5K_PISR);
882 /* If we later allow tuning for this, store into sc structure */
883 data = AR5K_TUNE_RSSI_THRES |
884 AR5K_TUNE_BMISS_THRES << AR5K_RSSI_THR_BMISS_S;
885 ath5k_hw_reg_write(ah, data, AR5K_RSSI_THR);
886 }
887
888 /*
889 * Set Rx/Tx DMA Configuration
890 *(passing dma size not available on 5210)
891 */
892 if (ah->ah_version != AR5K_AR5210) {
893 AR5K_REG_WRITE_BITS(ah, AR5K_TXCFG, AR5K_TXCFG_SDMAMR,
894 AR5K_DMASIZE_512B | AR5K_TXCFG_DMASIZE);
895 AR5K_REG_WRITE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_SDMAMW,
896 AR5K_DMASIZE_512B);
897 }
898
899 /*
900 * Enable the PHY and wait until completion
901 */
902 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT);
903
904 /*
905 * 5111/5112 Specific
906 */
907 if (ah->ah_version != AR5K_AR5210) {
908 data = ath5k_hw_reg_read(ah, AR5K_PHY_RX_DELAY) &
909 AR5K_PHY_RX_DELAY_M;
910 data = (channel->val & CHANNEL_CCK) ?
911 ((data << 2) / 22) : (data / 10);
912
913 udelay(100 + data);
914 } else {
915 mdelay(1);
916 }
917
918 /*
919 * Enable calibration and wait until completion
920 */
921 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
922 AR5K_PHY_AGCCTL_CAL);
923
924 if (ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
925 AR5K_PHY_AGCCTL_CAL, 0, false)) {
926 ATH5K_ERR(ah->ah_sc, "calibration timeout (%uMHz)\n",
927 channel->freq);
928 return -EAGAIN;
929 }
930
931 ret = ath5k_hw_noise_floor_calibration(ah, channel->freq);
932 if (ret)
933 return ret;
934
935 ah->ah_calibration = false;
936
937 /* A and G modes can use QAM modulation which requires enabling
938 * I and Q calibration. Don't bother in B mode. */
939 if (!(driver_mode == MODE_IEEE80211B)) {
940 ah->ah_calibration = true;
941 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ,
942 AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15);
943 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ,
944 AR5K_PHY_IQ_RUN);
945 }
946
947 /*
948 * Reset queues and start beacon timers at the end of the reset routine
949 */
950 for (i = 0; i < ah->ah_capabilities.cap_queues.q_tx_num; i++) {
951 /*No QCU on 5210*/
952 if (ah->ah_version != AR5K_AR5210)
953 AR5K_REG_WRITE_Q(ah, AR5K_QUEUE_QCUMASK(i), i);
954
955 ret = ath5k_hw_reset_tx_queue(ah, i);
956 if (ret) {
957 ATH5K_ERR(ah->ah_sc,
958 "failed to reset TX queue #%d\n", i);
959 return ret;
960 }
961 }
962
963 /* Pre-enable interrupts on 5211/5212*/
964 if (ah->ah_version != AR5K_AR5210)
965 ath5k_hw_set_intr(ah, AR5K_INT_RX | AR5K_INT_TX |
966 AR5K_INT_FATAL);
967
968 /*
969 * Set RF kill flags if supported by the device (read from the EEPROM)
970 * Disable gpio_intr for now since it results system hang.
971 * TODO: Handle this in ath5k_intr
972 */
973 #if 0
974 if (AR5K_EEPROM_HDR_RFKILL(ah->ah_capabilities.cap_eeprom.ee_header)) {
975 ath5k_hw_set_gpio_input(ah, 0);
976 ah->ah_gpio[0] = ath5k_hw_get_gpio(ah, 0);
977 if (ah->ah_gpio[0] == 0)
978 ath5k_hw_set_gpio_intr(ah, 0, 1);
979 else
980 ath5k_hw_set_gpio_intr(ah, 0, 0);
981 }
982 #endif
983
984 /*
985 * Set the 32MHz reference clock on 5212 phy clock sleep register
986 */
987 if (ah->ah_version == AR5K_AR5212) {
988 ath5k_hw_reg_write(ah, AR5K_PHY_SCR_32MHZ, AR5K_PHY_SCR);
989 ath5k_hw_reg_write(ah, AR5K_PHY_SLMT_32MHZ, AR5K_PHY_SLMT);
990 ath5k_hw_reg_write(ah, AR5K_PHY_SCAL_32MHZ, AR5K_PHY_SCAL);
991 ath5k_hw_reg_write(ah, AR5K_PHY_SCLOCK_32MHZ, AR5K_PHY_SCLOCK);
992 ath5k_hw_reg_write(ah, AR5K_PHY_SDELAY_32MHZ, AR5K_PHY_SDELAY);
993 ath5k_hw_reg_write(ah, ah->ah_radio == AR5K_RF5111 ?
994 AR5K_PHY_SPENDING_RF5111 : AR5K_PHY_SPENDING_RF5112,
995 AR5K_PHY_SPENDING);
996 }
997
998 /*
999 * Disable beacons and reset the register
1000 */
1001 AR5K_REG_DISABLE_BITS(ah, AR5K_BEACON, AR5K_BEACON_ENABLE |
1002 AR5K_BEACON_RESET_TSF);
1003
1004 return 0;
1005 }
1006
1007 /*
1008 * Reset chipset
1009 */
1010 static int ath5k_hw_nic_reset(struct ath5k_hw *ah, u32 val)
1011 {
1012 int ret;
1013 u32 mask = val ? val : ~0U;
1014
1015 ATH5K_TRACE(ah->ah_sc);
1016
1017 /* Read-and-clear RX Descriptor Pointer*/
1018 ath5k_hw_reg_read(ah, AR5K_RXDP);
1019
1020 /*
1021 * Reset the device and wait until success
1022 */
1023 ath5k_hw_reg_write(ah, val, AR5K_RESET_CTL);
1024
1025 /* Wait at least 128 PCI clocks */
1026 udelay(15);
1027
1028 if (ah->ah_version == AR5K_AR5210) {
1029 val &= AR5K_RESET_CTL_CHIP;
1030 mask &= AR5K_RESET_CTL_CHIP;
1031 } else {
1032 val &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND;
1033 mask &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND;
1034 }
1035
1036 ret = ath5k_hw_register_timeout(ah, AR5K_RESET_CTL, mask, val, false);
1037
1038 /*
1039 * Reset configuration register (for hw byte-swap). Note that this
1040 * is only set for big endian. We do the necessary magic in
1041 * AR5K_INIT_CFG.
1042 */
1043 if ((val & AR5K_RESET_CTL_PCU) == 0)
1044 ath5k_hw_reg_write(ah, AR5K_INIT_CFG, AR5K_CFG);
1045
1046 return ret;
1047 }
1048
1049 /*
1050 * Power management functions
1051 */
1052
1053 /*
1054 * Sleep control
1055 */
1056 int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode,
1057 bool set_chip, u16 sleep_duration)
1058 {
1059 unsigned int i;
1060 u32 staid;
1061
1062 ATH5K_TRACE(ah->ah_sc);
1063 staid = ath5k_hw_reg_read(ah, AR5K_STA_ID1);
1064
1065 switch (mode) {
1066 case AR5K_PM_AUTO:
1067 staid &= ~AR5K_STA_ID1_DEFAULT_ANTENNA;
1068 /* fallthrough */
1069 case AR5K_PM_NETWORK_SLEEP:
1070 if (set_chip == true)
1071 ath5k_hw_reg_write(ah,
1072 AR5K_SLEEP_CTL_SLE | sleep_duration,
1073 AR5K_SLEEP_CTL);
1074
1075 staid |= AR5K_STA_ID1_PWR_SV;
1076 break;
1077
1078 case AR5K_PM_FULL_SLEEP:
1079 if (set_chip == true)
1080 ath5k_hw_reg_write(ah, AR5K_SLEEP_CTL_SLE_SLP,
1081 AR5K_SLEEP_CTL);
1082
1083 staid |= AR5K_STA_ID1_PWR_SV;
1084 break;
1085
1086 case AR5K_PM_AWAKE:
1087 if (set_chip == false)
1088 goto commit;
1089
1090 ath5k_hw_reg_write(ah, AR5K_SLEEP_CTL_SLE_WAKE,
1091 AR5K_SLEEP_CTL);
1092
1093 for (i = 5000; i > 0; i--) {
1094 /* Check if the chip did wake up */
1095 if ((ath5k_hw_reg_read(ah, AR5K_PCICFG) &
1096 AR5K_PCICFG_SPWR_DN) == 0)
1097 break;
1098
1099 /* Wait a bit and retry */
1100 udelay(200);
1101 ath5k_hw_reg_write(ah, AR5K_SLEEP_CTL_SLE_WAKE,
1102 AR5K_SLEEP_CTL);
1103 }
1104
1105 /* Fail if the chip didn't wake up */
1106 if (i <= 0)
1107 return -EIO;
1108
1109 staid &= ~AR5K_STA_ID1_PWR_SV;
1110 break;
1111
1112 default:
1113 return -EINVAL;
1114 }
1115
1116 commit:
1117 ah->ah_power_mode = mode;
1118 ath5k_hw_reg_write(ah, staid, AR5K_STA_ID1);
1119
1120 return 0;
1121 }
1122
1123 /***********************\
1124 DMA Related Functions
1125 \***********************/
1126
1127 /*
1128 * Receive functions
1129 */
1130
1131 /*
1132 * Start DMA receive
1133 */
1134 void ath5k_hw_start_rx(struct ath5k_hw *ah)
1135 {
1136 ATH5K_TRACE(ah->ah_sc);
1137 ath5k_hw_reg_write(ah, AR5K_CR_RXE, AR5K_CR);
1138 }
1139
1140 /*
1141 * Stop DMA receive
1142 */
1143 int ath5k_hw_stop_rx_dma(struct ath5k_hw *ah)
1144 {
1145 unsigned int i;
1146
1147 ATH5K_TRACE(ah->ah_sc);
1148 ath5k_hw_reg_write(ah, AR5K_CR_RXD, AR5K_CR);
1149
1150 /*
1151 * It may take some time to disable the DMA receive unit
1152 */
1153 for (i = 2000; i > 0 &&
1154 (ath5k_hw_reg_read(ah, AR5K_CR) & AR5K_CR_RXE) != 0;
1155 i--)
1156 udelay(10);
1157
1158 return i ? 0 : -EBUSY;
1159 }
1160
1161 /*
1162 * Get the address of the RX Descriptor
1163 */
1164 u32 ath5k_hw_get_rx_buf(struct ath5k_hw *ah)
1165 {
1166 return ath5k_hw_reg_read(ah, AR5K_RXDP);
1167 }
1168
1169 /*
1170 * Set the address of the RX Descriptor
1171 */
1172 void ath5k_hw_put_rx_buf(struct ath5k_hw *ah, u32 phys_addr)
1173 {
1174 ATH5K_TRACE(ah->ah_sc);
1175
1176 /*TODO:Shouldn't we check if RX is enabled first ?*/
1177 ath5k_hw_reg_write(ah, phys_addr, AR5K_RXDP);
1178 }
1179
1180 /*
1181 * Transmit functions
1182 */
1183
1184 /*
1185 * Start DMA transmit for a specific queue
1186 * (see also QCU/DCU functions)
1187 */
1188 int ath5k_hw_tx_start(struct ath5k_hw *ah, unsigned int queue)
1189 {
1190 u32 tx_queue;
1191
1192 ATH5K_TRACE(ah->ah_sc);
1193 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
1194
1195 /* Return if queue is declared inactive */
1196 if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)
1197 return -EIO;
1198
1199 if (ah->ah_version == AR5K_AR5210) {
1200 tx_queue = ath5k_hw_reg_read(ah, AR5K_CR);
1201
1202 /*
1203 * Set the queue by type on 5210
1204 */
1205 switch (ah->ah_txq[queue].tqi_type) {
1206 case AR5K_TX_QUEUE_DATA:
1207 tx_queue |= AR5K_CR_TXE0 & ~AR5K_CR_TXD0;
1208 break;
1209 case AR5K_TX_QUEUE_BEACON:
1210 tx_queue |= AR5K_CR_TXE1 & ~AR5K_CR_TXD1;
1211 ath5k_hw_reg_write(ah, AR5K_BCR_TQ1V | AR5K_BCR_BDMAE,
1212 AR5K_BSR);
1213 break;
1214 case AR5K_TX_QUEUE_CAB:
1215 tx_queue |= AR5K_CR_TXE1 & ~AR5K_CR_TXD1;
1216 ath5k_hw_reg_write(ah, AR5K_BCR_TQ1FV | AR5K_BCR_TQ1V |
1217 AR5K_BCR_BDMAE, AR5K_BSR);
1218 break;
1219 default:
1220 return -EINVAL;
1221 }
1222 /* Start queue */
1223 ath5k_hw_reg_write(ah, tx_queue, AR5K_CR);
1224 } else {
1225 /* Return if queue is disabled */
1226 if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXD, queue))
1227 return -EIO;
1228
1229 /* Start queue */
1230 AR5K_REG_WRITE_Q(ah, AR5K_QCU_TXE, queue);
1231 }
1232
1233 return 0;
1234 }
1235
1236 /*
1237 * Stop DMA transmit for a specific queue
1238 * (see also QCU/DCU functions)
1239 */
1240 int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue)
1241 {
1242 unsigned int i = 100;
1243 u32 tx_queue, pending;
1244
1245 ATH5K_TRACE(ah->ah_sc);
1246 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
1247
1248 /* Return if queue is declared inactive */
1249 if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)
1250 return -EIO;
1251
1252 if (ah->ah_version == AR5K_AR5210) {
1253 tx_queue = ath5k_hw_reg_read(ah, AR5K_CR);
1254
1255 /*
1256 * Set by queue type
1257 */
1258 switch (ah->ah_txq[queue].tqi_type) {
1259 case AR5K_TX_QUEUE_DATA:
1260 tx_queue |= AR5K_CR_TXD0 & ~AR5K_CR_TXE0;
1261 break;
1262 case AR5K_TX_QUEUE_BEACON:
1263 case AR5K_TX_QUEUE_CAB:
1264 /* XXX Fix me... */
1265 tx_queue |= AR5K_CR_TXD1 & ~AR5K_CR_TXD1;
1266 ath5k_hw_reg_write(ah, 0, AR5K_BSR);
1267 break;
1268 default:
1269 return -EINVAL;
1270 }
1271
1272 /* Stop queue */
1273 ath5k_hw_reg_write(ah, tx_queue, AR5K_CR);
1274 } else {
1275 /*
1276 * Schedule TX disable and wait until queue is empty
1277 */
1278 AR5K_REG_WRITE_Q(ah, AR5K_QCU_TXD, queue);
1279
1280 /*Check for pending frames*/
1281 do {
1282 pending = ath5k_hw_reg_read(ah,
1283 AR5K_QUEUE_STATUS(queue)) &
1284 AR5K_QCU_STS_FRMPENDCNT;
1285 udelay(100);
1286 } while (--i && pending);
1287
1288 /* Clear register */
1289 ath5k_hw_reg_write(ah, 0, AR5K_QCU_TXD);
1290 }
1291
1292 /* TODO: Check for success else return error */
1293 return 0;
1294 }
1295
1296 /*
1297 * Get the address of the TX Descriptor for a specific queue
1298 * (see also QCU/DCU functions)
1299 */
1300 u32 ath5k_hw_get_tx_buf(struct ath5k_hw *ah, unsigned int queue)
1301 {
1302 u16 tx_reg;
1303
1304 ATH5K_TRACE(ah->ah_sc);
1305 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
1306
1307 /*
1308 * Get the transmit queue descriptor pointer from the selected queue
1309 */
1310 /*5210 doesn't have QCU*/
1311 if (ah->ah_version == AR5K_AR5210) {
1312 switch (ah->ah_txq[queue].tqi_type) {
1313 case AR5K_TX_QUEUE_DATA:
1314 tx_reg = AR5K_NOQCU_TXDP0;
1315 break;
1316 case AR5K_TX_QUEUE_BEACON:
1317 case AR5K_TX_QUEUE_CAB:
1318 tx_reg = AR5K_NOQCU_TXDP1;
1319 break;
1320 default:
1321 return 0xffffffff;
1322 }
1323 } else {
1324 tx_reg = AR5K_QUEUE_TXDP(queue);
1325 }
1326
1327 return ath5k_hw_reg_read(ah, tx_reg);
1328 }
1329
1330 /*
1331 * Set the address of the TX Descriptor for a specific queue
1332 * (see also QCU/DCU functions)
1333 */
1334 int ath5k_hw_put_tx_buf(struct ath5k_hw *ah, unsigned int queue, u32 phys_addr)
1335 {
1336 u16 tx_reg;
1337
1338 ATH5K_TRACE(ah->ah_sc);
1339 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
1340
1341 /*
1342 * Set the transmit queue descriptor pointer register by type
1343 * on 5210
1344 */
1345 if (ah->ah_version == AR5K_AR5210) {
1346 switch (ah->ah_txq[queue].tqi_type) {
1347 case AR5K_TX_QUEUE_DATA:
1348 tx_reg = AR5K_NOQCU_TXDP0;
1349 break;
1350 case AR5K_TX_QUEUE_BEACON:
1351 case AR5K_TX_QUEUE_CAB:
1352 tx_reg = AR5K_NOQCU_TXDP1;
1353 break;
1354 default:
1355 return -EINVAL;
1356 }
1357 } else {
1358 /*
1359 * Set the transmit queue descriptor pointer for
1360 * the selected queue on QCU for 5211+
1361 * (this won't work if the queue is still active)
1362 */
1363 if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXE, queue))
1364 return -EIO;
1365
1366 tx_reg = AR5K_QUEUE_TXDP(queue);
1367 }
1368
1369 /* Set descriptor pointer */
1370 ath5k_hw_reg_write(ah, phys_addr, tx_reg);
1371
1372 return 0;
1373 }
1374
1375 /*
1376 * Update tx trigger level
1377 */
1378 int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, bool increase)
1379 {
1380 u32 trigger_level, imr;
1381 int ret = -EIO;
1382
1383 ATH5K_TRACE(ah->ah_sc);
1384
1385 /*
1386 * Disable interrupts by setting the mask
1387 */
1388 imr = ath5k_hw_set_intr(ah, ah->ah_imr & ~AR5K_INT_GLOBAL);
1389
1390 /*TODO: Boundary check on trigger_level*/
1391 trigger_level = AR5K_REG_MS(ath5k_hw_reg_read(ah, AR5K_TXCFG),
1392 AR5K_TXCFG_TXFULL);
1393
1394 if (increase == false) {
1395 if (--trigger_level < AR5K_TUNE_MIN_TX_FIFO_THRES)
1396 goto done;
1397 } else
1398 trigger_level +=
1399 ((AR5K_TUNE_MAX_TX_FIFO_THRES - trigger_level) / 2);
1400
1401 /*
1402 * Update trigger level on success
1403 */
1404 if (ah->ah_version == AR5K_AR5210)
1405 ath5k_hw_reg_write(ah, trigger_level, AR5K_TRIG_LVL);
1406 else
1407 AR5K_REG_WRITE_BITS(ah, AR5K_TXCFG,
1408 AR5K_TXCFG_TXFULL, trigger_level);
1409
1410 ret = 0;
1411
1412 done:
1413 /*
1414 * Restore interrupt mask
1415 */
1416 ath5k_hw_set_intr(ah, imr);
1417
1418 return ret;
1419 }
1420
1421 /*
1422 * Interrupt handling
1423 */
1424
1425 /*
1426 * Check if we have pending interrupts
1427 */
1428 bool ath5k_hw_is_intr_pending(struct ath5k_hw *ah)
1429 {
1430 ATH5K_TRACE(ah->ah_sc);
1431 return ath5k_hw_reg_read(ah, AR5K_INTPEND);
1432 }
1433
1434 /*
1435 * Get interrupt mask (ISR)
1436 */
1437 int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask)
1438 {
1439 u32 data;
1440
1441 ATH5K_TRACE(ah->ah_sc);
1442
1443 /*
1444 * Read interrupt status from the Interrupt Status register
1445 * on 5210
1446 */
1447 if (ah->ah_version == AR5K_AR5210) {
1448 data = ath5k_hw_reg_read(ah, AR5K_ISR);
1449 if (unlikely(data == AR5K_INT_NOCARD)) {
1450 *interrupt_mask = data;
1451 return -ENODEV;
1452 }
1453 } else {
1454 /*
1455 * Read interrupt status from the Read-And-Clear shadow register
1456 * Note: PISR/SISR Not available on 5210
1457 */
1458 data = ath5k_hw_reg_read(ah, AR5K_RAC_PISR);
1459 }
1460
1461 /*
1462 * Get abstract interrupt mask (driver-compatible)
1463 */
1464 *interrupt_mask = (data & AR5K_INT_COMMON) & ah->ah_imr;
1465
1466 if (unlikely(data == AR5K_INT_NOCARD))
1467 return -ENODEV;
1468
1469 if (data & (AR5K_ISR_RXOK | AR5K_ISR_RXERR))
1470 *interrupt_mask |= AR5K_INT_RX;
1471
1472 if (data & (AR5K_ISR_TXOK | AR5K_ISR_TXERR
1473 | AR5K_ISR_TXDESC | AR5K_ISR_TXEOL))
1474 *interrupt_mask |= AR5K_INT_TX;
1475
1476 if (ah->ah_version != AR5K_AR5210) {
1477 /*HIU = Host Interface Unit (PCI etc)*/
1478 if (unlikely(data & (AR5K_ISR_HIUERR)))
1479 *interrupt_mask |= AR5K_INT_FATAL;
1480
1481 /*Beacon Not Ready*/
1482 if (unlikely(data & (AR5K_ISR_BNR)))
1483 *interrupt_mask |= AR5K_INT_BNR;
1484 }
1485
1486 /*
1487 * XXX: BMISS interrupts may occur after association.
1488 * I found this on 5210 code but it needs testing. If this is
1489 * true we should disable them before assoc and re-enable them
1490 * after a successfull assoc + some jiffies.
1491 */
1492 #if 0
1493 interrupt_mask &= ~AR5K_INT_BMISS;
1494 #endif
1495
1496 /*
1497 * In case we didn't handle anything,
1498 * print the register value.
1499 */
1500 if (unlikely(*interrupt_mask == 0 && net_ratelimit()))
1501 ATH5K_PRINTF("0x%08x\n", data);
1502
1503 return 0;
1504 }
1505
1506 /*
1507 * Set interrupt mask
1508 */
1509 enum ath5k_int ath5k_hw_set_intr(struct ath5k_hw *ah, enum ath5k_int new_mask)
1510 {
1511 enum ath5k_int old_mask, int_mask;
1512
1513 /*
1514 * Disable card interrupts to prevent any race conditions
1515 * (they will be re-enabled afterwards).
1516 */
1517 ath5k_hw_reg_write(ah, AR5K_IER_DISABLE, AR5K_IER);
1518
1519 old_mask = ah->ah_imr;
1520
1521 /*
1522 * Add additional, chipset-dependent interrupt mask flags
1523 * and write them to the IMR (interrupt mask register).
1524 */
1525 int_mask = new_mask & AR5K_INT_COMMON;
1526
1527 if (new_mask & AR5K_INT_RX)
1528 int_mask |= AR5K_IMR_RXOK | AR5K_IMR_RXERR | AR5K_IMR_RXORN |
1529 AR5K_IMR_RXDESC;
1530
1531 if (new_mask & AR5K_INT_TX)
1532 int_mask |= AR5K_IMR_TXOK | AR5K_IMR_TXERR | AR5K_IMR_TXDESC |
1533 AR5K_IMR_TXURN;
1534
1535 if (ah->ah_version != AR5K_AR5210) {
1536 if (new_mask & AR5K_INT_FATAL) {
1537 int_mask |= AR5K_IMR_HIUERR;
1538 AR5K_REG_ENABLE_BITS(ah, AR5K_SIMR2, AR5K_SIMR2_MCABT |
1539 AR5K_SIMR2_SSERR | AR5K_SIMR2_DPERR);
1540 }
1541 }
1542
1543 ath5k_hw_reg_write(ah, int_mask, AR5K_PIMR);
1544
1545 /* Store new interrupt mask */
1546 ah->ah_imr = new_mask;
1547
1548 /* ..re-enable interrupts */
1549 ath5k_hw_reg_write(ah, AR5K_IER_ENABLE, AR5K_IER);
1550
1551 return old_mask;
1552 }
1553
1554
1555 /*************************\
1556 EEPROM access functions
1557 \*************************/
1558
1559 /*
1560 * Read from eeprom
1561 */
1562 static int ath5k_hw_eeprom_read(struct ath5k_hw *ah, u32 offset, u16 *data)
1563 {
1564 u32 status, timeout;
1565
1566 ATH5K_TRACE(ah->ah_sc);
1567 /*
1568 * Initialize EEPROM access
1569 */
1570 if (ah->ah_version == AR5K_AR5210) {
1571 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_EEAE);
1572 (void)ath5k_hw_reg_read(ah, AR5K_EEPROM_BASE + (4 * offset));
1573 } else {
1574 ath5k_hw_reg_write(ah, offset, AR5K_EEPROM_BASE);
1575 AR5K_REG_ENABLE_BITS(ah, AR5K_EEPROM_CMD,
1576 AR5K_EEPROM_CMD_READ);
1577 }
1578
1579 for (timeout = AR5K_TUNE_REGISTER_TIMEOUT; timeout > 0; timeout--) {
1580 status = ath5k_hw_reg_read(ah, AR5K_EEPROM_STATUS);
1581 if (status & AR5K_EEPROM_STAT_RDDONE) {
1582 if (status & AR5K_EEPROM_STAT_RDERR)
1583 return -EIO;
1584 *data = (u16)(ath5k_hw_reg_read(ah, AR5K_EEPROM_DATA) &
1585 0xffff);
1586 return 0;
1587 }
1588 udelay(15);
1589 }
1590
1591 return -ETIMEDOUT;
1592 }
1593
1594 /*
1595 * Write to eeprom - currently disabled, use at your own risk
1596 */
1597 static int ath5k_hw_eeprom_write(struct ath5k_hw *ah, u32 offset, u16 data)
1598 {
1599 #if 0
1600 u32 status, timeout;
1601
1602 ATH5K_TRACE(ah->ah_sc);
1603
1604 /*
1605 * Initialize eeprom access
1606 */
1607
1608 if (ah->ah_version == AR5K_AR5210) {
1609 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_EEAE);
1610 } else {
1611 AR5K_REG_ENABLE_BITS(ah, AR5K_EEPROM_CMD,
1612 AR5K_EEPROM_CMD_RESET);
1613 }
1614
1615 /*
1616 * Write data to data register
1617 */
1618
1619 if (ah->ah_version == AR5K_AR5210) {
1620 ath5k_hw_reg_write(ah, data, AR5K_EEPROM_BASE + (4 * offset));
1621 } else {
1622 ath5k_hw_reg_write(ah, offset, AR5K_EEPROM_BASE);
1623 ath5k_hw_reg_write(ah, data, AR5K_EEPROM_DATA);
1624 AR5K_REG_ENABLE_BITS(ah, AR5K_EEPROM_CMD,
1625 AR5K_EEPROM_CMD_WRITE);
1626 }
1627
1628 /*
1629 * Check status
1630 */
1631
1632 for (timeout = AR5K_TUNE_REGISTER_TIMEOUT; timeout > 0; timeout--) {
1633 status = ath5k_hw_reg_read(ah, AR5K_EEPROM_STATUS);
1634 if (status & AR5K_EEPROM_STAT_WRDONE) {
1635 if (status & AR5K_EEPROM_STAT_WRERR)
1636 return EIO;
1637 return 0;
1638 }
1639 udelay(15);
1640 }
1641 #endif
1642 ATH5K_ERR(ah->ah_sc, "EEPROM Write is disabled!");
1643 return -EIO;
1644 }
1645
1646 /*
1647 * Translate binary channel representation in EEPROM to frequency
1648 */
1649 static u16 ath5k_eeprom_bin2freq(struct ath5k_hw *ah, u16 bin, unsigned int mode)
1650 {
1651 u16 val;
1652
1653 if (bin == AR5K_EEPROM_CHANNEL_DIS)
1654 return bin;
1655
1656 if (mode == AR5K_EEPROM_MODE_11A) {
1657 if (ah->ah_ee_version > AR5K_EEPROM_VERSION_3_2)
1658 val = (5 * bin) + 4800;
1659 else
1660 val = bin > 62 ? (10 * 62) + (5 * (bin - 62)) + 5100 :
1661 (bin * 10) + 5100;
1662 } else {
1663 if (ah->ah_ee_version > AR5K_EEPROM_VERSION_3_2)
1664 val = bin + 2300;
1665 else
1666 val = bin + 2400;
1667 }
1668
1669 return val;
1670 }
1671
1672 /*
1673 * Read antenna infos from eeprom
1674 */
1675 static int ath5k_eeprom_read_ants(struct ath5k_hw *ah, u32 *offset,
1676 unsigned int mode)
1677 {
1678 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1679 u32 o = *offset;
1680 u16 val;
1681 int ret, i = 0;
1682
1683 AR5K_EEPROM_READ(o++, val);
1684 ee->ee_switch_settling[mode] = (val >> 8) & 0x7f;
1685 ee->ee_ant_tx_rx[mode] = (val >> 2) & 0x3f;
1686 ee->ee_ant_control[mode][i] = (val << 4) & 0x3f;
1687
1688 AR5K_EEPROM_READ(o++, val);
1689 ee->ee_ant_control[mode][i++] |= (val >> 12) & 0xf;
1690 ee->ee_ant_control[mode][i++] = (val >> 6) & 0x3f;
1691 ee->ee_ant_control[mode][i++] = val & 0x3f;
1692
1693 AR5K_EEPROM_READ(o++, val);
1694 ee->ee_ant_control[mode][i++] = (val >> 10) & 0x3f;
1695 ee->ee_ant_control[mode][i++] = (val >> 4) & 0x3f;
1696 ee->ee_ant_control[mode][i] = (val << 2) & 0x3f;
1697
1698 AR5K_EEPROM_READ(o++, val);
1699 ee->ee_ant_control[mode][i++] |= (val >> 14) & 0x3;
1700 ee->ee_ant_control[mode][i++] = (val >> 8) & 0x3f;
1701 ee->ee_ant_control[mode][i++] = (val >> 2) & 0x3f;
1702 ee->ee_ant_control[mode][i] = (val << 4) & 0x3f;
1703
1704 AR5K_EEPROM_READ(o++, val);
1705 ee->ee_ant_control[mode][i++] |= (val >> 12) & 0xf;
1706 ee->ee_ant_control[mode][i++] = (val >> 6) & 0x3f;
1707 ee->ee_ant_control[mode][i++] = val & 0x3f;
1708
1709 /* Get antenna modes */
1710 ah->ah_antenna[mode][0] =
1711 (ee->ee_ant_control[mode][0] << 4) | 0x1;
1712 ah->ah_antenna[mode][AR5K_ANT_FIXED_A] =
1713 ee->ee_ant_control[mode][1] |
1714 (ee->ee_ant_control[mode][2] << 6) |
1715 (ee->ee_ant_control[mode][3] << 12) |
1716 (ee->ee_ant_control[mode][4] << 18) |
1717 (ee->ee_ant_control[mode][5] << 24);
1718 ah->ah_antenna[mode][AR5K_ANT_FIXED_B] =
1719 ee->ee_ant_control[mode][6] |
1720 (ee->ee_ant_control[mode][7] << 6) |
1721 (ee->ee_ant_control[mode][8] << 12) |
1722 (ee->ee_ant_control[mode][9] << 18) |
1723 (ee->ee_ant_control[mode][10] << 24);
1724
1725 /* return new offset */
1726 *offset = o;
1727
1728 return 0;
1729 }
1730
1731 /*
1732 * Read supported modes from eeprom
1733 */
1734 static int ath5k_eeprom_read_modes(struct ath5k_hw *ah, u32 *offset,
1735 unsigned int mode)
1736 {
1737 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1738 u32 o = *offset;
1739 u16 val;
1740 int ret;
1741
1742 AR5K_EEPROM_READ(o++, val);
1743 ee->ee_tx_end2xlna_enable[mode] = (val >> 8) & 0xff;
1744 ee->ee_thr_62[mode] = val & 0xff;
1745
1746 if (ah->ah_ee_version <= AR5K_EEPROM_VERSION_3_2)
1747 ee->ee_thr_62[mode] = mode == AR5K_EEPROM_MODE_11A ? 15 : 28;
1748
1749 AR5K_EEPROM_READ(o++, val);
1750 ee->ee_tx_end2xpa_disable[mode] = (val >> 8) & 0xff;
1751 ee->ee_tx_frm2xpa_enable[mode] = val & 0xff;
1752
1753 AR5K_EEPROM_READ(o++, val);
1754 ee->ee_pga_desired_size[mode] = (val >> 8) & 0xff;
1755
1756 if ((val & 0xff) & 0x80)
1757 ee->ee_noise_floor_thr[mode] = -((((val & 0xff) ^ 0xff)) + 1);
1758 else
1759 ee->ee_noise_floor_thr[mode] = val & 0xff;
1760
1761 if (ah->ah_ee_version <= AR5K_EEPROM_VERSION_3_2)
1762 ee->ee_noise_floor_thr[mode] =
1763 mode == AR5K_EEPROM_MODE_11A ? -54 : -1;
1764
1765 AR5K_EEPROM_READ(o++, val);
1766 ee->ee_xlna_gain[mode] = (val >> 5) & 0xff;
1767 ee->ee_x_gain[mode] = (val >> 1) & 0xf;
1768 ee->ee_xpd[mode] = val & 0x1;
1769
1770 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0)
1771 ee->ee_fixed_bias[mode] = (val >> 13) & 0x1;
1772
1773 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_3_3) {
1774 AR5K_EEPROM_READ(o++, val);
1775 ee->ee_false_detect[mode] = (val >> 6) & 0x7f;
1776
1777 if (mode == AR5K_EEPROM_MODE_11A)
1778 ee->ee_xr_power[mode] = val & 0x3f;
1779 else {
1780 ee->ee_ob[mode][0] = val & 0x7;
1781 ee->ee_db[mode][0] = (val >> 3) & 0x7;
1782 }
1783 }
1784
1785 if (ah->ah_ee_version < AR5K_EEPROM_VERSION_3_4) {
1786 ee->ee_i_gain[mode] = AR5K_EEPROM_I_GAIN;
1787 ee->ee_cck_ofdm_power_delta = AR5K_EEPROM_CCK_OFDM_DELTA;
1788 } else {
1789 ee->ee_i_gain[mode] = (val >> 13) & 0x7;
1790
1791 AR5K_EEPROM_READ(o++, val);
1792 ee->ee_i_gain[mode] |= (val << 3) & 0x38;
1793
1794 if (mode == AR5K_EEPROM_MODE_11G)
1795 ee->ee_cck_ofdm_power_delta = (val >> 3) & 0xff;
1796 }
1797
1798 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0 &&
1799 mode == AR5K_EEPROM_MODE_11A) {
1800 ee->ee_i_cal[mode] = (val >> 8) & 0x3f;
1801 ee->ee_q_cal[mode] = (val >> 3) & 0x1f;
1802 }
1803
1804 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_6 &&
1805 mode == AR5K_EEPROM_MODE_11G)
1806 ee->ee_scaled_cck_delta = (val >> 11) & 0x1f;
1807
1808 /* return new offset */
1809 *offset = o;
1810
1811 return 0;
1812 }
1813
1814 /*
1815 * Initialize eeprom & capabilities structs
1816 */
1817 static int ath5k_eeprom_init(struct ath5k_hw *ah)
1818 {
1819 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1820 unsigned int mode, i;
1821 int ret;
1822 u32 offset;
1823 u16 val;
1824
1825 /* Initial TX thermal adjustment values */
1826 ee->ee_tx_clip = 4;
1827 ee->ee_pwd_84 = ee->ee_pwd_90 = 1;
1828 ee->ee_gain_select = 1;
1829
1830 /*
1831 * Read values from EEPROM and store them in the capability structure
1832 */
1833 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MAGIC, ee_magic);
1834 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_PROTECT, ee_protect);
1835 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_REG_DOMAIN, ee_regdomain);
1836 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_VERSION, ee_version);
1837 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_HDR, ee_header);
1838
1839 /* Return if we have an old EEPROM */
1840 if (ah->ah_ee_version < AR5K_EEPROM_VERSION_3_0)
1841 return 0;
1842
1843 #ifdef notyet
1844 /*
1845 * Validate the checksum of the EEPROM date. There are some
1846 * devices with invalid EEPROMs.
1847 */
1848 for (cksum = 0, offset = 0; offset < AR5K_EEPROM_INFO_MAX; offset++) {
1849 AR5K_EEPROM_READ(AR5K_EEPROM_INFO(offset), val);
1850 cksum ^= val;
1851 }
1852 if (cksum != AR5K_EEPROM_INFO_CKSUM) {
1853 ATH5K_ERR(ah->ah_sc, "Invalid EEPROM checksum 0x%04x\n", cksum);
1854 return -EIO;
1855 }
1856 #endif
1857
1858 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_ANT_GAIN(ah->ah_ee_version),
1859 ee_ant_gain);
1860
1861 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) {
1862 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC0, ee_misc0);
1863 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC1, ee_misc1);
1864 }
1865
1866 if (ah->ah_ee_version < AR5K_EEPROM_VERSION_3_3) {
1867 AR5K_EEPROM_READ(AR5K_EEPROM_OBDB0_2GHZ, val);
1868 ee->ee_ob[AR5K_EEPROM_MODE_11B][0] = val & 0x7;
1869 ee->ee_db[AR5K_EEPROM_MODE_11B][0] = (val >> 3) & 0x7;
1870
1871 AR5K_EEPROM_READ(AR5K_EEPROM_OBDB1_2GHZ, val);
1872 ee->ee_ob[AR5K_EEPROM_MODE_11G][0] = val & 0x7;
1873 ee->ee_db[AR5K_EEPROM_MODE_11G][0] = (val >> 3) & 0x7;
1874 }
1875
1876 /*
1877 * Get conformance test limit values
1878 */
1879 offset = AR5K_EEPROM_CTL(ah->ah_ee_version);
1880 ee->ee_ctls = AR5K_EEPROM_N_CTLS(ah->ah_ee_version);
1881
1882 for (i = 0; i < ee->ee_ctls; i++) {
1883 AR5K_EEPROM_READ(offset++, val);
1884 ee->ee_ctl[i] = (val >> 8) & 0xff;
1885 ee->ee_ctl[i + 1] = val & 0xff;
1886 }
1887
1888 /*
1889 * Get values for 802.11a (5GHz)
1890 */
1891 mode = AR5K_EEPROM_MODE_11A;
1892
1893 ee->ee_turbo_max_power[mode] =
1894 AR5K_EEPROM_HDR_T_5GHZ_DBM(ee->ee_header);
1895
1896 offset = AR5K_EEPROM_MODES_11A(ah->ah_ee_version);
1897
1898 ret = ath5k_eeprom_read_ants(ah, &offset, mode);
1899 if (ret)
1900 return ret;
1901
1902 AR5K_EEPROM_READ(offset++, val);
1903 ee->ee_adc_desired_size[mode] = (s8)((val >> 8) & 0xff);
1904 ee->ee_ob[mode][3] = (val >> 5) & 0x7;
1905 ee->ee_db[mode][3] = (val >> 2) & 0x7;
1906 ee->ee_ob[mode][2] = (val << 1) & 0x7;
1907
1908 AR5K_EEPROM_READ(offset++, val);
1909 ee->ee_ob[mode][2] |= (val >> 15) & 0x1;
1910 ee->ee_db[mode][2] = (val >> 12) & 0x7;
1911 ee->ee_ob[mode][1] = (val >> 9) & 0x7;
1912 ee->ee_db[mode][1] = (val >> 6) & 0x7;
1913 ee->ee_ob[mode][0] = (val >> 3) & 0x7;
1914 ee->ee_db[mode][0] = val & 0x7;
1915
1916 ret = ath5k_eeprom_read_modes(ah, &offset, mode);
1917 if (ret)
1918 return ret;
1919
1920 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) {
1921 AR5K_EEPROM_READ(offset++, val);
1922 ee->ee_margin_tx_rx[mode] = val & 0x3f;
1923 }
1924
1925 /*
1926 * Get values for 802.11b (2.4GHz)
1927 */
1928 mode = AR5K_EEPROM_MODE_11B;
1929 offset = AR5K_EEPROM_MODES_11B(ah->ah_ee_version);
1930
1931 ret = ath5k_eeprom_read_ants(ah, &offset, mode);
1932 if (ret)
1933 return ret;
1934
1935 AR5K_EEPROM_READ(offset++, val);
1936 ee->ee_adc_desired_size[mode] = (s8)((val >> 8) & 0xff);
1937 ee->ee_ob[mode][1] = (val >> 4) & 0x7;
1938 ee->ee_db[mode][1] = val & 0x7;
1939
1940 ret = ath5k_eeprom_read_modes(ah, &offset, mode);
1941 if (ret)
1942 return ret;
1943
1944 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) {
1945 AR5K_EEPROM_READ(offset++, val);
1946 ee->ee_cal_pier[mode][0] =
1947 ath5k_eeprom_bin2freq(ah, val & 0xff, mode);
1948 ee->ee_cal_pier[mode][1] =
1949 ath5k_eeprom_bin2freq(ah, (val >> 8) & 0xff, mode);
1950
1951 AR5K_EEPROM_READ(offset++, val);
1952 ee->ee_cal_pier[mode][2] =
1953 ath5k_eeprom_bin2freq(ah, val & 0xff, mode);
1954 }
1955
1956 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1)
1957 ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f;
1958
1959 /*
1960 * Get values for 802.11g (2.4GHz)
1961 */
1962 mode = AR5K_EEPROM_MODE_11G;
1963 offset = AR5K_EEPROM_MODES_11G(ah->ah_ee_version);
1964
1965 ret = ath5k_eeprom_read_ants(ah, &offset, mode);
1966 if (ret)
1967 return ret;
1968
1969 AR5K_EEPROM_READ(offset++, val);
1970 ee->ee_adc_desired_size[mode] = (s8)((val >> 8) & 0xff);
1971 ee->ee_ob[mode][1] = (val >> 4) & 0x7;
1972 ee->ee_db[mode][1] = val & 0x7;
1973
1974 ret = ath5k_eeprom_read_modes(ah, &offset, mode);
1975 if (ret)
1976 return ret;
1977
1978 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) {
1979 AR5K_EEPROM_READ(offset++, val);
1980 ee->ee_cal_pier[mode][0] =
1981 ath5k_eeprom_bin2freq(ah, val & 0xff, mode);
1982 ee->ee_cal_pier[mode][1] =
1983 ath5k_eeprom_bin2freq(ah, (val >> 8) & 0xff, mode);
1984
1985 AR5K_EEPROM_READ(offset++, val);
1986 ee->ee_turbo_max_power[mode] = val & 0x7f;
1987 ee->ee_xr_power[mode] = (val >> 7) & 0x3f;
1988
1989 AR5K_EEPROM_READ(offset++, val);
1990 ee->ee_cal_pier[mode][2] =
1991 ath5k_eeprom_bin2freq(ah, val & 0xff, mode);
1992
1993 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1)
1994 ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f;
1995
1996 AR5K_EEPROM_READ(offset++, val);
1997 ee->ee_i_cal[mode] = (val >> 8) & 0x3f;
1998 ee->ee_q_cal[mode] = (val >> 3) & 0x1f;
1999
2000 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_2) {
2001 AR5K_EEPROM_READ(offset++, val);
2002 ee->ee_cck_ofdm_gain_delta = val & 0xff;
2003 }
2004 }
2005
2006 /*
2007 * Read 5GHz EEPROM channels
2008 */
2009
2010 return 0;
2011 }
2012
2013 /*
2014 * Read the MAC address from eeprom
2015 */
2016 static int ath5k_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac)
2017 {
2018 u8 mac_d[ETH_ALEN];
2019 u32 total, offset;
2020 u16 data;
2021 int octet, ret;
2022
2023 memset(mac, 0, ETH_ALEN);
2024 memset(mac_d, 0, ETH_ALEN);
2025
2026 ret = ath5k_hw_eeprom_read(ah, 0x20, &data);
2027 if (ret)
2028 return ret;
2029
2030 for (offset = 0x1f, octet = 0, total = 0; offset >= 0x1d; offset--) {
2031 ret = ath5k_hw_eeprom_read(ah, offset, &data);
2032 if (ret)
2033 return ret;
2034
2035 total += data;
2036 mac_d[octet + 1] = data & 0xff;
2037 mac_d[octet] = data >> 8;
2038 octet += 2;
2039 }
2040
2041 memcpy(mac, mac_d, ETH_ALEN);
2042
2043 if (!total || total == 3 * 0xffff)
2044 return -EINVAL;
2045
2046 return 0;
2047 }
2048
2049 /*
2050 * Read/Write regulatory domain
2051 */
2052 static bool ath5k_eeprom_regulation_domain(struct ath5k_hw *ah, bool write,
2053 enum ath5k_regdom *regdomain)
2054 {
2055 u16 ee_regdomain;
2056
2057 /* Read current value */
2058 if (write != true) {
2059 ee_regdomain = ah->ah_capabilities.cap_eeprom.ee_regdomain;
2060 *regdomain = ath5k_regdom_to_ieee(ee_regdomain);
2061 return true;
2062 }
2063
2064 ee_regdomain = ath5k_regdom_from_ieee(*regdomain);
2065
2066 /* Try to write a new value */
2067 if (ah->ah_capabilities.cap_eeprom.ee_protect &
2068 AR5K_EEPROM_PROTECT_WR_128_191)
2069 return false;
2070 if (ath5k_hw_eeprom_write(ah, AR5K_EEPROM_REG_DOMAIN, ee_regdomain)!=0)
2071 return false;
2072
2073 ah->ah_capabilities.cap_eeprom.ee_regdomain = ee_regdomain;
2074
2075 return true;
2076 }
2077
2078 /*
2079 * Use the above to write a new regulatory domain
2080 */
2081 int ath5k_hw_set_regdomain(struct ath5k_hw *ah, u16 regdomain)
2082 {
2083 enum ath5k_regdom ieee_regdomain;
2084
2085 ieee_regdomain = ath5k_regdom_to_ieee(regdomain);
2086
2087 if (ath5k_eeprom_regulation_domain(ah, true, &ieee_regdomain) == true)
2088 return 0;
2089
2090 return -EIO;
2091 }
2092
2093 /*
2094 * Fill the capabilities struct
2095 */
2096 static int ath5k_hw_get_capabilities(struct ath5k_hw *ah)
2097 {
2098 u16 ee_header;
2099
2100 ATH5K_TRACE(ah->ah_sc);
2101 /* Capabilities stored in the EEPROM */
2102 ee_header = ah->ah_capabilities.cap_eeprom.ee_header;
2103
2104 if (ah->ah_version == AR5K_AR5210) {
2105 /*
2106 * Set radio capabilities
2107 * (The AR5110 only supports the middle 5GHz band)
2108 */
2109 ah->ah_capabilities.cap_range.range_5ghz_min = 5120;
2110 ah->ah_capabilities.cap_range.range_5ghz_max = 5430;
2111 ah->ah_capabilities.cap_range.range_2ghz_min = 0;
2112 ah->ah_capabilities.cap_range.range_2ghz_max = 0;
2113
2114 /* Set supported modes */
2115 __set_bit(MODE_IEEE80211A, ah->ah_capabilities.cap_mode);
2116 __set_bit(MODE_ATHEROS_TURBO, ah->ah_capabilities.cap_mode);
2117 } else {
2118 /*
2119 * XXX The tranceiver supports frequencies from 4920 to 6100GHz
2120 * XXX and from 2312 to 2732GHz. There are problems with the
2121 * XXX current ieee80211 implementation because the IEEE
2122 * XXX channel mapping does not support negative channel
2123 * XXX numbers (2312MHz is channel -19). Of course, this
2124 * XXX doesn't matter because these channels are out of range
2125 * XXX but some regulation domains like MKK (Japan) will
2126 * XXX support frequencies somewhere around 4.8GHz.
2127 */
2128
2129 /*
2130 * Set radio capabilities
2131 */
2132
2133 if (AR5K_EEPROM_HDR_11A(ee_header)) {
2134 ah->ah_capabilities.cap_range.range_5ghz_min = 5005; /* 4920 */
2135 ah->ah_capabilities.cap_range.range_5ghz_max = 6100;
2136
2137 /* Set supported modes */
2138 __set_bit(MODE_IEEE80211A,
2139 ah->ah_capabilities.cap_mode);
2140 __set_bit(MODE_ATHEROS_TURBO,
2141 ah->ah_capabilities.cap_mode);
2142 if (ah->ah_version == AR5K_AR5212)
2143 __set_bit(MODE_ATHEROS_TURBOG,
2144 ah->ah_capabilities.cap_mode);
2145 }
2146
2147 /* Enable 802.11b if a 2GHz capable radio (2111/5112) is
2148 * connected */
2149 if (AR5K_EEPROM_HDR_11B(ee_header) ||
2150 AR5K_EEPROM_HDR_11G(ee_header)) {
2151 ah->ah_capabilities.cap_range.range_2ghz_min = 2412; /* 2312 */
2152 ah->ah_capabilities.cap_range.range_2ghz_max = 2732;
2153
2154 if (AR5K_EEPROM_HDR_11B(ee_header))
2155 __set_bit(MODE_IEEE80211B,
2156 ah->ah_capabilities.cap_mode);
2157
2158 if (AR5K_EEPROM_HDR_11G(ee_header))
2159 __set_bit(MODE_IEEE80211G,
2160 ah->ah_capabilities.cap_mode);
2161 }
2162 }
2163
2164 /* GPIO */
2165 ah->ah_gpio_npins = AR5K_NUM_GPIO;
2166
2167 /* Set number of supported TX queues */
2168 if (ah->ah_version == AR5K_AR5210)
2169 ah->ah_capabilities.cap_queues.q_tx_num =
2170 AR5K_NUM_TX_QUEUES_NOQCU;
2171 else
2172 ah->ah_capabilities.cap_queues.q_tx_num = AR5K_NUM_TX_QUEUES;
2173
2174 return 0;
2175 }
2176
2177 /*********************************\
2178 Protocol Control Unit Functions
2179 \*********************************/
2180
2181 /*
2182 * Set Operation mode
2183 */
2184 int ath5k_hw_set_opmode(struct ath5k_hw *ah)
2185 {
2186 u32 pcu_reg, beacon_reg, low_id, high_id;
2187
2188 pcu_reg = 0;
2189 beacon_reg = 0;
2190
2191 ATH5K_TRACE(ah->ah_sc);
2192
2193 switch (ah->ah_op_mode) {
2194 case IEEE80211_IF_TYPE_IBSS:
2195 pcu_reg |= AR5K_STA_ID1_ADHOC | AR5K_STA_ID1_DESC_ANTENNA |
2196 (ah->ah_version == AR5K_AR5210 ?
2197 AR5K_STA_ID1_NO_PSPOLL : 0);
2198 beacon_reg |= AR5K_BCR_ADHOC;
2199 break;
2200
2201 case IEEE80211_IF_TYPE_AP:
2202 pcu_reg |= AR5K_STA_ID1_AP | AR5K_STA_ID1_RTS_DEF_ANTENNA |
2203 (ah->ah_version == AR5K_AR5210 ?
2204 AR5K_STA_ID1_NO_PSPOLL : 0);
2205 beacon_reg |= AR5K_BCR_AP;
2206 break;
2207
2208 case IEEE80211_IF_TYPE_STA:
2209 pcu_reg |= AR5K_STA_ID1_DEFAULT_ANTENNA |
2210 (ah->ah_version == AR5K_AR5210 ?
2211 AR5K_STA_ID1_PWR_SV : 0);
2212 case IEEE80211_IF_TYPE_MNTR:
2213 pcu_reg |= AR5K_STA_ID1_DEFAULT_ANTENNA |
2214 (ah->ah_version == AR5K_AR5210 ?
2215 AR5K_STA_ID1_NO_PSPOLL : 0);
2216 break;
2217
2218 default:
2219 return -EINVAL;
2220 }
2221
2222 /*
2223 * Set PCU registers
2224 */
2225 low_id = AR5K_LOW_ID(ah->ah_sta_id);
2226 high_id = AR5K_HIGH_ID(ah->ah_sta_id);
2227 ath5k_hw_reg_write(ah, low_id, AR5K_STA_ID0);
2228 ath5k_hw_reg_write(ah, pcu_reg | high_id, AR5K_STA_ID1);
2229
2230 /*
2231 * Set Beacon Control Register on 5210
2232 */
2233 if (ah->ah_version == AR5K_AR5210)
2234 ath5k_hw_reg_write(ah, beacon_reg, AR5K_BCR);
2235
2236 return 0;
2237 }
2238
2239 /*
2240 * BSSID Functions
2241 */
2242
2243 /*
2244 * Get station id
2245 */
2246 void ath5k_hw_get_lladdr(struct ath5k_hw *ah, u8 *mac)
2247 {
2248 ATH5K_TRACE(ah->ah_sc);
2249 memcpy(mac, ah->ah_sta_id, ETH_ALEN);
2250 }
2251
2252 /*
2253 * Set station id
2254 */
2255 int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac)
2256 {
2257 u32 low_id, high_id;
2258
2259 ATH5K_TRACE(ah->ah_sc);
2260 /* Set new station ID */
2261 memcpy(ah->ah_sta_id, mac, ETH_ALEN);
2262
2263 low_id = AR5K_LOW_ID(mac);
2264 high_id = AR5K_HIGH_ID(mac);
2265
2266 ath5k_hw_reg_write(ah, low_id, AR5K_STA_ID0);
2267 ath5k_hw_reg_write(ah, high_id, AR5K_STA_ID1);
2268
2269 return 0;
2270 }
2271
2272 /*
2273 * Set BSSID
2274 */
2275 void ath5k_hw_set_associd(struct ath5k_hw *ah, const u8 *bssid, u16 assoc_id)
2276 {
2277 u32 low_id, high_id;
2278 u16 tim_offset = 0;
2279
2280 /*
2281 * Set simple BSSID mask on 5212
2282 */
2283 if (ah->ah_version == AR5K_AR5212) {
2284 ath5k_hw_reg_write(ah, 0xfffffff, AR5K_BSS_IDM0);
2285 ath5k_hw_reg_write(ah, 0xfffffff, AR5K_BSS_IDM1);
2286 }
2287
2288 /*
2289 * Set BSSID which triggers the "SME Join" operation
2290 */
2291 low_id = AR5K_LOW_ID(bssid);
2292 high_id = AR5K_HIGH_ID(bssid);
2293 ath5k_hw_reg_write(ah, low_id, AR5K_BSS_ID0);
2294 ath5k_hw_reg_write(ah, high_id | ((assoc_id & 0x3fff) <<
2295 AR5K_BSS_ID1_AID_S), AR5K_BSS_ID1);
2296
2297 if (assoc_id == 0) {
2298 ath5k_hw_disable_pspoll(ah);
2299 return;
2300 }
2301
2302 AR5K_REG_WRITE_BITS(ah, AR5K_BEACON, AR5K_BEACON_TIM,
2303 tim_offset ? tim_offset + 4 : 0);
2304
2305 ath5k_hw_enable_pspoll(ah, NULL, 0);
2306 }
2307 /**
2308 * ath5k_hw_set_bssid_mask - set common bits we should listen to
2309 *
2310 * The bssid_mask is a utility used by AR5212 hardware to inform the hardware
2311 * which bits of the interface's MAC address should be looked at when trying
2312 * to decide which packets to ACK. In station mode every bit matters. In AP
2313 * mode with a single BSS every bit matters as well. In AP mode with
2314 * multiple BSSes not every bit matters.
2315 *
2316 * @ah: the &struct ath5k_hw
2317 * @mask: the bssid_mask, a u8 array of size ETH_ALEN
2318 *
2319 * Note that this is a simple filter and *does* not filter out all
2320 * relevant frames. Some non-relevant frames will get through, probability
2321 * jocks are welcomed to compute.
2322 *
2323 * When handling multiple BSSes (or VAPs) you can get the BSSID mask by
2324 * computing the set of:
2325 *
2326 * ~ ( MAC XOR BSSID )
2327 *
2328 * When you do this you are essentially computing the common bits. Later it
2329 * is assumed the harware will "and" (&) the BSSID mask with the MAC address
2330 * to obtain the relevant bits which should match on the destination frame.
2331 *
2332 * Simple example: on your card you have have two BSSes you have created with
2333 * BSSID-01 and BSSID-02. Lets assume BSSID-01 will not use the MAC address.
2334 * There is another BSSID-03 but you are not part of it. For simplicity's sake,
2335 * assuming only 4 bits for a mac address and for BSSIDs you can then have:
2336 *
2337 * \
2338 * MAC: 0001 |
2339 * BSSID-01: 0100 | --> Belongs to us
2340 * BSSID-02: 1001 |
2341 * /
2342 * -------------------
2343 * BSSID-03: 0110 | --> External
2344 * -------------------
2345 *
2346 * Our bssid_mask would then be:
2347 *
2348 * On loop iteration for BSSID-01:
2349 * ~(0001 ^ 0100) -> ~(0101)
2350 * -> 1010
2351 * bssid_mask = 1010
2352 *
2353 * On loop iteration for BSSID-02:
2354 * bssid_mask &= ~(0001 ^ 1001)
2355 * bssid_mask = (1010) & ~(0001 ^ 1001)
2356 * bssid_mask = (1010) & ~(1001)
2357 * bssid_mask = (1010) & (0110)
2358 * bssid_mask = 0010
2359 *
2360 * A bssid_mask of 0010 means "only pay attention to the second least
2361 * significant bit". This is because its the only bit common
2362 * amongst the MAC and all BSSIDs we support. To findout what the real
2363 * common bit is we can simply "&" the bssid_mask now with any BSSID we have
2364 * or our MAC address (we assume the hardware uses the MAC address).
2365 *
2366 * Now, suppose there's an incoming frame for BSSID-03:
2367 *
2368 * IFRAME-01: 0110
2369 *
2370 * An easy eye-inspeciton of this already should tell you that this frame
2371 * will not pass our check. This is beacuse the bssid_mask tells the
2372 * hardware to only look at the second least significant bit and the
2373 * common bit amongst the MAC and BSSIDs is 0, this frame has the 2nd LSB
2374 * as 1, which does not match 0.
2375 *
2376 * So with IFRAME-01 we *assume* the hardware will do:
2377 *
2378 * allow = (IFRAME-01 & bssid_mask) == (bssid_mask & MAC) ? 1 : 0;
2379 * --> allow = (0110 & 0010) == (0010 & 0001) ? 1 : 0;
2380 * --> allow = (0010) == 0000 ? 1 : 0;
2381 * --> allow = 0
2382 *
2383 * Lets now test a frame that should work:
2384 *
2385 * IFRAME-02: 0001 (we should allow)
2386 *
2387 * allow = (0001 & 1010) == 1010
2388 *
2389 * allow = (IFRAME-02 & bssid_mask) == (bssid_mask & MAC) ? 1 : 0;
2390 * --> allow = (0001 & 0010) == (0010 & 0001) ? 1 :0;
2391 * --> allow = (0010) == (0010)
2392 * --> allow = 1
2393 *
2394 * Other examples:
2395 *
2396 * IFRAME-03: 0100 --> allowed
2397 * IFRAME-04: 1001 --> allowed
2398 * IFRAME-05: 1101 --> allowed but its not for us!!!
2399 *
2400 */
2401 int ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask)
2402 {
2403 u32 low_id, high_id;
2404 ATH5K_TRACE(ah->ah_sc);
2405
2406 if (ah->ah_version == AR5K_AR5212) {
2407 low_id = AR5K_LOW_ID(mask);
2408 high_id = AR5K_HIGH_ID(mask);
2409
2410 ath5k_hw_reg_write(ah, low_id, AR5K_BSS_IDM0);
2411 ath5k_hw_reg_write(ah, high_id, AR5K_BSS_IDM1);
2412
2413 return 0;
2414 }
2415
2416 return -EIO;
2417 }
2418
2419 /*
2420 * Receive start/stop functions
2421 */
2422
2423 /*
2424 * Start receive on PCU
2425 */
2426 void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah)
2427 {
2428 ATH5K_TRACE(ah->ah_sc);
2429 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX);
2430 }
2431
2432 /*
2433 * Stop receive on PCU
2434 */
2435 void ath5k_hw_stop_pcu_recv(struct ath5k_hw *ah)
2436 {
2437 ATH5K_TRACE(ah->ah_sc);
2438 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX);
2439 }
2440
2441 /*
2442 * RX Filter functions
2443 */
2444
2445 /*
2446 * Set multicast filter
2447 */
2448 void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1)
2449 {
2450 ATH5K_TRACE(ah->ah_sc);
2451 /* Set the multicat filter */
2452 ath5k_hw_reg_write(ah, filter0, AR5K_MCAST_FILTER0);
2453 ath5k_hw_reg_write(ah, filter1, AR5K_MCAST_FILTER1);
2454 }
2455
2456 /*
2457 * Set multicast filter by index
2458 */
2459 int ath5k_hw_set_mcast_filterindex(struct ath5k_hw *ah, u32 index)
2460 {
2461
2462 ATH5K_TRACE(ah->ah_sc);
2463 if (index >= 64)
2464 return -EINVAL;
2465 else if (index >= 32)
2466 AR5K_REG_ENABLE_BITS(ah, AR5K_MCAST_FILTER1,
2467 (1 << (index - 32)));
2468 else
2469 AR5K_REG_ENABLE_BITS(ah, AR5K_MCAST_FILTER0, (1 << index));
2470
2471 return 0;
2472 }
2473
2474 /*
2475 * Clear Multicast filter by index
2476 */
2477 int ath5k_hw_clear_mcast_filter_idx(struct ath5k_hw *ah, u32 index)
2478 {
2479
2480 ATH5K_TRACE(ah->ah_sc);
2481 if (index >= 64)
2482 return -EINVAL;
2483 else if (index >= 32)
2484 AR5K_REG_DISABLE_BITS(ah, AR5K_MCAST_FILTER1,
2485 (1 << (index - 32)));
2486 else
2487 AR5K_REG_DISABLE_BITS(ah, AR5K_MCAST_FILTER0, (1 << index));
2488
2489 return 0;
2490 }
2491
2492 /*
2493 * Get current rx filter
2494 */
2495 u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah)
2496 {
2497 u32 data, filter = 0;
2498
2499 ATH5K_TRACE(ah->ah_sc);
2500 filter = ath5k_hw_reg_read(ah, AR5K_RX_FILTER);
2501
2502 /*Radar detection for 5212*/
2503 if (ah->ah_version == AR5K_AR5212) {
2504 data = ath5k_hw_reg_read(ah, AR5K_PHY_ERR_FIL);
2505
2506 if (data & AR5K_PHY_ERR_FIL_RADAR)
2507 filter |= AR5K_RX_FILTER_RADARERR;
2508 if (data & (AR5K_PHY_ERR_FIL_OFDM | AR5K_PHY_ERR_FIL_CCK))
2509 filter |= AR5K_RX_FILTER_PHYERR;
2510 }
2511
2512 return filter;
2513 }
2514
2515 /*
2516 * Set rx filter
2517 */
2518 void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter)
2519 {
2520 u32 data = 0;
2521
2522 ATH5K_TRACE(ah->ah_sc);
2523
2524 /* Set PHY error filter register on 5212*/
2525 if (ah->ah_version == AR5K_AR5212) {
2526 if (filter & AR5K_RX_FILTER_RADARERR)
2527 data |= AR5K_PHY_ERR_FIL_RADAR;
2528 if (filter & AR5K_RX_FILTER_PHYERR)
2529 data |= AR5K_PHY_ERR_FIL_OFDM | AR5K_PHY_ERR_FIL_CCK;
2530 }
2531
2532 /*
2533 * The AR5210 uses promiscous mode to detect radar activity
2534 */
2535 if (ah->ah_version == AR5K_AR5210 &&
2536 (filter & AR5K_RX_FILTER_RADARERR)) {
2537 filter &= ~AR5K_RX_FILTER_RADARERR;
2538 filter |= AR5K_RX_FILTER_PROM;
2539 }
2540
2541 /*Zero length DMA*/
2542 if (data)
2543 AR5K_REG_ENABLE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA);
2544 else
2545 AR5K_REG_DISABLE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA);
2546
2547 /*Write RX Filter register*/
2548 ath5k_hw_reg_write(ah, filter & 0xff, AR5K_RX_FILTER);
2549
2550 /*Write PHY error filter register on 5212*/
2551 if (ah->ah_version == AR5K_AR5212)
2552 ath5k_hw_reg_write(ah, data, AR5K_PHY_ERR_FIL);
2553
2554 }
2555
2556 /*
2557 * Beacon related functions
2558 */
2559
2560 /*
2561 * Get a 32bit TSF
2562 */
2563 u32 ath5k_hw_get_tsf32(struct ath5k_hw *ah)
2564 {
2565 ATH5K_TRACE(ah->ah_sc);
2566 return ath5k_hw_reg_read(ah, AR5K_TSF_L32);
2567 }
2568
2569 /*
2570 * Get the full 64bit TSF
2571 */
2572 u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah)
2573 {
2574 u64 tsf = ath5k_hw_reg_read(ah, AR5K_TSF_U32);
2575 ATH5K_TRACE(ah->ah_sc);
2576
2577 return ath5k_hw_reg_read(ah, AR5K_TSF_L32) | (tsf << 32);
2578 }
2579
2580 /*
2581 * Force a TSF reset
2582 */
2583 void ath5k_hw_reset_tsf(struct ath5k_hw *ah)
2584 {
2585 ATH5K_TRACE(ah->ah_sc);
2586 AR5K_REG_ENABLE_BITS(ah, AR5K_BEACON, AR5K_BEACON_RESET_TSF);
2587 }
2588
2589 /*
2590 * Initialize beacon timers
2591 */
2592 void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval)
2593 {
2594 u32 timer1, timer2, timer3;
2595
2596 ATH5K_TRACE(ah->ah_sc);
2597 /*
2598 * Set the additional timers by mode
2599 */
2600 switch (ah->ah_op_mode) {
2601 case IEEE80211_IF_TYPE_STA:
2602 if (ah->ah_version == AR5K_AR5210) {
2603 timer1 = 0xffffffff;
2604 timer2 = 0xffffffff;
2605 } else {
2606 timer1 = 0x0000ffff;
2607 timer2 = 0x0007ffff;
2608 }
2609 break;
2610
2611 default:
2612 timer1 = (next_beacon - AR5K_TUNE_DMA_BEACON_RESP) << 3;
2613 timer2 = (next_beacon - AR5K_TUNE_SW_BEACON_RESP) << 3;
2614 }
2615
2616 timer3 = next_beacon + (ah->ah_atim_window ? ah->ah_atim_window : 1);
2617
2618 /*
2619 * Set the beacon register and enable all timers.
2620 * (next beacon, DMA beacon, software beacon, ATIM window time)
2621 */
2622 ath5k_hw_reg_write(ah, next_beacon, AR5K_TIMER0);
2623 ath5k_hw_reg_write(ah, timer1, AR5K_TIMER1);
2624 ath5k_hw_reg_write(ah, timer2, AR5K_TIMER2);
2625 ath5k_hw_reg_write(ah, timer3, AR5K_TIMER3);
2626
2627 ath5k_hw_reg_write(ah, interval & (AR5K_BEACON_PERIOD |
2628 AR5K_BEACON_RESET_TSF | AR5K_BEACON_ENABLE),
2629 AR5K_BEACON);
2630 }
2631
2632 #if 0
2633 /*
2634 * Set beacon timers
2635 */
2636 int ath5k_hw_set_beacon_timers(struct ath5k_hw *ah,
2637 const struct ath5k_beacon_state *state)
2638 {
2639 u32 cfp_period, next_cfp, dtim, interval, next_beacon;
2640
2641 /*
2642 * TODO: should be changed through *state
2643 * review struct ath5k_beacon_state struct
2644 *
2645 * XXX: These are used for cfp period bellow, are they
2646 * ok ? Is it O.K. for tsf here to be 0 or should we use
2647 * get_tsf ?
2648 */
2649 u32 dtim_count = 0; /* XXX */
2650 u32 cfp_count = 0; /* XXX */
2651 u32 tsf = 0; /* XXX */
2652
2653 ATH5K_TRACE(ah->ah_sc);
2654 /* Return on an invalid beacon state */
2655 if (state->bs_interval < 1)
2656 return -EINVAL;
2657
2658 interval = state->bs_interval;
2659 dtim = state->bs_dtim_period;
2660
2661 /*
2662 * PCF support?
2663 */
2664 if (state->bs_cfp_period > 0) {
2665 /*
2666 * Enable PCF mode and set the CFP
2667 * (Contention Free Period) and timer registers
2668 */
2669 cfp_period = state->bs_cfp_period * state->bs_dtim_period *
2670 state->bs_interval;
2671 next_cfp = (cfp_count * state->bs_dtim_period + dtim_count) *
2672 state->bs_interval;
2673
2674 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1,
2675 AR5K_STA_ID1_DEFAULT_ANTENNA |
2676 AR5K_STA_ID1_PCF);
2677 ath5k_hw_reg_write(ah, cfp_period, AR5K_CFP_PERIOD);
2678 ath5k_hw_reg_write(ah, state->bs_cfp_max_duration,
2679 AR5K_CFP_DUR);
2680 ath5k_hw_reg_write(ah, (tsf + (next_cfp == 0 ? cfp_period :
2681 next_cfp)) << 3, AR5K_TIMER2);
2682 } else {
2683 /* Disable PCF mode */
2684 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1,
2685 AR5K_STA_ID1_DEFAULT_ANTENNA |
2686 AR5K_STA_ID1_PCF);
2687 }
2688
2689 /*
2690 * Enable the beacon timer register
2691 */
2692 ath5k_hw_reg_write(ah, state->bs_next_beacon, AR5K_TIMER0);
2693
2694 /*
2695 * Start the beacon timers
2696 */
2697 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, AR5K_BEACON) &~
2698 (AR5K_BEACON_PERIOD | AR5K_BEACON_TIM)) |
2699 AR5K_REG_SM(state->bs_tim_offset ? state->bs_tim_offset + 4 : 0,
2700 AR5K_BEACON_TIM) | AR5K_REG_SM(state->bs_interval,
2701 AR5K_BEACON_PERIOD), AR5K_BEACON);
2702
2703 /*
2704 * Write new beacon miss threshold, if it appears to be valid
2705 * XXX: Figure out right values for min <= bs_bmiss_threshold <= max
2706 * and return if its not in range. We can test this by reading value and
2707 * setting value to a largest value and seeing which values register.
2708 */
2709
2710 AR5K_REG_WRITE_BITS(ah, AR5K_RSSI_THR, AR5K_RSSI_THR_BMISS,
2711 state->bs_bmiss_threshold);
2712
2713 /*
2714 * Set sleep control register
2715 * XXX: Didn't find this in 5210 code but since this register
2716 * exists also in ar5k's 5210 headers i leave it as common code.
2717 */
2718 AR5K_REG_WRITE_BITS(ah, AR5K_SLEEP_CTL, AR5K_SLEEP_CTL_SLDUR,
2719 (state->bs_sleep_duration - 3) << 3);
2720
2721 /*
2722 * Set enhanced sleep registers on 5212
2723 */
2724 if (ah->ah_version == AR5K_AR5212) {
2725 if (state->bs_sleep_duration > state->bs_interval &&
2726 roundup(state->bs_sleep_duration, interval) ==
2727 state->bs_sleep_duration)
2728 interval = state->bs_sleep_duration;
2729
2730 if (state->bs_sleep_duration > dtim && (dtim == 0 ||
2731 roundup(state->bs_sleep_duration, dtim) ==
2732 state->bs_sleep_duration))
2733 dtim = state->bs_sleep_duration;
2734
2735 if (interval > dtim)
2736 return -EINVAL;
2737
2738 next_beacon = interval == dtim ? state->bs_next_dtim :
2739 state->bs_next_beacon;
2740
2741 ath5k_hw_reg_write(ah,
2742 AR5K_REG_SM((state->bs_next_dtim - 3) << 3,
2743 AR5K_SLEEP0_NEXT_DTIM) |
2744 AR5K_REG_SM(10, AR5K_SLEEP0_CABTO) |
2745 AR5K_SLEEP0_ENH_SLEEP_EN |
2746 AR5K_SLEEP0_ASSUME_DTIM, AR5K_SLEEP0);
2747
2748 ath5k_hw_reg_write(ah, AR5K_REG_SM((next_beacon - 3) << 3,
2749 AR5K_SLEEP1_NEXT_TIM) |
2750 AR5K_REG_SM(10, AR5K_SLEEP1_BEACON_TO), AR5K_SLEEP1);
2751
2752 ath5k_hw_reg_write(ah,
2753 AR5K_REG_SM(interval, AR5K_SLEEP2_TIM_PER) |
2754 AR5K_REG_SM(dtim, AR5K_SLEEP2_DTIM_PER), AR5K_SLEEP2);
2755 }
2756
2757 return 0;
2758 }
2759
2760 /*
2761 * Reset beacon timers
2762 */
2763 void ath5k_hw_reset_beacon(struct ath5k_hw *ah)
2764 {
2765 ATH5K_TRACE(ah->ah_sc);
2766 /*
2767 * Disable beacon timer
2768 */
2769 ath5k_hw_reg_write(ah, 0, AR5K_TIMER0);
2770
2771 /*
2772 * Disable some beacon register values
2773 */
2774 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1,
2775 AR5K_STA_ID1_DEFAULT_ANTENNA | AR5K_STA_ID1_PCF);
2776 ath5k_hw_reg_write(ah, AR5K_BEACON_PERIOD, AR5K_BEACON);
2777 }
2778
2779 /*
2780 * Wait for beacon queue to finish
2781 */
2782 int ath5k_hw_beaconq_finish(struct ath5k_hw *ah, unsigned long phys_addr)
2783 {
2784 unsigned int i;
2785 int ret;
2786
2787 ATH5K_TRACE(ah->ah_sc);
2788
2789 /* 5210 doesn't have QCU*/
2790 if (ah->ah_version == AR5K_AR5210) {
2791 /*
2792 * Wait for beaconn queue to finish by checking
2793 * Control Register and Beacon Status Register.
2794 */
2795 for (i = AR5K_TUNE_BEACON_INTERVAL / 2; i > 0; i--) {
2796 if (!(ath5k_hw_reg_read(ah, AR5K_BSR) & AR5K_BSR_TXQ1F)
2797 ||
2798 !(ath5k_hw_reg_read(ah, AR5K_CR) & AR5K_BSR_TXQ1F))
2799 break;
2800 udelay(10);
2801 }
2802
2803 /* Timeout... */
2804 if (i <= 0) {
2805 /*
2806 * Re-schedule the beacon queue
2807 */
2808 ath5k_hw_reg_write(ah, phys_addr, AR5K_NOQCU_TXDP1);
2809 ath5k_hw_reg_write(ah, AR5K_BCR_TQ1V | AR5K_BCR_BDMAE,
2810 AR5K_BCR);
2811
2812 return -EIO;
2813 }
2814 ret = 0;
2815 } else {
2816 /*5211/5212*/
2817 ret = ath5k_hw_register_timeout(ah,
2818 AR5K_QUEUE_STATUS(AR5K_TX_QUEUE_ID_BEACON),
2819 AR5K_QCU_STS_FRMPENDCNT, 0, false);
2820
2821 if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXE, AR5K_TX_QUEUE_ID_BEACON))
2822 return -EIO;
2823 }
2824
2825 return ret;
2826 }
2827 #endif
2828
2829 /*
2830 * Update mib counters (statistics)
2831 */
2832 void ath5k_hw_update_mib_counters(struct ath5k_hw *ah,
2833 struct ath5k_mib_stats *statistics)
2834 {
2835 ATH5K_TRACE(ah->ah_sc);
2836 /* Read-And-Clear */
2837 statistics->ackrcv_bad += ath5k_hw_reg_read(ah, AR5K_ACK_FAIL);
2838 statistics->rts_bad += ath5k_hw_reg_read(ah, AR5K_RTS_FAIL);
2839 statistics->rts_good += ath5k_hw_reg_read(ah, AR5K_RTS_OK);
2840 statistics->fcs_bad += ath5k_hw_reg_read(ah, AR5K_FCS_FAIL);
2841 statistics->beacons += ath5k_hw_reg_read(ah, AR5K_BEACON_CNT);
2842
2843 /* Reset profile count registers on 5212*/
2844 if (ah->ah_version == AR5K_AR5212) {
2845 ath5k_hw_reg_write(ah, 0, AR5K_PROFCNT_TX);
2846 ath5k_hw_reg_write(ah, 0, AR5K_PROFCNT_RX);
2847 ath5k_hw_reg_write(ah, 0, AR5K_PROFCNT_RXCLR);
2848 ath5k_hw_reg_write(ah, 0, AR5K_PROFCNT_CYCLE);
2849 }
2850 }
2851
2852 /** ath5k_hw_set_ack_bitrate - set bitrate for ACKs
2853 *
2854 * @ah: the &struct ath5k_hw
2855 * @high: determines if to use low bit rate or now
2856 */
2857 void ath5k_hw_set_ack_bitrate_high(struct ath5k_hw *ah, bool high)
2858 {
2859 if (ah->ah_version != AR5K_AR5212)
2860 return;
2861 else {
2862 u32 val = AR5K_STA_ID1_BASE_RATE_11B | AR5K_STA_ID1_ACKCTS_6MB;
2863 if (high)
2864 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, val);
2865 else
2866 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, val);
2867 }
2868 }
2869
2870
2871 /*
2872 * ACK/CTS Timeouts
2873 */
2874
2875 /*
2876 * Set ACK timeout on PCU
2877 */
2878 int ath5k_hw_set_ack_timeout(struct ath5k_hw *ah, unsigned int timeout)
2879 {
2880 ATH5K_TRACE(ah->ah_sc);
2881 if (ath5k_hw_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_ACK),
2882 ah->ah_turbo) <= timeout)
2883 return -EINVAL;
2884
2885 AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_ACK,
2886 ath5k_hw_htoclock(timeout, ah->ah_turbo));
2887
2888 return 0;
2889 }
2890
2891 /*
2892 * Read the ACK timeout from PCU
2893 */
2894 unsigned int ath5k_hw_get_ack_timeout(struct ath5k_hw *ah)
2895 {
2896 ATH5K_TRACE(ah->ah_sc);
2897
2898 return ath5k_hw_clocktoh(AR5K_REG_MS(ath5k_hw_reg_read(ah,
2899 AR5K_TIME_OUT), AR5K_TIME_OUT_ACK), ah->ah_turbo);
2900 }
2901
2902 /*
2903 * Set CTS timeout on PCU
2904 */
2905 int ath5k_hw_set_cts_timeout(struct ath5k_hw *ah, unsigned int timeout)
2906 {
2907 ATH5K_TRACE(ah->ah_sc);
2908 if (ath5k_hw_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_CTS),
2909 ah->ah_turbo) <= timeout)
2910 return -EINVAL;
2911
2912 AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_CTS,
2913 ath5k_hw_htoclock(timeout, ah->ah_turbo));
2914
2915 return 0;
2916 }
2917
2918 /*
2919 * Read CTS timeout from PCU
2920 */
2921 unsigned int ath5k_hw_get_cts_timeout(struct ath5k_hw *ah)
2922 {
2923 ATH5K_TRACE(ah->ah_sc);
2924 return ath5k_hw_clocktoh(AR5K_REG_MS(ath5k_hw_reg_read(ah,
2925 AR5K_TIME_OUT), AR5K_TIME_OUT_CTS), ah->ah_turbo);
2926 }
2927
2928 /*
2929 * Key table (WEP) functions
2930 */
2931
2932 int ath5k_hw_reset_key(struct ath5k_hw *ah, u16 entry)
2933 {
2934 unsigned int i;
2935
2936 ATH5K_TRACE(ah->ah_sc);
2937 AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE);
2938
2939 for (i = 0; i < AR5K_KEYCACHE_SIZE; i++)
2940 ath5k_hw_reg_write(ah, 0, AR5K_KEYTABLE_OFF(entry, i));
2941
2942 /* Set NULL encryption on non-5210*/
2943 if (ah->ah_version != AR5K_AR5210)
2944 ath5k_hw_reg_write(ah, AR5K_KEYTABLE_TYPE_NULL,
2945 AR5K_KEYTABLE_TYPE(entry));
2946
2947 return 0;
2948 }
2949
2950 int ath5k_hw_is_key_valid(struct ath5k_hw *ah, u16 entry)
2951 {
2952 ATH5K_TRACE(ah->ah_sc);
2953 AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE);
2954
2955 /* Check the validation flag at the end of the entry */
2956 return ath5k_hw_reg_read(ah, AR5K_KEYTABLE_MAC1(entry)) &
2957 AR5K_KEYTABLE_VALID;
2958 }
2959
2960 int ath5k_hw_set_key(struct ath5k_hw *ah, u16 entry,
2961 const struct ieee80211_key_conf *key, const u8 *mac)
2962 {
2963 unsigned int i;
2964 __le32 key_v[5] = {};
2965 u32 keytype;
2966
2967 ATH5K_TRACE(ah->ah_sc);
2968
2969 /* key->keylen comes in from mac80211 in bytes */
2970
2971 if (key->keylen > AR5K_KEYTABLE_SIZE / 8)
2972 return -EOPNOTSUPP;
2973
2974 switch (key->keylen) {
2975 /* WEP 40-bit = 40-bit entered key + 24 bit IV = 64-bit */
2976 case 40 / 8:
2977 memcpy(&key_v[0], key->key, 5);
2978 keytype = AR5K_KEYTABLE_TYPE_40;
2979 break;
2980
2981 /* WEP 104-bit = 104-bit entered key + 24-bit IV = 128-bit */
2982 case 104 / 8:
2983 memcpy(&key_v[0], &key->key[0], 6);
2984 memcpy(&key_v[2], &key->key[6], 6);
2985 memcpy(&key_v[4], &key->key[12], 1);
2986 keytype = AR5K_KEYTABLE_TYPE_104;
2987 break;
2988 /* WEP 128-bit = 128-bit entered key + 24 bit IV = 152-bit */
2989 case 128 / 8:
2990 memcpy(&key_v[0], &key->key[0], 6);
2991 memcpy(&key_v[2], &key->key[6], 6);
2992 memcpy(&key_v[4], &key->key[12], 4);
2993 keytype = AR5K_KEYTABLE_TYPE_128;
2994 break;
2995
2996 default:
2997 return -EINVAL; /* shouldn't happen */
2998 }
2999
3000 for (i = 0; i < ARRAY_SIZE(key_v); i++)
3001 ath5k_hw_reg_write(ah, le32_to_cpu(key_v[i]),
3002 AR5K_KEYTABLE_OFF(entry, i));
3003
3004 ath5k_hw_reg_write(ah, keytype, AR5K_KEYTABLE_TYPE(entry));
3005
3006 return ath5k_hw_set_key_lladdr(ah, entry, mac);
3007 }
3008
3009 int ath5k_hw_set_key_lladdr(struct ath5k_hw *ah, u16 entry, const u8 *mac)
3010 {
3011 u32 low_id, high_id;
3012
3013 ATH5K_TRACE(ah->ah_sc);
3014 /* Invalid entry (key table overflow) */
3015 AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE);
3016
3017 /* MAC may be NULL if it's a broadcast key. In this case no need to
3018 * to compute AR5K_LOW_ID and AR5K_HIGH_ID as we already know it. */
3019 if (unlikely(mac == NULL)) {
3020 low_id = 0xffffffff;
3021 high_id = 0xffff | AR5K_KEYTABLE_VALID;
3022 } else {
3023 low_id = AR5K_LOW_ID(mac);
3024 high_id = AR5K_HIGH_ID(mac) | AR5K_KEYTABLE_VALID;
3025 }
3026
3027 ath5k_hw_reg_write(ah, low_id, AR5K_KEYTABLE_MAC0(entry));
3028 ath5k_hw_reg_write(ah, high_id, AR5K_KEYTABLE_MAC1(entry));
3029
3030 return 0;
3031 }
3032
3033
3034 /********************************************\
3035 Queue Control Unit, DFS Control Unit Functions
3036 \********************************************/
3037
3038 /*
3039 * Initialize a transmit queue
3040 */
3041 int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah, enum ath5k_tx_queue queue_type,
3042 struct ath5k_txq_info *queue_info)
3043 {
3044 unsigned int queue;
3045 int ret;
3046
3047 ATH5K_TRACE(ah->ah_sc);
3048
3049 /*
3050 * Get queue by type
3051 */
3052 /*5210 only has 2 queues*/
3053 if (ah->ah_version == AR5K_AR5210) {
3054 switch (queue_type) {
3055 case AR5K_TX_QUEUE_DATA:
3056 queue = AR5K_TX_QUEUE_ID_NOQCU_DATA;
3057 break;
3058 case AR5K_TX_QUEUE_BEACON:
3059 case AR5K_TX_QUEUE_CAB:
3060 queue = AR5K_TX_QUEUE_ID_NOQCU_BEACON;
3061 break;
3062 default:
3063 return -EINVAL;
3064 }
3065 } else {
3066 switch (queue_type) {
3067 case AR5K_TX_QUEUE_DATA:
3068 for (queue = AR5K_TX_QUEUE_ID_DATA_MIN;
3069 ah->ah_txq[queue].tqi_type !=
3070 AR5K_TX_QUEUE_INACTIVE; queue++) {
3071
3072 if (queue > AR5K_TX_QUEUE_ID_DATA_MAX)
3073 return -EINVAL;
3074 }
3075 break;
3076 case AR5K_TX_QUEUE_UAPSD:
3077 queue = AR5K_TX_QUEUE_ID_UAPSD;
3078 break;
3079 case AR5K_TX_QUEUE_BEACON:
3080 queue = AR5K_TX_QUEUE_ID_BEACON;
3081 break;
3082 case AR5K_TX_QUEUE_CAB:
3083 queue = AR5K_TX_QUEUE_ID_CAB;
3084 break;
3085 case AR5K_TX_QUEUE_XR_DATA:
3086 if (ah->ah_version != AR5K_AR5212)
3087 ATH5K_ERR(ah->ah_sc,
3088 "XR data queues only supported in"
3089 " 5212!\n");
3090 queue = AR5K_TX_QUEUE_ID_XR_DATA;
3091 break;
3092 default:
3093 return -EINVAL;
3094 }
3095 }
3096
3097 /*
3098 * Setup internal queue structure
3099 */
3100 memset(&ah->ah_txq[queue], 0, sizeof(struct ath5k_txq_info));
3101 ah->ah_txq[queue].tqi_type = queue_type;
3102
3103 if (queue_info != NULL) {
3104 queue_info->tqi_type = queue_type;
3105 ret = ath5k_hw_setup_tx_queueprops(ah, queue, queue_info);
3106 if (ret)
3107 return ret;
3108 }
3109 /*
3110 * We use ah_txq_status to hold a temp value for
3111 * the Secondary interrupt mask registers on 5211+
3112 * check out ath5k_hw_reset_tx_queue
3113 */
3114 AR5K_Q_ENABLE_BITS(ah->ah_txq_status, queue);
3115
3116 return queue;
3117 }
3118
3119 /*
3120 * Setup a transmit queue
3121 */
3122 int ath5k_hw_setup_tx_queueprops(struct ath5k_hw *ah, int queue,
3123 const struct ath5k_txq_info *queue_info)
3124 {
3125 ATH5K_TRACE(ah->ah_sc);
3126 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
3127
3128 if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)
3129 return -EIO;
3130
3131 memcpy(&ah->ah_txq[queue], queue_info, sizeof(struct ath5k_txq_info));
3132
3133 /*XXX: Is this supported on 5210 ?*/
3134 if ((queue_info->tqi_type == AR5K_TX_QUEUE_DATA &&
3135 ((queue_info->tqi_subtype == AR5K_WME_AC_VI) ||
3136 (queue_info->tqi_subtype == AR5K_WME_AC_VO))) ||
3137 queue_info->tqi_type == AR5K_TX_QUEUE_UAPSD)
3138 ah->ah_txq[queue].tqi_flags |= AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS;
3139
3140 return 0;
3141 }
3142
3143 /*
3144 * Get properties for a specific transmit queue
3145 */
3146 int ath5k_hw_get_tx_queueprops(struct ath5k_hw *ah, int queue,
3147 struct ath5k_txq_info *queue_info)
3148 {
3149 ATH5K_TRACE(ah->ah_sc);
3150 memcpy(queue_info, &ah->ah_txq[queue], sizeof(struct ath5k_txq_info));
3151 return 0;
3152 }
3153
3154 /*
3155 * Set a transmit queue inactive
3156 */
3157 void ath5k_hw_release_tx_queue(struct ath5k_hw *ah, unsigned int queue)
3158 {
3159 ATH5K_TRACE(ah->ah_sc);
3160 if (WARN_ON(queue >= ah->ah_capabilities.cap_queues.q_tx_num))
3161 return;
3162
3163 /* This queue will be skipped in further operations */
3164 ah->ah_txq[queue].tqi_type = AR5K_TX_QUEUE_INACTIVE;
3165 /*For SIMR setup*/
3166 AR5K_Q_DISABLE_BITS(ah->ah_txq_status, queue);
3167 }
3168
3169 /*
3170 * Set DFS params for a transmit queue
3171 */
3172 int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue)
3173 {
3174 u32 cw_min, cw_max, retry_lg, retry_sh;
3175 struct ath5k_txq_info *tq = &ah->ah_txq[queue];
3176
3177 ATH5K_TRACE(ah->ah_sc);
3178 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
3179
3180 tq = &ah->ah_txq[queue];
3181
3182 if (tq->tqi_type == AR5K_TX_QUEUE_INACTIVE)
3183 return 0;
3184
3185 if (ah->ah_version == AR5K_AR5210) {
3186 /* Only handle data queues, others will be ignored */
3187 if (tq->tqi_type != AR5K_TX_QUEUE_DATA)
3188 return 0;
3189
3190 /* Set Slot time */
3191 ath5k_hw_reg_write(ah, ah->ah_turbo == true ?
3192 AR5K_INIT_SLOT_TIME_TURBO : AR5K_INIT_SLOT_TIME,
3193 AR5K_SLOT_TIME);
3194 /* Set ACK_CTS timeout */
3195 ath5k_hw_reg_write(ah, ah->ah_turbo == true ?
3196 AR5K_INIT_ACK_CTS_TIMEOUT_TURBO :
3197 AR5K_INIT_ACK_CTS_TIMEOUT, AR5K_SLOT_TIME);
3198 /* Set Transmit Latency */
3199 ath5k_hw_reg_write(ah, ah->ah_turbo == true ?
3200 AR5K_INIT_TRANSMIT_LATENCY_TURBO :
3201 AR5K_INIT_TRANSMIT_LATENCY, AR5K_USEC_5210);
3202 /* Set IFS0 */
3203 if (ah->ah_turbo == true)
3204 ath5k_hw_reg_write(ah, ((AR5K_INIT_SIFS_TURBO +
3205 (ah->ah_aifs + tq->tqi_aifs) *
3206 AR5K_INIT_SLOT_TIME_TURBO) <<
3207 AR5K_IFS0_DIFS_S) | AR5K_INIT_SIFS_TURBO,
3208 AR5K_IFS0);
3209 else
3210 ath5k_hw_reg_write(ah, ((AR5K_INIT_SIFS +
3211 (ah->ah_aifs + tq->tqi_aifs) *
3212 AR5K_INIT_SLOT_TIME) << AR5K_IFS0_DIFS_S) |
3213 AR5K_INIT_SIFS, AR5K_IFS0);
3214
3215 /* Set IFS1 */
3216 ath5k_hw_reg_write(ah, ah->ah_turbo == true ?
3217 AR5K_INIT_PROTO_TIME_CNTRL_TURBO :
3218 AR5K_INIT_PROTO_TIME_CNTRL, AR5K_IFS1);
3219 /* Set PHY register 0x9844 (??) */
3220 ath5k_hw_reg_write(ah, ah->ah_turbo == true ?
3221 (ath5k_hw_reg_read(ah, AR5K_PHY(17)) & ~0x7F) | 0x38 :
3222 (ath5k_hw_reg_read(ah, AR5K_PHY(17)) & ~0x7F) | 0x1C,
3223 AR5K_PHY(17));
3224 /* Set Frame Control Register */
3225 ath5k_hw_reg_write(ah, ah->ah_turbo == true ?
3226 (AR5K_PHY_FRAME_CTL_INI | AR5K_PHY_TURBO_MODE |
3227 AR5K_PHY_TURBO_SHORT | 0x2020) :
3228 (AR5K_PHY_FRAME_CTL_INI | 0x1020),
3229 AR5K_PHY_FRAME_CTL_5210);
3230 }
3231
3232 /*
3233 * Calculate cwmin/max by channel mode
3234 */
3235 cw_min = ah->ah_cw_min = AR5K_TUNE_CWMIN;
3236 cw_max = ah->ah_cw_max = AR5K_TUNE_CWMAX;
3237 ah->ah_aifs = AR5K_TUNE_AIFS;
3238 /*XR is only supported on 5212*/
3239 if (IS_CHAN_XR(ah->ah_current_channel) &&
3240 ah->ah_version == AR5K_AR5212) {
3241 cw_min = ah->ah_cw_min = AR5K_TUNE_CWMIN_XR;
3242 cw_max = ah->ah_cw_max = AR5K_TUNE_CWMAX_XR;
3243 ah->ah_aifs = AR5K_TUNE_AIFS_XR;
3244 /*B mode is not supported on 5210*/
3245 } else if (IS_CHAN_B(ah->ah_current_channel) &&
3246 ah->ah_version != AR5K_AR5210) {
3247 cw_min = ah->ah_cw_min = AR5K_TUNE_CWMIN_11B;
3248 cw_max = ah->ah_cw_max = AR5K_TUNE_CWMAX_11B;
3249 ah->ah_aifs = AR5K_TUNE_AIFS_11B;
3250 }
3251
3252 cw_min = 1;
3253 while (cw_min < ah->ah_cw_min)
3254 cw_min = (cw_min << 1) | 1;
3255
3256 cw_min = tq->tqi_cw_min < 0 ? (cw_min >> (-tq->tqi_cw_min)) :
3257 ((cw_min << tq->tqi_cw_min) + (1 << tq->tqi_cw_min) - 1);
3258 cw_max = tq->tqi_cw_max < 0 ? (cw_max >> (-tq->tqi_cw_max)) :
3259 ((cw_max << tq->tqi_cw_max) + (1 << tq->tqi_cw_max) - 1);
3260
3261 /*
3262 * Calculate and set retry limits
3263 */
3264 if (ah->ah_software_retry == true) {
3265 /* XXX Need to test this */
3266 retry_lg = ah->ah_limit_tx_retries;
3267 retry_sh = retry_lg = retry_lg > AR5K_DCU_RETRY_LMT_SH_RETRY ?
3268 AR5K_DCU_RETRY_LMT_SH_RETRY : retry_lg;
3269 } else {
3270 retry_lg = AR5K_INIT_LG_RETRY;
3271 retry_sh = AR5K_INIT_SH_RETRY;
3272 }
3273
3274 /*No QCU/DCU [5210]*/
3275 if (ah->ah_version == AR5K_AR5210) {
3276 ath5k_hw_reg_write(ah,
3277 (cw_min << AR5K_NODCU_RETRY_LMT_CW_MIN_S)
3278 | AR5K_REG_SM(AR5K_INIT_SLG_RETRY,
3279 AR5K_NODCU_RETRY_LMT_SLG_RETRY)
3280 | AR5K_REG_SM(AR5K_INIT_SSH_RETRY,
3281 AR5K_NODCU_RETRY_LMT_SSH_RETRY)
3282 | AR5K_REG_SM(retry_lg, AR5K_NODCU_RETRY_LMT_LG_RETRY)
3283 | AR5K_REG_SM(retry_sh, AR5K_NODCU_RETRY_LMT_SH_RETRY),
3284 AR5K_NODCU_RETRY_LMT);
3285 } else {
3286 /*QCU/DCU [5211+]*/
3287 ath5k_hw_reg_write(ah,
3288 AR5K_REG_SM(AR5K_INIT_SLG_RETRY,
3289 AR5K_DCU_RETRY_LMT_SLG_RETRY) |
3290 AR5K_REG_SM(AR5K_INIT_SSH_RETRY,
3291 AR5K_DCU_RETRY_LMT_SSH_RETRY) |
3292 AR5K_REG_SM(retry_lg, AR5K_DCU_RETRY_LMT_LG_RETRY) |
3293 AR5K_REG_SM(retry_sh, AR5K_DCU_RETRY_LMT_SH_RETRY),
3294 AR5K_QUEUE_DFS_RETRY_LIMIT(queue));
3295
3296 /*===Rest is also for QCU/DCU only [5211+]===*/
3297
3298 /*
3299 * Set initial content window (cw_min/cw_max)
3300 * and arbitrated interframe space (aifs)...
3301 */
3302 ath5k_hw_reg_write(ah,
3303 AR5K_REG_SM(cw_min, AR5K_DCU_LCL_IFS_CW_MIN) |
3304 AR5K_REG_SM(cw_max, AR5K_DCU_LCL_IFS_CW_MAX) |
3305 AR5K_REG_SM(ah->ah_aifs + tq->tqi_aifs,
3306 AR5K_DCU_LCL_IFS_AIFS),
3307 AR5K_QUEUE_DFS_LOCAL_IFS(queue));
3308
3309 /*
3310 * Set misc registers
3311 */
3312 ath5k_hw_reg_write(ah, AR5K_QCU_MISC_DCU_EARLY,
3313 AR5K_QUEUE_MISC(queue));
3314
3315 if (tq->tqi_cbr_period) {
3316 ath5k_hw_reg_write(ah, AR5K_REG_SM(tq->tqi_cbr_period,
3317 AR5K_QCU_CBRCFG_INTVAL) |
3318 AR5K_REG_SM(tq->tqi_cbr_overflow_limit,
3319 AR5K_QCU_CBRCFG_ORN_THRES),
3320 AR5K_QUEUE_CBRCFG(queue));
3321 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
3322 AR5K_QCU_MISC_FRSHED_CBR);
3323 if (tq->tqi_cbr_overflow_limit)
3324 AR5K_REG_ENABLE_BITS(ah,
3325 AR5K_QUEUE_MISC(queue),
3326 AR5K_QCU_MISC_CBR_THRES_ENABLE);
3327 }
3328
3329 if (tq->tqi_ready_time)
3330 ath5k_hw_reg_write(ah, AR5K_REG_SM(tq->tqi_ready_time,
3331 AR5K_QCU_RDYTIMECFG_INTVAL) |
3332 AR5K_QCU_RDYTIMECFG_ENABLE,
3333 AR5K_QUEUE_RDYTIMECFG(queue));
3334
3335 if (tq->tqi_burst_time) {
3336 ath5k_hw_reg_write(ah, AR5K_REG_SM(tq->tqi_burst_time,
3337 AR5K_DCU_CHAN_TIME_DUR) |
3338 AR5K_DCU_CHAN_TIME_ENABLE,
3339 AR5K_QUEUE_DFS_CHANNEL_TIME(queue));
3340
3341 if (tq->tqi_flags & AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE)
3342 AR5K_REG_ENABLE_BITS(ah,
3343 AR5K_QUEUE_MISC(queue),
3344 AR5K_QCU_MISC_TXE);
3345 }
3346
3347 if (tq->tqi_flags & AR5K_TXQ_FLAG_BACKOFF_DISABLE)
3348 ath5k_hw_reg_write(ah, AR5K_DCU_MISC_POST_FR_BKOFF_DIS,
3349 AR5K_QUEUE_DFS_MISC(queue));
3350
3351 if (tq->tqi_flags & AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE)
3352 ath5k_hw_reg_write(ah, AR5K_DCU_MISC_BACKOFF_FRAG,
3353 AR5K_QUEUE_DFS_MISC(queue));
3354
3355 /*
3356 * Set registers by queue type
3357 */
3358 switch (tq->tqi_type) {
3359 case AR5K_TX_QUEUE_BEACON:
3360 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
3361 AR5K_QCU_MISC_FRSHED_DBA_GT |
3362 AR5K_QCU_MISC_CBREXP_BCN |
3363 AR5K_QCU_MISC_BCN_ENABLE);
3364
3365 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue),
3366 (AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL <<
3367 AR5K_DCU_MISC_ARBLOCK_CTL_S) |
3368 AR5K_DCU_MISC_POST_FR_BKOFF_DIS |
3369 AR5K_DCU_MISC_BCN_ENABLE);
3370
3371 ath5k_hw_reg_write(ah, ((AR5K_TUNE_BEACON_INTERVAL -
3372 (AR5K_TUNE_SW_BEACON_RESP -
3373 AR5K_TUNE_DMA_BEACON_RESP) -
3374 AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF) * 1024) |
3375 AR5K_QCU_RDYTIMECFG_ENABLE,
3376 AR5K_QUEUE_RDYTIMECFG(queue));
3377 break;
3378
3379 case AR5K_TX_QUEUE_CAB:
3380 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
3381 AR5K_QCU_MISC_FRSHED_DBA_GT |
3382 AR5K_QCU_MISC_CBREXP |
3383 AR5K_QCU_MISC_CBREXP_BCN);
3384
3385 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue),
3386 (AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL <<
3387 AR5K_DCU_MISC_ARBLOCK_CTL_S));
3388 break;
3389
3390 case AR5K_TX_QUEUE_UAPSD:
3391 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
3392 AR5K_QCU_MISC_CBREXP);
3393 break;
3394
3395 case AR5K_TX_QUEUE_DATA:
3396 default:
3397 break;
3398 }
3399
3400 /*
3401 * Enable interrupts for this tx queue
3402 * in the secondary interrupt mask registers
3403 */
3404 if (tq->tqi_flags & AR5K_TXQ_FLAG_TXOKINT_ENABLE)
3405 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txok, queue);
3406
3407 if (tq->tqi_flags & AR5K_TXQ_FLAG_TXERRINT_ENABLE)
3408 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txerr, queue);
3409
3410 if (tq->tqi_flags & AR5K_TXQ_FLAG_TXURNINT_ENABLE)
3411 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txurn, queue);
3412
3413 if (tq->tqi_flags & AR5K_TXQ_FLAG_TXDESCINT_ENABLE)
3414 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txdesc, queue);
3415
3416 if (tq->tqi_flags & AR5K_TXQ_FLAG_TXEOLINT_ENABLE)
3417 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txeol, queue);
3418
3419
3420 /* Update secondary interrupt mask registers */
3421 ah->ah_txq_imr_txok &= ah->ah_txq_status;
3422 ah->ah_txq_imr_txerr &= ah->ah_txq_status;
3423 ah->ah_txq_imr_txurn &= ah->ah_txq_status;
3424 ah->ah_txq_imr_txdesc &= ah->ah_txq_status;
3425 ah->ah_txq_imr_txeol &= ah->ah_txq_status;
3426
3427 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_txok,
3428 AR5K_SIMR0_QCU_TXOK) |
3429 AR5K_REG_SM(ah->ah_txq_imr_txdesc,
3430 AR5K_SIMR0_QCU_TXDESC), AR5K_SIMR0);
3431 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_txerr,
3432 AR5K_SIMR1_QCU_TXERR) |
3433 AR5K_REG_SM(ah->ah_txq_imr_txeol,
3434 AR5K_SIMR1_QCU_TXEOL), AR5K_SIMR1);
3435 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_txurn,
3436 AR5K_SIMR2_QCU_TXURN), AR5K_SIMR2);
3437 }
3438
3439 return 0;
3440 }
3441
3442 /*
3443 * Get number of pending frames
3444 * for a specific queue [5211+]
3445 */
3446 u32 ath5k_hw_num_tx_pending(struct ath5k_hw *ah, unsigned int queue) {
3447 ATH5K_TRACE(ah->ah_sc);
3448 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
3449
3450 /* Return if queue is declared inactive */
3451 if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)
3452 return false;
3453
3454 /* XXX: How about AR5K_CFG_TXCNT ? */
3455 if (ah->ah_version == AR5K_AR5210)
3456 return false;
3457
3458 return AR5K_QUEUE_STATUS(queue) & AR5K_QCU_STS_FRMPENDCNT;
3459 }
3460
3461 /*
3462 * Set slot time
3463 */
3464 int ath5k_hw_set_slot_time(struct ath5k_hw *ah, unsigned int slot_time)
3465 {
3466 ATH5K_TRACE(ah->ah_sc);
3467 if (slot_time < AR5K_SLOT_TIME_9 || slot_time > AR5K_SLOT_TIME_MAX)
3468 return -EINVAL;
3469
3470 if (ah->ah_version == AR5K_AR5210)
3471 ath5k_hw_reg_write(ah, ath5k_hw_htoclock(slot_time,
3472 ah->ah_turbo), AR5K_SLOT_TIME);
3473 else
3474 ath5k_hw_reg_write(ah, slot_time, AR5K_DCU_GBL_IFS_SLOT);
3475
3476 return 0;
3477 }
3478
3479 /*
3480 * Get slot time
3481 */
3482 unsigned int ath5k_hw_get_slot_time(struct ath5k_hw *ah)
3483 {
3484 ATH5K_TRACE(ah->ah_sc);
3485 if (ah->ah_version == AR5K_AR5210)
3486 return ath5k_hw_clocktoh(ath5k_hw_reg_read(ah,
3487 AR5K_SLOT_TIME) & 0xffff, ah->ah_turbo);
3488 else
3489 return ath5k_hw_reg_read(ah, AR5K_DCU_GBL_IFS_SLOT) & 0xffff;
3490 }
3491
3492
3493 /******************************\
3494 Hardware Descriptor Functions
3495 \******************************/
3496
3497 /*
3498 * TX Descriptor
3499 */
3500
3501 /*
3502 * Initialize the 2-word tx descriptor on 5210/5211
3503 */
3504 static int
3505 ath5k_hw_setup_2word_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
3506 unsigned int pkt_len, unsigned int hdr_len, enum ath5k_pkt_type type,
3507 unsigned int tx_power, unsigned int tx_rate0, unsigned int tx_tries0,
3508 unsigned int key_index, unsigned int antenna_mode, unsigned int flags,
3509 unsigned int rtscts_rate, unsigned int rtscts_duration)
3510 {
3511 u32 frame_type;
3512 struct ath5k_hw_2w_tx_desc *tx_desc;
3513 <<<<<<< HEAD:drivers/net/wireless/ath5k/hw.c
3514 unsigned int buff_len;
3515 =======
3516 unsigned int frame_len;
3517 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/net/wireless/ath5k/hw.c
3518
3519 tx_desc = (struct ath5k_hw_2w_tx_desc *)&desc->ds_ctl0;
3520
3521 /*
3522 * Validate input
3523 * - Zero retries don't make sense.
3524 * - A zero rate will put the HW into a mode where it continously sends
3525 * noise on the channel, so it is important to avoid this.
3526 */
3527 if (unlikely(tx_tries0 == 0)) {
3528 ATH5K_ERR(ah->ah_sc, "zero retries\n");
3529 WARN_ON(1);
3530 return -EINVAL;
3531 }
3532 if (unlikely(tx_rate0 == 0)) {
3533 ATH5K_ERR(ah->ah_sc, "zero rate\n");
3534 WARN_ON(1);
3535 return -EINVAL;
3536 }
3537
3538 /* Clear status descriptor */
3539 memset(desc->ds_hw, 0, sizeof(struct ath5k_hw_tx_status));
3540
3541 /* Initialize control descriptor */
3542 tx_desc->tx_control_0 = 0;
3543 tx_desc->tx_control_1 = 0;
3544
3545 /* Setup control descriptor */
3546
3547 /* Verify and set frame length */
3548 <<<<<<< HEAD:drivers/net/wireless/ath5k/hw.c
3549 if (pkt_len & ~AR5K_2W_TX_DESC_CTL0_FRAME_LEN)
3550 =======
3551
3552 /* remove padding we might have added before */
3553 frame_len = pkt_len - (hdr_len & 3) + FCS_LEN;
3554
3555 if (frame_len & ~AR5K_2W_TX_DESC_CTL0_FRAME_LEN)
3556 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/net/wireless/ath5k/hw.c
3557 return -EINVAL;
3558
3559 <<<<<<< HEAD:drivers/net/wireless/ath5k/hw.c
3560 tx_desc->tx_control_0 = pkt_len & AR5K_2W_TX_DESC_CTL0_FRAME_LEN;
3561 =======
3562 tx_desc->tx_control_0 = frame_len & AR5K_2W_TX_DESC_CTL0_FRAME_LEN;
3563 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/net/wireless/ath5k/hw.c
3564
3565 /* Verify and set buffer length */
3566 <<<<<<< HEAD:drivers/net/wireless/ath5k/hw.c
3567 buff_len = pkt_len - FCS_LEN;
3568 =======
3569 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/net/wireless/ath5k/hw.c
3570
3571 /* NB: beacon's BufLen must be a multiple of 4 bytes */
3572 if(type == AR5K_PKT_TYPE_BEACON)
3573 <<<<<<< HEAD:drivers/net/wireless/ath5k/hw.c
3574 buff_len = roundup(buff_len, 4);
3575 =======
3576 pkt_len = roundup(pkt_len, 4);
3577 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/net/wireless/ath5k/hw.c
3578
3579 <<<<<<< HEAD:drivers/net/wireless/ath5k/hw.c
3580 if (buff_len & ~AR5K_2W_TX_DESC_CTL1_BUF_LEN)
3581 =======
3582 if (pkt_len & ~AR5K_2W_TX_DESC_CTL1_BUF_LEN)
3583 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/net/wireless/ath5k/hw.c
3584 return -EINVAL;
3585
3586 <<<<<<< HEAD:drivers/net/wireless/ath5k/hw.c
3587 tx_desc->tx_control_1 = buff_len & AR5K_2W_TX_DESC_CTL1_BUF_LEN;
3588 =======
3589 tx_desc->tx_control_1 = pkt_len & AR5K_2W_TX_DESC_CTL1_BUF_LEN;
3590 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/net/wireless/ath5k/hw.c
3591
3592 /*
3593 * Verify and set header length
3594 * XXX: I only found that on 5210 code, does it work on 5211 ?
3595 */
3596 if (ah->ah_version == AR5K_AR5210) {
3597 if (hdr_len & ~AR5K_2W_TX_DESC_CTL0_HEADER_LEN)
3598 return -EINVAL;
3599 tx_desc->tx_control_0 |=
3600 AR5K_REG_SM(hdr_len, AR5K_2W_TX_DESC_CTL0_HEADER_LEN);
3601 }
3602
3603 /*Diferences between 5210-5211*/
3604 if (ah->ah_version == AR5K_AR5210) {
3605 switch (type) {
3606 case AR5K_PKT_TYPE_BEACON:
3607 case AR5K_PKT_TYPE_PROBE_RESP:
3608 frame_type = AR5K_AR5210_TX_DESC_FRAME_TYPE_NO_DELAY;
3609 case AR5K_PKT_TYPE_PIFS:
3610 frame_type = AR5K_AR5210_TX_DESC_FRAME_TYPE_PIFS;
3611 default:
3612 frame_type = type /*<< 2 ?*/;
3613 }
3614
3615 tx_desc->tx_control_0 |=
3616 AR5K_REG_SM(frame_type, AR5K_2W_TX_DESC_CTL0_FRAME_TYPE) |
3617 AR5K_REG_SM(tx_rate0, AR5K_2W_TX_DESC_CTL0_XMIT_RATE);
3618 } else {
3619 tx_desc->tx_control_0 |=
3620 AR5K_REG_SM(tx_rate0, AR5K_2W_TX_DESC_CTL0_XMIT_RATE) |
3621 AR5K_REG_SM(antenna_mode, AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT);
3622 tx_desc->tx_control_1 |=
3623 AR5K_REG_SM(type, AR5K_2W_TX_DESC_CTL1_FRAME_TYPE);
3624 }
3625 #define _TX_FLAGS(_c, _flag) \
3626 if (flags & AR5K_TXDESC_##_flag) \
3627 tx_desc->tx_control_##_c |= \
3628 AR5K_2W_TX_DESC_CTL##_c##_##_flag
3629
3630 _TX_FLAGS(0, CLRDMASK);
3631 _TX_FLAGS(0, VEOL);
3632 _TX_FLAGS(0, INTREQ);
3633 _TX_FLAGS(0, RTSENA);
3634 _TX_FLAGS(1, NOACK);
3635
3636 #undef _TX_FLAGS
3637
3638 /*
3639 * WEP crap
3640 */
3641 if (key_index != AR5K_TXKEYIX_INVALID) {
3642 tx_desc->tx_control_0 |=
3643 AR5K_2W_TX_DESC_CTL0_ENCRYPT_KEY_VALID;
3644 tx_desc->tx_control_1 |=
3645 AR5K_REG_SM(key_index,
3646 AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX);
3647 }
3648
3649 /*
3650 * RTS/CTS Duration [5210 ?]
3651 */
3652 if ((ah->ah_version == AR5K_AR5210) &&
3653 (flags & (AR5K_TXDESC_RTSENA | AR5K_TXDESC_CTSENA)))
3654 tx_desc->tx_control_1 |= rtscts_duration &
3655 AR5K_2W_TX_DESC_CTL1_RTS_DURATION;
3656
3657 return 0;
3658 }
3659
3660 /*
3661 * Initialize the 4-word tx descriptor on 5212
3662 */
3663 static int ath5k_hw_setup_4word_tx_desc(struct ath5k_hw *ah,
3664 struct ath5k_desc *desc, unsigned int pkt_len, unsigned int hdr_len,
3665 enum ath5k_pkt_type type, unsigned int tx_power, unsigned int tx_rate0,
3666 unsigned int tx_tries0, unsigned int key_index,
3667 unsigned int antenna_mode, unsigned int flags, unsigned int rtscts_rate,
3668 unsigned int rtscts_duration)
3669 {
3670 struct ath5k_hw_4w_tx_desc *tx_desc;
3671 struct ath5k_hw_tx_status *tx_status;
3672 <<<<<<< HEAD:drivers/net/wireless/ath5k/hw.c
3673 unsigned int buff_len;
3674 =======
3675 unsigned int frame_len;
3676 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/net/wireless/ath5k/hw.c
3677
3678 ATH5K_TRACE(ah->ah_sc);
3679 tx_desc = (struct ath5k_hw_4w_tx_desc *)&desc->ds_ctl0;
3680 tx_status = (struct ath5k_hw_tx_status *)&desc->ds_hw[2];
3681
3682 /*
3683 * Validate input
3684 * - Zero retries don't make sense.
3685 * - A zero rate will put the HW into a mode where it continously sends
3686 * noise on the channel, so it is important to avoid this.
3687 */
3688 if (unlikely(tx_tries0 == 0)) {
3689 ATH5K_ERR(ah->ah_sc, "zero retries\n");
3690 WARN_ON(1);
3691 return -EINVAL;
3692 }
3693 if (unlikely(tx_rate0 == 0)) {
3694 ATH5K_ERR(ah->ah_sc, "zero rate\n");
3695 WARN_ON(1);
3696 return -EINVAL;
3697 }
3698
3699 /* Clear status descriptor */
3700 memset(tx_status, 0, sizeof(struct ath5k_hw_tx_status));
3701
3702 /* Initialize control descriptor */
3703 tx_desc->tx_control_0 = 0;
3704 tx_desc->tx_control_1 = 0;
3705 tx_desc->tx_control_2 = 0;
3706 tx_desc->tx_control_3 = 0;
3707
3708 /* Setup control descriptor */
3709
3710 /* Verify and set frame length */
3711 <<<<<<< HEAD:drivers/net/wireless/ath5k/hw.c
3712 if (pkt_len & ~AR5K_4W_TX_DESC_CTL0_FRAME_LEN)
3713 =======
3714
3715 /* remove padding we might have added before */
3716 frame_len = pkt_len - (hdr_len & 3) + FCS_LEN;
3717
3718 if (frame_len & ~AR5K_4W_TX_DESC_CTL0_FRAME_LEN)
3719 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/net/wireless/ath5k/hw.c
3720 return -EINVAL;
3721
3722 <<<<<<< HEAD:drivers/net/wireless/ath5k/hw.c
3723 tx_desc->tx_control_0 = pkt_len & AR5K_4W_TX_DESC_CTL0_FRAME_LEN;
3724 =======
3725 tx_desc->tx_control_0 = frame_len & AR5K_4W_TX_DESC_CTL0_FRAME_LEN;
3726 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/net/wireless/ath5k/hw.c
3727
3728 /* Verify and set buffer length */
3729 <<<<<<< HEAD:drivers/net/wireless/ath5k/hw.c
3730 buff_len = pkt_len - FCS_LEN;
3731 =======
3732 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/net/wireless/ath5k/hw.c
3733
3734 /* NB: beacon's BufLen must be a multiple of 4 bytes */
3735 if(type == AR5K_PKT_TYPE_BEACON)
3736 <<<<<<< HEAD:drivers/net/wireless/ath5k/hw.c
3737 buff_len = roundup(buff_len, 4);
3738 =======
3739 pkt_len = roundup(pkt_len, 4);
3740 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/net/wireless/ath5k/hw.c
3741
3742 <<<<<<< HEAD:drivers/net/wireless/ath5k/hw.c
3743 if (buff_len & ~AR5K_4W_TX_DESC_CTL1_BUF_LEN)
3744 =======
3745 if (pkt_len & ~AR5K_4W_TX_DESC_CTL1_BUF_LEN)
3746 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/net/wireless/ath5k/hw.c
3747 return -EINVAL;
3748
3749 <<<<<<< HEAD:drivers/net/wireless/ath5k/hw.c
3750 tx_desc->tx_control_1 = buff_len & AR5K_4W_TX_DESC_CTL1_BUF_LEN;
3751 =======
3752 tx_desc->tx_control_1 = pkt_len & AR5K_4W_TX_DESC_CTL1_BUF_LEN;
3753 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/net/wireless/ath5k/hw.c
3754
3755 tx_desc->tx_control_0 |=
3756 AR5K_REG_SM(tx_power, AR5K_4W_TX_DESC_CTL0_XMIT_POWER) |
3757 AR5K_REG_SM(antenna_mode, AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT);
3758 tx_desc->tx_control_1 |= AR5K_REG_SM(type,
3759 AR5K_4W_TX_DESC_CTL1_FRAME_TYPE);
3760 tx_desc->tx_control_2 = AR5K_REG_SM(tx_tries0 + AR5K_TUNE_HWTXTRIES,
3761 AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0);
3762 tx_desc->tx_control_3 = tx_rate0 & AR5K_4W_TX_DESC_CTL3_XMIT_RATE0;
3763
3764 #define _TX_FLAGS(_c, _flag) \
3765 if (flags & AR5K_TXDESC_##_flag) \
3766 tx_desc->tx_control_##_c |= \
3767 AR5K_4W_TX_DESC_CTL##_c##_##_flag
3768
3769 _TX_FLAGS(0, CLRDMASK);
3770 _TX_FLAGS(0, VEOL);
3771 _TX_FLAGS(0, INTREQ);
3772 _TX_FLAGS(0, RTSENA);
3773 _TX_FLAGS(0, CTSENA);
3774 _TX_FLAGS(1, NOACK);
3775
3776 #undef _TX_FLAGS
3777
3778 /*
3779 * WEP crap
3780 */
3781 if (key_index != AR5K_TXKEYIX_INVALID) {
3782 tx_desc->tx_control_0 |= AR5K_4W_TX_DESC_CTL0_ENCRYPT_KEY_VALID;
3783 tx_desc->tx_control_1 |= AR5K_REG_SM(key_index,
3784 AR5K_4W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX);
3785 }
3786
3787 /*
3788 * RTS/CTS
3789 */
3790 if (flags & (AR5K_TXDESC_RTSENA | AR5K_TXDESC_CTSENA)) {
3791 if ((flags & AR5K_TXDESC_RTSENA) &&
3792 (flags & AR5K_TXDESC_CTSENA))
3793 return -EINVAL;
3794 tx_desc->tx_control_2 |= rtscts_duration &
3795 AR5K_4W_TX_DESC_CTL2_RTS_DURATION;
3796 tx_desc->tx_control_3 |= AR5K_REG_SM(rtscts_rate,
3797 AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE);
3798 }
3799
3800 return 0;
3801 }
3802
3803 /*
3804 * Initialize a 4-word multirate tx descriptor on 5212
3805 */
3806 <<<<<<< HEAD:drivers/net/wireless/ath5k/hw.c
3807 static bool
3808 =======
3809 static int
3810 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/net/wireless/ath5k/hw.c
3811 ath5k_hw_setup_xr_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
3812 unsigned int tx_rate1, u_int tx_tries1, u_int tx_rate2, u_int tx_tries2,
3813 unsigned int tx_rate3, u_int tx_tries3)
3814 {
3815 struct ath5k_hw_4w_tx_desc *tx_desc;
3816
3817 /*
3818 * Rates can be 0 as long as the retry count is 0 too.
3819 * A zero rate and nonzero retry count will put the HW into a mode where
3820 * it continously sends noise on the channel, so it is important to
3821 * avoid this.
3822 */
3823 if (unlikely((tx_rate1 == 0 && tx_tries1 != 0) ||
3824 (tx_rate2 == 0 && tx_tries2 != 0) ||
3825 (tx_rate3 == 0 && tx_tries3 != 0))) {
3826 ATH5K_ERR(ah->ah_sc, "zero rate\n");
3827 WARN_ON(1);
3828 return -EINVAL;
3829 }
3830
3831 if (ah->ah_version == AR5K_AR5212) {
3832 tx_desc = (struct ath5k_hw_4w_tx_desc *)&desc->ds_ctl0;
3833
3834 #define _XTX_TRIES(_n) \
3835 if (tx_tries##_n) { \
3836 tx_desc->tx_control_2 |= \
3837 AR5K_REG_SM(tx_tries##_n, \
3838 AR5K_4W_TX_DESC_CTL2_XMIT_TRIES##_n); \
3839 tx_desc->tx_control_3 |= \
3840 AR5K_REG_SM(tx_rate##_n, \
3841 AR5K_4W_TX_DESC_CTL3_XMIT_RATE##_n); \
3842 }
3843
3844 _XTX_TRIES(1);
3845 _XTX_TRIES(2);
3846 _XTX_TRIES(3);
3847
3848 #undef _XTX_TRIES
3849
3850 <<<<<<< HEAD:drivers/net/wireless/ath5k/hw.c
3851 return true;
3852 =======
3853 return 1;
3854 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/net/wireless/ath5k/hw.c
3855 }
3856
3857 <<<<<<< HEAD:drivers/net/wireless/ath5k/hw.c
3858 return false;
3859 =======
3860 return 0;
3861 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/net/wireless/ath5k/hw.c
3862 }
3863
3864 /*
3865 * Proccess the tx status descriptor on 5210/5211
3866 */
3867 static int ath5k_hw_proc_2word_tx_status(struct ath5k_hw *ah,
3868 struct ath5k_desc *desc)
3869 {
3870 struct ath5k_hw_tx_status *tx_status;
3871 struct ath5k_hw_2w_tx_desc *tx_desc;
3872
3873 tx_desc = (struct ath5k_hw_2w_tx_desc *)&desc->ds_ctl0;
3874 tx_status = (struct ath5k_hw_tx_status *)&desc->ds_hw[0];
3875
3876 /* No frame has been send or error */
3877 if (unlikely((tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE) == 0))
3878 return -EINPROGRESS;
3879
3880 /*
3881 * Get descriptor status
3882 */
3883 desc->ds_us.tx.ts_tstamp = AR5K_REG_MS(tx_status->tx_status_0,
3884 AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP);
3885 desc->ds_us.tx.ts_shortretry = AR5K_REG_MS(tx_status->tx_status_0,
3886 AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT);
3887 desc->ds_us.tx.ts_longretry = AR5K_REG_MS(tx_status->tx_status_0,
3888 AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT);
3889 /*TODO: desc->ds_us.tx.ts_virtcol + test*/
3890 desc->ds_us.tx.ts_seqnum = AR5K_REG_MS(tx_status->tx_status_1,
3891 AR5K_DESC_TX_STATUS1_SEQ_NUM);
3892 desc->ds_us.tx.ts_rssi = AR5K_REG_MS(tx_status->tx_status_1,
3893 AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH);
3894 desc->ds_us.tx.ts_antenna = 1;
3895 desc->ds_us.tx.ts_status = 0;
3896 desc->ds_us.tx.ts_rate = AR5K_REG_MS(tx_desc->tx_control_0,
3897 AR5K_2W_TX_DESC_CTL0_XMIT_RATE);
3898
3899 if ((tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK) == 0){
3900 if (tx_status->tx_status_0 &
3901 AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES)
3902 desc->ds_us.tx.ts_status |= AR5K_TXERR_XRETRY;
3903
3904 if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN)
3905 desc->ds_us.tx.ts_status |= AR5K_TXERR_FIFO;
3906
3907 if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FILTERED)
3908 desc->ds_us.tx.ts_status |= AR5K_TXERR_FILT;
3909 }
3910
3911 return 0;
3912 }
3913
3914 /*
3915 * Proccess a tx descriptor on 5212
3916 */
3917 static int ath5k_hw_proc_4word_tx_status(struct ath5k_hw *ah,
3918 struct ath5k_desc *desc)
3919 {
3920 struct ath5k_hw_tx_status *tx_status;
3921 struct ath5k_hw_4w_tx_desc *tx_desc;
3922
3923 ATH5K_TRACE(ah->ah_sc);
3924 tx_desc = (struct ath5k_hw_4w_tx_desc *)&desc->ds_ctl0;
3925 tx_status = (struct ath5k_hw_tx_status *)&desc->ds_hw[2];
3926
3927 /* No frame has been send or error */
3928 if (unlikely((tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE) == 0))
3929 return -EINPROGRESS;
3930
3931 /*
3932 * Get descriptor status
3933 */
3934 desc->ds_us.tx.ts_tstamp = AR5K_REG_MS(tx_status->tx_status_0,
3935 AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP);
3936 desc->ds_us.tx.ts_shortretry = AR5K_REG_MS(tx_status->tx_status_0,
3937 AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT);
3938 desc->ds_us.tx.ts_longretry = AR5K_REG_MS(tx_status->tx_status_0,
3939 AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT);
3940 desc->ds_us.tx.ts_seqnum = AR5K_REG_MS(tx_status->tx_status_1,
3941 AR5K_DESC_TX_STATUS1_SEQ_NUM);
3942 desc->ds_us.tx.ts_rssi = AR5K_REG_MS(tx_status->tx_status_1,
3943 AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH);
3944 desc->ds_us.tx.ts_antenna = (tx_status->tx_status_1 &
3945 AR5K_DESC_TX_STATUS1_XMIT_ANTENNA) ? 2 : 1;
3946 desc->ds_us.tx.ts_status = 0;
3947
3948 switch (AR5K_REG_MS(tx_status->tx_status_1,
3949 AR5K_DESC_TX_STATUS1_FINAL_TS_INDEX)) {
3950 case 0:
3951 desc->ds_us.tx.ts_rate = tx_desc->tx_control_3 &
3952 AR5K_4W_TX_DESC_CTL3_XMIT_RATE0;
3953 break;
3954 case 1:
3955 desc->ds_us.tx.ts_rate = AR5K_REG_MS(tx_desc->tx_control_3,
3956 AR5K_4W_TX_DESC_CTL3_XMIT_RATE1);
3957 desc->ds_us.tx.ts_longretry +=AR5K_REG_MS(tx_desc->tx_control_2,
3958 AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1);
3959 break;
3960 case 2:
3961 desc->ds_us.tx.ts_rate = AR5K_REG_MS(tx_desc->tx_control_3,
3962 AR5K_4W_TX_DESC_CTL3_XMIT_RATE2);
3963 desc->ds_us.tx.ts_longretry +=AR5K_REG_MS(tx_desc->tx_control_2,
3964 AR5K_4W_TX_DESC_CTL2_XMIT_TRIES2);
3965 break;
3966 case 3:
3967 desc->ds_us.tx.ts_rate = AR5K_REG_MS(tx_desc->tx_control_3,
3968 AR5K_4W_TX_DESC_CTL3_XMIT_RATE3);
3969 desc->ds_us.tx.ts_longretry +=AR5K_REG_MS(tx_desc->tx_control_2,
3970 AR5K_4W_TX_DESC_CTL2_XMIT_TRIES3);
3971 break;
3972 }
3973
3974 if ((tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK) == 0){
3975 if (tx_status->tx_status_0 &
3976 AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES)
3977 desc->ds_us.tx.ts_status |= AR5K_TXERR_XRETRY;
3978
3979 if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN)
3980 desc->ds_us.tx.ts_status |= AR5K_TXERR_FIFO;
3981
3982 if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FILTERED)
3983 desc->ds_us.tx.ts_status |= AR5K_TXERR_FILT;
3984 }
3985
3986 return 0;
3987 }
3988
3989 /*
3990 * RX Descriptor
3991 */
3992
3993 /*
3994 * Initialize an rx descriptor
3995 */
3996 int ath5k_hw_setup_rx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
3997 u32 size, unsigned int flags)
3998 {
3999 struct ath5k_rx_desc *rx_desc;
4000
4001 ATH5K_TRACE(ah->ah_sc);
4002 rx_desc = (struct ath5k_rx_desc *)&desc->ds_ctl0;
4003
4004 /*
4005 *Clear ds_hw
4006 * If we don't clean the status descriptor,
4007 * while scanning we get too many results,
4008 * most of them virtual, after some secs
4009 * of scanning system hangs. M.F.
4010 */
4011 memset(desc->ds_hw, 0, sizeof(desc->ds_hw));
4012
4013 /*Initialize rx descriptor*/
4014 rx_desc->rx_control_0 = 0;
4015 rx_desc->rx_control_1 = 0;
4016
4017 /* Setup descriptor */
4018 rx_desc->rx_control_1 = size & AR5K_DESC_RX_CTL1_BUF_LEN;
4019 if (unlikely(rx_desc->rx_control_1 != size))
4020 return -EINVAL;
4021
4022 if (flags & AR5K_RXDESC_INTREQ)
4023 rx_desc->rx_control_1 |= AR5K_DESC_RX_CTL1_INTREQ;
4024
4025 return 0;
4026 }
4027
4028 /*
4029 * Proccess the rx status descriptor on 5210/5211
4030 */
4031 static int ath5k_hw_proc_old_rx_status(struct ath5k_hw *ah,
4032 struct ath5k_desc *desc)
4033 {
4034 struct ath5k_hw_old_rx_status *rx_status;
4035
4036 rx_status = (struct ath5k_hw_old_rx_status *)&desc->ds_hw[0];
4037
4038 /* No frame received / not ready */
4039 if (unlikely((rx_status->rx_status_1 & AR5K_OLD_RX_DESC_STATUS1_DONE)
4040 == 0))
4041 return -EINPROGRESS;
4042
4043 /*
4044 * Frame receive status
4045 */
4046 desc->ds_us.rx.rs_datalen = rx_status->rx_status_0 &
4047 AR5K_OLD_RX_DESC_STATUS0_DATA_LEN;
4048 desc->ds_us.rx.rs_rssi = AR5K_REG_MS(rx_status->rx_status_0,
4049 AR5K_OLD_RX_DESC_STATUS0_RECEIVE_SIGNAL);
4050 desc->ds_us.rx.rs_rate = AR5K_REG_MS(rx_status->rx_status_0,
4051 AR5K_OLD_RX_DESC_STATUS0_RECEIVE_RATE);
4052 desc->ds_us.rx.rs_antenna = rx_status->rx_status_0 &
4053 AR5K_OLD_RX_DESC_STATUS0_RECEIVE_ANTENNA;
4054 desc->ds_us.rx.rs_more = rx_status->rx_status_0 &
4055 AR5K_OLD_RX_DESC_STATUS0_MORE;
4056 desc->ds_us.rx.rs_tstamp = AR5K_REG_MS(rx_status->rx_status_1,
4057 AR5K_OLD_RX_DESC_STATUS1_RECEIVE_TIMESTAMP);
4058 desc->ds_us.rx.rs_status = 0;
4059
4060 /*
4061 * Key table status
4062 */
4063 if (rx_status->rx_status_1 & AR5K_OLD_RX_DESC_STATUS1_KEY_INDEX_VALID)
4064 desc->ds_us.rx.rs_keyix = AR5K_REG_MS(rx_status->rx_status_1,
4065 AR5K_OLD_RX_DESC_STATUS1_KEY_INDEX);
4066 else
4067 desc->ds_us.rx.rs_keyix = AR5K_RXKEYIX_INVALID;
4068
4069 /*
4070 * Receive/descriptor errors
4071 */
4072 if ((rx_status->rx_status_1 & AR5K_OLD_RX_DESC_STATUS1_FRAME_RECEIVE_OK)
4073 == 0) {
4074 if (rx_status->rx_status_1 & AR5K_OLD_RX_DESC_STATUS1_CRC_ERROR)
4075 desc->ds_us.rx.rs_status |= AR5K_RXERR_CRC;
4076
4077 if (rx_status->rx_status_1 &
4078 AR5K_OLD_RX_DESC_STATUS1_FIFO_OVERRUN)
4079 desc->ds_us.rx.rs_status |= AR5K_RXERR_FIFO;
4080
4081 if (rx_status->rx_status_1 &
4082 AR5K_OLD_RX_DESC_STATUS1_PHY_ERROR) {
4083 desc->ds_us.rx.rs_status |= AR5K_RXERR_PHY;
4084 desc->ds_us.rx.rs_phyerr =
4085 AR5K_REG_MS(rx_status->rx_status_1,
4086 AR5K_OLD_RX_DESC_STATUS1_PHY_ERROR);
4087 }
4088
4089 if (rx_status->rx_status_1 &
4090 AR5K_OLD_RX_DESC_STATUS1_DECRYPT_CRC_ERROR)
4091 desc->ds_us.rx.rs_status |= AR5K_RXERR_DECRYPT;
4092 }
4093
4094 return 0;
4095 }
4096
4097 /*
4098 * Proccess the rx status descriptor on 5212
4099 */
4100 static int ath5k_hw_proc_new_rx_status(struct ath5k_hw *ah,
4101 struct ath5k_desc *desc)
4102 {
4103 struct ath5k_hw_new_rx_status *rx_status;
4104 struct ath5k_hw_rx_error *rx_err;
4105
4106 ATH5K_TRACE(ah->ah_sc);
4107 rx_status = (struct ath5k_hw_new_rx_status *)&desc->ds_hw[0];
4108
4109 /* Overlay on error */
4110 rx_err = (struct ath5k_hw_rx_error *)&desc->ds_hw[0];
4111
4112 /* No frame received / not ready */
4113 if (unlikely((rx_status->rx_status_1 & AR5K_NEW_RX_DESC_STATUS1_DONE)
4114 == 0))
4115 return -EINPROGRESS;
4116
4117 /*
4118 * Frame receive status
4119 */
4120 desc->ds_us.rx.rs_datalen = rx_status->rx_status_0 &
4121 AR5K_NEW_RX_DESC_STATUS0_DATA_LEN;
4122 desc->ds_us.rx.rs_rssi = AR5K_REG_MS(rx_status->rx_status_0,
4123 AR5K_NEW_RX_DESC_STATUS0_RECEIVE_SIGNAL);
4124 desc->ds_us.rx.rs_rate = AR5K_REG_MS(rx_status->rx_status_0,
4125 AR5K_NEW_RX_DESC_STATUS0_RECEIVE_RATE);
4126 desc->ds_us.rx.rs_antenna = rx_status->rx_status_0 &
4127 AR5K_NEW_RX_DESC_STATUS0_RECEIVE_ANTENNA;
4128 desc->ds_us.rx.rs_more = rx_status->rx_status_0 &
4129 AR5K_NEW_RX_DESC_STATUS0_MORE;
4130 desc->ds_us.rx.rs_tstamp = AR5K_REG_MS(rx_status->rx_status_1,
4131 AR5K_NEW_RX_DESC_STATUS1_RECEIVE_TIMESTAMP);
4132 desc->ds_us.rx.rs_status = 0;
4133
4134 /*
4135 * Key table status
4136 */
4137 if (rx_status->rx_status_1 & AR5K_NEW_RX_DESC_STATUS1_KEY_INDEX_VALID)
4138 desc->ds_us.rx.rs_keyix = AR5K_REG_MS(rx_status->rx_status_1,
4139 AR5K_NEW_RX_DESC_STATUS1_KEY_INDEX);
4140 else
4141 desc->ds_us.rx.rs_keyix = AR5K_RXKEYIX_INVALID;
4142
4143 /*
4144 * Receive/descriptor errors
4145 */
4146 if ((rx_status->rx_status_1 &
4147 AR5K_NEW_RX_DESC_STATUS1_FRAME_RECEIVE_OK) == 0) {
4148 if (rx_status->rx_status_1 & AR5K_NEW_RX_DESC_STATUS1_CRC_ERROR)
4149 desc->ds_us.rx.rs_status |= AR5K_RXERR_CRC;
4150
4151 if (rx_status->rx_status_1 &
4152 AR5K_NEW_RX_DESC_STATUS1_PHY_ERROR) {
4153 desc->ds_us.rx.rs_status |= AR5K_RXERR_PHY;
4154 desc->ds_us.rx.rs_phyerr =
4155 AR5K_REG_MS(rx_err->rx_error_1,
4156 AR5K_RX_DESC_ERROR1_PHY_ERROR_CODE);
4157 }
4158
4159 if (rx_status->rx_status_1 &
4160 AR5K_NEW_RX_DESC_STATUS1_DECRYPT_CRC_ERROR)
4161 desc->ds_us.rx.rs_status |= AR5K_RXERR_DECRYPT;
4162
4163 if (rx_status->rx_status_1 & AR5K_NEW_RX_DESC_STATUS1_MIC_ERROR)
4164 desc->ds_us.rx.rs_status |= AR5K_RXERR_MIC;
4165 }
4166
4167 return 0;
4168 }
4169
4170
4171 /****************\
4172 GPIO Functions
4173 \****************/
4174
4175 /*
4176 * Set led state
4177 */
4178 void ath5k_hw_set_ledstate(struct ath5k_hw *ah, unsigned int state)
4179 {
4180 u32 led;
4181 /*5210 has different led mode handling*/
4182 u32 led_5210;
4183
4184 ATH5K_TRACE(ah->ah_sc);
4185
4186 /*Reset led status*/
4187 if (ah->ah_version != AR5K_AR5210)
4188 AR5K_REG_DISABLE_BITS(ah, AR5K_PCICFG,
4189 AR5K_PCICFG_LEDMODE | AR5K_PCICFG_LED);
4190 else
4191 AR5K_REG_DISABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_LED);
4192
4193 /*
4194 * Some blinking values, define at your wish
4195 */
4196 switch (state) {
4197 case AR5K_LED_SCAN:
4198 case AR5K_LED_AUTH:
4199 led = AR5K_PCICFG_LEDMODE_PROP | AR5K_PCICFG_LED_PEND;
4200 led_5210 = AR5K_PCICFG_LED_PEND | AR5K_PCICFG_LED_BCTL;
4201 break;
4202
4203 case AR5K_LED_INIT:
4204 led = AR5K_PCICFG_LEDMODE_PROP | AR5K_PCICFG_LED_NONE;
4205 led_5210 = AR5K_PCICFG_LED_PEND;
4206 break;
4207
4208 case AR5K_LED_ASSOC:
4209 case AR5K_LED_RUN:
4210 led = AR5K_PCICFG_LEDMODE_PROP | AR5K_PCICFG_LED_ASSOC;
4211 led_5210 = AR5K_PCICFG_LED_ASSOC;
4212 break;
4213
4214 default:
4215 led = AR5K_PCICFG_LEDMODE_PROM | AR5K_PCICFG_LED_NONE;
4216 led_5210 = AR5K_PCICFG_LED_PEND;
4217 break;
4218 }
4219
4220 /*Write new status to the register*/
4221 if (ah->ah_version != AR5K_AR5210)
4222 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, led);
4223 else
4224 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, led_5210);
4225 }
4226
4227 /*
4228 * Set GPIO outputs
4229 */
4230 int ath5k_hw_set_gpio_output(struct ath5k_hw *ah, u32 gpio)
4231 {
4232 ATH5K_TRACE(ah->ah_sc);
4233 if (gpio > AR5K_NUM_GPIO)
4234 return -EINVAL;
4235
4236 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, AR5K_GPIOCR) &~
4237 AR5K_GPIOCR_OUT(gpio)) | AR5K_GPIOCR_OUT(gpio), AR5K_GPIOCR);
4238
4239 return 0;
4240 }
4241
4242 /*
4243 * Set GPIO inputs
4244 */
4245 int ath5k_hw_set_gpio_input(struct ath5k_hw *ah, u32 gpio)
4246 {
4247 ATH5K_TRACE(ah->ah_sc);
4248 if (gpio > AR5K_NUM_GPIO)
4249 return -EINVAL;
4250
4251 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, AR5K_GPIOCR) &~
4252 AR5K_GPIOCR_OUT(gpio)) | AR5K_GPIOCR_IN(gpio), AR5K_GPIOCR);
4253
4254 return 0;
4255 }
4256
4257 /*
4258 * Get GPIO state
4259 */
4260 u32 ath5k_hw_get_gpio(struct ath5k_hw *ah, u32 gpio)
4261 {
4262 ATH5K_TRACE(ah->ah_sc);
4263 if (gpio > AR5K_NUM_GPIO)
4264 return 0xffffffff;
4265
4266 /* GPIO input magic */
4267 return ((ath5k_hw_reg_read(ah, AR5K_GPIODI) & AR5K_GPIODI_M) >> gpio) &
4268 0x1;
4269 }
4270
4271 /*
4272 * Set GPIO state
4273 */
4274 int ath5k_hw_set_gpio(struct ath5k_hw *ah, u32 gpio, u32 val)
4275 {
4276 u32 data;
4277 ATH5K_TRACE(ah->ah_sc);
4278
4279 if (gpio > AR5K_NUM_GPIO)
4280 return -EINVAL;
4281
4282 /* GPIO output magic */
4283 data = ath5k_hw_reg_read(ah, AR5K_GPIODO);
4284
4285 data &= ~(1 << gpio);
4286 data |= (val & 1) << gpio;
4287
4288 ath5k_hw_reg_write(ah, data, AR5K_GPIODO);
4289
4290 return 0;
4291 }
4292
4293 /*
4294 * Initialize the GPIO interrupt (RFKill switch)
4295 */
4296 void ath5k_hw_set_gpio_intr(struct ath5k_hw *ah, unsigned int gpio,
4297 u32 interrupt_level)
4298 {
4299 u32 data;
4300
4301 ATH5K_TRACE(ah->ah_sc);
4302 if (gpio > AR5K_NUM_GPIO)
4303 return;
4304
4305 /*
4306 * Set the GPIO interrupt
4307 */
4308 data = (ath5k_hw_reg_read(ah, AR5K_GPIOCR) &
4309 ~(AR5K_GPIOCR_INT_SEL(gpio) | AR5K_GPIOCR_INT_SELH |
4310 AR5K_GPIOCR_INT_ENA | AR5K_GPIOCR_OUT(gpio))) |
4311 (AR5K_GPIOCR_INT_SEL(gpio) | AR5K_GPIOCR_INT_ENA);
4312
4313 ath5k_hw_reg_write(ah, interrupt_level ? data :
4314 (data | AR5K_GPIOCR_INT_SELH), AR5K_GPIOCR);
4315
4316 ah->ah_imr |= AR5K_IMR_GPIO;
4317
4318 /* Enable GPIO interrupts */
4319 AR5K_REG_ENABLE_BITS(ah, AR5K_PIMR, AR5K_IMR_GPIO);
4320 }
4321
4322
4323 /*********************************\
4324 Regulatory Domain/Channels Setup
4325 \*********************************/
4326
4327 u16 ath5k_get_regdomain(struct ath5k_hw *ah)
4328 {
4329 u16 regdomain;
4330 enum ath5k_regdom ieee_regdomain;
4331 #ifdef COUNTRYCODE
4332 u16 code;
4333 #endif
4334
4335 ath5k_eeprom_regulation_domain(ah, false, &ieee_regdomain);
4336 ah->ah_capabilities.cap_regdomain.reg_hw = ieee_regdomain;
4337
4338 #ifdef COUNTRYCODE
4339 /*
4340 * Get the regulation domain by country code. This will ignore
4341 * the settings found in the EEPROM.
4342 */
4343 code = ieee80211_name2countrycode(COUNTRYCODE);
4344 ieee_regdomain = ieee80211_countrycode2regdomain(code);
4345 #endif
4346
4347 regdomain = ath5k_regdom_from_ieee(ieee_regdomain);
4348 ah->ah_capabilities.cap_regdomain.reg_current = regdomain;
4349
4350 return regdomain;
4351 }
4352
4353
4354 /****************\
4355 Misc functions
4356 \****************/
4357
4358 int ath5k_hw_get_capability(struct ath5k_hw *ah,
4359 enum ath5k_capability_type cap_type,
4360 u32 capability, u32 *result)
4361 {
4362 ATH5K_TRACE(ah->ah_sc);
4363
4364 switch (cap_type) {
4365 case AR5K_CAP_NUM_TXQUEUES:
4366 if (result) {
4367 if (ah->ah_version == AR5K_AR5210)
4368 *result = AR5K_NUM_TX_QUEUES_NOQCU;
4369 else
4370 *result = AR5K_NUM_TX_QUEUES;
4371 goto yes;
4372 }
4373 case AR5K_CAP_VEOL:
4374 goto yes;
4375 case AR5K_CAP_COMPRESSION:
4376 if (ah->ah_version == AR5K_AR5212)
4377 goto yes;
4378 else
4379 goto no;
4380 case AR5K_CAP_BURST:
4381 goto yes;
4382 case AR5K_CAP_TPC:
4383 goto yes;
4384 case AR5K_CAP_BSSIDMASK:
4385 if (ah->ah_version == AR5K_AR5212)
4386 goto yes;
4387 else
4388 goto no;
4389 case AR5K_CAP_XR:
4390 if (ah->ah_version == AR5K_AR5212)
4391 goto yes;
4392 else
4393 goto no;
4394 default:
4395 goto no;
4396 }
4397
4398 no:
4399 return -EINVAL;
4400 yes:
4401 return 0;
4402 }
4403
4404 static int ath5k_hw_enable_pspoll(struct ath5k_hw *ah, u8 *bssid,
4405 u16 assoc_id)
4406 {
4407 ATH5K_TRACE(ah->ah_sc);
4408
4409 if (ah->ah_version == AR5K_AR5210) {
4410 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1,
4411 AR5K_STA_ID1_NO_PSPOLL | AR5K_STA_ID1_DEFAULT_ANTENNA);
4412 return 0;
4413 }
4414
4415 return -EIO;
4416 }
4417
4418 static int ath5k_hw_disable_pspoll(struct ath5k_hw *ah)
4419 {
4420 ATH5K_TRACE(ah->ah_sc);
4421
4422 if (ah->ah_version == AR5K_AR5210) {
4423 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1,
4424 AR5K_STA_ID1_NO_PSPOLL | AR5K_STA_ID1_DEFAULT_ANTENNA);
4425 return 0;
4426 }
4427
4428 return -EIO;
4429 }
WRT350N Kernel Patches