drivers/net/wireless/iwlwifi/iwl-3945-hw.h

   1 /******************************************************************************
   2  *
   3  * This file is provided under a dual BSD/GPLv2 license.  When using or
   4  * redistributing this file, you may do so under either license.
   5  *
   6  * GPL LICENSE SUMMARY
   7  *
   8  * Copyright(c) 2005 - 2007 Intel Corporation. All rights reserved.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of version 2 of the GNU General Public License as
  12  * published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but
  15  * WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
  22  * USA
  23  *
  24  * The full GNU General Public License is included in this distribution
  25  * in the file called LICENSE.GPL.
  26  *
  27  * Contact Information:
  28  * James P. Ketrenos <ipw2100-admin@linux.intel.com>
  29  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  30  *
  31  * BSD LICENSE
  32  *
  33  * Copyright(c) 2005 - 2007 Intel Corporation. All rights reserved.
  34  * All rights reserved.
  35  *
  36  * Redistribution and use in source and binary forms, with or without
  37  * modification, are permitted provided that the following conditions
  38  * are met:
  39  *
  40  *  * Redistributions of source code must retain the above copyright
  41  *    notice, this list of conditions and the following disclaimer.
  42  *  * Redistributions in binary form must reproduce the above copyright
  43  *    notice, this list of conditions and the following disclaimer in
  44  *    the documentation and/or other materials provided with the
  45  *    distribution.
  46  *  * Neither the name Intel Corporation nor the names of its
  47  *    contributors may be used to endorse or promote products derived
  48  *    from this software without specific prior written permission.
  49  *
  50  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  51  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  52  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  53  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  54  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  55  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  56  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  57  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  58  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  59  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  60  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  61  *
  62  *****************************************************************************/
  63 /*
  64  * Please use this file (iwl-3945-hw.h) only for hardware-related definitions.
  65  * Please use iwl-3945-commands.h for uCode API definitions.
  66  * Please use iwl-3945.h for driver implementation definitions.
  67  */
  68
  69 #ifndef __iwl_3945_hw__
  70 #define __iwl_3945_hw__
  71
  72 /*
  73  * uCode queue management definitions ...
  74  * Queue #4 is the command queue for 3945 and 4965.
  75  */
  76 #define IWL_CMD_QUEUE_NUM       4
  77
  78 /* Tx rates */
  79 #define IWL_CCK_RATES 4
  80 #define IWL_OFDM_RATES 8
  81 #define IWL_HT_RATES 0
  82 #define IWL_MAX_RATES  (IWL_CCK_RATES+IWL_OFDM_RATES+IWL_HT_RATES)
  83
  84 /* Time constants */
  85 #define SHORT_SLOT_TIME 9
  86 #define LONG_SLOT_TIME 20
  87
  88 /* RSSI to dBm */
  89 #define IWL_RSSI_OFFSET 95
  90
  91 /*
  92  * EEPROM related constants, enums, and structures.
  93  */
  94
  95 /*
  96  * EEPROM access time values:
  97  *
  98  * Driver initiates EEPROM read by writing byte address << 1 to CSR_EEPROM_REG,
  99  *   then clearing (with subsequent read/modify/write) CSR_EEPROM_REG bit
 100  *   CSR_EEPROM_REG_BIT_CMD (0x2).
 101  * Driver then polls CSR_EEPROM_REG for CSR_EEPROM_REG_READ_VALID_MSK (0x1).
 102  * When polling, wait 10 uSec between polling loops, up to a maximum 5000 uSec.
 103  * Driver reads 16-bit value from bits 31-16 of CSR_EEPROM_REG.
 104  */
 105 #define IWL_EEPROM_ACCESS_TIMEOUT       5000 /* uSec */
 106 #define IWL_EEPROM_ACCESS_DELAY         10   /* uSec */
 107
 108 /*
 109  * Regulatory channel usage flags in EEPROM struct iwl_eeprom_channel.flags.
 110  *
 111  * IBSS and/or AP operation is allowed *only* on those channels with
 112  * (VALID && IBSS && ACTIVE && !RADAR).  This restriction is in place because
 113  * RADAR detection is not supported by the 3945 driver, but is a
 114  * requirement for establishing a new network for legal operation on channels
 115  * requiring RADAR detection or restricting ACTIVE scanning.
 116  *
 117  * NOTE:  "WIDE" flag indicates that 20 MHz channel is supported;
 118  *        3945 does not support FAT 40 MHz-wide channels.
 119  *
 120  * NOTE:  Using a channel inappropriately will result in a uCode error!
 121  */
 122 enum {
 123         EEPROM_CHANNEL_VALID = (1 << 0),        /* usable for this SKU/geo */
 124         EEPROM_CHANNEL_IBSS = (1 << 1),         /* usable as an IBSS channel */
 125         /* Bit 2 Reserved */
 126         EEPROM_CHANNEL_ACTIVE = (1 << 3),       /* active scanning allowed */
 127         EEPROM_CHANNEL_RADAR = (1 << 4),        /* radar detection required */
 128         EEPROM_CHANNEL_WIDE = (1 << 5),         /* 20 MHz channel okay */
 129         EEPROM_CHANNEL_NARROW = (1 << 6),       /* 10 MHz channel (not used) */
 130         EEPROM_CHANNEL_DFS = (1 << 7),  /* dynamic freq selection candidate */
 131 };
 132
 133 /* SKU Capabilities */
 134 #define EEPROM_SKU_CAP_SW_RF_KILL_ENABLE                (1 << 0)
 135 #define EEPROM_SKU_CAP_HW_RF_KILL_ENABLE                (1 << 1)
 136 #define EEPROM_SKU_CAP_OP_MODE_MRC                      (1 << 7)
 137
 138 /* *regulatory* channel data from eeprom, one for each channel */
 139 struct iwl3945_eeprom_channel {
 140         u8 flags;               /* flags copied from EEPROM */
 141         s8 max_power_avg;       /* max power (dBm) on this chnl, limit 31 */
 142 } __attribute__ ((packed));
 143
 144 /*
 145  * Mapping of a Tx power level, at factory calibration temperature,
 146  *   to a radio/DSP gain table index.
 147  * One for each of 5 "sample" power levels in each band.
 148  * v_det is measured at the factory, using the 3945's built-in power amplifier
 149  *   (PA) output voltage detector.  This same detector is used during Tx of
 150  *   long packets in normal operation to provide feedback as to proper output
 151  *   level.
 152  * Data copied from EEPROM.
 153  * DO NOT ALTER THIS STRUCTURE!!!
 154  */
 155 struct iwl3945_eeprom_txpower_sample {
 156         u8 gain_index;          /* index into power (gain) setup table ... */
 157         s8 power;               /* ... for this pwr level for this chnl group */
 158         u16 v_det;              /* PA output voltage */
 159 } __attribute__ ((packed));
 160
 161 /*
 162  * Mappings of Tx power levels -> nominal radio/DSP gain table indexes.
 163  * One for each channel group (a.k.a. "band") (1 for BG, 4 for A).
 164  * Tx power setup code interpolates between the 5 "sample" power levels
 165  *    to determine the nominal setup for a requested power level.
 166  * Data copied from EEPROM.
 167  * DO NOT ALTER THIS STRUCTURE!!!
 168  */
 169 struct iwl3945_eeprom_txpower_group {
 170         struct iwl3945_eeprom_txpower_sample samples[5];  /* 5 power levels */
 171         s32 a, b, c, d, e;      /* coefficients for voltage->power
 172                                  * formula (signed) */
 173         s32 Fa, Fb, Fc, Fd, Fe; /* these modify coeffs based on
 174                                  * frequency (signed) */
 175         s8 saturation_power;    /* highest power possible by h/w in this
 176                                  * band */
 177         u8 group_channel;       /* "representative" channel # in this band */
 178         s16 temperature;        /* h/w temperature at factory calib this band
 179                                  * (signed) */
 180 } __attribute__ ((packed));
 181
 182 /*
 183  * Temperature-based Tx-power compensation data, not band-specific.
 184  * These coefficients are use to modify a/b/c/d/e coeffs based on
 185  *   difference between current temperature and factory calib temperature.
 186  * Data copied from EEPROM.
 187  */
 188 struct iwl3945_eeprom_temperature_corr {
 189         u32 Ta;
 190         u32 Tb;
 191         u32 Tc;
 192         u32 Td;
 193         u32 Te;
 194 } __attribute__ ((packed));
 195
 196 /*
 197  * EEPROM map
 198  */
 199 struct iwl3945_eeprom {
 200         u8 reserved0[16];
 201 #define EEPROM_DEVICE_ID                    (2*0x08)    /* 2 bytes */
 202         u16 device_id;  /* abs.ofs: 16 */
 203         u8 reserved1[2];
 204 #define EEPROM_PMC                          (2*0x0A)    /* 2 bytes */
 205         u16 pmc;                /* abs.ofs: 20 */
 206         u8 reserved2[20];
 207 #define EEPROM_MAC_ADDRESS                  (2*0x15)    /* 6  bytes */
 208         u8 mac_address[6];      /* abs.ofs: 42 */
 209         u8 reserved3[58];
 210 #define EEPROM_BOARD_REVISION               (2*0x35)    /* 2  bytes */
 211         u16 board_revision;     /* abs.ofs: 106 */
 212         u8 reserved4[11];
 213 #define EEPROM_BOARD_PBA_NUMBER             (2*0x3B+1)  /* 9  bytes */
 214         u8 board_pba_number[9]; /* abs.ofs: 119 */
 215         u8 reserved5[8];
 216 #define EEPROM_VERSION                      (2*0x44)    /* 2  bytes */
 217         u16 version;            /* abs.ofs: 136 */
 218 #define EEPROM_SKU_CAP                      (2*0x45)    /* 1  bytes */
 219         u8 sku_cap;             /* abs.ofs: 138 */
 220 #define EEPROM_LEDS_MODE                    (2*0x45+1)  /* 1  bytes */
 221         u8 leds_mode;           /* abs.ofs: 139 */
 222 #define EEPROM_OEM_MODE                     (2*0x46)    /* 2  bytes */
 223         u16 oem_mode;
 224 #define EEPROM_WOWLAN_MODE                  (2*0x47)    /* 2  bytes */
 225         u16 wowlan_mode;        /* abs.ofs: 142 */
 226 #define EEPROM_LEDS_TIME_INTERVAL           (2*0x48)    /* 2  bytes */
 227         u16 leds_time_interval; /* abs.ofs: 144 */
 228 #define EEPROM_LEDS_OFF_TIME                (2*0x49)    /* 1  bytes */
 229         u8 leds_off_time;       /* abs.ofs: 146 */
 230 #define EEPROM_LEDS_ON_TIME                 (2*0x49+1)  /* 1  bytes */
 231         u8 leds_on_time;        /* abs.ofs: 147 */
 232 #define EEPROM_ALMGOR_M_VERSION             (2*0x4A)    /* 1  bytes */
 233         u8 almgor_m_version;    /* abs.ofs: 148 */
 234 #define EEPROM_ANTENNA_SWITCH_TYPE          (2*0x4A+1)  /* 1  bytes */
 235         u8 antenna_switch_type; /* abs.ofs: 149 */
 236         u8 reserved6[42];
 237 #define EEPROM_REGULATORY_SKU_ID            (2*0x60)    /* 4  bytes */
 238         u8 sku_id[4];           /* abs.ofs: 192 */
 239
 240 /*
 241  * Per-channel regulatory data.
 242  *
 243  * Each channel that *might* be supported by 3945 or 4965 has a fixed location
 244  * in EEPROM containing EEPROM_CHANNEL_* usage flags (LSB) and max regulatory
 245  * txpower (MSB).
 246  *
 247  * Entries immediately below are for 20 MHz channel width.  FAT (40 MHz)
 248  * channels (only for 4965, not supported by 3945) appear later in the EEPROM.
 249  *
 250  * 2.4 GHz channels 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
 251  */
 252 #define EEPROM_REGULATORY_BAND_1            (2*0x62)    /* 2  bytes */
 253         u16 band_1_count;       /* abs.ofs: 196 */
 254 #define EEPROM_REGULATORY_BAND_1_CHANNELS   (2*0x63)    /* 28 bytes */
 255         struct iwl3945_eeprom_channel band_1_channels[14];  /* abs.ofs: 196 */
 256
 257 /*
 258  * 4.9 GHz channels 183, 184, 185, 187, 188, 189, 192, 196,
 259  * 5.0 GHz channels 7, 8, 11, 12, 16
 260  * (4915-5080MHz) (none of these is ever supported)
 261  */
 262 #define EEPROM_REGULATORY_BAND_2            (2*0x71)    /* 2  bytes */
 263         u16 band_2_count;       /* abs.ofs: 226 */
 264 #define EEPROM_REGULATORY_BAND_2_CHANNELS   (2*0x72)    /* 26 bytes */
 265         struct iwl3945_eeprom_channel band_2_channels[13];  /* abs.ofs: 228 */
 266
 267 /*
 268  * 5.2 GHz channels 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
 269  * (5170-5320MHz)
 270  */
 271 #define EEPROM_REGULATORY_BAND_3            (2*0x7F)    /* 2  bytes */
 272         u16 band_3_count;       /* abs.ofs: 254 */
 273 #define EEPROM_REGULATORY_BAND_3_CHANNELS   (2*0x80)    /* 24 bytes */
 274         struct iwl3945_eeprom_channel band_3_channels[12];  /* abs.ofs: 256 */
 275
 276 /*
 277  * 5.5 GHz channels 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
 278  * (5500-5700MHz)
 279  */
 280 #define EEPROM_REGULATORY_BAND_4            (2*0x8C)    /* 2  bytes */
 281         u16 band_4_count;       /* abs.ofs: 280 */
 282 #define EEPROM_REGULATORY_BAND_4_CHANNELS   (2*0x8D)    /* 22 bytes */
 283         struct iwl3945_eeprom_channel band_4_channels[11];  /* abs.ofs: 282 */
 284
 285 /*
 286  * 5.7 GHz channels 145, 149, 153, 157, 161, 165
 287  * (5725-5825MHz)
 288  */
 289 #define EEPROM_REGULATORY_BAND_5            (2*0x98)    /* 2  bytes */
 290         u16 band_5_count;       /* abs.ofs: 304 */
 291 #define EEPROM_REGULATORY_BAND_5_CHANNELS   (2*0x99)    /* 12 bytes */
 292         struct iwl3945_eeprom_channel band_5_channels[6];  /* abs.ofs: 306 */
 293
 294         u8 reserved9[194];
 295
 296 /*
 297  * 3945 Txpower calibration data.
 298  */
 299 #define EEPROM_TXPOWER_CALIB_GROUP0 0x200
 300 #define EEPROM_TXPOWER_CALIB_GROUP1 0x240
 301 #define EEPROM_TXPOWER_CALIB_GROUP2 0x280
 302 #define EEPROM_TXPOWER_CALIB_GROUP3 0x2c0
 303 #define EEPROM_TXPOWER_CALIB_GROUP4 0x300
 304 #define IWL_NUM_TX_CALIB_GROUPS 5
 305         struct iwl3945_eeprom_txpower_group groups[IWL_NUM_TX_CALIB_GROUPS];
 306 /* abs.ofs: 512 */
 307 #define EEPROM_CALIB_TEMPERATURE_CORRECT 0x340
 308         struct iwl3945_eeprom_temperature_corr corrections;  /* abs.ofs: 832 */
 309         u8 reserved16[172];     /* fill out to full 1024 byte block */
 310 } __attribute__ ((packed));
 311
 312 #define IWL_EEPROM_IMAGE_SIZE 1024
 313
 314 /* End of EEPROM */
 315
 316
 317 #include "iwl-3945-commands.h"
 318
 319 #define PCI_LINK_CTRL      0x0F0
 320 #define PCI_POWER_SOURCE   0x0C8
 321 #define PCI_REG_WUM8       0x0E8
 322 #define PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT         (0x80000000)
 323
 324 /*=== CSR (control and status registers) ===*/
 325 #define CSR_BASE    (0x000)
 326
 327 #define CSR_SW_VER              (CSR_BASE+0x000)
 328 #define CSR_HW_IF_CONFIG_REG    (CSR_BASE+0x000) /* hardware interface config */
 329 #define CSR_INT_COALESCING      (CSR_BASE+0x004) /* accum ints, 32-usec units */
 330 #define CSR_INT                 (CSR_BASE+0x008) /* host interrupt status/ack */
 331 #define CSR_INT_MASK            (CSR_BASE+0x00c) /* host interrupt enable */
 332 #define CSR_FH_INT_STATUS       (CSR_BASE+0x010) /* busmaster int status/ack*/
 333 #define CSR_GPIO_IN             (CSR_BASE+0x018) /* read external chip pins */
 334 #define CSR_RESET               (CSR_BASE+0x020) /* busmaster enable, NMI, etc*/
 335 #define CSR_GP_CNTRL            (CSR_BASE+0x024)
 336
 337 /*
 338  * Hardware revision info
 339  * Bit fields:
 340  * 31-8:  Reserved
 341  *  7-4:  Type of device:  0x0 = 4965, 0xd = 3945
 342  *  3-2:  Revision step:  0 = A, 1 = B, 2 = C, 3 = D
 343  *  1-0:  "Dash" value, as in A-1, etc.
 344  */
 345 #define CSR_HW_REV              (CSR_BASE+0x028)
 346
 347 /* EEPROM reads */
 348 #define CSR_EEPROM_REG          (CSR_BASE+0x02c)
 349 #define CSR_EEPROM_GP           (CSR_BASE+0x030)
 350 #define CSR_GP_UCODE            (CSR_BASE+0x044)
 351 #define CSR_UCODE_DRV_GP1       (CSR_BASE+0x054)
 352 #define CSR_UCODE_DRV_GP1_SET   (CSR_BASE+0x058)
 353 #define CSR_UCODE_DRV_GP1_CLR   (CSR_BASE+0x05c)
 354 #define CSR_UCODE_DRV_GP2       (CSR_BASE+0x060)
 355 #define CSR_GIO_CHICKEN_BITS    (CSR_BASE+0x100)
 356
 357 /* Analog phase-lock-loop configuration (3945 only)
 358  * Set bit 24. */
 359 #define CSR_ANA_PLL_CFG         (CSR_BASE+0x20c)
 360
 361 /* Bits for CSR_HW_IF_CONFIG_REG */
 362 #define CSR_HW_IF_CONFIG_REG_BIT_ALMAGOR_MB         (0x00000100)
 363 #define CSR_HW_IF_CONFIG_REG_BIT_ALMAGOR_MM         (0x00000200)
 364 #define CSR_HW_IF_CONFIG_REG_BIT_SKU_MRC            (0x00000400)
 365 #define CSR_HW_IF_CONFIG_REG_BIT_BOARD_TYPE         (0x00000800)
 366 #define CSR_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A    (0x00000000)
 367 #define CSR_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B    (0x00001000)
 368 #define CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM     (0x00200000)
 369
 370 /* interrupt flags in INTA, set by uCode or hardware (e.g. dma),
 371  * acknowledged (reset) by host writing "1" to flagged bits. */
 372 #define CSR_INT_BIT_FH_RX        (1 << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */
 373 #define CSR_INT_BIT_HW_ERR       (1 << 29) /* DMA hardware error FH_INT[31] */
 374 #define CSR_INT_BIT_DNLD         (1 << 28) /* uCode Download */
 375 #define CSR_INT_BIT_FH_TX        (1 << 27) /* Tx DMA FH_INT[1:0] */
 376 #define CSR_INT_BIT_SCD          (1 << 26) /* TXQ pointer advanced */
 377 #define CSR_INT_BIT_SW_ERR       (1 << 25) /* uCode error */
 378 #define CSR_INT_BIT_RF_KILL      (1 << 7)  /* HW RFKILL switch GP_CNTRL[27] toggled */
 379 #define CSR_INT_BIT_CT_KILL      (1 << 6)  /* Critical temp (chip too hot) rfkill */
 380 #define CSR_INT_BIT_SW_RX        (1 << 3)  /* Rx, command responses, 3945 */
 381 #define CSR_INT_BIT_WAKEUP       (1 << 1)  /* NIC controller waking up (pwr mgmt) */
 382 #define CSR_INT_BIT_ALIVE        (1 << 0)  /* uCode interrupts once it initializes */
 383
 384 #define CSR_INI_SET_MASK        (CSR_INT_BIT_FH_RX   | \
 385                                  CSR_INT_BIT_HW_ERR  | \
 386                                  CSR_INT_BIT_FH_TX   | \
 387                                  CSR_INT_BIT_SW_ERR  | \
 388                                  CSR_INT_BIT_RF_KILL | \
 389                                  CSR_INT_BIT_SW_RX   | \
 390                                  CSR_INT_BIT_WAKEUP  | \
 391                                  CSR_INT_BIT_ALIVE)
 392
 393 /* interrupt flags in FH (flow handler) (PCI busmaster DMA) */
 394 #define CSR_FH_INT_BIT_ERR       (1 << 31) /* Error */
 395 #define CSR_FH_INT_BIT_HI_PRIOR  (1 << 30) /* High priority Rx, bypass coalescing */
 396 #define CSR_FH_INT_BIT_RX_CHNL2  (1 << 18) /* Rx channel 2 (3945 only) */
 397 #define CSR_FH_INT_BIT_RX_CHNL1  (1 << 17) /* Rx channel 1 */
 398 #define CSR_FH_INT_BIT_RX_CHNL0  (1 << 16) /* Rx channel 0 */
 399 #define CSR_FH_INT_BIT_TX_CHNL6  (1 << 6)  /* Tx channel 6 (3945 only) */
 400 #define CSR_FH_INT_BIT_TX_CHNL1  (1 << 1)  /* Tx channel 1 */
 401 #define CSR_FH_INT_BIT_TX_CHNL0  (1 << 0)  /* Tx channel 0 */
 402
 403 #define CSR_FH_INT_RX_MASK      (CSR_FH_INT_BIT_HI_PRIOR | \
 404                                  CSR_FH_INT_BIT_RX_CHNL2 | \
 405                                  CSR_FH_INT_BIT_RX_CHNL1 | \
 406                                  CSR_FH_INT_BIT_RX_CHNL0)
 407
 408 #define CSR_FH_INT_TX_MASK      (CSR_FH_INT_BIT_TX_CHNL6 | \
 409                                  CSR_FH_INT_BIT_TX_CHNL1 | \
 410                                  CSR_FH_INT_BIT_TX_CHNL0)
 411
 412
 413 /* RESET */
 414 #define CSR_RESET_REG_FLAG_NEVO_RESET                (0x00000001)
 415 #define CSR_RESET_REG_FLAG_FORCE_NMI                 (0x00000002)
 416 #define CSR_RESET_REG_FLAG_SW_RESET                  (0x00000080)
 417 #define CSR_RESET_REG_FLAG_MASTER_DISABLED           (0x00000100)
 418 #define CSR_RESET_REG_FLAG_STOP_MASTER               (0x00000200)
 419
 420 /* GP (general purpose) CONTROL */
 421 #define CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY        (0x00000001)
 422 #define CSR_GP_CNTRL_REG_FLAG_INIT_DONE              (0x00000004)
 423 #define CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ         (0x00000008)
 424 #define CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP         (0x00000010)
 425
 426 #define CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN           (0x00000001)
 427
 428 #define CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE         (0x07000000)
 429 #define CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE         (0x04000000)
 430 #define CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW          (0x08000000)
 431
 432
 433 /* EEPROM REG */
 434 #define CSR_EEPROM_REG_READ_VALID_MSK   (0x00000001)
 435 #define CSR_EEPROM_REG_BIT_CMD          (0x00000002)
 436
 437 /* EEPROM GP */
 438 #define CSR_EEPROM_GP_VALID_MSK         (0x00000006)
 439 #define CSR_EEPROM_GP_BAD_SIGNATURE     (0x00000000)
 440 #define CSR_EEPROM_GP_IF_OWNER_MSK      (0x00000180)
 441
 442 /* UCODE DRV GP */
 443 #define CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP             (0x00000001)
 444 #define CSR_UCODE_SW_BIT_RFKILL                     (0x00000002)
 445 #define CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED           (0x00000004)
 446 #define CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT      (0x00000008)
 447
 448 /* GPIO */
 449 #define CSR_GPIO_IN_BIT_AUX_POWER                   (0x00000200)
 450 #define CSR_GPIO_IN_VAL_VAUX_PWR_SRC                (0x00000000)
 451 #define CSR_GPIO_IN_VAL_VMAIN_PWR_SRC           CSR_GPIO_IN_BIT_AUX_POWER
 452
 453 /* GI Chicken Bits */
 454 #define CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX  (0x00800000)
 455 #define CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER  (0x20000000)
 456
 457 /* CSR_ANA_PLL_CFG */
 458 #define CSR_ANA_PLL_CFG_SH              (0x00880300)
 459
 460 /*=== HBUS (Host-side Bus) ===*/
 461 #define HBUS_BASE       (0x400)
 462
 463 /*
 464  * Registers for accessing device's internal SRAM memory (e.g. SCD SRAM
 465  * structures, error log, event log, verifying uCode load).
 466  * First write to address register, then read from or write to data register
 467  * to complete the job.  Once the address register is set up, accesses to
 468  * data registers auto-increment the address by one dword.
 469  * Bit usage for address registers (read or write):
 470  *  0-31:  memory address within device
 471  */
 472 #define HBUS_TARG_MEM_RADDR     (HBUS_BASE+0x00c)
 473 #define HBUS_TARG_MEM_WADDR     (HBUS_BASE+0x010)
 474 #define HBUS_TARG_MEM_WDAT      (HBUS_BASE+0x018)
 475 #define HBUS_TARG_MEM_RDAT      (HBUS_BASE+0x01c)
 476
 477 /*
 478  * Registers for accessing device's internal peripheral registers
 479  * (e.g. SCD, BSM, etc.).  First write to address register,
 480  * then read from or write to data register to complete the job.
 481  * Bit usage for address registers (read or write):
 482  *  0-15:  register address (offset) within device
 483  * 24-25:  (# bytes - 1) to read or write (e.g. 3 for dword)
 484  */
 485 #define HBUS_TARG_PRPH_WADDR    (HBUS_BASE+0x044)
 486 #define HBUS_TARG_PRPH_RADDR    (HBUS_BASE+0x048)
 487 #define HBUS_TARG_PRPH_WDAT     (HBUS_BASE+0x04c)
 488 #define HBUS_TARG_PRPH_RDAT     (HBUS_BASE+0x050)
 489
 490 /*
 491  * Per-Tx-queue write pointer (index, really!) (3945 and 4965).
 492  * Indicates index to next TFD that driver will fill (1 past latest filled).
 493  * Bit usage:
 494  *  0-7:  queue write index
 495  * 11-8:  queue selector
 496  */
 497 #define HBUS_TARG_WRPTR         (HBUS_BASE+0x060)
 498
 499 /* SCD (3945 Tx Frame Scheduler) */
 500 #define SCD_BASE                        (CSR_BASE + 0x2E00)
 501
 502 #define SCD_MODE_REG                    (SCD_BASE + 0x000)
 503 #define SCD_ARASTAT_REG                 (SCD_BASE + 0x004)
 504 #define SCD_TXFACT_REG                  (SCD_BASE + 0x010)
 505 #define SCD_TXF4MF_REG                  (SCD_BASE + 0x014)
 506 #define SCD_TXF5MF_REG                  (SCD_BASE + 0x020)
 507 #define SCD_SBYP_MODE_1_REG             (SCD_BASE + 0x02C)
 508 #define SCD_SBYP_MODE_2_REG             (SCD_BASE + 0x030)
 509
 510 /*=== FH (data Flow Handler) ===*/
 511 #define FH_BASE     (0x800)
 512
 513 #define FH_CBCC_TABLE           (FH_BASE+0x140)
 514 #define FH_TFDB_TABLE           (FH_BASE+0x180)
 515 #define FH_RCSR_TABLE           (FH_BASE+0x400)
 516 #define FH_RSSR_TABLE           (FH_BASE+0x4c0)
 517 #define FH_TCSR_TABLE           (FH_BASE+0x500)
 518 #define FH_TSSR_TABLE           (FH_BASE+0x680)
 519
 520 /* TFDB (Transmit Frame Buffer Descriptor) */
 521 #define FH_TFDB(_channel, buf) \
 522         (FH_TFDB_TABLE+((_channel)*2+(buf))*0x28)
 523 #define ALM_FH_TFDB_CHNL_BUF_CTRL_REG(_channel) \
 524         (FH_TFDB_TABLE + 0x50 * _channel)
 525 /* CBCC _channel is [0,2] */
 526 #define FH_CBCC(_channel)           (FH_CBCC_TABLE+(_channel)*0x8)
 527 #define FH_CBCC_CTRL(_channel)      (FH_CBCC(_channel)+0x00)
 528 #define FH_CBCC_BASE(_channel)      (FH_CBCC(_channel)+0x04)
 529
 530 /* RCSR _channel is [0,2] */
 531 #define FH_RCSR(_channel)           (FH_RCSR_TABLE+(_channel)*0x40)
 532 #define FH_RCSR_CONFIG(_channel)    (FH_RCSR(_channel)+0x00)
 533 #define FH_RCSR_RBD_BASE(_channel)  (FH_RCSR(_channel)+0x04)
 534 #define FH_RCSR_WPTR(_channel)      (FH_RCSR(_channel)+0x20)
 535 #define FH_RCSR_RPTR_ADDR(_channel) (FH_RCSR(_channel)+0x24)
 536
 537 #define FH_RSCSR_CHNL0_WPTR        (FH_RCSR_WPTR(0))
 538
 539 /* RSSR */
 540 #define FH_RSSR_CTRL            (FH_RSSR_TABLE+0x000)
 541 #define FH_RSSR_STATUS          (FH_RSSR_TABLE+0x004)
 542 /* TCSR */
 543 #define FH_TCSR(_channel)           (FH_TCSR_TABLE+(_channel)*0x20)
 544 #define FH_TCSR_CONFIG(_channel)    (FH_TCSR(_channel)+0x00)
 545 #define FH_TCSR_CREDIT(_channel)    (FH_TCSR(_channel)+0x04)
 546 #define FH_TCSR_BUFF_STTS(_channel) (FH_TCSR(_channel)+0x08)
 547 /* TSSR */
 548 #define FH_TSSR_CBB_BASE        (FH_TSSR_TABLE+0x000)
 549 #define FH_TSSR_MSG_CONFIG      (FH_TSSR_TABLE+0x008)
 550 #define FH_TSSR_TX_STATUS       (FH_TSSR_TABLE+0x010)
 551
 552
 553 /* DBM */
 554
 555 #define ALM_FH_SRVC_CHNL                            (6)
 556
 557 #define ALM_FH_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE     (20)
 558 #define ALM_FH_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH      (4)
 559
 560 #define ALM_FH_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN    (0x08000000)
 561
 562 #define ALM_FH_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE        (0x80000000)
 563
 564 #define ALM_FH_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE           (0x20000000)
 565
 566 #define ALM_FH_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128         (0x01000000)
 567
 568 #define ALM_FH_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST         (0x00001000)
 569
 570 #define ALM_FH_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH               (0x00000000)
 571
 572 #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF              (0x00000000)
 573 #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRIVER           (0x00000001)
 574
 575 #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE_VAL    (0x00000000)
 576 #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL     (0x00000008)
 577
 578 #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD           (0x00200000)
 579
 580 #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT            (0x00000000)
 581
 582 #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE            (0x00000000)
 583 #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE           (0x80000000)
 584
 585 #define ALM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID          (0x00004000)
 586
 587 #define ALM_FH_TCSR_CHNL_TX_BUF_STS_REG_BIT_TFDB_WPTR           (0x00000001)
 588
 589 #define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON      (0xFF000000)
 590 #define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON      (0x00FF0000)
 591
 592 #define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B    (0x00000400)
 593
 594 #define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON       (0x00000100)
 595 #define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON       (0x00000080)
 596
 597 #define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH     (0x00000020)
 598 #define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH           (0x00000005)
 599
 600 #define ALM_TB_MAX_BYTES_COUNT      (0xFFF0)
 601
 602 #define ALM_FH_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_channel) \
 603         ((1LU << _channel) << 24)
 604 #define ALM_FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_channel) \
 605         ((1LU << _channel) << 16)
 606
 607 #define ALM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_channel) \
 608         (ALM_FH_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_channel) | \
 609          ALM_FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_channel))
 610 #define PCI_CFG_REV_ID_BIT_BASIC_SKU                (0x40)      /* bit 6    */
 611 #define PCI_CFG_REV_ID_BIT_RTP                      (0x80)      /* bit 7    */
 612
 613 #define TFD_QUEUE_MIN           0
 614 #define TFD_QUEUE_MAX           6
 615 #define TFD_QUEUE_SIZE_MAX      (256)
 616
 617 #define IWL_NUM_SCAN_RATES         (2)
 618
 619 #define IWL_DEFAULT_TX_RETRY  15
 620
 621 /*********************************************/
 622
 623 #define RFD_SIZE                              4
 624 #define NUM_TFD_CHUNKS                        4
 625
 626 #define RX_QUEUE_SIZE                         256
 627 #define RX_QUEUE_MASK                         255
 628 #define RX_QUEUE_SIZE_LOG                     8
 629
 630 #define U32_PAD(n)              ((4-(n))&0x3)
 631
 632 #define TFD_CTL_COUNT_SET(n)       (n << 24)
 633 #define TFD_CTL_COUNT_GET(ctl)     ((ctl >> 24) & 7)
 634 #define TFD_CTL_PAD_SET(n)         (n << 28)
 635 #define TFD_CTL_PAD_GET(ctl)       (ctl >> 28)
 636
 637 #define TFD_TX_CMD_SLOTS 256
 638 #define TFD_CMD_SLOTS 32
 639
 640 #define TFD_MAX_PAYLOAD_SIZE (sizeof(struct iwl3945_cmd) - \
 641                               sizeof(struct iwl3945_cmd_meta))
 642
 643 /*
 644  * RX related structures and functions
 645  */
 646 #define RX_FREE_BUFFERS 64
 647 #define RX_LOW_WATERMARK 8
 648
 649 /* Sizes and addresses for instruction and data memory (SRAM) in
 650  * 3945's embedded processor.  Driver access is via HBUS_TARG_MEM_* regs. */
 651 #define RTC_INST_LOWER_BOUND                    (0x000000)
 652 #define ALM_RTC_INST_UPPER_BOUND                (0x014000)
 653
 654 #define RTC_DATA_LOWER_BOUND                    (0x800000)
 655 #define ALM_RTC_DATA_UPPER_BOUND                (0x808000)
 656
 657 #define ALM_RTC_INST_SIZE (ALM_RTC_INST_UPPER_BOUND - RTC_INST_LOWER_BOUND)
 658 #define ALM_RTC_DATA_SIZE (ALM_RTC_DATA_UPPER_BOUND - RTC_DATA_LOWER_BOUND)
 659
 660 #define IWL_MAX_INST_SIZE ALM_RTC_INST_SIZE
 661 #define IWL_MAX_DATA_SIZE ALM_RTC_DATA_SIZE
 662
 663 /* Size of uCode instruction memory in bootstrap state machine */
 664 #define IWL_MAX_BSM_SIZE ALM_RTC_INST_SIZE
 665
 666 #define IWL_MAX_NUM_QUEUES      8
 667
 668 static inline int iwl3945_hw_valid_rtc_data_addr(u32 addr)
 669 {
 670         return (addr >= RTC_DATA_LOWER_BOUND) &&
 671                (addr < ALM_RTC_DATA_UPPER_BOUND);
 672 }
 673
 674 /* Base physical address of iwl3945_shared is provided to FH_TSSR_CBB_BASE
 675  * and &iwl3945_shared.rx_read_ptr[0] is provided to FH_RCSR_RPTR_ADDR(0) */
 676 struct iwl3945_shared {
 677         __le32 tx_base_ptr[8];
 678         __le32 rx_read_ptr[3];
 679 } __attribute__ ((packed));
 680
 681 struct iwl3945_tfd_frame_data {
 682         __le32 addr;
 683         __le32 len;
 684 } __attribute__ ((packed));
 685
 686 struct iwl3945_tfd_frame {
 687         __le32 control_flags;
 688         struct iwl3945_tfd_frame_data pa[4];
 689         u8 reserved[28];
 690 } __attribute__ ((packed));
 691
 692 static inline u8 iwl3945_hw_get_rate(__le16 rate_n_flags)
 693 {
 694         return le16_to_cpu(rate_n_flags) & 0xFF;
 695 }
 696
 697 static inline u16 iwl3945_hw_get_rate_n_flags(__le16 rate_n_flags)
 698 {
 699         return le16_to_cpu(rate_n_flags);
 700 }
 701
 702 static inline __le16 iwl3945_hw_set_rate_n_flags(u8 rate, u16 flags)
 703 {
 704         return cpu_to_le16((u16)rate|flags);
 705 }
 706 #endif