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Merge git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
[wrt350n-kernel.git] / drivers / net / wireless / rtl8180_dev.c
blob0f6b2975d652f467fe431a2bdbeb779acd7cf7a0
1
2 /*
3 * Linux device driver for RTL8180 / RTL8185
4 *
5 * Copyright 2007 Michael Wu <flamingice@sourmilk.net>
6 * Copyright 2007 Andrea Merello <andreamrl@tiscali.it>
7 *
8 * Based on the r8180 driver, which is:
9 * Copyright 2004-2005 Andrea Merello <andreamrl@tiscali.it>, et al.
10 *
11 * Thanks to Realtek for their support!
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
18 #include <linux/init.h>
19 #include <linux/pci.h>
20 #include <linux/delay.h>
21 #include <linux/etherdevice.h>
22 #include <linux/eeprom_93cx6.h>
23 #include <net/mac80211.h>
24
25 #include "rtl8180.h"
26 #include "rtl8180_rtl8225.h"
27 #include "rtl8180_sa2400.h"
28 #include "rtl8180_max2820.h"
29 #include "rtl8180_grf5101.h"
30
31 MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
32 MODULE_AUTHOR("Andrea Merello <andreamrl@tiscali.it>");
33 MODULE_DESCRIPTION("RTL8180 / RTL8185 PCI wireless driver");
34 MODULE_LICENSE("GPL");
35
36 static struct pci_device_id rtl8180_table[] __devinitdata = {
37 /* rtl8185 */
38 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8185) },
39 { PCI_DEVICE(PCI_VENDOR_ID_BELKIN, 0x700f) },
40 { PCI_DEVICE(PCI_VENDOR_ID_BELKIN, 0x701f) },
41
42 /* rtl8180 */
43 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8180) },
44 { PCI_DEVICE(0x1799, 0x6001) },
45 { PCI_DEVICE(0x1799, 0x6020) },
46 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x3300) },
47 { }
48 };
49
50 MODULE_DEVICE_TABLE(pci, rtl8180_table);
51
52 void rtl8180_write_phy(struct ieee80211_hw *dev, u8 addr, u32 data)
53 {
54 struct rtl8180_priv *priv = dev->priv;
55 int i = 10;
56 u32 buf;
57
58 buf = (data << 8) | addr;
59
60 rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->PHY[0], buf | 0x80);
61 while (i--) {
62 rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->PHY[0], buf);
63 if (rtl818x_ioread8(priv, &priv->map->PHY[2]) == (data & 0xFF))
64 return;
65 }
66 }
67
68 static void rtl8180_handle_rx(struct ieee80211_hw *dev)
69 {
70 struct rtl8180_priv *priv = dev->priv;
71 unsigned int count = 32;
72
73 while (count--) {
74 struct rtl8180_rx_desc *entry = &priv->rx_ring[priv->rx_idx];
75 struct sk_buff *skb = priv->rx_buf[priv->rx_idx];
76 u32 flags = le32_to_cpu(entry->flags);
77
78 if (flags & RTL8180_RX_DESC_FLAG_OWN)
79 return;
80
81 if (unlikely(flags & (RTL8180_RX_DESC_FLAG_DMA_FAIL |
82 RTL8180_RX_DESC_FLAG_FOF |
83 RTL8180_RX_DESC_FLAG_RX_ERR)))
84 goto done;
85 else {
86 u32 flags2 = le32_to_cpu(entry->flags2);
87 struct ieee80211_rx_status rx_status = {0};
88 struct sk_buff *new_skb = dev_alloc_skb(MAX_RX_SIZE);
89
90 if (unlikely(!new_skb))
91 goto done;
92
93 pci_unmap_single(priv->pdev,
94 *((dma_addr_t *)skb->cb),
95 MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
96 skb_put(skb, flags & 0xFFF);
97
98 rx_status.antenna = (flags2 >> 15) & 1;
99 /* TODO: improve signal/rssi reporting */
100 rx_status.signal = flags2 & 0xFF;
101 rx_status.ssi = (flags2 >> 8) & 0x7F;
102 rx_status.rate = (flags >> 20) & 0xF;
103 rx_status.freq = dev->conf.freq;
104 rx_status.channel = dev->conf.channel;
105 rx_status.phymode = dev->conf.phymode;
106 rx_status.mactime = le64_to_cpu(entry->tsft);
107 rx_status.flag |= RX_FLAG_TSFT;
108 if (flags & RTL8180_RX_DESC_FLAG_CRC32_ERR)
109 rx_status.flag |= RX_FLAG_FAILED_FCS_CRC;
110
111 ieee80211_rx_irqsafe(dev, skb, &rx_status);
112
113 skb = new_skb;
114 priv->rx_buf[priv->rx_idx] = skb;
115 *((dma_addr_t *) skb->cb) =
116 pci_map_single(priv->pdev, skb_tail_pointer(skb),
117 MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
118 }
119
120 done:
121 entry->rx_buf = cpu_to_le32(*((dma_addr_t *)skb->cb));
122 entry->flags = cpu_to_le32(RTL8180_RX_DESC_FLAG_OWN |
123 MAX_RX_SIZE);
124 if (priv->rx_idx == 31)
125 entry->flags |= cpu_to_le32(RTL8180_RX_DESC_FLAG_EOR);
126 priv->rx_idx = (priv->rx_idx + 1) % 32;
127 }
128 }
129
130 static void rtl8180_handle_tx(struct ieee80211_hw *dev, unsigned int prio)
131 {
132 struct rtl8180_priv *priv = dev->priv;
133 struct rtl8180_tx_ring *ring = &priv->tx_ring[prio];
134
135 while (skb_queue_len(&ring->queue)) {
136 struct rtl8180_tx_desc *entry = &ring->desc[ring->idx];
137 struct sk_buff *skb;
138 <<<<<<< HEAD:drivers/net/wireless/rtl8180_dev.c
139 struct ieee80211_tx_status status = { {0} };
140 =======
141 struct ieee80211_tx_status status;
142 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/net/wireless/rtl8180_dev.c
143 struct ieee80211_tx_control *control;
144 u32 flags = le32_to_cpu(entry->flags);
145
146 if (flags & RTL8180_TX_DESC_FLAG_OWN)
147 return;
148
149 <<<<<<< HEAD:drivers/net/wireless/rtl8180_dev.c
150 =======
151 memset(&status, 0, sizeof(status));
152
153 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/net/wireless/rtl8180_dev.c
154 ring->idx = (ring->idx + 1) % ring->entries;
155 skb = __skb_dequeue(&ring->queue);
156 pci_unmap_single(priv->pdev, le32_to_cpu(entry->tx_buf),
157 skb->len, PCI_DMA_TODEVICE);
158
159 control = *((struct ieee80211_tx_control **)skb->cb);
160 if (control)
161 memcpy(&status.control, control, sizeof(*control));
162 kfree(control);
163
164 if (!(status.control.flags & IEEE80211_TXCTL_NO_ACK)) {
165 if (flags & RTL8180_TX_DESC_FLAG_TX_OK)
166 status.flags = IEEE80211_TX_STATUS_ACK;
167 else
168 status.excessive_retries = 1;
169 }
170 status.retry_count = flags & 0xFF;
171
172 ieee80211_tx_status_irqsafe(dev, skb, &status);
173 if (ring->entries - skb_queue_len(&ring->queue) == 2)
174 ieee80211_wake_queue(dev, prio);
175 }
176 }
177
178 static irqreturn_t rtl8180_interrupt(int irq, void *dev_id)
179 {
180 struct ieee80211_hw *dev = dev_id;
181 struct rtl8180_priv *priv = dev->priv;
182 u16 reg;
183
184 spin_lock(&priv->lock);
185 reg = rtl818x_ioread16(priv, &priv->map->INT_STATUS);
186 if (unlikely(reg == 0xFFFF)) {
187 spin_unlock(&priv->lock);
188 return IRQ_HANDLED;
189 }
190
191 rtl818x_iowrite16(priv, &priv->map->INT_STATUS, reg);
192
193 if (reg & (RTL818X_INT_TXB_OK | RTL818X_INT_TXB_ERR))
194 rtl8180_handle_tx(dev, 3);
195
196 if (reg & (RTL818X_INT_TXH_OK | RTL818X_INT_TXH_ERR))
197 rtl8180_handle_tx(dev, 2);
198
199 if (reg & (RTL818X_INT_TXN_OK | RTL818X_INT_TXN_ERR))
200 rtl8180_handle_tx(dev, 1);
201
202 if (reg & (RTL818X_INT_TXL_OK | RTL818X_INT_TXL_ERR))
203 rtl8180_handle_tx(dev, 0);
204
205 if (reg & (RTL818X_INT_RX_OK | RTL818X_INT_RX_ERR))
206 rtl8180_handle_rx(dev);
207
208 spin_unlock(&priv->lock);
209
210 return IRQ_HANDLED;
211 }
212
213 static int rtl8180_tx(struct ieee80211_hw *dev, struct sk_buff *skb,
214 struct ieee80211_tx_control *control)
215 {
216 struct rtl8180_priv *priv = dev->priv;
217 struct rtl8180_tx_ring *ring;
218 struct rtl8180_tx_desc *entry;
219 unsigned long flags;
220 unsigned int idx, prio;
221 dma_addr_t mapping;
222 u32 tx_flags;
223 u16 plcp_len = 0;
224 __le16 rts_duration = 0;
225
226 prio = control->queue;
227 ring = &priv->tx_ring[prio];
228
229 mapping = pci_map_single(priv->pdev, skb->data,
230 skb->len, PCI_DMA_TODEVICE);
231
232 tx_flags = RTL8180_TX_DESC_FLAG_OWN | RTL8180_TX_DESC_FLAG_FS |
233 RTL8180_TX_DESC_FLAG_LS | (control->tx_rate << 24) |
234 (control->rts_cts_rate << 19) | skb->len;
235
236 if (priv->r8185)
237 tx_flags |= RTL8180_TX_DESC_FLAG_DMA |
238 RTL8180_TX_DESC_FLAG_NO_ENC;
239
240 if (control->flags & IEEE80211_TXCTL_USE_RTS_CTS)
241 tx_flags |= RTL8180_TX_DESC_FLAG_RTS;
242 else if (control->flags & IEEE80211_TXCTL_USE_CTS_PROTECT)
243 tx_flags |= RTL8180_TX_DESC_FLAG_CTS;
244
245 *((struct ieee80211_tx_control **) skb->cb) =
246 kmemdup(control, sizeof(*control), GFP_ATOMIC);
247
248 if (control->flags & IEEE80211_TXCTL_USE_RTS_CTS)
249 rts_duration = ieee80211_rts_duration(dev, priv->vif, skb->len,
250 control);
251
252 if (!priv->r8185) {
253 unsigned int remainder;
254
255 plcp_len = DIV_ROUND_UP(16 * (skb->len + 4),
256 (control->rate->rate * 2) / 10);
257 remainder = (16 * (skb->len + 4)) %
258 ((control->rate->rate * 2) / 10);
259 if (remainder > 0 && remainder <= 6)
260 plcp_len |= 1 << 15;
261 }
262
263 spin_lock_irqsave(&priv->lock, flags);
264 idx = (ring->idx + skb_queue_len(&ring->queue)) % ring->entries;
265 entry = &ring->desc[idx];
266
267 entry->rts_duration = rts_duration;
268 entry->plcp_len = cpu_to_le16(plcp_len);
269 entry->tx_buf = cpu_to_le32(mapping);
270 entry->frame_len = cpu_to_le32(skb->len);
271 entry->flags2 = control->alt_retry_rate != -1 ?
272 control->alt_retry_rate << 4 : 0;
273 entry->retry_limit = control->retry_limit;
274 entry->flags = cpu_to_le32(tx_flags);
275 __skb_queue_tail(&ring->queue, skb);
276 if (ring->entries - skb_queue_len(&ring->queue) < 2)
277 ieee80211_stop_queue(dev, control->queue);
278 spin_unlock_irqrestore(&priv->lock, flags);
279
280 rtl818x_iowrite8(priv, &priv->map->TX_DMA_POLLING, (1 << (prio + 4)));
281
282 return 0;
283 }
284
285 void rtl8180_set_anaparam(struct rtl8180_priv *priv, u32 anaparam)
286 {
287 u8 reg;
288
289 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
290 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
291 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
292 reg | RTL818X_CONFIG3_ANAPARAM_WRITE);
293 rtl818x_iowrite32(priv, &priv->map->ANAPARAM, anaparam);
294 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
295 reg & ~RTL818X_CONFIG3_ANAPARAM_WRITE);
296 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
297 }
298
299 static int rtl8180_init_hw(struct ieee80211_hw *dev)
300 {
301 struct rtl8180_priv *priv = dev->priv;
302 u16 reg;
303
304 rtl818x_iowrite8(priv, &priv->map->CMD, 0);
305 rtl818x_ioread8(priv, &priv->map->CMD);
306 msleep(10);
307
308 /* reset */
309 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
310 rtl818x_ioread8(priv, &priv->map->CMD);
311
312 reg = rtl818x_ioread8(priv, &priv->map->CMD);
313 reg &= (1 << 1);
314 reg |= RTL818X_CMD_RESET;
315 rtl818x_iowrite8(priv, &priv->map->CMD, RTL818X_CMD_RESET);
316 rtl818x_ioread8(priv, &priv->map->CMD);
317 msleep(200);
318
319 /* check success of reset */
320 if (rtl818x_ioread8(priv, &priv->map->CMD) & RTL818X_CMD_RESET) {
321 printk(KERN_ERR "%s: reset timeout!\n", wiphy_name(dev->wiphy));
322 return -ETIMEDOUT;
323 }
324
325 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_LOAD);
326 rtl818x_ioread8(priv, &priv->map->CMD);
327 msleep(200);
328
329 if (rtl818x_ioread8(priv, &priv->map->CONFIG3) & (1 << 3)) {
330 /* For cardbus */
331 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
332 reg |= 1 << 1;
333 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg);
334 reg = rtl818x_ioread16(priv, &priv->map->FEMR);
335 reg |= (1 << 15) | (1 << 14) | (1 << 4);
336 rtl818x_iowrite16(priv, &priv->map->FEMR, reg);
337 }
338
339 rtl818x_iowrite8(priv, &priv->map->MSR, 0);
340
341 if (!priv->r8185)
342 rtl8180_set_anaparam(priv, priv->anaparam);
343
344 rtl818x_iowrite32(priv, &priv->map->RDSAR, priv->rx_ring_dma);
345 rtl818x_iowrite32(priv, &priv->map->TBDA, priv->tx_ring[3].dma);
346 rtl818x_iowrite32(priv, &priv->map->THPDA, priv->tx_ring[2].dma);
347 rtl818x_iowrite32(priv, &priv->map->TNPDA, priv->tx_ring[1].dma);
348 rtl818x_iowrite32(priv, &priv->map->TLPDA, priv->tx_ring[0].dma);
349
350 /* TODO: necessary? specs indicate not */
351 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
352 reg = rtl818x_ioread8(priv, &priv->map->CONFIG2);
353 rtl818x_iowrite8(priv, &priv->map->CONFIG2, reg & ~(1 << 3));
354 if (priv->r8185) {
355 reg = rtl818x_ioread8(priv, &priv->map->CONFIG2);
356 rtl818x_iowrite8(priv, &priv->map->CONFIG2, reg | (1 << 4));
357 }
358 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
359
360 /* TODO: set CONFIG5 for calibrating AGC on rtl8180 + philips radio? */
361
362 /* TODO: turn off hw wep on rtl8180 */
363
364 rtl818x_iowrite32(priv, &priv->map->INT_TIMEOUT, 0);
365
366 if (priv->r8185) {
367 rtl818x_iowrite8(priv, &priv->map->WPA_CONF, 0);
368 rtl818x_iowrite8(priv, &priv->map->RATE_FALLBACK, 0x81);
369 rtl818x_iowrite8(priv, &priv->map->RESP_RATE, (8 << 4) | 0);
370
371 rtl818x_iowrite16(priv, &priv->map->BRSR, 0x01F3);
372
373 /* TODO: set ClkRun enable? necessary? */
374 reg = rtl818x_ioread8(priv, &priv->map->GP_ENABLE);
375 rtl818x_iowrite8(priv, &priv->map->GP_ENABLE, reg & ~(1 << 6));
376 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
377 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
378 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg | (1 << 2));
379 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
380 } else {
381 rtl818x_iowrite16(priv, &priv->map->BRSR, 0x1);
382 rtl818x_iowrite8(priv, &priv->map->SECURITY, 0);
383
384 rtl818x_iowrite8(priv, &priv->map->PHY_DELAY, 0x6);
385 rtl818x_iowrite8(priv, &priv->map->CARRIER_SENSE_COUNTER, 0x4C);
386 }
387
388 priv->rf->init(dev);
389 if (priv->r8185)
390 rtl818x_iowrite16(priv, &priv->map->BRSR, 0x01F3);
391 return 0;
392 }
393
394 static int rtl8180_init_rx_ring(struct ieee80211_hw *dev)
395 {
396 struct rtl8180_priv *priv = dev->priv;
397 struct rtl8180_rx_desc *entry;
398 int i;
399
400 priv->rx_ring = pci_alloc_consistent(priv->pdev,
401 sizeof(*priv->rx_ring) * 32,
402 &priv->rx_ring_dma);
403
404 if (!priv->rx_ring || (unsigned long)priv->rx_ring & 0xFF) {
405 printk(KERN_ERR "%s: Cannot allocate RX ring\n",
406 wiphy_name(dev->wiphy));
407 return -ENOMEM;
408 }
409
410 memset(priv->rx_ring, 0, sizeof(*priv->rx_ring) * 32);
411 priv->rx_idx = 0;
412
413 for (i = 0; i < 32; i++) {
414 struct sk_buff *skb = dev_alloc_skb(MAX_RX_SIZE);
415 dma_addr_t *mapping;
416 entry = &priv->rx_ring[i];
417 if (!skb)
418 return 0;
419
420 priv->rx_buf[i] = skb;
421 mapping = (dma_addr_t *)skb->cb;
422 *mapping = pci_map_single(priv->pdev, skb_tail_pointer(skb),
423 MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
424 entry->rx_buf = cpu_to_le32(*mapping);
425 entry->flags = cpu_to_le32(RTL8180_RX_DESC_FLAG_OWN |
426 MAX_RX_SIZE);
427 }
428 entry->flags |= cpu_to_le32(RTL8180_RX_DESC_FLAG_EOR);
429 return 0;
430 }
431
432 static void rtl8180_free_rx_ring(struct ieee80211_hw *dev)
433 {
434 struct rtl8180_priv *priv = dev->priv;
435 int i;
436
437 for (i = 0; i < 32; i++) {
438 struct sk_buff *skb = priv->rx_buf[i];
439 if (!skb)
440 continue;
441
442 pci_unmap_single(priv->pdev,
443 *((dma_addr_t *)skb->cb),
444 MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
445 kfree_skb(skb);
446 }
447
448 pci_free_consistent(priv->pdev, sizeof(*priv->rx_ring) * 32,
449 priv->rx_ring, priv->rx_ring_dma);
450 priv->rx_ring = NULL;
451 }
452
453 static int rtl8180_init_tx_ring(struct ieee80211_hw *dev,
454 unsigned int prio, unsigned int entries)
455 {
456 struct rtl8180_priv *priv = dev->priv;
457 struct rtl8180_tx_desc *ring;
458 dma_addr_t dma;
459 int i;
460
461 ring = pci_alloc_consistent(priv->pdev, sizeof(*ring) * entries, &dma);
462 if (!ring || (unsigned long)ring & 0xFF) {
463 printk(KERN_ERR "%s: Cannot allocate TX ring (prio = %d)\n",
464 wiphy_name(dev->wiphy), prio);
465 return -ENOMEM;
466 }
467
468 memset(ring, 0, sizeof(*ring)*entries);
469 priv->tx_ring[prio].desc = ring;
470 priv->tx_ring[prio].dma = dma;
471 priv->tx_ring[prio].idx = 0;
472 priv->tx_ring[prio].entries = entries;
473 skb_queue_head_init(&priv->tx_ring[prio].queue);
474
475 for (i = 0; i < entries; i++)
476 ring[i].next_tx_desc =
477 cpu_to_le32((u32)dma + ((i + 1) % entries) * sizeof(*ring));
478
479 return 0;
480 }
481
482 static void rtl8180_free_tx_ring(struct ieee80211_hw *dev, unsigned int prio)
483 {
484 struct rtl8180_priv *priv = dev->priv;
485 struct rtl8180_tx_ring *ring = &priv->tx_ring[prio];
486
487 while (skb_queue_len(&ring->queue)) {
488 struct rtl8180_tx_desc *entry = &ring->desc[ring->idx];
489 struct sk_buff *skb = __skb_dequeue(&ring->queue);
490
491 pci_unmap_single(priv->pdev, le32_to_cpu(entry->tx_buf),
492 skb->len, PCI_DMA_TODEVICE);
493 kfree(*((struct ieee80211_tx_control **) skb->cb));
494 kfree_skb(skb);
495 ring->idx = (ring->idx + 1) % ring->entries;
496 }
497
498 pci_free_consistent(priv->pdev, sizeof(*ring->desc)*ring->entries,
499 ring->desc, ring->dma);
500 ring->desc = NULL;
501 }
502
503 static int rtl8180_start(struct ieee80211_hw *dev)
504 {
505 struct rtl8180_priv *priv = dev->priv;
506 int ret, i;
507 u32 reg;
508
509 ret = rtl8180_init_rx_ring(dev);
510 if (ret)
511 return ret;
512
513 for (i = 0; i < 4; i++)
514 if ((ret = rtl8180_init_tx_ring(dev, i, 16)))
515 goto err_free_rings;
516
517 ret = rtl8180_init_hw(dev);
518 if (ret)
519 goto err_free_rings;
520
521 rtl818x_iowrite32(priv, &priv->map->RDSAR, priv->rx_ring_dma);
522 rtl818x_iowrite32(priv, &priv->map->TBDA, priv->tx_ring[3].dma);
523 rtl818x_iowrite32(priv, &priv->map->THPDA, priv->tx_ring[2].dma);
524 rtl818x_iowrite32(priv, &priv->map->TNPDA, priv->tx_ring[1].dma);
525 rtl818x_iowrite32(priv, &priv->map->TLPDA, priv->tx_ring[0].dma);
526
527 ret = request_irq(priv->pdev->irq, &rtl8180_interrupt,
528 IRQF_SHARED, KBUILD_MODNAME, dev);
529 if (ret) {
530 printk(KERN_ERR "%s: failed to register IRQ handler\n",
531 wiphy_name(dev->wiphy));
532 goto err_free_rings;
533 }
534
535 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0xFFFF);
536
537 rtl818x_iowrite32(priv, &priv->map->MAR[0], ~0);
538 rtl818x_iowrite32(priv, &priv->map->MAR[1], ~0);
539
540 reg = RTL818X_RX_CONF_ONLYERLPKT |
541 RTL818X_RX_CONF_RX_AUTORESETPHY |
542 RTL818X_RX_CONF_MGMT |
543 RTL818X_RX_CONF_DATA |
544 (7 << 8 /* MAX RX DMA */) |
545 RTL818X_RX_CONF_BROADCAST |
546 RTL818X_RX_CONF_NICMAC;
547
548 if (priv->r8185)
549 reg |= RTL818X_RX_CONF_CSDM1 | RTL818X_RX_CONF_CSDM2;
550 else {
551 reg |= (priv->rfparam & RF_PARAM_CARRIERSENSE1)
552 ? RTL818X_RX_CONF_CSDM1 : 0;
553 reg |= (priv->rfparam & RF_PARAM_CARRIERSENSE2)
554 ? RTL818X_RX_CONF_CSDM2 : 0;
555 }
556
557 priv->rx_conf = reg;
558 rtl818x_iowrite32(priv, &priv->map->RX_CONF, reg);
559
560 if (priv->r8185) {
561 reg = rtl818x_ioread8(priv, &priv->map->CW_CONF);
562 reg &= ~RTL818X_CW_CONF_PERPACKET_CW_SHIFT;
563 reg |= RTL818X_CW_CONF_PERPACKET_RETRY_SHIFT;
564 rtl818x_iowrite8(priv, &priv->map->CW_CONF, reg);
565
566 reg = rtl818x_ioread8(priv, &priv->map->TX_AGC_CTL);
567 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_GAIN_SHIFT;
568 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT;
569 reg |= RTL818X_TX_AGC_CTL_FEEDBACK_ANT;
570 rtl818x_iowrite8(priv, &priv->map->TX_AGC_CTL, reg);
571
572 /* disable early TX */
573 rtl818x_iowrite8(priv, (u8 __iomem *)priv->map + 0xec, 0x3f);
574 }
575
576 reg = rtl818x_ioread32(priv, &priv->map->TX_CONF);
577 reg |= (6 << 21 /* MAX TX DMA */) |
578 RTL818X_TX_CONF_NO_ICV;
579
580 if (priv->r8185)
581 reg &= ~RTL818X_TX_CONF_PROBE_DTS;
582 else
583 reg &= ~RTL818X_TX_CONF_HW_SEQNUM;
584
585 /* different meaning, same value on both rtl8185 and rtl8180 */
586 reg &= ~RTL818X_TX_CONF_SAT_HWPLCP;
587
588 rtl818x_iowrite32(priv, &priv->map->TX_CONF, reg);
589
590 reg = rtl818x_ioread8(priv, &priv->map->CMD);
591 reg |= RTL818X_CMD_RX_ENABLE;
592 reg |= RTL818X_CMD_TX_ENABLE;
593 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
594
595 priv->mode = IEEE80211_IF_TYPE_MNTR;
596 return 0;
597
598 err_free_rings:
599 rtl8180_free_rx_ring(dev);
600 for (i = 0; i < 4; i++)
601 if (priv->tx_ring[i].desc)
602 rtl8180_free_tx_ring(dev, i);
603
604 return ret;
605 }
606
607 static void rtl8180_stop(struct ieee80211_hw *dev)
608 {
609 struct rtl8180_priv *priv = dev->priv;
610 u8 reg;
611 int i;
612
613 priv->mode = IEEE80211_IF_TYPE_INVALID;
614
615 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
616
617 reg = rtl818x_ioread8(priv, &priv->map->CMD);
618 reg &= ~RTL818X_CMD_TX_ENABLE;
619 reg &= ~RTL818X_CMD_RX_ENABLE;
620 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
621
622 priv->rf->stop(dev);
623
624 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
625 reg = rtl818x_ioread8(priv, &priv->map->CONFIG4);
626 rtl818x_iowrite8(priv, &priv->map->CONFIG4, reg | RTL818X_CONFIG4_VCOOFF);
627 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
628
629 free_irq(priv->pdev->irq, dev);
630
631 rtl8180_free_rx_ring(dev);
632 for (i = 0; i < 4; i++)
633 rtl8180_free_tx_ring(dev, i);
634 }
635
636 static int rtl8180_add_interface(struct ieee80211_hw *dev,
637 struct ieee80211_if_init_conf *conf)
638 {
639 struct rtl8180_priv *priv = dev->priv;
640
641 if (priv->mode != IEEE80211_IF_TYPE_MNTR)
642 return -EOPNOTSUPP;
643
644 switch (conf->type) {
645 case IEEE80211_IF_TYPE_STA:
646 priv->mode = conf->type;
647 break;
648 default:
649 return -EOPNOTSUPP;
650 }
651
652 priv->vif = conf->vif;
653
654 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
655 rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->MAC[0],
656 cpu_to_le32(*(u32 *)conf->mac_addr));
657 rtl818x_iowrite16(priv, (__le16 __iomem *)&priv->map->MAC[4],
658 cpu_to_le16(*(u16 *)(conf->mac_addr + 4)));
659 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
660
661 return 0;
662 }
663
664 static void rtl8180_remove_interface(struct ieee80211_hw *dev,
665 struct ieee80211_if_init_conf *conf)
666 {
667 struct rtl8180_priv *priv = dev->priv;
668 priv->mode = IEEE80211_IF_TYPE_MNTR;
669 priv->vif = NULL;
670 }
671
672 static int rtl8180_config(struct ieee80211_hw *dev, struct ieee80211_conf *conf)
673 {
674 struct rtl8180_priv *priv = dev->priv;
675
676 priv->rf->set_chan(dev, conf);
677
678 return 0;
679 }
680
681 static int rtl8180_config_interface(struct ieee80211_hw *dev,
682 struct ieee80211_vif *vif,
683 struct ieee80211_if_conf *conf)
684 {
685 struct rtl8180_priv *priv = dev->priv;
686 int i;
687
688 for (i = 0; i < ETH_ALEN; i++)
689 rtl818x_iowrite8(priv, &priv->map->BSSID[i], conf->bssid[i]);
690
691 if (is_valid_ether_addr(conf->bssid))
692 rtl818x_iowrite8(priv, &priv->map->MSR, RTL818X_MSR_INFRA);
693 else
694 rtl818x_iowrite8(priv, &priv->map->MSR, RTL818X_MSR_NO_LINK);
695
696 return 0;
697 }
698
699 static void rtl8180_configure_filter(struct ieee80211_hw *dev,
700 unsigned int changed_flags,
701 unsigned int *total_flags,
702 int mc_count, struct dev_addr_list *mclist)
703 {
704 struct rtl8180_priv *priv = dev->priv;
705
706 if (changed_flags & FIF_FCSFAIL)
707 priv->rx_conf ^= RTL818X_RX_CONF_FCS;
708 if (changed_flags & FIF_CONTROL)
709 priv->rx_conf ^= RTL818X_RX_CONF_CTRL;
710 if (changed_flags & FIF_OTHER_BSS)
711 priv->rx_conf ^= RTL818X_RX_CONF_MONITOR;
712 if (*total_flags & FIF_ALLMULTI || mc_count > 0)
713 priv->rx_conf |= RTL818X_RX_CONF_MULTICAST;
714 else
715 priv->rx_conf &= ~RTL818X_RX_CONF_MULTICAST;
716
717 *total_flags = 0;
718
719 if (priv->rx_conf & RTL818X_RX_CONF_FCS)
720 *total_flags |= FIF_FCSFAIL;
721 if (priv->rx_conf & RTL818X_RX_CONF_CTRL)
722 *total_flags |= FIF_CONTROL;
723 if (priv->rx_conf & RTL818X_RX_CONF_MONITOR)
724 *total_flags |= FIF_OTHER_BSS;
725 if (priv->rx_conf & RTL818X_RX_CONF_MULTICAST)
726 *total_flags |= FIF_ALLMULTI;
727
728 rtl818x_iowrite32(priv, &priv->map->RX_CONF, priv->rx_conf);
729 }
730
731 static const struct ieee80211_ops rtl8180_ops = {
732 .tx = rtl8180_tx,
733 .start = rtl8180_start,
734 .stop = rtl8180_stop,
735 .add_interface = rtl8180_add_interface,
736 .remove_interface = rtl8180_remove_interface,
737 .config = rtl8180_config,
738 .config_interface = rtl8180_config_interface,
739 .configure_filter = rtl8180_configure_filter,
740 };
741
742 static void rtl8180_eeprom_register_read(struct eeprom_93cx6 *eeprom)
743 {
744 struct ieee80211_hw *dev = eeprom->data;
745 struct rtl8180_priv *priv = dev->priv;
746 u8 reg = rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
747
748 eeprom->reg_data_in = reg & RTL818X_EEPROM_CMD_WRITE;
749 eeprom->reg_data_out = reg & RTL818X_EEPROM_CMD_READ;
750 eeprom->reg_data_clock = reg & RTL818X_EEPROM_CMD_CK;
751 eeprom->reg_chip_select = reg & RTL818X_EEPROM_CMD_CS;
752 }
753
754 static void rtl8180_eeprom_register_write(struct eeprom_93cx6 *eeprom)
755 {
756 struct ieee80211_hw *dev = eeprom->data;
757 struct rtl8180_priv *priv = dev->priv;
758 u8 reg = 2 << 6;
759
760 if (eeprom->reg_data_in)
761 reg |= RTL818X_EEPROM_CMD_WRITE;
762 if (eeprom->reg_data_out)
763 reg |= RTL818X_EEPROM_CMD_READ;
764 if (eeprom->reg_data_clock)
765 reg |= RTL818X_EEPROM_CMD_CK;
766 if (eeprom->reg_chip_select)
767 reg |= RTL818X_EEPROM_CMD_CS;
768
769 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, reg);
770 rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
771 udelay(10);
772 }
773
774 static int __devinit rtl8180_probe(struct pci_dev *pdev,
775 const struct pci_device_id *id)
776 {
777 struct ieee80211_hw *dev;
778 struct rtl8180_priv *priv;
779 unsigned long mem_addr, mem_len;
780 unsigned int io_addr, io_len;
781 int err, i;
782 struct eeprom_93cx6 eeprom;
783 const char *chip_name, *rf_name = NULL;
784 u32 reg;
785 u16 eeprom_val;
786 DECLARE_MAC_BUF(mac);
787
788 err = pci_enable_device(pdev);
789 if (err) {
790 printk(KERN_ERR "%s (rtl8180): Cannot enable new PCI device\n",
791 pci_name(pdev));
792 return err;
793 }
794
795 err = pci_request_regions(pdev, KBUILD_MODNAME);
796 if (err) {
797 printk(KERN_ERR "%s (rtl8180): Cannot obtain PCI resources\n",
798 pci_name(pdev));
799 return err;
800 }
801
802 io_addr = pci_resource_start(pdev, 0);
803 io_len = pci_resource_len(pdev, 0);
804 mem_addr = pci_resource_start(pdev, 1);
805 mem_len = pci_resource_len(pdev, 1);
806
807 if (mem_len < sizeof(struct rtl818x_csr) ||
808 io_len < sizeof(struct rtl818x_csr)) {
809 printk(KERN_ERR "%s (rtl8180): Too short PCI resources\n",
810 pci_name(pdev));
811 err = -ENOMEM;
812 goto err_free_reg;
813 }
814
815 if ((err = pci_set_dma_mask(pdev, 0xFFFFFF00ULL)) ||
816 (err = pci_set_consistent_dma_mask(pdev, 0xFFFFFF00ULL))) {
817 printk(KERN_ERR "%s (rtl8180): No suitable DMA available\n",
818 pci_name(pdev));
819 goto err_free_reg;
820 }
821
822 pci_set_master(pdev);
823
824 dev = ieee80211_alloc_hw(sizeof(*priv), &rtl8180_ops);
825 if (!dev) {
826 printk(KERN_ERR "%s (rtl8180): ieee80211 alloc failed\n",
827 pci_name(pdev));
828 err = -ENOMEM;
829 goto err_free_reg;
830 }
831
832 priv = dev->priv;
833 priv->pdev = pdev;
834
835 SET_IEEE80211_DEV(dev, &pdev->dev);
836 pci_set_drvdata(pdev, dev);
837
838 priv->map = pci_iomap(pdev, 1, mem_len);
839 if (!priv->map)
840 priv->map = pci_iomap(pdev, 0, io_len);
841
842 if (!priv->map) {
843 printk(KERN_ERR "%s (rtl8180): Cannot map device memory\n",
844 pci_name(pdev));
845 goto err_free_dev;
846 }
847
848 memcpy(priv->channels, rtl818x_channels, sizeof(rtl818x_channels));
849 memcpy(priv->rates, rtl818x_rates, sizeof(rtl818x_rates));
850 priv->modes[0].mode = MODE_IEEE80211G;
851 priv->modes[0].num_rates = ARRAY_SIZE(rtl818x_rates);
852 priv->modes[0].rates = priv->rates;
853 priv->modes[0].num_channels = ARRAY_SIZE(rtl818x_channels);
854 priv->modes[0].channels = priv->channels;
855 priv->modes[1].mode = MODE_IEEE80211B;
856 priv->modes[1].num_rates = 4;
857 priv->modes[1].rates = priv->rates;
858 priv->modes[1].num_channels = ARRAY_SIZE(rtl818x_channels);
859 priv->modes[1].channels = priv->channels;
860 priv->mode = IEEE80211_IF_TYPE_INVALID;
861 dev->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
862 IEEE80211_HW_RX_INCLUDES_FCS;
863 dev->queues = 1;
864 dev->max_rssi = 65;
865
866 reg = rtl818x_ioread32(priv, &priv->map->TX_CONF);
867 reg &= RTL818X_TX_CONF_HWVER_MASK;
868 switch (reg) {
869 case RTL818X_TX_CONF_R8180_ABCD:
870 chip_name = "RTL8180";
871 break;
872 case RTL818X_TX_CONF_R8180_F:
873 chip_name = "RTL8180vF";
874 break;
875 case RTL818X_TX_CONF_R8185_ABC:
876 chip_name = "RTL8185";
877 break;
878 case RTL818X_TX_CONF_R8185_D:
879 chip_name = "RTL8185vD";
880 break;
881 default:
882 printk(KERN_ERR "%s (rtl8180): Unknown chip! (0x%x)\n",
883 pci_name(pdev), reg >> 25);
884 goto err_iounmap;
885 }
886
887 priv->r8185 = reg & RTL818X_TX_CONF_R8185_ABC;
888 if (priv->r8185) {
889 if ((err = ieee80211_register_hwmode(dev, &priv->modes[0])))
890 goto err_iounmap;
891
892 pci_try_set_mwi(pdev);
893 }
894
895 if ((err = ieee80211_register_hwmode(dev, &priv->modes[1])))
896 goto err_iounmap;
897
898 eeprom.data = dev;
899 eeprom.register_read = rtl8180_eeprom_register_read;
900 eeprom.register_write = rtl8180_eeprom_register_write;
901 if (rtl818x_ioread32(priv, &priv->map->RX_CONF) & (1 << 6))
902 eeprom.width = PCI_EEPROM_WIDTH_93C66;
903 else
904 eeprom.width = PCI_EEPROM_WIDTH_93C46;
905
906 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_PROGRAM);
907 rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
908 udelay(10);
909
910 eeprom_93cx6_read(&eeprom, 0x06, &eeprom_val);
911 eeprom_val &= 0xFF;
912 switch (eeprom_val) {
913 case 1: rf_name = "Intersil";
914 break;
915 case 2: rf_name = "RFMD";
916 break;
917 case 3: priv->rf = &sa2400_rf_ops;
918 break;
919 case 4: priv->rf = &max2820_rf_ops;
920 break;
921 case 5: priv->rf = &grf5101_rf_ops;
922 break;
923 case 9: priv->rf = rtl8180_detect_rf(dev);
924 break;
925 case 10:
926 rf_name = "RTL8255";
927 break;
928 default:
929 printk(KERN_ERR "%s (rtl8180): Unknown RF! (0x%x)\n",
930 pci_name(pdev), eeprom_val);
931 goto err_iounmap;
932 }
933
934 if (!priv->rf) {
935 printk(KERN_ERR "%s (rtl8180): %s RF frontend not supported!\n",
936 pci_name(pdev), rf_name);
937 goto err_iounmap;
938 }
939
940 eeprom_93cx6_read(&eeprom, 0x17, &eeprom_val);
941 priv->csthreshold = eeprom_val >> 8;
942 if (!priv->r8185) {
943 __le32 anaparam;
944 eeprom_93cx6_multiread(&eeprom, 0xD, (__le16 *)&anaparam, 2);
945 priv->anaparam = le32_to_cpu(anaparam);
946 eeprom_93cx6_read(&eeprom, 0x19, &priv->rfparam);
947 }
948
949 eeprom_93cx6_multiread(&eeprom, 0x7, (__le16 *)dev->wiphy->perm_addr, 3);
950 if (!is_valid_ether_addr(dev->wiphy->perm_addr)) {
951 printk(KERN_WARNING "%s (rtl8180): Invalid hwaddr! Using"
952 " randomly generated MAC addr\n", pci_name(pdev));
953 random_ether_addr(dev->wiphy->perm_addr);
954 }
955
956 /* CCK TX power */
957 for (i = 0; i < 14; i += 2) {
958 u16 txpwr;
959 eeprom_93cx6_read(&eeprom, 0x10 + (i >> 1), &txpwr);
960 priv->channels[i].val = txpwr & 0xFF;
961 priv->channels[i + 1].val = txpwr >> 8;
962 }
963
964 /* OFDM TX power */
965 if (priv->r8185) {
966 for (i = 0; i < 14; i += 2) {
967 u16 txpwr;
968 eeprom_93cx6_read(&eeprom, 0x20 + (i >> 1), &txpwr);
969 priv->channels[i].val |= (txpwr & 0xFF) << 8;
970 priv->channels[i + 1].val |= txpwr & 0xFF00;
971 }
972 }
973
974 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
975
976 spin_lock_init(&priv->lock);
977
978 err = ieee80211_register_hw(dev);
979 if (err) {
980 printk(KERN_ERR "%s (rtl8180): Cannot register device\n",
981 pci_name(pdev));
982 goto err_iounmap;
983 }
984
985 printk(KERN_INFO "%s: hwaddr %s, %s + %s\n",
986 wiphy_name(dev->wiphy), print_mac(mac, dev->wiphy->perm_addr),
987 chip_name, priv->rf->name);
988
989 return 0;
990
991 err_iounmap:
992 iounmap(priv->map);
993
994 err_free_dev:
995 pci_set_drvdata(pdev, NULL);
996 ieee80211_free_hw(dev);
997
998 err_free_reg:
999 pci_release_regions(pdev);
1000 pci_disable_device(pdev);
1001 return err;
1002 }
1003
1004 static void __devexit rtl8180_remove(struct pci_dev *pdev)
1005 {
1006 struct ieee80211_hw *dev = pci_get_drvdata(pdev);
1007 struct rtl8180_priv *priv;
1008
1009 if (!dev)
1010 return;
1011
1012 ieee80211_unregister_hw(dev);
1013
1014 priv = dev->priv;
1015
1016 pci_iounmap(pdev, priv->map);
1017 pci_release_regions(pdev);
1018 pci_disable_device(pdev);
1019 ieee80211_free_hw(dev);
1020 }
1021
1022 #ifdef CONFIG_PM
1023 static int rtl8180_suspend(struct pci_dev *pdev, pm_message_t state)
1024 {
1025 pci_save_state(pdev);
1026 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1027 return 0;
1028 }
1029
1030 static int rtl8180_resume(struct pci_dev *pdev)
1031 {
1032 pci_set_power_state(pdev, PCI_D0);
1033 pci_restore_state(pdev);
1034 return 0;
1035 }
1036
1037 #endif /* CONFIG_PM */
1038
1039 static struct pci_driver rtl8180_driver = {
1040 .name = KBUILD_MODNAME,
1041 .id_table = rtl8180_table,
1042 .probe = rtl8180_probe,
1043 .remove = __devexit_p(rtl8180_remove),
1044 #ifdef CONFIG_PM
1045 .suspend = rtl8180_suspend,
1046 .resume = rtl8180_resume,
1047 #endif /* CONFIG_PM */
1048 };
1049
1050 static int __init rtl8180_init(void)
1051 {
1052 return pci_register_driver(&rtl8180_driver);
1053 }
1054
1055 static void __exit rtl8180_exit(void)
1056 {
1057 pci_unregister_driver(&rtl8180_driver);
1058 }
1059
1060 module_init(rtl8180_init);
1061 module_exit(rtl8180_exit);
WRT350N Kernel Patches