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Merge git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
[wrt350n-kernel.git] / drivers / scsi / gdth.c
blob70e84e508451c598d1d1587f21651d561177de32
1 /************************************************************************
2 * Linux driver for *
3 * ICP vortex GmbH: GDT ISA/EISA/PCI Disk Array Controllers *
4 * Intel Corporation: Storage RAID Controllers *
5 * *
6 * gdth.c *
7 * Copyright (C) 1995-06 ICP vortex GmbH, Achim Leubner *
8 * Copyright (C) 2002-04 Intel Corporation *
9 * Copyright (C) 2003-06 Adaptec Inc. *
10 * <achim_leubner@adaptec.com> *
11 * *
12 * Additions/Fixes: *
13 * Boji Tony Kannanthanam <boji.t.kannanthanam@intel.com> *
14 * Johannes Dinner <johannes_dinner@adaptec.com> *
15 * *
16 * This program is free software; you can redistribute it and/or modify *
17 * it under the terms of the GNU General Public License as published *
18 * by the Free Software Foundation; either version 2 of the License, *
19 * or (at your option) any later version. *
20 * *
21 * This program is distributed in the hope that it will be useful, *
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
24 * GNU General Public License for more details. *
25 * *
26 * You should have received a copy of the GNU General Public License *
27 * along with this kernel; if not, write to the Free Software *
28 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. *
29 * *
30 * Linux kernel 2.6.x supported *
31 * *
32 ************************************************************************/
33
34 /* All GDT Disk Array Controllers are fully supported by this driver.
35 * This includes the PCI/EISA/ISA SCSI Disk Array Controllers and the
36 * PCI Fibre Channel Disk Array Controllers. See gdth.h for a complete
37 * list of all controller types.
38 *
39 * If you have one or more GDT3000/3020 EISA controllers with
40 * controller BIOS disabled, you have to set the IRQ values with the
41 * command line option "gdth=irq1,irq2,...", where the irq1,irq2,... are
42 * the IRQ values for the EISA controllers.
43 *
44 * After the optional list of IRQ values, other possible
45 * command line options are:
46 * disable:Y disable driver
47 * disable:N enable driver
48 * reserve_mode:0 reserve no drives for the raw service
49 * reserve_mode:1 reserve all not init., removable drives
50 * reserve_mode:2 reserve all not init. drives
51 * reserve_list:h,b,t,l,h,b,t,l,... reserve particular drive(s) with
52 * h- controller no., b- channel no.,
53 * t- target ID, l- LUN
54 * reverse_scan:Y reverse scan order for PCI controllers
55 * reverse_scan:N scan PCI controllers like BIOS
56 * max_ids:x x - target ID count per channel (1..MAXID)
57 * rescan:Y rescan all channels/IDs
58 * rescan:N use all devices found until now
59 * hdr_channel:x x - number of virtual bus for host drives
60 * shared_access:Y disable driver reserve/release protocol to
61 * access a shared resource from several nodes,
62 * appropriate controller firmware required
63 * shared_access:N enable driver reserve/release protocol
64 * probe_eisa_isa:Y scan for EISA/ISA controllers
65 * probe_eisa_isa:N do not scan for EISA/ISA controllers
66 * force_dma32:Y use only 32 bit DMA mode
67 * force_dma32:N use 64 bit DMA mode, if supported
68 *
69 * The default values are: "gdth=disable:N,reserve_mode:1,reverse_scan:N,
70 * max_ids:127,rescan:N,hdr_channel:0,
71 * shared_access:Y,probe_eisa_isa:N,force_dma32:N".
72 * Here is another example: "gdth=reserve_list:0,1,2,0,0,1,3,0,rescan:Y".
73 *
74 * When loading the gdth driver as a module, the same options are available.
75 * You can set the IRQs with "IRQ=...". However, the syntax to specify the
76 * options changes slightly. You must replace all ',' between options
77 * with ' ' and all ':' with '=' and you must use
78 * '1' in place of 'Y' and '0' in place of 'N'.
79 *
80 * Default: "modprobe gdth disable=0 reserve_mode=1 reverse_scan=0
81 * max_ids=127 rescan=0 hdr_channel=0 shared_access=0
82 * probe_eisa_isa=0 force_dma32=0"
83 * The other example: "modprobe gdth reserve_list=0,1,2,0,0,1,3,0 rescan=1".
84 */
85
86 /* The meaning of the Scsi_Pointer members in this driver is as follows:
87 * ptr: Chaining
88 * this_residual: gdth_bufflen
89 * buffer: gdth_sglist
90 * dma_handle: unused
91 * buffers_residual: gdth_sg_count
92 * Status: unused
93 * Message: unused
94 * have_data_in: unused
95 * sent_command: unused
96 * phase: unused
97 */
98
99
100 /* interrupt coalescing */
101 /* #define INT_COAL */
102
103 /* statistics */
104 #define GDTH_STATISTICS
105
106 #include <linux/module.h>
107
108 #include <linux/version.h>
109 #include <linux/kernel.h>
110 #include <linux/types.h>
111 #include <linux/pci.h>
112 #include <linux/string.h>
113 #include <linux/ctype.h>
114 #include <linux/ioport.h>
115 #include <linux/delay.h>
116 #include <linux/interrupt.h>
117 #include <linux/in.h>
118 #include <linux/proc_fs.h>
119 #include <linux/time.h>
120 #include <linux/timer.h>
121 #include <linux/dma-mapping.h>
122 #include <linux/list.h>
123
124 #ifdef GDTH_RTC
125 #include <linux/mc146818rtc.h>
126 #endif
127 #include <linux/reboot.h>
128
129 #include <asm/dma.h>
130 #include <asm/system.h>
131 #include <asm/io.h>
132 #include <asm/uaccess.h>
133 #include <linux/spinlock.h>
134 #include <linux/blkdev.h>
135 #include <linux/scatterlist.h>
136
137 #include "scsi.h"
138 #include <scsi/scsi_host.h>
139 #include "gdth.h"
140
141 static void gdth_delay(int milliseconds);
142 static void gdth_eval_mapping(ulong32 size, ulong32 *cyls, int *heads, int *secs);
143 static irqreturn_t gdth_interrupt(int irq, void *dev_id);
144 static irqreturn_t __gdth_interrupt(gdth_ha_str *ha,
145 int gdth_from_wait, int* pIndex);
146 static int gdth_sync_event(gdth_ha_str *ha, int service, unchar index,
147 Scsi_Cmnd *scp);
148 static int gdth_async_event(gdth_ha_str *ha);
149 static void gdth_log_event(gdth_evt_data *dvr, char *buffer);
150
151 static void gdth_putq(gdth_ha_str *ha, Scsi_Cmnd *scp, unchar priority);
152 static void gdth_next(gdth_ha_str *ha);
153 static int gdth_fill_raw_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp, unchar b);
154 static int gdth_special_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp);
155 static gdth_evt_str *gdth_store_event(gdth_ha_str *ha, ushort source,
156 ushort idx, gdth_evt_data *evt);
157 static int gdth_read_event(gdth_ha_str *ha, int handle, gdth_evt_str *estr);
158 static void gdth_readapp_event(gdth_ha_str *ha, unchar application,
159 gdth_evt_str *estr);
160 static void gdth_clear_events(void);
161
162 static void gdth_copy_internal_data(gdth_ha_str *ha, Scsi_Cmnd *scp,
163 <<<<<<< HEAD:drivers/scsi/gdth.c
164 char *buffer, ushort count, int to_buffer);
165 =======
166 char *buffer, ushort count);
167 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/scsi/gdth.c
168 static int gdth_internal_cache_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp);
169 static int gdth_fill_cache_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp, ushort hdrive);
170
171 static void gdth_enable_int(gdth_ha_str *ha);
172 static int gdth_test_busy(gdth_ha_str *ha);
173 static int gdth_get_cmd_index(gdth_ha_str *ha);
174 static void gdth_release_event(gdth_ha_str *ha);
175 static int gdth_wait(gdth_ha_str *ha, int index,ulong32 time);
176 static int gdth_internal_cmd(gdth_ha_str *ha, unchar service, ushort opcode,
177 ulong32 p1, ulong64 p2,ulong64 p3);
178 static int gdth_search_drives(gdth_ha_str *ha);
179 static int gdth_analyse_hdrive(gdth_ha_str *ha, ushort hdrive);
180
181 static const char *gdth_ctr_name(gdth_ha_str *ha);
182
183 static int gdth_open(struct inode *inode, struct file *filep);
184 static int gdth_close(struct inode *inode, struct file *filep);
185 static int gdth_ioctl(struct inode *inode, struct file *filep,
186 unsigned int cmd, unsigned long arg);
187
188 static void gdth_flush(gdth_ha_str *ha);
189 <<<<<<< HEAD:drivers/scsi/gdth.c
190 static int gdth_halt(struct notifier_block *nb, ulong event, void *buf);
191 =======
192 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/scsi/gdth.c
193 static int gdth_queuecommand(Scsi_Cmnd *scp,void (*done)(Scsi_Cmnd *));
194 static int __gdth_queuecommand(gdth_ha_str *ha, struct scsi_cmnd *scp,
195 struct gdth_cmndinfo *cmndinfo);
196 static void gdth_scsi_done(struct scsi_cmnd *scp);
197
198 #ifdef DEBUG_GDTH
199 static unchar DebugState = DEBUG_GDTH;
200
201 #ifdef __SERIAL__
202 #define MAX_SERBUF 160
203 static void ser_init(void);
204 static void ser_puts(char *str);
205 static void ser_putc(char c);
206 static int ser_printk(const char *fmt, ...);
207 static char strbuf[MAX_SERBUF+1];
208 #ifdef __COM2__
209 #define COM_BASE 0x2f8
210 #else
211 #define COM_BASE 0x3f8
212 #endif
213 static void ser_init()
214 {
215 unsigned port=COM_BASE;
216
217 outb(0x80,port+3);
218 outb(0,port+1);
219 /* 19200 Baud, if 9600: outb(12,port) */
220 outb(6, port);
221 outb(3,port+3);
222 outb(0,port+1);
223 /*
224 ser_putc('I');
225 ser_putc(' ');
226 */
227 }
228
229 static void ser_puts(char *str)
230 {
231 char *ptr;
232
233 ser_init();
234 for (ptr=str;*ptr;++ptr)
235 ser_putc(*ptr);
236 }
237
238 static void ser_putc(char c)
239 {
240 unsigned port=COM_BASE;
241
242 while ((inb(port+5) & 0x20)==0);
243 outb(c,port);
244 if (c==0x0a)
245 {
246 while ((inb(port+5) & 0x20)==0);
247 outb(0x0d,port);
248 }
249 }
250
251 static int ser_printk(const char *fmt, ...)
252 {
253 va_list args;
254 int i;
255
256 va_start(args,fmt);
257 i = vsprintf(strbuf,fmt,args);
258 ser_puts(strbuf);
259 va_end(args);
260 return i;
261 }
262
263 #define TRACE(a) {if (DebugState==1) {ser_printk a;}}
264 #define TRACE2(a) {if (DebugState==1 || DebugState==2) {ser_printk a;}}
265 #define TRACE3(a) {if (DebugState!=0) {ser_printk a;}}
266
267 #else /* !__SERIAL__ */
268 #define TRACE(a) {if (DebugState==1) {printk a;}}
269 #define TRACE2(a) {if (DebugState==1 || DebugState==2) {printk a;}}
270 #define TRACE3(a) {if (DebugState!=0) {printk a;}}
271 #endif
272
273 #else /* !DEBUG */
274 #define TRACE(a)
275 #define TRACE2(a)
276 #define TRACE3(a)
277 #endif
278
279 #ifdef GDTH_STATISTICS
280 static ulong32 max_rq=0, max_index=0, max_sg=0;
281 #ifdef INT_COAL
282 static ulong32 max_int_coal=0;
283 #endif
284 static ulong32 act_ints=0, act_ios=0, act_stats=0, act_rq=0;
285 static struct timer_list gdth_timer;
286 #endif
287
288 #define PTR2USHORT(a) (ushort)(ulong)(a)
289 #define GDTOFFSOF(a,b) (size_t)&(((a*)0)->b)
290 #define INDEX_OK(i,t) ((i)<ARRAY_SIZE(t))
291
292 #define BUS_L2P(a,b) ((b)>(a)->virt_bus ? (b-1):(b))
293
294 #ifdef CONFIG_ISA
295 static unchar gdth_drq_tab[4] = {5,6,7,7}; /* DRQ table */
296 #endif
297 #if defined(CONFIG_EISA) || defined(CONFIG_ISA)
298 static unchar gdth_irq_tab[6] = {0,10,11,12,14,0}; /* IRQ table */
299 #endif
300 static unchar gdth_polling; /* polling if TRUE */
301 static int gdth_ctr_count = 0; /* controller count */
302 static LIST_HEAD(gdth_instances); /* controller list */
303 static unchar gdth_write_through = FALSE; /* write through */
304 static gdth_evt_str ebuffer[MAX_EVENTS]; /* event buffer */
305 static int elastidx;
306 static int eoldidx;
307 static int major;
308
309 #define DIN 1 /* IN data direction */
310 #define DOU 2 /* OUT data direction */
311 #define DNO DIN /* no data transfer */
312 #define DUN DIN /* unknown data direction */
313 static unchar gdth_direction_tab[0x100] = {
314 DNO,DNO,DIN,DIN,DOU,DIN,DIN,DOU,DIN,DUN,DOU,DOU,DUN,DUN,DUN,DIN,
315 DNO,DIN,DIN,DOU,DIN,DOU,DNO,DNO,DOU,DNO,DIN,DNO,DIN,DOU,DNO,DUN,
316 DIN,DUN,DIN,DUN,DOU,DIN,DUN,DUN,DIN,DIN,DOU,DNO,DUN,DIN,DOU,DOU,
317 DOU,DOU,DOU,DNO,DIN,DNO,DNO,DIN,DOU,DOU,DOU,DOU,DIN,DOU,DIN,DOU,
318 DOU,DOU,DIN,DIN,DIN,DNO,DUN,DNO,DNO,DNO,DUN,DNO,DOU,DIN,DUN,DUN,
319 DUN,DUN,DUN,DUN,DUN,DOU,DUN,DUN,DUN,DUN,DIN,DUN,DUN,DUN,DUN,DUN,
320 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
321 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
322 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DIN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,
323 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DIN,DUN,
324 DUN,DUN,DUN,DUN,DUN,DNO,DNO,DUN,DIN,DNO,DOU,DUN,DNO,DUN,DOU,DOU,
325 DOU,DOU,DOU,DNO,DUN,DIN,DOU,DIN,DIN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
326 DUN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
327 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
328 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,
329 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN
330 };
331
332 /* LILO and modprobe/insmod parameters */
333 /* IRQ list for GDT3000/3020 EISA controllers */
334 static int irq[MAXHA] __initdata =
335 {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
336 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};
337 /* disable driver flag */
338 static int disable __initdata = 0;
339 /* reserve flag */
340 static int reserve_mode = 1;
341 /* reserve list */
342 static int reserve_list[MAX_RES_ARGS] =
343 {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
344 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
345 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};
346 /* scan order for PCI controllers */
347 static int reverse_scan = 0;
348 /* virtual channel for the host drives */
349 static int hdr_channel = 0;
350 /* max. IDs per channel */
351 static int max_ids = MAXID;
352 /* rescan all IDs */
353 static int rescan = 0;
354 /* shared access */
355 static int shared_access = 1;
356 /* enable support for EISA and ISA controllers */
357 static int probe_eisa_isa = 0;
358 /* 64 bit DMA mode, support for drives > 2 TB, if force_dma32 = 0 */
359 static int force_dma32 = 0;
360
361 /* parameters for modprobe/insmod */
362 module_param_array(irq, int, NULL, 0);
363 module_param(disable, int, 0);
364 module_param(reserve_mode, int, 0);
365 module_param_array(reserve_list, int, NULL, 0);
366 module_param(reverse_scan, int, 0);
367 module_param(hdr_channel, int, 0);
368 module_param(max_ids, int, 0);
369 module_param(rescan, int, 0);
370 module_param(shared_access, int, 0);
371 module_param(probe_eisa_isa, int, 0);
372 module_param(force_dma32, int, 0);
373 MODULE_AUTHOR("Achim Leubner");
374 MODULE_LICENSE("GPL");
375
376 /* ioctl interface */
377 static const struct file_operations gdth_fops = {
378 .ioctl = gdth_ioctl,
379 .open = gdth_open,
380 .release = gdth_close,
381 };
382
383 /*
384 * gdth scsi_command access wrappers.
385 * below 6 functions are used throughout the driver to access scsi_command's
386 * io parameters. The reason we do not use the regular accessors from
387 * scsi_cmnd.h is because of gdth_execute(). Since it is unrecommended for
388 * llds to directly set scsi_cmnd's IO members. This driver will use SCp
389 * members for IO parameters, and will copy scsi_cmnd's members to Scp
390 * members in queuecommand. For internal commands through gdth_execute()
391 * SCp's members will be set directly.
392 */
393 static inline unsigned gdth_bufflen(struct scsi_cmnd *cmd)
394 {
395 return (unsigned)cmd->SCp.this_residual;
396 }
397
398 static inline void gdth_set_bufflen(struct scsi_cmnd *cmd, unsigned bufflen)
399 {
400 cmd->SCp.this_residual = bufflen;
401 }
402
403 static inline unsigned gdth_sg_count(struct scsi_cmnd *cmd)
404 {
405 return (unsigned)cmd->SCp.buffers_residual;
406 }
407
408 static inline void gdth_set_sg_count(struct scsi_cmnd *cmd, unsigned sg_count)
409 {
410 cmd->SCp.buffers_residual = sg_count;
411 }
412
413 static inline struct scatterlist *gdth_sglist(struct scsi_cmnd *cmd)
414 {
415 return cmd->SCp.buffer;
416 }
417
418 static inline void gdth_set_sglist(struct scsi_cmnd *cmd,
419 struct scatterlist *sglist)
420 {
421 cmd->SCp.buffer = sglist;
422 }
423
424 #include "gdth_proc.h"
425 #include "gdth_proc.c"
426
427 <<<<<<< HEAD:drivers/scsi/gdth.c
428 /* notifier block to get a notify on system shutdown/halt/reboot */
429 static struct notifier_block gdth_notifier = {
430 gdth_halt, NULL, 0
431 };
432 static int notifier_disabled = 0;
433
434 =======
435 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/scsi/gdth.c
436 static gdth_ha_str *gdth_find_ha(int hanum)
437 {
438 gdth_ha_str *ha;
439
440 list_for_each_entry(ha, &gdth_instances, list)
441 if (hanum == ha->hanum)
442 return ha;
443
444 return NULL;
445 }
446
447 static struct gdth_cmndinfo *gdth_get_cmndinfo(gdth_ha_str *ha)
448 {
449 struct gdth_cmndinfo *priv = NULL;
450 ulong flags;
451 int i;
452
453 spin_lock_irqsave(&ha->smp_lock, flags);
454
455 for (i=0; i<GDTH_MAXCMDS; ++i) {
456 if (ha->cmndinfo[i].index == 0) {
457 priv = &ha->cmndinfo[i];
458 <<<<<<< HEAD:drivers/scsi/gdth.c
459 priv->index = i+1;
460 =======
461 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/scsi/gdth.c
462 memset(priv, 0, sizeof(*priv));
463 <<<<<<< HEAD:drivers/scsi/gdth.c
464 =======
465 priv->index = i+1;
466 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/scsi/gdth.c
467 break;
468 }
469 }
470
471 spin_unlock_irqrestore(&ha->smp_lock, flags);
472
473 return priv;
474 }
475
476 static void gdth_put_cmndinfo(struct gdth_cmndinfo *priv)
477 {
478 BUG_ON(!priv);
479 priv->index = 0;
480 }
481
482 static void gdth_delay(int milliseconds)
483 {
484 if (milliseconds == 0) {
485 udelay(1);
486 } else {
487 mdelay(milliseconds);
488 }
489 }
490
491 static void gdth_scsi_done(struct scsi_cmnd *scp)
492 {
493 struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
494 int internal_command = cmndinfo->internal_command;
495
496 TRACE2(("gdth_scsi_done()\n"));
497
498 gdth_put_cmndinfo(cmndinfo);
499 scp->host_scribble = NULL;
500
501 if (internal_command)
502 complete((struct completion *)scp->request);
503 else
504 scp->scsi_done(scp);
505 }
506
507 int __gdth_execute(struct scsi_device *sdev, gdth_cmd_str *gdtcmd, char *cmnd,
508 int timeout, u32 *info)
509 {
510 gdth_ha_str *ha = shost_priv(sdev->host);
511 Scsi_Cmnd *scp;
512 struct gdth_cmndinfo cmndinfo;
513 <<<<<<< HEAD:drivers/scsi/gdth.c
514 struct scatterlist one_sg;
515 =======
516 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/scsi/gdth.c
517 DECLARE_COMPLETION_ONSTACK(wait);
518 int rval;
519
520 scp = kzalloc(sizeof(*scp), GFP_KERNEL);
521 if (!scp)
522 return -ENOMEM;
523
524 scp->device = sdev;
525 memset(&cmndinfo, 0, sizeof(cmndinfo));
526
527 /* use request field to save the ptr. to completion struct. */
528 scp->request = (struct request *)&wait;
529 scp->timeout_per_command = timeout*HZ;
530 <<<<<<< HEAD:drivers/scsi/gdth.c
531 sg_init_one(&one_sg, gdtcmd, sizeof(*gdtcmd));
532 gdth_set_sglist(scp, &one_sg);
533 gdth_set_sg_count(scp, 1);
534 gdth_set_bufflen(scp, sizeof(*gdtcmd));
535 =======
536 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/scsi/gdth.c
537 scp->cmd_len = 12;
538 memcpy(scp->cmnd, cmnd, 12);
539 cmndinfo.priority = IOCTL_PRI;
540 <<<<<<< HEAD:drivers/scsi/gdth.c
541 =======
542 cmndinfo.internal_cmd_str = gdtcmd;
543 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/scsi/gdth.c
544 cmndinfo.internal_command = 1;
545
546 TRACE(("__gdth_execute() cmd 0x%x\n", scp->cmnd[0]));
547 __gdth_queuecommand(ha, scp, &cmndinfo);
548
549 wait_for_completion(&wait);
550
551 rval = cmndinfo.status;
552 if (info)
553 *info = cmndinfo.info;
554 kfree(scp);
555 return rval;
556 }
557
558 int gdth_execute(struct Scsi_Host *shost, gdth_cmd_str *gdtcmd, char *cmnd,
559 int timeout, u32 *info)
560 {
561 struct scsi_device *sdev = scsi_get_host_dev(shost);
562 int rval = __gdth_execute(sdev, gdtcmd, cmnd, timeout, info);
563
564 scsi_free_host_dev(sdev);
565 return rval;
566 }
567
568 static void gdth_eval_mapping(ulong32 size, ulong32 *cyls, int *heads, int *secs)
569 {
570 *cyls = size /HEADS/SECS;
571 if (*cyls <= MAXCYLS) {
572 *heads = HEADS;
573 *secs = SECS;
574 } else { /* too high for 64*32 */
575 *cyls = size /MEDHEADS/MEDSECS;
576 if (*cyls <= MAXCYLS) {
577 *heads = MEDHEADS;
578 *secs = MEDSECS;
579 } else { /* too high for 127*63 */
580 *cyls = size /BIGHEADS/BIGSECS;
581 *heads = BIGHEADS;
582 *secs = BIGSECS;
583 }
584 }
585 }
586
587 /* controller search and initialization functions */
588 #ifdef CONFIG_EISA
589 static int __init gdth_search_eisa(ushort eisa_adr)
590 {
591 ulong32 id;
592
593 TRACE(("gdth_search_eisa() adr. %x\n",eisa_adr));
594 id = inl(eisa_adr+ID0REG);
595 if (id == GDT3A_ID || id == GDT3B_ID) { /* GDT3000A or GDT3000B */
596 if ((inb(eisa_adr+EISAREG) & 8) == 0)
597 return 0; /* not EISA configured */
598 return 1;
599 }
600 if (id == GDT3_ID) /* GDT3000 */
601 return 1;
602
603 return 0;
604 }
605 #endif /* CONFIG_EISA */
606
607 #ifdef CONFIG_ISA
608 static int __init gdth_search_isa(ulong32 bios_adr)
609 {
610 void __iomem *addr;
611 ulong32 id;
612
613 TRACE(("gdth_search_isa() bios adr. %x\n",bios_adr));
614 if ((addr = ioremap(bios_adr+BIOS_ID_OFFS, sizeof(ulong32))) != NULL) {
615 id = readl(addr);
616 iounmap(addr);
617 if (id == GDT2_ID) /* GDT2000 */
618 return 1;
619 }
620 return 0;
621 }
622 #endif /* CONFIG_ISA */
623
624 #ifdef CONFIG_PCI
625 static void gdth_search_dev(gdth_pci_str *pcistr, ushort *cnt,
626 ushort vendor, ushort dev);
627
628 static int __init gdth_search_pci(gdth_pci_str *pcistr)
629 {
630 ushort device, cnt;
631
632 TRACE(("gdth_search_pci()\n"));
633
634 cnt = 0;
635 for (device = 0; device <= PCI_DEVICE_ID_VORTEX_GDT6555; ++device)
636 gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX, device);
637 for (device = PCI_DEVICE_ID_VORTEX_GDT6x17RP;
638 device <= PCI_DEVICE_ID_VORTEX_GDTMAXRP; ++device)
639 gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX, device);
640 gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX,
641 PCI_DEVICE_ID_VORTEX_GDTNEWRX);
642 gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX,
643 PCI_DEVICE_ID_VORTEX_GDTNEWRX2);
644 gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_INTEL,
645 PCI_DEVICE_ID_INTEL_SRC);
646 gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_INTEL,
647 PCI_DEVICE_ID_INTEL_SRC_XSCALE);
648 return cnt;
649 }
650
651 /* Vortex only makes RAID controllers.
652 * We do not really want to specify all 550 ids here, so wildcard match.
653 */
654 static struct pci_device_id gdthtable[] __maybe_unused = {
655 {PCI_VENDOR_ID_VORTEX,PCI_ANY_ID,PCI_ANY_ID, PCI_ANY_ID},
656 {PCI_VENDOR_ID_INTEL,PCI_DEVICE_ID_INTEL_SRC,PCI_ANY_ID,PCI_ANY_ID},
657 {PCI_VENDOR_ID_INTEL,PCI_DEVICE_ID_INTEL_SRC_XSCALE,PCI_ANY_ID,PCI_ANY_ID},
658 {0}
659 };
660 MODULE_DEVICE_TABLE(pci,gdthtable);
661
662 static void __init gdth_search_dev(gdth_pci_str *pcistr, ushort *cnt,
663 ushort vendor, ushort device)
664 {
665 ulong base0, base1, base2;
666 struct pci_dev *pdev;
667
668 TRACE(("gdth_search_dev() cnt %d vendor %x device %x\n",
669 *cnt, vendor, device));
670
671 pdev = NULL;
672 while ((pdev = pci_get_device(vendor, device, pdev))
673 != NULL) {
674 if (pci_enable_device(pdev))
675 continue;
676 if (*cnt >= MAXHA) {
677 pci_dev_put(pdev);
678 return;
679 }
680
681 /* GDT PCI controller found, resources are already in pdev */
682 pcistr[*cnt].pdev = pdev;
683 pcistr[*cnt].irq = pdev->irq;
684 base0 = pci_resource_flags(pdev, 0);
685 base1 = pci_resource_flags(pdev, 1);
686 base2 = pci_resource_flags(pdev, 2);
687 if (device <= PCI_DEVICE_ID_VORTEX_GDT6000B || /* GDT6000/B */
688 device >= PCI_DEVICE_ID_VORTEX_GDT6x17RP) { /* MPR */
689 if (!(base0 & IORESOURCE_MEM))
690 continue;
691 pcistr[*cnt].dpmem = pci_resource_start(pdev, 0);
692 } else { /* GDT6110, GDT6120, .. */
693 if (!(base0 & IORESOURCE_MEM) ||
694 !(base2 & IORESOURCE_MEM) ||
695 !(base1 & IORESOURCE_IO))
696 continue;
697 pcistr[*cnt].dpmem = pci_resource_start(pdev, 2);
698 pcistr[*cnt].io_mm = pci_resource_start(pdev, 0);
699 pcistr[*cnt].io = pci_resource_start(pdev, 1);
700 }
701 TRACE2(("Controller found at %d/%d, irq %d, dpmem 0x%lx\n",
702 pcistr[*cnt].pdev->bus->number,
703 PCI_SLOT(pcistr[*cnt].pdev->devfn),
704 pcistr[*cnt].irq, pcistr[*cnt].dpmem));
705 (*cnt)++;
706 }
707 }
708
709 static void __init gdth_sort_pci(gdth_pci_str *pcistr, int cnt)
710 {
711 gdth_pci_str temp;
712 int i, changed;
713
714 TRACE(("gdth_sort_pci() cnt %d\n",cnt));
715 if (cnt == 0)
716 return;
717
718 do {
719 changed = FALSE;
720 for (i = 0; i < cnt-1; ++i) {
721 if (!reverse_scan) {
722 if ((pcistr[i].pdev->bus->number > pcistr[i+1].pdev->bus->number) ||
723 (pcistr[i].pdev->bus->number == pcistr[i+1].pdev->bus->number &&
724 PCI_SLOT(pcistr[i].pdev->devfn) >
725 PCI_SLOT(pcistr[i+1].pdev->devfn))) {
726 temp = pcistr[i];
727 pcistr[i] = pcistr[i+1];
728 pcistr[i+1] = temp;
729 changed = TRUE;
730 }
731 } else {
732 if ((pcistr[i].pdev->bus->number < pcistr[i+1].pdev->bus->number) ||
733 (pcistr[i].pdev->bus->number == pcistr[i+1].pdev->bus->number &&
734 PCI_SLOT(pcistr[i].pdev->devfn) <
735 PCI_SLOT(pcistr[i+1].pdev->devfn))) {
736 temp = pcistr[i];
737 pcistr[i] = pcistr[i+1];
738 pcistr[i+1] = temp;
739 changed = TRUE;
740 }
741 }
742 }
743 } while (changed);
744 }
745 #endif /* CONFIG_PCI */
746
747 #ifdef CONFIG_EISA
748 static int __init gdth_init_eisa(ushort eisa_adr,gdth_ha_str *ha)
749 {
750 ulong32 retries,id;
751 unchar prot_ver,eisacf,i,irq_found;
752
753 TRACE(("gdth_init_eisa() adr. %x\n",eisa_adr));
754
755 /* disable board interrupts, deinitialize services */
756 outb(0xff,eisa_adr+EDOORREG);
757 outb(0x00,eisa_adr+EDENABREG);
758 outb(0x00,eisa_adr+EINTENABREG);
759
760 outb(0xff,eisa_adr+LDOORREG);
761 retries = INIT_RETRIES;
762 gdth_delay(20);
763 while (inb(eisa_adr+EDOORREG) != 0xff) {
764 if (--retries == 0) {
765 printk("GDT-EISA: Initialization error (DEINIT failed)\n");
766 return 0;
767 }
768 gdth_delay(1);
769 TRACE2(("wait for DEINIT: retries=%d\n",retries));
770 }
771 prot_ver = inb(eisa_adr+MAILBOXREG);
772 outb(0xff,eisa_adr+EDOORREG);
773 if (prot_ver != PROTOCOL_VERSION) {
774 printk("GDT-EISA: Illegal protocol version\n");
775 return 0;
776 }
777 ha->bmic = eisa_adr;
778 ha->brd_phys = (ulong32)eisa_adr >> 12;
779
780 outl(0,eisa_adr+MAILBOXREG);
781 outl(0,eisa_adr+MAILBOXREG+4);
782 outl(0,eisa_adr+MAILBOXREG+8);
783 outl(0,eisa_adr+MAILBOXREG+12);
784
785 /* detect IRQ */
786 if ((id = inl(eisa_adr+ID0REG)) == GDT3_ID) {
787 ha->oem_id = OEM_ID_ICP;
788 ha->type = GDT_EISA;
789 ha->stype = id;
790 outl(1,eisa_adr+MAILBOXREG+8);
791 outb(0xfe,eisa_adr+LDOORREG);
792 retries = INIT_RETRIES;
793 gdth_delay(20);
794 while (inb(eisa_adr+EDOORREG) != 0xfe) {
795 if (--retries == 0) {
796 printk("GDT-EISA: Initialization error (get IRQ failed)\n");
797 return 0;
798 }
799 gdth_delay(1);
800 }
801 ha->irq = inb(eisa_adr+MAILBOXREG);
802 outb(0xff,eisa_adr+EDOORREG);
803 TRACE2(("GDT3000/3020: IRQ=%d\n",ha->irq));
804 /* check the result */
805 if (ha->irq == 0) {
806 TRACE2(("Unknown IRQ, use IRQ table from cmd line !\n"));
807 for (i = 0, irq_found = FALSE;
808 i < MAXHA && irq[i] != 0xff; ++i) {
809 if (irq[i]==10 || irq[i]==11 || irq[i]==12 || irq[i]==14) {
810 irq_found = TRUE;
811 break;
812 }
813 }
814 if (irq_found) {
815 ha->irq = irq[i];
816 irq[i] = 0;
817 printk("GDT-EISA: Can not detect controller IRQ,\n");
818 printk("Use IRQ setting from command line (IRQ = %d)\n",
819 ha->irq);
820 } else {
821 printk("GDT-EISA: Initialization error (unknown IRQ), Enable\n");
822 printk("the controller BIOS or use command line parameters\n");
823 return 0;
824 }
825 }
826 } else {
827 eisacf = inb(eisa_adr+EISAREG) & 7;
828 if (eisacf > 4) /* level triggered */
829 eisacf -= 4;
830 ha->irq = gdth_irq_tab[eisacf];
831 ha->oem_id = OEM_ID_ICP;
832 ha->type = GDT_EISA;
833 ha->stype = id;
834 }
835
836 ha->dma64_support = 0;
837 return 1;
838 }
839 #endif /* CONFIG_EISA */
840
841 #ifdef CONFIG_ISA
842 static int __init gdth_init_isa(ulong32 bios_adr,gdth_ha_str *ha)
843 {
844 register gdt2_dpram_str __iomem *dp2_ptr;
845 int i;
846 unchar irq_drq,prot_ver;
847 ulong32 retries;
848
849 TRACE(("gdth_init_isa() bios adr. %x\n",bios_adr));
850
851 ha->brd = ioremap(bios_adr, sizeof(gdt2_dpram_str));
852 if (ha->brd == NULL) {
853 printk("GDT-ISA: Initialization error (DPMEM remap error)\n");
854 return 0;
855 }
856 dp2_ptr = ha->brd;
857 writeb(1, &dp2_ptr->io.memlock); /* switch off write protection */
858 /* reset interface area */
859 memset_io(&dp2_ptr->u, 0, sizeof(dp2_ptr->u));
860 if (readl(&dp2_ptr->u) != 0) {
861 printk("GDT-ISA: Initialization error (DPMEM write error)\n");
862 iounmap(ha->brd);
863 return 0;
864 }
865
866 /* disable board interrupts, read DRQ and IRQ */
867 writeb(0xff, &dp2_ptr->io.irqdel);
868 writeb(0x00, &dp2_ptr->io.irqen);
869 writeb(0x00, &dp2_ptr->u.ic.S_Status);
870 writeb(0x00, &dp2_ptr->u.ic.Cmd_Index);
871
872 irq_drq = readb(&dp2_ptr->io.rq);
873 for (i=0; i<3; ++i) {
874 if ((irq_drq & 1)==0)
875 break;
876 irq_drq >>= 1;
877 }
878 ha->drq = gdth_drq_tab[i];
879
880 irq_drq = readb(&dp2_ptr->io.rq) >> 3;
881 for (i=1; i<5; ++i) {
882 if ((irq_drq & 1)==0)
883 break;
884 irq_drq >>= 1;
885 }
886 ha->irq = gdth_irq_tab[i];
887
888 /* deinitialize services */
889 writel(bios_adr, &dp2_ptr->u.ic.S_Info[0]);
890 writeb(0xff, &dp2_ptr->u.ic.S_Cmd_Indx);
891 writeb(0, &dp2_ptr->io.event);
892 retries = INIT_RETRIES;
893 gdth_delay(20);
894 while (readb(&dp2_ptr->u.ic.S_Status) != 0xff) {
895 if (--retries == 0) {
896 printk("GDT-ISA: Initialization error (DEINIT failed)\n");
897 iounmap(ha->brd);
898 return 0;
899 }
900 gdth_delay(1);
901 }
902 prot_ver = (unchar)readl(&dp2_ptr->u.ic.S_Info[0]);
903 writeb(0, &dp2_ptr->u.ic.Status);
904 writeb(0xff, &dp2_ptr->io.irqdel);
905 if (prot_ver != PROTOCOL_VERSION) {
906 printk("GDT-ISA: Illegal protocol version\n");
907 iounmap(ha->brd);
908 return 0;
909 }
910
911 ha->oem_id = OEM_ID_ICP;
912 ha->type = GDT_ISA;
913 ha->ic_all_size = sizeof(dp2_ptr->u);
914 ha->stype= GDT2_ID;
915 ha->brd_phys = bios_adr >> 4;
916
917 /* special request to controller BIOS */
918 writel(0x00, &dp2_ptr->u.ic.S_Info[0]);
919 writel(0x00, &dp2_ptr->u.ic.S_Info[1]);
920 writel(0x01, &dp2_ptr->u.ic.S_Info[2]);
921 writel(0x00, &dp2_ptr->u.ic.S_Info[3]);
922 writeb(0xfe, &dp2_ptr->u.ic.S_Cmd_Indx);
923 writeb(0, &dp2_ptr->io.event);
924 retries = INIT_RETRIES;
925 gdth_delay(20);
926 while (readb(&dp2_ptr->u.ic.S_Status) != 0xfe) {
927 if (--retries == 0) {
928 printk("GDT-ISA: Initialization error\n");
929 iounmap(ha->brd);
930 return 0;
931 }
932 gdth_delay(1);
933 }
934 writeb(0, &dp2_ptr->u.ic.Status);
935 writeb(0xff, &dp2_ptr->io.irqdel);
936
937 ha->dma64_support = 0;
938 return 1;
939 }
940 #endif /* CONFIG_ISA */
941
942 #ifdef CONFIG_PCI
943 static int __init gdth_init_pci(gdth_pci_str *pcistr,gdth_ha_str *ha)
944 {
945 register gdt6_dpram_str __iomem *dp6_ptr;
946 register gdt6c_dpram_str __iomem *dp6c_ptr;
947 register gdt6m_dpram_str __iomem *dp6m_ptr;
948 ulong32 retries;
949 unchar prot_ver;
950 ushort command;
951 int i, found = FALSE;
952
953 TRACE(("gdth_init_pci()\n"));
954
955 if (pcistr->pdev->vendor == PCI_VENDOR_ID_INTEL)
956 ha->oem_id = OEM_ID_INTEL;
957 else
958 ha->oem_id = OEM_ID_ICP;
959 ha->brd_phys = (pcistr->pdev->bus->number << 8) | (pcistr->pdev->devfn & 0xf8);
960 ha->stype = (ulong32)pcistr->pdev->device;
961 ha->irq = pcistr->irq;
962 ha->pdev = pcistr->pdev;
963
964 if (ha->pdev->device <= PCI_DEVICE_ID_VORTEX_GDT6000B) { /* GDT6000/B */
965 TRACE2(("init_pci() dpmem %lx irq %d\n",pcistr->dpmem,ha->irq));
966 ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6_dpram_str));
967 if (ha->brd == NULL) {
968 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
969 return 0;
970 }
971 /* check and reset interface area */
972 dp6_ptr = ha->brd;
973 writel(DPMEM_MAGIC, &dp6_ptr->u);
974 if (readl(&dp6_ptr->u) != DPMEM_MAGIC) {
975 printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
976 pcistr->dpmem);
977 found = FALSE;
978 for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
979 iounmap(ha->brd);
980 ha->brd = ioremap(i, sizeof(ushort));
981 if (ha->brd == NULL) {
982 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
983 return 0;
984 }
985 if (readw(ha->brd) != 0xffff) {
986 TRACE2(("init_pci_old() address 0x%x busy\n", i));
987 continue;
988 }
989 iounmap(ha->brd);
990 pci_write_config_dword(pcistr->pdev,
991 PCI_BASE_ADDRESS_0, i);
992 ha->brd = ioremap(i, sizeof(gdt6_dpram_str));
993 if (ha->brd == NULL) {
994 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
995 return 0;
996 }
997 dp6_ptr = ha->brd;
998 writel(DPMEM_MAGIC, &dp6_ptr->u);
999 if (readl(&dp6_ptr->u) == DPMEM_MAGIC) {
1000 printk("GDT-PCI: Use free address at 0x%x\n", i);
1001 found = TRUE;
1002 break;
1003 }
1004 }
1005 if (!found) {
1006 printk("GDT-PCI: No free address found!\n");
1007 iounmap(ha->brd);
1008 return 0;
1009 }
1010 }
1011 memset_io(&dp6_ptr->u, 0, sizeof(dp6_ptr->u));
1012 if (readl(&dp6_ptr->u) != 0) {
1013 printk("GDT-PCI: Initialization error (DPMEM write error)\n");
1014 iounmap(ha->brd);
1015 return 0;
1016 }
1017
1018 /* disable board interrupts, deinit services */
1019 writeb(0xff, &dp6_ptr->io.irqdel);
1020 writeb(0x00, &dp6_ptr->io.irqen);
1021 writeb(0x00, &dp6_ptr->u.ic.S_Status);
1022 writeb(0x00, &dp6_ptr->u.ic.Cmd_Index);
1023
1024 writel(pcistr->dpmem, &dp6_ptr->u.ic.S_Info[0]);
1025 writeb(0xff, &dp6_ptr->u.ic.S_Cmd_Indx);
1026 writeb(0, &dp6_ptr->io.event);
1027 retries = INIT_RETRIES;
1028 gdth_delay(20);
1029 while (readb(&dp6_ptr->u.ic.S_Status) != 0xff) {
1030 if (--retries == 0) {
1031 printk("GDT-PCI: Initialization error (DEINIT failed)\n");
1032 iounmap(ha->brd);
1033 return 0;
1034 }
1035 gdth_delay(1);
1036 }
1037 prot_ver = (unchar)readl(&dp6_ptr->u.ic.S_Info[0]);
1038 writeb(0, &dp6_ptr->u.ic.S_Status);
1039 writeb(0xff, &dp6_ptr->io.irqdel);
1040 if (prot_ver != PROTOCOL_VERSION) {
1041 printk("GDT-PCI: Illegal protocol version\n");
1042 iounmap(ha->brd);
1043 return 0;
1044 }
1045
1046 ha->type = GDT_PCI;
1047 ha->ic_all_size = sizeof(dp6_ptr->u);
1048
1049 /* special command to controller BIOS */
1050 writel(0x00, &dp6_ptr->u.ic.S_Info[0]);
1051 writel(0x00, &dp6_ptr->u.ic.S_Info[1]);
1052 writel(0x00, &dp6_ptr->u.ic.S_Info[2]);
1053 writel(0x00, &dp6_ptr->u.ic.S_Info[3]);
1054 writeb(0xfe, &dp6_ptr->u.ic.S_Cmd_Indx);
1055 writeb(0, &dp6_ptr->io.event);
1056 retries = INIT_RETRIES;
1057 gdth_delay(20);
1058 while (readb(&dp6_ptr->u.ic.S_Status) != 0xfe) {
1059 if (--retries == 0) {
1060 printk("GDT-PCI: Initialization error\n");
1061 iounmap(ha->brd);
1062 return 0;
1063 }
1064 gdth_delay(1);
1065 }
1066 writeb(0, &dp6_ptr->u.ic.S_Status);
1067 writeb(0xff, &dp6_ptr->io.irqdel);
1068
1069 ha->dma64_support = 0;
1070
1071 } else if (ha->pdev->device <= PCI_DEVICE_ID_VORTEX_GDT6555) { /* GDT6110, ... */
1072 ha->plx = (gdt6c_plx_regs *)pcistr->io;
1073 TRACE2(("init_pci_new() dpmem %lx irq %d\n",
1074 pcistr->dpmem,ha->irq));
1075 ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6c_dpram_str));
1076 if (ha->brd == NULL) {
1077 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1078 iounmap(ha->brd);
1079 return 0;
1080 }
1081 /* check and reset interface area */
1082 dp6c_ptr = ha->brd;
1083 writel(DPMEM_MAGIC, &dp6c_ptr->u);
1084 if (readl(&dp6c_ptr->u) != DPMEM_MAGIC) {
1085 printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
1086 pcistr->dpmem);
1087 found = FALSE;
1088 for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
1089 iounmap(ha->brd);
1090 ha->brd = ioremap(i, sizeof(ushort));
1091 if (ha->brd == NULL) {
1092 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1093 return 0;
1094 }
1095 if (readw(ha->brd) != 0xffff) {
1096 TRACE2(("init_pci_plx() address 0x%x busy\n", i));
1097 continue;
1098 }
1099 iounmap(ha->brd);
1100 pci_write_config_dword(pcistr->pdev,
1101 PCI_BASE_ADDRESS_2, i);
1102 ha->brd = ioremap(i, sizeof(gdt6c_dpram_str));
1103 if (ha->brd == NULL) {
1104 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1105 return 0;
1106 }
1107 dp6c_ptr = ha->brd;
1108 writel(DPMEM_MAGIC, &dp6c_ptr->u);
1109 if (readl(&dp6c_ptr->u) == DPMEM_MAGIC) {
1110 printk("GDT-PCI: Use free address at 0x%x\n", i);
1111 found = TRUE;
1112 break;
1113 }
1114 }
1115 if (!found) {
1116 printk("GDT-PCI: No free address found!\n");
1117 iounmap(ha->brd);
1118 return 0;
1119 }
1120 }
1121 memset_io(&dp6c_ptr->u, 0, sizeof(dp6c_ptr->u));
1122 if (readl(&dp6c_ptr->u) != 0) {
1123 printk("GDT-PCI: Initialization error (DPMEM write error)\n");
1124 iounmap(ha->brd);
1125 return 0;
1126 }
1127
1128 /* disable board interrupts, deinit services */
1129 outb(0x00,PTR2USHORT(&ha->plx->control1));
1130 outb(0xff,PTR2USHORT(&ha->plx->edoor_reg));
1131
1132 writeb(0x00, &dp6c_ptr->u.ic.S_Status);
1133 writeb(0x00, &dp6c_ptr->u.ic.Cmd_Index);
1134
1135 writel(pcistr->dpmem, &dp6c_ptr->u.ic.S_Info[0]);
1136 writeb(0xff, &dp6c_ptr->u.ic.S_Cmd_Indx);
1137
1138 outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
1139
1140 retries = INIT_RETRIES;
1141 gdth_delay(20);
1142 while (readb(&dp6c_ptr->u.ic.S_Status) != 0xff) {
1143 if (--retries == 0) {
1144 printk("GDT-PCI: Initialization error (DEINIT failed)\n");
1145 iounmap(ha->brd);
1146 return 0;
1147 }
1148 gdth_delay(1);
1149 }
1150 prot_ver = (unchar)readl(&dp6c_ptr->u.ic.S_Info[0]);
1151 writeb(0, &dp6c_ptr->u.ic.Status);
1152 if (prot_ver != PROTOCOL_VERSION) {
1153 printk("GDT-PCI: Illegal protocol version\n");
1154 iounmap(ha->brd);
1155 return 0;
1156 }
1157
1158 ha->type = GDT_PCINEW;
1159 ha->ic_all_size = sizeof(dp6c_ptr->u);
1160
1161 /* special command to controller BIOS */
1162 writel(0x00, &dp6c_ptr->u.ic.S_Info[0]);
1163 writel(0x00, &dp6c_ptr->u.ic.S_Info[1]);
1164 writel(0x00, &dp6c_ptr->u.ic.S_Info[2]);
1165 writel(0x00, &dp6c_ptr->u.ic.S_Info[3]);
1166 writeb(0xfe, &dp6c_ptr->u.ic.S_Cmd_Indx);
1167
1168 outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
1169
1170 retries = INIT_RETRIES;
1171 gdth_delay(20);
1172 while (readb(&dp6c_ptr->u.ic.S_Status) != 0xfe) {
1173 if (--retries == 0) {
1174 printk("GDT-PCI: Initialization error\n");
1175 iounmap(ha->brd);
1176 return 0;
1177 }
1178 gdth_delay(1);
1179 }
1180 writeb(0, &dp6c_ptr->u.ic.S_Status);
1181
1182 ha->dma64_support = 0;
1183
1184 } else { /* MPR */
1185 TRACE2(("init_pci_mpr() dpmem %lx irq %d\n",pcistr->dpmem,ha->irq));
1186 ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6m_dpram_str));
1187 if (ha->brd == NULL) {
1188 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1189 return 0;
1190 }
1191
1192 /* manipulate config. space to enable DPMEM, start RP controller */
1193 pci_read_config_word(pcistr->pdev, PCI_COMMAND, &command);
1194 command |= 6;
1195 pci_write_config_word(pcistr->pdev, PCI_COMMAND, command);
1196 if (pci_resource_start(pcistr->pdev, 8) == 1UL)
1197 pci_resource_start(pcistr->pdev, 8) = 0UL;
1198 i = 0xFEFF0001UL;
1199 pci_write_config_dword(pcistr->pdev, PCI_ROM_ADDRESS, i);
1200 gdth_delay(1);
1201 pci_write_config_dword(pcistr->pdev, PCI_ROM_ADDRESS,
1202 pci_resource_start(pcistr->pdev, 8));
1203
1204 dp6m_ptr = ha->brd;
1205
1206 /* Ensure that it is safe to access the non HW portions of DPMEM.
1207 * Aditional check needed for Xscale based RAID controllers */
1208 while( ((int)readb(&dp6m_ptr->i960r.sema0_reg) ) & 3 )
1209 gdth_delay(1);
1210
1211 /* check and reset interface area */
1212 writel(DPMEM_MAGIC, &dp6m_ptr->u);
1213 if (readl(&dp6m_ptr->u) != DPMEM_MAGIC) {
1214 printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
1215 pcistr->dpmem);
1216 found = FALSE;
1217 for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
1218 iounmap(ha->brd);
1219 ha->brd = ioremap(i, sizeof(ushort));
1220 if (ha->brd == NULL) {
1221 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1222 return 0;
1223 }
1224 if (readw(ha->brd) != 0xffff) {
1225 TRACE2(("init_pci_mpr() address 0x%x busy\n", i));
1226 continue;
1227 }
1228 iounmap(ha->brd);
1229 pci_write_config_dword(pcistr->pdev,
1230 PCI_BASE_ADDRESS_0, i);
1231 ha->brd = ioremap(i, sizeof(gdt6m_dpram_str));
1232 if (ha->brd == NULL) {
1233 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1234 return 0;
1235 }
1236 dp6m_ptr = ha->brd;
1237 writel(DPMEM_MAGIC, &dp6m_ptr->u);
1238 if (readl(&dp6m_ptr->u) == DPMEM_MAGIC) {
1239 printk("GDT-PCI: Use free address at 0x%x\n", i);
1240 found = TRUE;
1241 break;
1242 }
1243 }
1244 if (!found) {
1245 printk("GDT-PCI: No free address found!\n");
1246 iounmap(ha->brd);
1247 return 0;
1248 }
1249 }
1250 memset_io(&dp6m_ptr->u, 0, sizeof(dp6m_ptr->u));
1251
1252 /* disable board interrupts, deinit services */
1253 writeb(readb(&dp6m_ptr->i960r.edoor_en_reg) | 4,
1254 &dp6m_ptr->i960r.edoor_en_reg);
1255 writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
1256 writeb(0x00, &dp6m_ptr->u.ic.S_Status);
1257 writeb(0x00, &dp6m_ptr->u.ic.Cmd_Index);
1258
1259 writel(pcistr->dpmem, &dp6m_ptr->u.ic.S_Info[0]);
1260 writeb(0xff, &dp6m_ptr->u.ic.S_Cmd_Indx);
1261 writeb(1, &dp6m_ptr->i960r.ldoor_reg);
1262 retries = INIT_RETRIES;
1263 gdth_delay(20);
1264 while (readb(&dp6m_ptr->u.ic.S_Status) != 0xff) {
1265 if (--retries == 0) {
1266 printk("GDT-PCI: Initialization error (DEINIT failed)\n");
1267 iounmap(ha->brd);
1268 return 0;
1269 }
1270 gdth_delay(1);
1271 }
1272 prot_ver = (unchar)readl(&dp6m_ptr->u.ic.S_Info[0]);
1273 writeb(0, &dp6m_ptr->u.ic.S_Status);
1274 if (prot_ver != PROTOCOL_VERSION) {
1275 printk("GDT-PCI: Illegal protocol version\n");
1276 iounmap(ha->brd);
1277 return 0;
1278 }
1279
1280 ha->type = GDT_PCIMPR;
1281 ha->ic_all_size = sizeof(dp6m_ptr->u);
1282
1283 /* special command to controller BIOS */
1284 writel(0x00, &dp6m_ptr->u.ic.S_Info[0]);
1285 writel(0x00, &dp6m_ptr->u.ic.S_Info[1]);
1286 writel(0x00, &dp6m_ptr->u.ic.S_Info[2]);
1287 writel(0x00, &dp6m_ptr->u.ic.S_Info[3]);
1288 writeb(0xfe, &dp6m_ptr->u.ic.S_Cmd_Indx);
1289 writeb(1, &dp6m_ptr->i960r.ldoor_reg);
1290 retries = INIT_RETRIES;
1291 gdth_delay(20);
1292 while (readb(&dp6m_ptr->u.ic.S_Status) != 0xfe) {
1293 if (--retries == 0) {
1294 printk("GDT-PCI: Initialization error\n");
1295 iounmap(ha->brd);
1296 return 0;
1297 }
1298 gdth_delay(1);
1299 }
1300 writeb(0, &dp6m_ptr->u.ic.S_Status);
1301
1302 /* read FW version to detect 64-bit DMA support */
1303 writeb(0xfd, &dp6m_ptr->u.ic.S_Cmd_Indx);
1304 writeb(1, &dp6m_ptr->i960r.ldoor_reg);
1305 retries = INIT_RETRIES;
1306 gdth_delay(20);
1307 while (readb(&dp6m_ptr->u.ic.S_Status) != 0xfd) {
1308 if (--retries == 0) {
1309 printk("GDT-PCI: Initialization error (DEINIT failed)\n");
1310 iounmap(ha->brd);
1311 return 0;
1312 }
1313 gdth_delay(1);
1314 }
1315 prot_ver = (unchar)(readl(&dp6m_ptr->u.ic.S_Info[0]) >> 16);
1316 writeb(0, &dp6m_ptr->u.ic.S_Status);
1317 if (prot_ver < 0x2b) /* FW < x.43: no 64-bit DMA support */
1318 ha->dma64_support = 0;
1319 else
1320 ha->dma64_support = 1;
1321 }
1322
1323 return 1;
1324 }
1325 #endif /* CONFIG_PCI */
1326
1327 /* controller protocol functions */
1328
1329 static void __init gdth_enable_int(gdth_ha_str *ha)
1330 {
1331 ulong flags;
1332 gdt2_dpram_str __iomem *dp2_ptr;
1333 gdt6_dpram_str __iomem *dp6_ptr;
1334 gdt6m_dpram_str __iomem *dp6m_ptr;
1335
1336 TRACE(("gdth_enable_int() hanum %d\n",ha->hanum));
1337 spin_lock_irqsave(&ha->smp_lock, flags);
1338
1339 if (ha->type == GDT_EISA) {
1340 outb(0xff, ha->bmic + EDOORREG);
1341 outb(0xff, ha->bmic + EDENABREG);
1342 outb(0x01, ha->bmic + EINTENABREG);
1343 } else if (ha->type == GDT_ISA) {
1344 dp2_ptr = ha->brd;
1345 writeb(1, &dp2_ptr->io.irqdel);
1346 writeb(0, &dp2_ptr->u.ic.Cmd_Index);
1347 writeb(1, &dp2_ptr->io.irqen);
1348 } else if (ha->type == GDT_PCI) {
1349 dp6_ptr = ha->brd;
1350 writeb(1, &dp6_ptr->io.irqdel);
1351 writeb(0, &dp6_ptr->u.ic.Cmd_Index);
1352 writeb(1, &dp6_ptr->io.irqen);
1353 } else if (ha->type == GDT_PCINEW) {
1354 outb(0xff, PTR2USHORT(&ha->plx->edoor_reg));
1355 outb(0x03, PTR2USHORT(&ha->plx->control1));
1356 } else if (ha->type == GDT_PCIMPR) {
1357 dp6m_ptr = ha->brd;
1358 writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
1359 writeb(readb(&dp6m_ptr->i960r.edoor_en_reg) & ~4,
1360 &dp6m_ptr->i960r.edoor_en_reg);
1361 }
1362 spin_unlock_irqrestore(&ha->smp_lock, flags);
1363 }
1364
1365 /* return IStatus if interrupt was from this card else 0 */
1366 static unchar gdth_get_status(gdth_ha_str *ha)
1367 {
1368 unchar IStatus = 0;
1369
1370 TRACE(("gdth_get_status() irq %d ctr_count %d\n", ha->irq, gdth_ctr_count));
1371
1372 if (ha->type == GDT_EISA)
1373 IStatus = inb((ushort)ha->bmic + EDOORREG);
1374 else if (ha->type == GDT_ISA)
1375 IStatus =
1376 readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index);
1377 else if (ha->type == GDT_PCI)
1378 IStatus =
1379 readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index);
1380 else if (ha->type == GDT_PCINEW)
1381 IStatus = inb(PTR2USHORT(&ha->plx->edoor_reg));
1382 else if (ha->type == GDT_PCIMPR)
1383 IStatus =
1384 readb(&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.edoor_reg);
1385
1386 return IStatus;
1387 }
1388
1389 static int gdth_test_busy(gdth_ha_str *ha)
1390 {
1391 register int gdtsema0 = 0;
1392
1393 TRACE(("gdth_test_busy() hanum %d\n", ha->hanum));
1394
1395 if (ha->type == GDT_EISA)
1396 gdtsema0 = (int)inb(ha->bmic + SEMA0REG);
1397 else if (ha->type == GDT_ISA)
1398 gdtsema0 = (int)readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
1399 else if (ha->type == GDT_PCI)
1400 gdtsema0 = (int)readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
1401 else if (ha->type == GDT_PCINEW)
1402 gdtsema0 = (int)inb(PTR2USHORT(&ha->plx->sema0_reg));
1403 else if (ha->type == GDT_PCIMPR)
1404 gdtsema0 =
1405 (int)readb(&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.sema0_reg);
1406
1407 return (gdtsema0 & 1);
1408 }
1409
1410
1411 static int gdth_get_cmd_index(gdth_ha_str *ha)
1412 {
1413 int i;
1414
1415 TRACE(("gdth_get_cmd_index() hanum %d\n", ha->hanum));
1416
1417 for (i=0; i<GDTH_MAXCMDS; ++i) {
1418 if (ha->cmd_tab[i].cmnd == UNUSED_CMND) {
1419 ha->cmd_tab[i].cmnd = ha->pccb->RequestBuffer;
1420 ha->cmd_tab[i].service = ha->pccb->Service;
1421 ha->pccb->CommandIndex = (ulong32)i+2;
1422 return (i+2);
1423 }
1424 }
1425 return 0;
1426 }
1427
1428
1429 static void gdth_set_sema0(gdth_ha_str *ha)
1430 {
1431 TRACE(("gdth_set_sema0() hanum %d\n", ha->hanum));
1432
1433 if (ha->type == GDT_EISA) {
1434 outb(1, ha->bmic + SEMA0REG);
1435 } else if (ha->type == GDT_ISA) {
1436 writeb(1, &((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
1437 } else if (ha->type == GDT_PCI) {
1438 writeb(1, &((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
1439 } else if (ha->type == GDT_PCINEW) {
1440 outb(1, PTR2USHORT(&ha->plx->sema0_reg));
1441 } else if (ha->type == GDT_PCIMPR) {
1442 writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.sema0_reg);
1443 }
1444 }
1445
1446
1447 static void gdth_copy_command(gdth_ha_str *ha)
1448 {
1449 register gdth_cmd_str *cmd_ptr;
1450 register gdt6m_dpram_str __iomem *dp6m_ptr;
1451 register gdt6c_dpram_str __iomem *dp6c_ptr;
1452 gdt6_dpram_str __iomem *dp6_ptr;
1453 gdt2_dpram_str __iomem *dp2_ptr;
1454 ushort cp_count,dp_offset,cmd_no;
1455
1456 TRACE(("gdth_copy_command() hanum %d\n", ha->hanum));
1457
1458 cp_count = ha->cmd_len;
1459 dp_offset= ha->cmd_offs_dpmem;
1460 cmd_no = ha->cmd_cnt;
1461 cmd_ptr = ha->pccb;
1462
1463 ++ha->cmd_cnt;
1464 if (ha->type == GDT_EISA)
1465 return; /* no DPMEM, no copy */
1466
1467 /* set cpcount dword aligned */
1468 if (cp_count & 3)
1469 cp_count += (4 - (cp_count & 3));
1470
1471 ha->cmd_offs_dpmem += cp_count;
1472
1473 /* set offset and service, copy command to DPMEM */
1474 if (ha->type == GDT_ISA) {
1475 dp2_ptr = ha->brd;
1476 writew(dp_offset + DPMEM_COMMAND_OFFSET,
1477 &dp2_ptr->u.ic.comm_queue[cmd_no].offset);
1478 writew((ushort)cmd_ptr->Service,
1479 &dp2_ptr->u.ic.comm_queue[cmd_no].serv_id);
1480 memcpy_toio(&dp2_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
1481 } else if (ha->type == GDT_PCI) {
1482 dp6_ptr = ha->brd;
1483 writew(dp_offset + DPMEM_COMMAND_OFFSET,
1484 &dp6_ptr->u.ic.comm_queue[cmd_no].offset);
1485 writew((ushort)cmd_ptr->Service,
1486 &dp6_ptr->u.ic.comm_queue[cmd_no].serv_id);
1487 memcpy_toio(&dp6_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
1488 } else if (ha->type == GDT_PCINEW) {
1489 dp6c_ptr = ha->brd;
1490 writew(dp_offset + DPMEM_COMMAND_OFFSET,
1491 &dp6c_ptr->u.ic.comm_queue[cmd_no].offset);
1492 writew((ushort)cmd_ptr->Service,
1493 &dp6c_ptr->u.ic.comm_queue[cmd_no].serv_id);
1494 memcpy_toio(&dp6c_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
1495 } else if (ha->type == GDT_PCIMPR) {
1496 dp6m_ptr = ha->brd;
1497 writew(dp_offset + DPMEM_COMMAND_OFFSET,
1498 &dp6m_ptr->u.ic.comm_queue[cmd_no].offset);
1499 writew((ushort)cmd_ptr->Service,
1500 &dp6m_ptr->u.ic.comm_queue[cmd_no].serv_id);
1501 memcpy_toio(&dp6m_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
1502 }
1503 }
1504
1505
1506 static void gdth_release_event(gdth_ha_str *ha)
1507 {
1508 TRACE(("gdth_release_event() hanum %d\n", ha->hanum));
1509
1510 #ifdef GDTH_STATISTICS
1511 {
1512 ulong32 i,j;
1513 for (i=0,j=0; j<GDTH_MAXCMDS; ++j) {
1514 if (ha->cmd_tab[j].cmnd != UNUSED_CMND)
1515 ++i;
1516 }
1517 if (max_index < i) {
1518 max_index = i;
1519 TRACE3(("GDT: max_index = %d\n",(ushort)i));
1520 }
1521 }
1522 #endif
1523
1524 if (ha->pccb->OpCode == GDT_INIT)
1525 ha->pccb->Service |= 0x80;
1526
1527 if (ha->type == GDT_EISA) {
1528 if (ha->pccb->OpCode == GDT_INIT) /* store DMA buffer */
1529 outl(ha->ccb_phys, ha->bmic + MAILBOXREG);
1530 outb(ha->pccb->Service, ha->bmic + LDOORREG);
1531 } else if (ha->type == GDT_ISA) {
1532 writeb(0, &((gdt2_dpram_str __iomem *)ha->brd)->io.event);
1533 } else if (ha->type == GDT_PCI) {
1534 writeb(0, &((gdt6_dpram_str __iomem *)ha->brd)->io.event);
1535 } else if (ha->type == GDT_PCINEW) {
1536 outb(1, PTR2USHORT(&ha->plx->ldoor_reg));
1537 } else if (ha->type == GDT_PCIMPR) {
1538 writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.ldoor_reg);
1539 }
1540 }
1541
1542 static int gdth_wait(gdth_ha_str *ha, int index, ulong32 time)
1543 {
1544 int answer_found = FALSE;
1545 int wait_index = 0;
1546
1547 TRACE(("gdth_wait() hanum %d index %d time %d\n", ha->hanum, index, time));
1548
1549 if (index == 0)
1550 return 1; /* no wait required */
1551
1552 do {
1553 __gdth_interrupt(ha, true, &wait_index);
1554 if (wait_index == index) {
1555 answer_found = TRUE;
1556 break;
1557 }
1558 gdth_delay(1);
1559 } while (--time);
1560
1561 while (gdth_test_busy(ha))
1562 gdth_delay(0);
1563
1564 return (answer_found);
1565 }
1566
1567
1568 static int gdth_internal_cmd(gdth_ha_str *ha, unchar service, ushort opcode,
1569 ulong32 p1, ulong64 p2, ulong64 p3)
1570 {
1571 register gdth_cmd_str *cmd_ptr;
1572 int retries,index;
1573
1574 TRACE2(("gdth_internal_cmd() service %d opcode %d\n",service,opcode));
1575
1576 cmd_ptr = ha->pccb;
1577 memset((char*)cmd_ptr,0,sizeof(gdth_cmd_str));
1578
1579 /* make command */
1580 for (retries = INIT_RETRIES;;) {
1581 cmd_ptr->Service = service;
1582 cmd_ptr->RequestBuffer = INTERNAL_CMND;
1583 if (!(index=gdth_get_cmd_index(ha))) {
1584 TRACE(("GDT: No free command index found\n"));
1585 return 0;
1586 }
1587 gdth_set_sema0(ha);
1588 cmd_ptr->OpCode = opcode;
1589 cmd_ptr->BoardNode = LOCALBOARD;
1590 if (service == CACHESERVICE) {
1591 if (opcode == GDT_IOCTL) {
1592 cmd_ptr->u.ioctl.subfunc = p1;
1593 cmd_ptr->u.ioctl.channel = (ulong32)p2;
1594 cmd_ptr->u.ioctl.param_size = (ushort)p3;
1595 cmd_ptr->u.ioctl.p_param = ha->scratch_phys;
1596 } else {
1597 if (ha->cache_feat & GDT_64BIT) {
1598 cmd_ptr->u.cache64.DeviceNo = (ushort)p1;
1599 cmd_ptr->u.cache64.BlockNo = p2;
1600 } else {
1601 cmd_ptr->u.cache.DeviceNo = (ushort)p1;
1602 cmd_ptr->u.cache.BlockNo = (ulong32)p2;
1603 }
1604 }
1605 } else if (service == SCSIRAWSERVICE) {
1606 if (ha->raw_feat & GDT_64BIT) {
1607 cmd_ptr->u.raw64.direction = p1;
1608 cmd_ptr->u.raw64.bus = (unchar)p2;
1609 cmd_ptr->u.raw64.target = (unchar)p3;
1610 cmd_ptr->u.raw64.lun = (unchar)(p3 >> 8);
1611 } else {
1612 cmd_ptr->u.raw.direction = p1;
1613 cmd_ptr->u.raw.bus = (unchar)p2;
1614 cmd_ptr->u.raw.target = (unchar)p3;
1615 cmd_ptr->u.raw.lun = (unchar)(p3 >> 8);
1616 }
1617 } else if (service == SCREENSERVICE) {
1618 if (opcode == GDT_REALTIME) {
1619 *(ulong32 *)&cmd_ptr->u.screen.su.data[0] = p1;
1620 *(ulong32 *)&cmd_ptr->u.screen.su.data[4] = (ulong32)p2;
1621 *(ulong32 *)&cmd_ptr->u.screen.su.data[8] = (ulong32)p3;
1622 }
1623 }
1624 ha->cmd_len = sizeof(gdth_cmd_str);
1625 ha->cmd_offs_dpmem = 0;
1626 ha->cmd_cnt = 0;
1627 gdth_copy_command(ha);
1628 gdth_release_event(ha);
1629 gdth_delay(20);
1630 if (!gdth_wait(ha, index, INIT_TIMEOUT)) {
1631 printk("GDT: Initialization error (timeout service %d)\n",service);
1632 return 0;
1633 }
1634 if (ha->status != S_BSY || --retries == 0)
1635 break;
1636 gdth_delay(1);
1637 }
1638
1639 return (ha->status != S_OK ? 0:1);
1640 }
1641
1642
1643 /* search for devices */
1644
1645 static int __init gdth_search_drives(gdth_ha_str *ha)
1646 {
1647 ushort cdev_cnt, i;
1648 int ok;
1649 ulong32 bus_no, drv_cnt, drv_no, j;
1650 gdth_getch_str *chn;
1651 gdth_drlist_str *drl;
1652 gdth_iochan_str *ioc;
1653 gdth_raw_iochan_str *iocr;
1654 gdth_arcdl_str *alst;
1655 gdth_alist_str *alst2;
1656 gdth_oem_str_ioctl *oemstr;
1657 #ifdef INT_COAL
1658 gdth_perf_modes *pmod;
1659 #endif
1660
1661 #ifdef GDTH_RTC
1662 unchar rtc[12];
1663 ulong flags;
1664 #endif
1665
1666 TRACE(("gdth_search_drives() hanum %d\n", ha->hanum));
1667 ok = 0;
1668
1669 /* initialize controller services, at first: screen service */
1670 ha->screen_feat = 0;
1671 if (!force_dma32) {
1672 ok = gdth_internal_cmd(ha, SCREENSERVICE, GDT_X_INIT_SCR, 0, 0, 0);
1673 if (ok)
1674 ha->screen_feat = GDT_64BIT;
1675 }
1676 if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
1677 ok = gdth_internal_cmd(ha, SCREENSERVICE, GDT_INIT, 0, 0, 0);
1678 if (!ok) {
1679 printk("GDT-HA %d: Initialization error screen service (code %d)\n",
1680 ha->hanum, ha->status);
1681 return 0;
1682 }
1683 TRACE2(("gdth_search_drives(): SCREENSERVICE initialized\n"));
1684
1685 #ifdef GDTH_RTC
1686 /* read realtime clock info, send to controller */
1687 /* 1. wait for the falling edge of update flag */
1688 spin_lock_irqsave(&rtc_lock, flags);
1689 for (j = 0; j < 1000000; ++j)
1690 if (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP)
1691 break;
1692 for (j = 0; j < 1000000; ++j)
1693 if (!(CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP))
1694 break;
1695 /* 2. read info */
1696 do {
1697 for (j = 0; j < 12; ++j)
1698 rtc[j] = CMOS_READ(j);
1699 } while (rtc[0] != CMOS_READ(0));
1700 spin_unlock_irqrestore(&rtc_lock, flags);
1701 TRACE2(("gdth_search_drives(): RTC: %x/%x/%x\n",*(ulong32 *)&rtc[0],
1702 *(ulong32 *)&rtc[4], *(ulong32 *)&rtc[8]));
1703 /* 3. send to controller firmware */
1704 gdth_internal_cmd(ha, SCREENSERVICE, GDT_REALTIME, *(ulong32 *)&rtc[0],
1705 *(ulong32 *)&rtc[4], *(ulong32 *)&rtc[8]);
1706 #endif
1707
1708 /* unfreeze all IOs */
1709 gdth_internal_cmd(ha, CACHESERVICE, GDT_UNFREEZE_IO, 0, 0, 0);
1710
1711 /* initialize cache service */
1712 ha->cache_feat = 0;
1713 if (!force_dma32) {
1714 ok = gdth_internal_cmd(ha, CACHESERVICE, GDT_X_INIT_HOST, LINUX_OS,
1715 0, 0);
1716 if (ok)
1717 ha->cache_feat = GDT_64BIT;
1718 }
1719 if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
1720 ok = gdth_internal_cmd(ha, CACHESERVICE, GDT_INIT, LINUX_OS, 0, 0);
1721 if (!ok) {
1722 printk("GDT-HA %d: Initialization error cache service (code %d)\n",
1723 ha->hanum, ha->status);
1724 return 0;
1725 }
1726 TRACE2(("gdth_search_drives(): CACHESERVICE initialized\n"));
1727 cdev_cnt = (ushort)ha->info;
1728 ha->fw_vers = ha->service;
1729
1730 #ifdef INT_COAL
1731 if (ha->type == GDT_PCIMPR) {
1732 /* set perf. modes */
1733 pmod = (gdth_perf_modes *)ha->pscratch;
1734 pmod->version = 1;
1735 pmod->st_mode = 1; /* enable one status buffer */
1736 *((ulong64 *)&pmod->st_buff_addr1) = ha->coal_stat_phys;
1737 pmod->st_buff_indx1 = COALINDEX;
1738 pmod->st_buff_addr2 = 0;
1739 pmod->st_buff_u_addr2 = 0;
1740 pmod->st_buff_indx2 = 0;
1741 pmod->st_buff_size = sizeof(gdth_coal_status) * MAXOFFSETS;
1742 pmod->cmd_mode = 0; // disable all cmd buffers
1743 pmod->cmd_buff_addr1 = 0;
1744 pmod->cmd_buff_u_addr1 = 0;
1745 pmod->cmd_buff_indx1 = 0;
1746 pmod->cmd_buff_addr2 = 0;
1747 pmod->cmd_buff_u_addr2 = 0;
1748 pmod->cmd_buff_indx2 = 0;
1749 pmod->cmd_buff_size = 0;
1750 pmod->reserved1 = 0;
1751 pmod->reserved2 = 0;
1752 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, SET_PERF_MODES,
1753 INVALID_CHANNEL,sizeof(gdth_perf_modes))) {
1754 printk("GDT-HA %d: Interrupt coalescing activated\n", ha->hanum);
1755 }
1756 }
1757 #endif
1758
1759 /* detect number of buses - try new IOCTL */
1760 iocr = (gdth_raw_iochan_str *)ha->pscratch;
1761 iocr->hdr.version = 0xffffffff;
1762 iocr->hdr.list_entries = MAXBUS;
1763 iocr->hdr.first_chan = 0;
1764 iocr->hdr.last_chan = MAXBUS-1;
1765 iocr->hdr.list_offset = GDTOFFSOF(gdth_raw_iochan_str, list[0]);
1766 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, IOCHAN_RAW_DESC,
1767 INVALID_CHANNEL,sizeof(gdth_raw_iochan_str))) {
1768 TRACE2(("IOCHAN_RAW_DESC supported!\n"));
1769 ha->bus_cnt = iocr->hdr.chan_count;
1770 for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
1771 if (iocr->list[bus_no].proc_id < MAXID)
1772 ha->bus_id[bus_no] = iocr->list[bus_no].proc_id;
1773 else
1774 ha->bus_id[bus_no] = 0xff;
1775 }
1776 } else {
1777 /* old method */
1778 chn = (gdth_getch_str *)ha->pscratch;
1779 for (bus_no = 0; bus_no < MAXBUS; ++bus_no) {
1780 chn->channel_no = bus_no;
1781 if (!gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
1782 SCSI_CHAN_CNT | L_CTRL_PATTERN,
1783 IO_CHANNEL | INVALID_CHANNEL,
1784 sizeof(gdth_getch_str))) {
1785 if (bus_no == 0) {
1786 printk("GDT-HA %d: Error detecting channel count (0x%x)\n",
1787 ha->hanum, ha->status);
1788 return 0;
1789 }
1790 break;
1791 }
1792 if (chn->siop_id < MAXID)
1793 ha->bus_id[bus_no] = chn->siop_id;
1794 else
1795 ha->bus_id[bus_no] = 0xff;
1796 }
1797 ha->bus_cnt = (unchar)bus_no;
1798 }
1799 TRACE2(("gdth_search_drives() %d channels\n",ha->bus_cnt));
1800
1801 /* read cache configuration */
1802 if (!gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, CACHE_INFO,
1803 INVALID_CHANNEL,sizeof(gdth_cinfo_str))) {
1804 printk("GDT-HA %d: Initialization error cache service (code %d)\n",
1805 ha->hanum, ha->status);
1806 return 0;
1807 }
1808 ha->cpar = ((gdth_cinfo_str *)ha->pscratch)->cpar;
1809 TRACE2(("gdth_search_drives() cinfo: vs %x sta %d str %d dw %d b %d\n",
1810 ha->cpar.version,ha->cpar.state,ha->cpar.strategy,
1811 ha->cpar.write_back,ha->cpar.block_size));
1812
1813 /* read board info and features */
1814 ha->more_proc = FALSE;
1815 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, BOARD_INFO,
1816 INVALID_CHANNEL,sizeof(gdth_binfo_str))) {
1817 memcpy(&ha->binfo, (gdth_binfo_str *)ha->pscratch,
1818 sizeof(gdth_binfo_str));
1819 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, BOARD_FEATURES,
1820 INVALID_CHANNEL,sizeof(gdth_bfeat_str))) {
1821 TRACE2(("BOARD_INFO/BOARD_FEATURES supported\n"));
1822 ha->bfeat = *(gdth_bfeat_str *)ha->pscratch;
1823 ha->more_proc = TRUE;
1824 }
1825 } else {
1826 TRACE2(("BOARD_INFO requires firmware >= 1.10/2.08\n"));
1827 strcpy(ha->binfo.type_string, gdth_ctr_name(ha));
1828 }
1829 TRACE2(("Controller name: %s\n",ha->binfo.type_string));
1830
1831 /* read more informations */
1832 if (ha->more_proc) {
1833 /* physical drives, channel addresses */
1834 ioc = (gdth_iochan_str *)ha->pscratch;
1835 ioc->hdr.version = 0xffffffff;
1836 ioc->hdr.list_entries = MAXBUS;
1837 ioc->hdr.first_chan = 0;
1838 ioc->hdr.last_chan = MAXBUS-1;
1839 ioc->hdr.list_offset = GDTOFFSOF(gdth_iochan_str, list[0]);
1840 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, IOCHAN_DESC,
1841 INVALID_CHANNEL,sizeof(gdth_iochan_str))) {
1842 for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
1843 ha->raw[bus_no].address = ioc->list[bus_no].address;
1844 ha->raw[bus_no].local_no = ioc->list[bus_no].local_no;
1845 }
1846 } else {
1847 for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
1848 ha->raw[bus_no].address = IO_CHANNEL;
1849 ha->raw[bus_no].local_no = bus_no;
1850 }
1851 }
1852 for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
1853 chn = (gdth_getch_str *)ha->pscratch;
1854 chn->channel_no = ha->raw[bus_no].local_no;
1855 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
1856 SCSI_CHAN_CNT | L_CTRL_PATTERN,
1857 ha->raw[bus_no].address | INVALID_CHANNEL,
1858 sizeof(gdth_getch_str))) {
1859 ha->raw[bus_no].pdev_cnt = chn->drive_cnt;
1860 TRACE2(("Channel %d: %d phys. drives\n",
1861 bus_no,chn->drive_cnt));
1862 }
1863 if (ha->raw[bus_no].pdev_cnt > 0) {
1864 drl = (gdth_drlist_str *)ha->pscratch;
1865 drl->sc_no = ha->raw[bus_no].local_no;
1866 drl->sc_cnt = ha->raw[bus_no].pdev_cnt;
1867 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
1868 SCSI_DR_LIST | L_CTRL_PATTERN,
1869 ha->raw[bus_no].address | INVALID_CHANNEL,
1870 sizeof(gdth_drlist_str))) {
1871 for (j = 0; j < ha->raw[bus_no].pdev_cnt; ++j)
1872 ha->raw[bus_no].id_list[j] = drl->sc_list[j];
1873 } else {
1874 ha->raw[bus_no].pdev_cnt = 0;
1875 }
1876 }
1877 }
1878
1879 /* logical drives */
1880 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, CACHE_DRV_CNT,
1881 INVALID_CHANNEL,sizeof(ulong32))) {
1882 drv_cnt = *(ulong32 *)ha->pscratch;
1883 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, CACHE_DRV_LIST,
1884 INVALID_CHANNEL,drv_cnt * sizeof(ulong32))) {
1885 for (j = 0; j < drv_cnt; ++j) {
1886 drv_no = ((ulong32 *)ha->pscratch)[j];
1887 if (drv_no < MAX_LDRIVES) {
1888 ha->hdr[drv_no].is_logdrv = TRUE;
1889 TRACE2(("Drive %d is log. drive\n",drv_no));
1890 }
1891 }
1892 }
1893 alst = (gdth_arcdl_str *)ha->pscratch;
1894 alst->entries_avail = MAX_LDRIVES;
1895 alst->first_entry = 0;
1896 alst->list_offset = GDTOFFSOF(gdth_arcdl_str, list[0]);
1897 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
1898 ARRAY_DRV_LIST2 | LA_CTRL_PATTERN,
1899 INVALID_CHANNEL, sizeof(gdth_arcdl_str) +
1900 (alst->entries_avail-1) * sizeof(gdth_alist_str))) {
1901 for (j = 0; j < alst->entries_init; ++j) {
1902 ha->hdr[j].is_arraydrv = alst->list[j].is_arrayd;
1903 ha->hdr[j].is_master = alst->list[j].is_master;
1904 ha->hdr[j].is_parity = alst->list[j].is_parity;
1905 ha->hdr[j].is_hotfix = alst->list[j].is_hotfix;
1906 ha->hdr[j].master_no = alst->list[j].cd_handle;
1907 }
1908 } else if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
1909 ARRAY_DRV_LIST | LA_CTRL_PATTERN,
1910 0, 35 * sizeof(gdth_alist_str))) {
1911 for (j = 0; j < 35; ++j) {
1912 alst2 = &((gdth_alist_str *)ha->pscratch)[j];
1913 ha->hdr[j].is_arraydrv = alst2->is_arrayd;
1914 ha->hdr[j].is_master = alst2->is_master;
1915 ha->hdr[j].is_parity = alst2->is_parity;
1916 ha->hdr[j].is_hotfix = alst2->is_hotfix;
1917 ha->hdr[j].master_no = alst2->cd_handle;
1918 }
1919 }
1920 }
1921 }
1922
1923 /* initialize raw service */
1924 ha->raw_feat = 0;
1925 if (!force_dma32) {
1926 ok = gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_X_INIT_RAW, 0, 0, 0);
1927 if (ok)
1928 ha->raw_feat = GDT_64BIT;
1929 }
1930 if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
1931 ok = gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_INIT, 0, 0, 0);
1932 if (!ok) {
1933 printk("GDT-HA %d: Initialization error raw service (code %d)\n",
1934 ha->hanum, ha->status);
1935 return 0;
1936 }
1937 TRACE2(("gdth_search_drives(): RAWSERVICE initialized\n"));
1938
1939 /* set/get features raw service (scatter/gather) */
1940 if (gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_SET_FEAT, SCATTER_GATHER,
1941 0, 0)) {
1942 TRACE2(("gdth_search_drives(): set features RAWSERVICE OK\n"));
1943 if (gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_GET_FEAT, 0, 0, 0)) {
1944 TRACE2(("gdth_search_dr(): get feat RAWSERVICE %d\n",
1945 ha->info));
1946 ha->raw_feat |= (ushort)ha->info;
1947 }
1948 }
1949
1950 /* set/get features cache service (equal to raw service) */
1951 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_SET_FEAT, 0,
1952 SCATTER_GATHER,0)) {
1953 TRACE2(("gdth_search_drives(): set features CACHESERVICE OK\n"));
1954 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_GET_FEAT, 0, 0, 0)) {
1955 TRACE2(("gdth_search_dr(): get feat CACHESERV. %d\n",
1956 ha->info));
1957 ha->cache_feat |= (ushort)ha->info;
1958 }
1959 }
1960
1961 /* reserve drives for raw service */
1962 if (reserve_mode != 0) {
1963 gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_RESERVE_ALL,
1964 reserve_mode == 1 ? 1 : 3, 0, 0);
1965 TRACE2(("gdth_search_drives(): RESERVE_ALL code %d\n",
1966 ha->status));
1967 }
1968 for (i = 0; i < MAX_RES_ARGS; i += 4) {
1969 if (reserve_list[i] == ha->hanum && reserve_list[i+1] < ha->bus_cnt &&
1970 reserve_list[i+2] < ha->tid_cnt && reserve_list[i+3] < MAXLUN) {
1971 TRACE2(("gdth_search_drives(): reserve ha %d bus %d id %d lun %d\n",
1972 reserve_list[i], reserve_list[i+1],
1973 reserve_list[i+2], reserve_list[i+3]));
1974 if (!gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_RESERVE, 0,
1975 reserve_list[i+1], reserve_list[i+2] |
1976 (reserve_list[i+3] << 8))) {
1977 printk("GDT-HA %d: Error raw service (RESERVE, code %d)\n",
1978 ha->hanum, ha->status);
1979 }
1980 }
1981 }
1982
1983 /* Determine OEM string using IOCTL */
1984 oemstr = (gdth_oem_str_ioctl *)ha->pscratch;
1985 oemstr->params.ctl_version = 0x01;
1986 oemstr->params.buffer_size = sizeof(oemstr->text);
1987 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
1988 CACHE_READ_OEM_STRING_RECORD,INVALID_CHANNEL,
1989 sizeof(gdth_oem_str_ioctl))) {
1990 TRACE2(("gdth_search_drives(): CACHE_READ_OEM_STRING_RECORD OK\n"));
1991 printk("GDT-HA %d: Vendor: %s Name: %s\n",
1992 ha->hanum, oemstr->text.oem_company_name, ha->binfo.type_string);
1993 /* Save the Host Drive inquiry data */
1994 strlcpy(ha->oem_name,oemstr->text.scsi_host_drive_inquiry_vendor_id,
1995 sizeof(ha->oem_name));
1996 } else {
1997 /* Old method, based on PCI ID */
1998 TRACE2(("gdth_search_drives(): CACHE_READ_OEM_STRING_RECORD failed\n"));
1999 printk("GDT-HA %d: Name: %s\n",
2000 ha->hanum, ha->binfo.type_string);
2001 if (ha->oem_id == OEM_ID_INTEL)
2002 strlcpy(ha->oem_name,"Intel ", sizeof(ha->oem_name));
2003 else
2004 strlcpy(ha->oem_name,"ICP ", sizeof(ha->oem_name));
2005 }
2006
2007 /* scanning for host drives */
2008 for (i = 0; i < cdev_cnt; ++i)
2009 gdth_analyse_hdrive(ha, i);
2010
2011 TRACE(("gdth_search_drives() OK\n"));
2012 return 1;
2013 }
2014
2015 static int gdth_analyse_hdrive(gdth_ha_str *ha, ushort hdrive)
2016 {
2017 ulong32 drv_cyls;
2018 int drv_hds, drv_secs;
2019
2020 TRACE(("gdth_analyse_hdrive() hanum %d drive %d\n", ha->hanum, hdrive));
2021 if (hdrive >= MAX_HDRIVES)
2022 return 0;
2023
2024 if (!gdth_internal_cmd(ha, CACHESERVICE, GDT_INFO, hdrive, 0, 0))
2025 return 0;
2026 ha->hdr[hdrive].present = TRUE;
2027 ha->hdr[hdrive].size = ha->info;
2028
2029 /* evaluate mapping (sectors per head, heads per cylinder) */
2030 ha->hdr[hdrive].size &= ~SECS32;
2031 if (ha->info2 == 0) {
2032 gdth_eval_mapping(ha->hdr[hdrive].size,&drv_cyls,&drv_hds,&drv_secs);
2033 } else {
2034 drv_hds = ha->info2 & 0xff;
2035 drv_secs = (ha->info2 >> 8) & 0xff;
2036 drv_cyls = (ulong32)ha->hdr[hdrive].size / drv_hds / drv_secs;
2037 }
2038 ha->hdr[hdrive].heads = (unchar)drv_hds;
2039 ha->hdr[hdrive].secs = (unchar)drv_secs;
2040 /* round size */
2041 ha->hdr[hdrive].size = drv_cyls * drv_hds * drv_secs;
2042
2043 if (ha->cache_feat & GDT_64BIT) {
2044 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_X_INFO, hdrive, 0, 0)
2045 && ha->info2 != 0) {
2046 ha->hdr[hdrive].size = ((ulong64)ha->info2 << 32) | ha->info;
2047 }
2048 }
2049 TRACE2(("gdth_search_dr() cdr. %d size %d hds %d scs %d\n",
2050 hdrive,ha->hdr[hdrive].size,drv_hds,drv_secs));
2051
2052 /* get informations about device */
2053 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_DEVTYPE, hdrive, 0, 0)) {
2054 TRACE2(("gdth_search_dr() cache drive %d devtype %d\n",
2055 hdrive,ha->info));
2056 ha->hdr[hdrive].devtype = (ushort)ha->info;
2057 }
2058
2059 /* cluster info */
2060 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_CLUST_INFO, hdrive, 0, 0)) {
2061 TRACE2(("gdth_search_dr() cache drive %d cluster info %d\n",
2062 hdrive,ha->info));
2063 if (!shared_access)
2064 ha->hdr[hdrive].cluster_type = (unchar)ha->info;
2065 }
2066
2067 /* R/W attributes */
2068 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_RW_ATTRIBS, hdrive, 0, 0)) {
2069 TRACE2(("gdth_search_dr() cache drive %d r/w attrib. %d\n",
2070 hdrive,ha->info));
2071 ha->hdr[hdrive].rw_attribs = (unchar)ha->info;
2072 }
2073
2074 return 1;
2075 }
2076
2077
2078 /* command queueing/sending functions */
2079
2080 static void gdth_putq(gdth_ha_str *ha, Scsi_Cmnd *scp, unchar priority)
2081 {
2082 struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
2083 register Scsi_Cmnd *pscp;
2084 register Scsi_Cmnd *nscp;
2085 ulong flags;
2086 unchar b, t;
2087
2088 TRACE(("gdth_putq() priority %d\n",priority));
2089 spin_lock_irqsave(&ha->smp_lock, flags);
2090
2091 if (!cmndinfo->internal_command) {
2092 cmndinfo->priority = priority;
2093 b = scp->device->channel;
2094 t = scp->device->id;
2095 if (priority >= DEFAULT_PRI) {
2096 if ((b != ha->virt_bus && ha->raw[BUS_L2P(ha,b)].lock) ||
2097 (b==ha->virt_bus && t<MAX_HDRIVES && ha->hdr[t].lock)) {
2098 TRACE2(("gdth_putq(): locked IO ->update_timeout()\n"));
2099 cmndinfo->timeout = gdth_update_timeout(scp, 0);
2100 }
2101 }
2102 }
2103
2104 if (ha->req_first==NULL) {
2105 ha->req_first = scp; /* queue was empty */
2106 scp->SCp.ptr = NULL;
2107 } else { /* queue not empty */
2108 pscp = ha->req_first;
2109 nscp = (Scsi_Cmnd *)pscp->SCp.ptr;
2110 /* priority: 0-highest,..,0xff-lowest */
2111 while (nscp && gdth_cmnd_priv(nscp)->priority <= priority) {
2112 pscp = nscp;
2113 nscp = (Scsi_Cmnd *)pscp->SCp.ptr;
2114 }
2115 pscp->SCp.ptr = (char *)scp;
2116 scp->SCp.ptr = (char *)nscp;
2117 }
2118 spin_unlock_irqrestore(&ha->smp_lock, flags);
2119
2120 #ifdef GDTH_STATISTICS
2121 flags = 0;
2122 for (nscp=ha->req_first; nscp; nscp=(Scsi_Cmnd*)nscp->SCp.ptr)
2123 ++flags;
2124 if (max_rq < flags) {
2125 max_rq = flags;
2126 TRACE3(("GDT: max_rq = %d\n",(ushort)max_rq));
2127 }
2128 #endif
2129 }
2130
2131 static void gdth_next(gdth_ha_str *ha)
2132 {
2133 register Scsi_Cmnd *pscp;
2134 register Scsi_Cmnd *nscp;
2135 unchar b, t, l, firsttime;
2136 unchar this_cmd, next_cmd;
2137 ulong flags = 0;
2138 int cmd_index;
2139
2140 TRACE(("gdth_next() hanum %d\n", ha->hanum));
2141 if (!gdth_polling)
2142 spin_lock_irqsave(&ha->smp_lock, flags);
2143
2144 ha->cmd_cnt = ha->cmd_offs_dpmem = 0;
2145 this_cmd = firsttime = TRUE;
2146 next_cmd = gdth_polling ? FALSE:TRUE;
2147 cmd_index = 0;
2148
2149 for (nscp = pscp = ha->req_first; nscp; nscp = (Scsi_Cmnd *)nscp->SCp.ptr) {
2150 struct gdth_cmndinfo *nscp_cmndinfo = gdth_cmnd_priv(nscp);
2151 if (nscp != pscp && nscp != (Scsi_Cmnd *)pscp->SCp.ptr)
2152 pscp = (Scsi_Cmnd *)pscp->SCp.ptr;
2153 if (!nscp_cmndinfo->internal_command) {
2154 b = nscp->device->channel;
2155 t = nscp->device->id;
2156 l = nscp->device->lun;
2157 if (nscp_cmndinfo->priority >= DEFAULT_PRI) {
2158 if ((b != ha->virt_bus && ha->raw[BUS_L2P(ha,b)].lock) ||
2159 (b == ha->virt_bus && t < MAX_HDRIVES && ha->hdr[t].lock))
2160 continue;
2161 }
2162 } else
2163 b = t = l = 0;
2164
2165 if (firsttime) {
2166 if (gdth_test_busy(ha)) { /* controller busy ? */
2167 TRACE(("gdth_next() controller %d busy !\n", ha->hanum));
2168 if (!gdth_polling) {
2169 spin_unlock_irqrestore(&ha->smp_lock, flags);
2170 return;
2171 }
2172 while (gdth_test_busy(ha))
2173 gdth_delay(1);
2174 }
2175 firsttime = FALSE;
2176 }
2177
2178 if (!nscp_cmndinfo->internal_command) {
2179 if (nscp_cmndinfo->phase == -1) {
2180 nscp_cmndinfo->phase = CACHESERVICE; /* default: cache svc. */
2181 if (nscp->cmnd[0] == TEST_UNIT_READY) {
2182 TRACE2(("TEST_UNIT_READY Bus %d Id %d LUN %d\n",
2183 b, t, l));
2184 /* TEST_UNIT_READY -> set scan mode */
2185 if ((ha->scan_mode & 0x0f) == 0) {
2186 if (b == 0 && t == 0 && l == 0) {
2187 ha->scan_mode |= 1;
2188 TRACE2(("Scan mode: 0x%x\n", ha->scan_mode));
2189 }
2190 } else if ((ha->scan_mode & 0x0f) == 1) {
2191 if (b == 0 && ((t == 0 && l == 1) ||
2192 (t == 1 && l == 0))) {
2193 nscp_cmndinfo->OpCode = GDT_SCAN_START;
2194 nscp_cmndinfo->phase = ((ha->scan_mode & 0x10 ? 1:0) << 8)
2195 | SCSIRAWSERVICE;
2196 ha->scan_mode = 0x12;
2197 TRACE2(("Scan mode: 0x%x (SCAN_START)\n",
2198 ha->scan_mode));
2199 } else {
2200 ha->scan_mode &= 0x10;
2201 TRACE2(("Scan mode: 0x%x\n", ha->scan_mode));
2202 }
2203 } else if (ha->scan_mode == 0x12) {
2204 if (b == ha->bus_cnt && t == ha->tid_cnt-1) {
2205 nscp_cmndinfo->phase = SCSIRAWSERVICE;
2206 nscp_cmndinfo->OpCode = GDT_SCAN_END;
2207 ha->scan_mode &= 0x10;
2208 TRACE2(("Scan mode: 0x%x (SCAN_END)\n",
2209 ha->scan_mode));
2210 }
2211 }
2212 }
2213 if (b == ha->virt_bus && nscp->cmnd[0] != INQUIRY &&
2214 nscp->cmnd[0] != READ_CAPACITY && nscp->cmnd[0] != MODE_SENSE &&
2215 (ha->hdr[t].cluster_type & CLUSTER_DRIVE)) {
2216 /* always GDT_CLUST_INFO! */
2217 nscp_cmndinfo->OpCode = GDT_CLUST_INFO;
2218 }
2219 }
2220 }
2221
2222 if (nscp_cmndinfo->OpCode != -1) {
2223 if ((nscp_cmndinfo->phase & 0xff) == CACHESERVICE) {
2224 if (!(cmd_index=gdth_fill_cache_cmd(ha, nscp, t)))
2225 this_cmd = FALSE;
2226 next_cmd = FALSE;
2227 } else if ((nscp_cmndinfo->phase & 0xff) == SCSIRAWSERVICE) {
2228 if (!(cmd_index=gdth_fill_raw_cmd(ha, nscp, BUS_L2P(ha, b))))
2229 this_cmd = FALSE;
2230 next_cmd = FALSE;
2231 } else {
2232 memset((char*)nscp->sense_buffer,0,16);
2233 nscp->sense_buffer[0] = 0x70;
2234 nscp->sense_buffer[2] = NOT_READY;
2235 nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
2236 if (!nscp_cmndinfo->wait_for_completion)
2237 nscp_cmndinfo->wait_for_completion++;
2238 else
2239 gdth_scsi_done(nscp);
2240 }
2241 } else if (gdth_cmnd_priv(nscp)->internal_command) {
2242 if (!(cmd_index=gdth_special_cmd(ha, nscp)))
2243 this_cmd = FALSE;
2244 next_cmd = FALSE;
2245 } else if (b != ha->virt_bus) {
2246 if (ha->raw[BUS_L2P(ha,b)].io_cnt[t] >= GDTH_MAX_RAW ||
2247 !(cmd_index=gdth_fill_raw_cmd(ha, nscp, BUS_L2P(ha, b))))
2248 this_cmd = FALSE;
2249 else
2250 ha->raw[BUS_L2P(ha,b)].io_cnt[t]++;
2251 } else if (t >= MAX_HDRIVES || !ha->hdr[t].present || l != 0) {
2252 TRACE2(("Command 0x%x to bus %d id %d lun %d -> IGNORE\n",
2253 nscp->cmnd[0], b, t, l));
2254 nscp->result = DID_BAD_TARGET << 16;
2255 if (!nscp_cmndinfo->wait_for_completion)
2256 nscp_cmndinfo->wait_for_completion++;
2257 else
2258 gdth_scsi_done(nscp);
2259 } else {
2260 switch (nscp->cmnd[0]) {
2261 case TEST_UNIT_READY:
2262 case INQUIRY:
2263 case REQUEST_SENSE:
2264 case READ_CAPACITY:
2265 case VERIFY:
2266 case START_STOP:
2267 case MODE_SENSE:
2268 case SERVICE_ACTION_IN:
2269 TRACE(("cache cmd %x/%x/%x/%x/%x/%x\n",nscp->cmnd[0],
2270 nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
2271 nscp->cmnd[4],nscp->cmnd[5]));
2272 if (ha->hdr[t].media_changed && nscp->cmnd[0] != INQUIRY) {
2273 /* return UNIT_ATTENTION */
2274 TRACE2(("cmd 0x%x target %d: UNIT_ATTENTION\n",
2275 nscp->cmnd[0], t));
2276 ha->hdr[t].media_changed = FALSE;
2277 memset((char*)nscp->sense_buffer,0,16);
2278 nscp->sense_buffer[0] = 0x70;
2279 nscp->sense_buffer[2] = UNIT_ATTENTION;
2280 nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
2281 if (!nscp_cmndinfo->wait_for_completion)
2282 nscp_cmndinfo->wait_for_completion++;
2283 else
2284 gdth_scsi_done(nscp);
2285 } else if (gdth_internal_cache_cmd(ha, nscp))
2286 gdth_scsi_done(nscp);
2287 break;
2288
2289 case ALLOW_MEDIUM_REMOVAL:
2290 TRACE(("cache cmd %x/%x/%x/%x/%x/%x\n",nscp->cmnd[0],
2291 nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
2292 nscp->cmnd[4],nscp->cmnd[5]));
2293 if ( (nscp->cmnd[4]&1) && !(ha->hdr[t].devtype&1) ) {
2294 TRACE(("Prevent r. nonremov. drive->do nothing\n"));
2295 nscp->result = DID_OK << 16;
2296 nscp->sense_buffer[0] = 0;
2297 if (!nscp_cmndinfo->wait_for_completion)
2298 nscp_cmndinfo->wait_for_completion++;
2299 else
2300 gdth_scsi_done(nscp);
2301 } else {
2302 nscp->cmnd[3] = (ha->hdr[t].devtype&1) ? 1:0;
2303 TRACE(("Prevent/allow r. %d rem. drive %d\n",
2304 nscp->cmnd[4],nscp->cmnd[3]));
2305 if (!(cmd_index=gdth_fill_cache_cmd(ha, nscp, t)))
2306 this_cmd = FALSE;
2307 }
2308 break;
2309
2310 case RESERVE:
2311 case RELEASE:
2312 TRACE2(("cache cmd %s\n",nscp->cmnd[0] == RESERVE ?
2313 "RESERVE" : "RELEASE"));
2314 if (!(cmd_index=gdth_fill_cache_cmd(ha, nscp, t)))
2315 this_cmd = FALSE;
2316 break;
2317
2318 case READ_6:
2319 case WRITE_6:
2320 case READ_10:
2321 case WRITE_10:
2322 case READ_16:
2323 case WRITE_16:
2324 if (ha->hdr[t].media_changed) {
2325 /* return UNIT_ATTENTION */
2326 TRACE2(("cmd 0x%x target %d: UNIT_ATTENTION\n",
2327 nscp->cmnd[0], t));
2328 ha->hdr[t].media_changed = FALSE;
2329 memset((char*)nscp->sense_buffer,0,16);
2330 nscp->sense_buffer[0] = 0x70;
2331 nscp->sense_buffer[2] = UNIT_ATTENTION;
2332 nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
2333 if (!nscp_cmndinfo->wait_for_completion)
2334 nscp_cmndinfo->wait_for_completion++;
2335 else
2336 gdth_scsi_done(nscp);
2337 } else if (!(cmd_index=gdth_fill_cache_cmd(ha, nscp, t)))
2338 this_cmd = FALSE;
2339 break;
2340
2341 default:
2342 TRACE2(("cache cmd %x/%x/%x/%x/%x/%x unknown\n",nscp->cmnd[0],
2343 nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
2344 nscp->cmnd[4],nscp->cmnd[5]));
2345 printk("GDT-HA %d: Unknown SCSI command 0x%x to cache service !\n",
2346 ha->hanum, nscp->cmnd[0]);
2347 nscp->result = DID_ABORT << 16;
2348 if (!nscp_cmndinfo->wait_for_completion)
2349 nscp_cmndinfo->wait_for_completion++;
2350 else
2351 gdth_scsi_done(nscp);
2352 break;
2353 }
2354 }
2355
2356 if (!this_cmd)
2357 break;
2358 if (nscp == ha->req_first)
2359 ha->req_first = pscp = (Scsi_Cmnd *)nscp->SCp.ptr;
2360 else
2361 pscp->SCp.ptr = nscp->SCp.ptr;
2362 if (!next_cmd)
2363 break;
2364 }
2365
2366 if (ha->cmd_cnt > 0) {
2367 gdth_release_event(ha);
2368 }
2369
2370 if (!gdth_polling)
2371 spin_unlock_irqrestore(&ha->smp_lock, flags);
2372
2373 if (gdth_polling && ha->cmd_cnt > 0) {
2374 if (!gdth_wait(ha, cmd_index, POLL_TIMEOUT))
2375 printk("GDT-HA %d: Command %d timed out !\n",
2376 ha->hanum, cmd_index);
2377 }
2378 }
2379
2380 /*
2381 * gdth_copy_internal_data() - copy to/from a buffer onto a scsi_cmnd's
2382 * buffers, kmap_atomic() as needed.
2383 */
2384 static void gdth_copy_internal_data(gdth_ha_str *ha, Scsi_Cmnd *scp,
2385 <<<<<<< HEAD:drivers/scsi/gdth.c
2386 char *buffer, ushort count, int to_buffer)
2387 =======
2388 char *buffer, ushort count)
2389 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/scsi/gdth.c
2390 {
2391 ushort cpcount,i, max_sg = gdth_sg_count(scp);
2392 ushort cpsum,cpnow;
2393 struct scatterlist *sl;
2394 char *address;
2395
2396 cpcount = min_t(ushort, count, gdth_bufflen(scp));
2397
2398 if (cpcount) {
2399 cpsum=0;
2400 scsi_for_each_sg(scp, sl, max_sg, i) {
2401 unsigned long flags;
2402 cpnow = (ushort)sl->length;
2403 TRACE(("copy_internal() now %d sum %d count %d %d\n",
2404 cpnow, cpsum, cpcount, gdth_bufflen(scp)));
2405 if (cpsum+cpnow > cpcount)
2406 cpnow = cpcount - cpsum;
2407 cpsum += cpnow;
2408 if (!sg_page(sl)) {
2409 printk("GDT-HA %d: invalid sc/gt element in gdth_copy_internal_data()\n",
2410 ha->hanum);
2411 return;
2412 }
2413 local_irq_save(flags);
2414 address = kmap_atomic(sg_page(sl), KM_BIO_SRC_IRQ) + sl->offset;
2415 <<<<<<< HEAD:drivers/scsi/gdth.c
2416 if (to_buffer)
2417 memcpy(buffer, address, cpnow);
2418 else
2419 memcpy(address, buffer, cpnow);
2420 =======
2421 memcpy(address, buffer, cpnow);
2422 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/scsi/gdth.c
2423 flush_dcache_page(sg_page(sl));
2424 kunmap_atomic(address, KM_BIO_SRC_IRQ);
2425 local_irq_restore(flags);
2426 if (cpsum == cpcount)
2427 break;
2428 buffer += cpnow;
2429 }
2430 } else if (count) {
2431 printk("GDT-HA %d: SCSI command with no buffers but data transfer expected!\n",
2432 ha->hanum);
2433 WARN_ON(1);
2434 }
2435 }
2436
2437 static int gdth_internal_cache_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp)
2438 {
2439 unchar t;
2440 gdth_inq_data inq;
2441 gdth_rdcap_data rdc;
2442 gdth_sense_data sd;
2443 gdth_modep_data mpd;
2444 struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
2445
2446 t = scp->device->id;
2447 TRACE(("gdth_internal_cache_cmd() cmd 0x%x hdrive %d\n",
2448 scp->cmnd[0],t));
2449
2450 scp->result = DID_OK << 16;
2451 scp->sense_buffer[0] = 0;
2452
2453 switch (scp->cmnd[0]) {
2454 case TEST_UNIT_READY:
2455 case VERIFY:
2456 case START_STOP:
2457 TRACE2(("Test/Verify/Start hdrive %d\n",t));
2458 break;
2459
2460 case INQUIRY:
2461 TRACE2(("Inquiry hdrive %d devtype %d\n",
2462 t,ha->hdr[t].devtype));
2463 inq.type_qual = (ha->hdr[t].devtype&4) ? TYPE_ROM:TYPE_DISK;
2464 /* you can here set all disks to removable, if you want to do
2465 a flush using the ALLOW_MEDIUM_REMOVAL command */
2466 inq.modif_rmb = 0x00;
2467 if ((ha->hdr[t].devtype & 1) ||
2468 (ha->hdr[t].cluster_type & CLUSTER_DRIVE))
2469 inq.modif_rmb = 0x80;
2470 inq.version = 2;
2471 inq.resp_aenc = 2;
2472 inq.add_length= 32;
2473 strcpy(inq.vendor,ha->oem_name);
2474 sprintf(inq.product,"Host Drive #%02d",t);
2475 strcpy(inq.revision," ");
2476 <<<<<<< HEAD:drivers/scsi/gdth.c
2477 gdth_copy_internal_data(ha, scp, (char*)&inq, sizeof(gdth_inq_data), 0);
2478 =======
2479 gdth_copy_internal_data(ha, scp, (char*)&inq, sizeof(gdth_inq_data));
2480 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/scsi/gdth.c
2481 break;
2482
2483 case REQUEST_SENSE:
2484 TRACE2(("Request sense hdrive %d\n",t));
2485 sd.errorcode = 0x70;
2486 sd.segno = 0x00;
2487 sd.key = NO_SENSE;
2488 sd.info = 0;
2489 sd.add_length= 0;
2490 <<<<<<< HEAD:drivers/scsi/gdth.c
2491 gdth_copy_internal_data(ha, scp, (char*)&sd, sizeof(gdth_sense_data), 0);
2492 =======
2493 gdth_copy_internal_data(ha, scp, (char*)&sd, sizeof(gdth_sense_data));
2494 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/scsi/gdth.c
2495 break;
2496
2497 case MODE_SENSE:
2498 TRACE2(("Mode sense hdrive %d\n",t));
2499 memset((char*)&mpd,0,sizeof(gdth_modep_data));
2500 mpd.hd.data_length = sizeof(gdth_modep_data);
2501 mpd.hd.dev_par = (ha->hdr[t].devtype&2) ? 0x80:0;
2502 mpd.hd.bd_length = sizeof(mpd.bd);
2503 mpd.bd.block_length[0] = (SECTOR_SIZE & 0x00ff0000) >> 16;
2504 mpd.bd.block_length[1] = (SECTOR_SIZE & 0x0000ff00) >> 8;
2505 mpd.bd.block_length[2] = (SECTOR_SIZE & 0x000000ff);
2506 <<<<<<< HEAD:drivers/scsi/gdth.c
2507 gdth_copy_internal_data(ha, scp, (char*)&mpd, sizeof(gdth_modep_data), 0);
2508 =======
2509 gdth_copy_internal_data(ha, scp, (char*)&mpd, sizeof(gdth_modep_data));
2510 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/scsi/gdth.c
2511 break;
2512
2513 case READ_CAPACITY:
2514 TRACE2(("Read capacity hdrive %d\n",t));
2515 if (ha->hdr[t].size > (ulong64)0xffffffff)
2516 rdc.last_block_no = 0xffffffff;
2517 else
2518 rdc.last_block_no = cpu_to_be32(ha->hdr[t].size-1);
2519 rdc.block_length = cpu_to_be32(SECTOR_SIZE);
2520 <<<<<<< HEAD:drivers/scsi/gdth.c
2521 gdth_copy_internal_data(ha, scp, (char*)&rdc, sizeof(gdth_rdcap_data), 0);
2522 =======
2523 gdth_copy_internal_data(ha, scp, (char*)&rdc, sizeof(gdth_rdcap_data));
2524 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/scsi/gdth.c
2525 break;
2526
2527 case SERVICE_ACTION_IN:
2528 if ((scp->cmnd[1] & 0x1f) == SAI_READ_CAPACITY_16 &&
2529 (ha->cache_feat & GDT_64BIT)) {
2530 gdth_rdcap16_data rdc16;
2531
2532 TRACE2(("Read capacity (16) hdrive %d\n",t));
2533 rdc16.last_block_no = cpu_to_be64(ha->hdr[t].size-1);
2534 rdc16.block_length = cpu_to_be32(SECTOR_SIZE);
2535 gdth_copy_internal_data(ha, scp, (char*)&rdc16,
2536 <<<<<<< HEAD:drivers/scsi/gdth.c
2537 sizeof(gdth_rdcap16_data), 0);
2538 =======
2539 sizeof(gdth_rdcap16_data));
2540 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/scsi/gdth.c
2541 } else {
2542 scp->result = DID_ABORT << 16;
2543 }
2544 break;
2545
2546 default:
2547 TRACE2(("Internal cache cmd 0x%x unknown\n",scp->cmnd[0]));
2548 break;
2549 }
2550
2551 if (!cmndinfo->wait_for_completion)
2552 cmndinfo->wait_for_completion++;
2553 else
2554 return 1;
2555
2556 return 0;
2557 }
2558
2559 static int gdth_fill_cache_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp, ushort hdrive)
2560 {
2561 register gdth_cmd_str *cmdp;
2562 struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
2563 ulong32 cnt, blockcnt;
2564 ulong64 no, blockno;
2565 int i, cmd_index, read_write, sgcnt, mode64;
2566
2567 cmdp = ha->pccb;
2568 TRACE(("gdth_fill_cache_cmd() cmd 0x%x cmdsize %d hdrive %d\n",
2569 scp->cmnd[0],scp->cmd_len,hdrive));
2570
2571 if (ha->type==GDT_EISA && ha->cmd_cnt>0)
2572 return 0;
2573
2574 mode64 = (ha->cache_feat & GDT_64BIT) ? TRUE : FALSE;
2575 /* test for READ_16, WRITE_16 if !mode64 ? ---
2576 not required, should not occur due to error return on
2577 READ_CAPACITY_16 */
2578
2579 cmdp->Service = CACHESERVICE;
2580 cmdp->RequestBuffer = scp;
2581 /* search free command index */
2582 if (!(cmd_index=gdth_get_cmd_index(ha))) {
2583 TRACE(("GDT: No free command index found\n"));
2584 return 0;
2585 }
2586 /* if it's the first command, set command semaphore */
2587 if (ha->cmd_cnt == 0)
2588 gdth_set_sema0(ha);
2589
2590 /* fill command */
2591 read_write = 0;
2592 if (cmndinfo->OpCode != -1)
2593 cmdp->OpCode = cmndinfo->OpCode; /* special cache cmd. */
2594 else if (scp->cmnd[0] == RESERVE)
2595 cmdp->OpCode = GDT_RESERVE_DRV;
2596 else if (scp->cmnd[0] == RELEASE)
2597 cmdp->OpCode = GDT_RELEASE_DRV;
2598 else if (scp->cmnd[0] == ALLOW_MEDIUM_REMOVAL) {
2599 if (scp->cmnd[4] & 1) /* prevent ? */
2600 cmdp->OpCode = GDT_MOUNT;
2601 else if (scp->cmnd[3] & 1) /* removable drive ? */
2602 cmdp->OpCode = GDT_UNMOUNT;
2603 else
2604 cmdp->OpCode = GDT_FLUSH;
2605 } else if (scp->cmnd[0] == WRITE_6 || scp->cmnd[0] == WRITE_10 ||
2606 scp->cmnd[0] == WRITE_12 || scp->cmnd[0] == WRITE_16
2607 ) {
2608 read_write = 1;
2609 if (gdth_write_through || ((ha->hdr[hdrive].rw_attribs & 1) &&
2610 (ha->cache_feat & GDT_WR_THROUGH)))
2611 cmdp->OpCode = GDT_WRITE_THR;
2612 else
2613 cmdp->OpCode = GDT_WRITE;
2614 } else {
2615 read_write = 2;
2616 cmdp->OpCode = GDT_READ;
2617 }
2618
2619 cmdp->BoardNode = LOCALBOARD;
2620 if (mode64) {
2621 cmdp->u.cache64.DeviceNo = hdrive;
2622 cmdp->u.cache64.BlockNo = 1;
2623 cmdp->u.cache64.sg_canz = 0;
2624 } else {
2625 cmdp->u.cache.DeviceNo = hdrive;
2626 cmdp->u.cache.BlockNo = 1;
2627 cmdp->u.cache.sg_canz = 0;
2628 }
2629
2630 if (read_write) {
2631 if (scp->cmd_len == 16) {
2632 memcpy(&no, &scp->cmnd[2], sizeof(ulong64));
2633 blockno = be64_to_cpu(no);
2634 memcpy(&cnt, &scp->cmnd[10], sizeof(ulong32));
2635 blockcnt = be32_to_cpu(cnt);
2636 } else if (scp->cmd_len == 10) {
2637 memcpy(&no, &scp->cmnd[2], sizeof(ulong32));
2638 blockno = be32_to_cpu(no);
2639 memcpy(&cnt, &scp->cmnd[7], sizeof(ushort));
2640 blockcnt = be16_to_cpu(cnt);
2641 } else {
2642 memcpy(&no, &scp->cmnd[0], sizeof(ulong32));
2643 blockno = be32_to_cpu(no) & 0x001fffffUL;
2644 blockcnt= scp->cmnd[4]==0 ? 0x100 : scp->cmnd[4];
2645 }
2646 if (mode64) {
2647 cmdp->u.cache64.BlockNo = blockno;
2648 cmdp->u.cache64.BlockCnt = blockcnt;
2649 } else {
2650 cmdp->u.cache.BlockNo = (ulong32)blockno;
2651 cmdp->u.cache.BlockCnt = blockcnt;
2652 }
2653
2654 if (gdth_bufflen(scp)) {
2655 cmndinfo->dma_dir = (read_write == 1 ?
2656 PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
2657 sgcnt = pci_map_sg(ha->pdev, gdth_sglist(scp), gdth_sg_count(scp),
2658 cmndinfo->dma_dir);
2659 if (mode64) {
2660 struct scatterlist *sl;
2661
2662 cmdp->u.cache64.DestAddr= (ulong64)-1;
2663 cmdp->u.cache64.sg_canz = sgcnt;
2664 scsi_for_each_sg(scp, sl, sgcnt, i) {
2665 cmdp->u.cache64.sg_lst[i].sg_ptr = sg_dma_address(sl);
2666 #ifdef GDTH_DMA_STATISTICS
2667 if (cmdp->u.cache64.sg_lst[i].sg_ptr > (ulong64)0xffffffff)
2668 ha->dma64_cnt++;
2669 else
2670 ha->dma32_cnt++;
2671 #endif
2672 cmdp->u.cache64.sg_lst[i].sg_len = sg_dma_len(sl);
2673 }
2674 } else {
2675 struct scatterlist *sl;
2676
2677 cmdp->u.cache.DestAddr= 0xffffffff;
2678 cmdp->u.cache.sg_canz = sgcnt;
2679 scsi_for_each_sg(scp, sl, sgcnt, i) {
2680 cmdp->u.cache.sg_lst[i].sg_ptr = sg_dma_address(sl);
2681 #ifdef GDTH_DMA_STATISTICS
2682 ha->dma32_cnt++;
2683 #endif
2684 cmdp->u.cache.sg_lst[i].sg_len = sg_dma_len(sl);
2685 }
2686 }
2687
2688 #ifdef GDTH_STATISTICS
2689 if (max_sg < (ulong32)sgcnt) {
2690 max_sg = (ulong32)sgcnt;
2691 TRACE3(("GDT: max_sg = %d\n",max_sg));
2692 }
2693 #endif
2694
2695 }
2696 }
2697 /* evaluate command size, check space */
2698 if (mode64) {
2699 TRACE(("cache cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
2700 cmdp->u.cache64.DestAddr,cmdp->u.cache64.sg_canz,
2701 cmdp->u.cache64.sg_lst[0].sg_ptr,
2702 cmdp->u.cache64.sg_lst[0].sg_len));
2703 TRACE(("cache cmd: cmd %d blockno. %d, blockcnt %d\n",
2704 cmdp->OpCode,cmdp->u.cache64.BlockNo,cmdp->u.cache64.BlockCnt));
2705 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.cache64.sg_lst) +
2706 (ushort)cmdp->u.cache64.sg_canz * sizeof(gdth_sg64_str);
2707 } else {
2708 TRACE(("cache cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
2709 cmdp->u.cache.DestAddr,cmdp->u.cache.sg_canz,
2710 cmdp->u.cache.sg_lst[0].sg_ptr,
2711 cmdp->u.cache.sg_lst[0].sg_len));
2712 TRACE(("cache cmd: cmd %d blockno. %d, blockcnt %d\n",
2713 cmdp->OpCode,cmdp->u.cache.BlockNo,cmdp->u.cache.BlockCnt));
2714 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.cache.sg_lst) +
2715 (ushort)cmdp->u.cache.sg_canz * sizeof(gdth_sg_str);
2716 }
2717 if (ha->cmd_len & 3)
2718 ha->cmd_len += (4 - (ha->cmd_len & 3));
2719
2720 if (ha->cmd_cnt > 0) {
2721 if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
2722 ha->ic_all_size) {
2723 TRACE2(("gdth_fill_cache() DPMEM overflow\n"));
2724 ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
2725 return 0;
2726 }
2727 }
2728
2729 /* copy command */
2730 gdth_copy_command(ha);
2731 return cmd_index;
2732 }
2733
2734 static int gdth_fill_raw_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp, unchar b)
2735 {
2736 register gdth_cmd_str *cmdp;
2737 ushort i;
2738 dma_addr_t sense_paddr;
2739 int cmd_index, sgcnt, mode64;
2740 unchar t,l;
2741 struct page *page;
2742 ulong offset;
2743 struct gdth_cmndinfo *cmndinfo;
2744
2745 t = scp->device->id;
2746 l = scp->device->lun;
2747 cmdp = ha->pccb;
2748 TRACE(("gdth_fill_raw_cmd() cmd 0x%x bus %d ID %d LUN %d\n",
2749 scp->cmnd[0],b,t,l));
2750
2751 if (ha->type==GDT_EISA && ha->cmd_cnt>0)
2752 return 0;
2753
2754 mode64 = (ha->raw_feat & GDT_64BIT) ? TRUE : FALSE;
2755
2756 cmdp->Service = SCSIRAWSERVICE;
2757 cmdp->RequestBuffer = scp;
2758 /* search free command index */
2759 if (!(cmd_index=gdth_get_cmd_index(ha))) {
2760 TRACE(("GDT: No free command index found\n"));
2761 return 0;
2762 }
2763 /* if it's the first command, set command semaphore */
2764 if (ha->cmd_cnt == 0)
2765 gdth_set_sema0(ha);
2766
2767 cmndinfo = gdth_cmnd_priv(scp);
2768 /* fill command */
2769 if (cmndinfo->OpCode != -1) {
2770 cmdp->OpCode = cmndinfo->OpCode; /* special raw cmd. */
2771 cmdp->BoardNode = LOCALBOARD;
2772 if (mode64) {
2773 cmdp->u.raw64.direction = (cmndinfo->phase >> 8);
2774 TRACE2(("special raw cmd 0x%x param 0x%x\n",
2775 cmdp->OpCode, cmdp->u.raw64.direction));
2776 /* evaluate command size */
2777 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst);
2778 } else {
2779 cmdp->u.raw.direction = (cmndinfo->phase >> 8);
2780 TRACE2(("special raw cmd 0x%x param 0x%x\n",
2781 cmdp->OpCode, cmdp->u.raw.direction));
2782 /* evaluate command size */
2783 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst);
2784 }
2785
2786 } else {
2787 page = virt_to_page(scp->sense_buffer);
2788 offset = (ulong)scp->sense_buffer & ~PAGE_MASK;
2789 sense_paddr = pci_map_page(ha->pdev,page,offset,
2790 16,PCI_DMA_FROMDEVICE);
2791
2792 cmndinfo->sense_paddr = sense_paddr;
2793 cmdp->OpCode = GDT_WRITE; /* always */
2794 cmdp->BoardNode = LOCALBOARD;
2795 if (mode64) {
2796 cmdp->u.raw64.reserved = 0;
2797 cmdp->u.raw64.mdisc_time = 0;
2798 cmdp->u.raw64.mcon_time = 0;
2799 cmdp->u.raw64.clen = scp->cmd_len;
2800 cmdp->u.raw64.target = t;
2801 cmdp->u.raw64.lun = l;
2802 cmdp->u.raw64.bus = b;
2803 cmdp->u.raw64.priority = 0;
2804 cmdp->u.raw64.sdlen = gdth_bufflen(scp);
2805 cmdp->u.raw64.sense_len = 16;
2806 cmdp->u.raw64.sense_data = sense_paddr;
2807 cmdp->u.raw64.direction =
2808 gdth_direction_tab[scp->cmnd[0]]==DOU ? GDTH_DATA_OUT:GDTH_DATA_IN;
2809 memcpy(cmdp->u.raw64.cmd,scp->cmnd,16);
2810 cmdp->u.raw64.sg_ranz = 0;
2811 } else {
2812 cmdp->u.raw.reserved = 0;
2813 cmdp->u.raw.mdisc_time = 0;
2814 cmdp->u.raw.mcon_time = 0;
2815 cmdp->u.raw.clen = scp->cmd_len;
2816 cmdp->u.raw.target = t;
2817 cmdp->u.raw.lun = l;
2818 cmdp->u.raw.bus = b;
2819 cmdp->u.raw.priority = 0;
2820 cmdp->u.raw.link_p = 0;
2821 cmdp->u.raw.sdlen = gdth_bufflen(scp);
2822 cmdp->u.raw.sense_len = 16;
2823 cmdp->u.raw.sense_data = sense_paddr;
2824 cmdp->u.raw.direction =
2825 gdth_direction_tab[scp->cmnd[0]]==DOU ? GDTH_DATA_OUT:GDTH_DATA_IN;
2826 memcpy(cmdp->u.raw.cmd,scp->cmnd,12);
2827 cmdp->u.raw.sg_ranz = 0;
2828 }
2829
2830 if (gdth_bufflen(scp)) {
2831 cmndinfo->dma_dir = PCI_DMA_BIDIRECTIONAL;
2832 sgcnt = pci_map_sg(ha->pdev, gdth_sglist(scp), gdth_sg_count(scp),
2833 cmndinfo->dma_dir);
2834 if (mode64) {
2835 struct scatterlist *sl;
2836
2837 cmdp->u.raw64.sdata = (ulong64)-1;
2838 cmdp->u.raw64.sg_ranz = sgcnt;
2839 scsi_for_each_sg(scp, sl, sgcnt, i) {
2840 cmdp->u.raw64.sg_lst[i].sg_ptr = sg_dma_address(sl);
2841 #ifdef GDTH_DMA_STATISTICS
2842 if (cmdp->u.raw64.sg_lst[i].sg_ptr > (ulong64)0xffffffff)
2843 ha->dma64_cnt++;
2844 else
2845 ha->dma32_cnt++;
2846 #endif
2847 cmdp->u.raw64.sg_lst[i].sg_len = sg_dma_len(sl);
2848 }
2849 } else {
2850 struct scatterlist *sl;
2851
2852 cmdp->u.raw.sdata = 0xffffffff;
2853 cmdp->u.raw.sg_ranz = sgcnt;
2854 scsi_for_each_sg(scp, sl, sgcnt, i) {
2855 cmdp->u.raw.sg_lst[i].sg_ptr = sg_dma_address(sl);
2856 #ifdef GDTH_DMA_STATISTICS
2857 ha->dma32_cnt++;
2858 #endif
2859 cmdp->u.raw.sg_lst[i].sg_len = sg_dma_len(sl);
2860 }
2861 }
2862
2863 #ifdef GDTH_STATISTICS
2864 if (max_sg < sgcnt) {
2865 max_sg = sgcnt;
2866 TRACE3(("GDT: max_sg = %d\n",sgcnt));
2867 }
2868 #endif
2869
2870 }
2871 if (mode64) {
2872 TRACE(("raw cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
2873 cmdp->u.raw64.sdata,cmdp->u.raw64.sg_ranz,
2874 cmdp->u.raw64.sg_lst[0].sg_ptr,
2875 cmdp->u.raw64.sg_lst[0].sg_len));
2876 /* evaluate command size */
2877 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst) +
2878 (ushort)cmdp->u.raw64.sg_ranz * sizeof(gdth_sg64_str);
2879 } else {
2880 TRACE(("raw cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
2881 cmdp->u.raw.sdata,cmdp->u.raw.sg_ranz,
2882 cmdp->u.raw.sg_lst[0].sg_ptr,
2883 cmdp->u.raw.sg_lst[0].sg_len));
2884 /* evaluate command size */
2885 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst) +
2886 (ushort)cmdp->u.raw.sg_ranz * sizeof(gdth_sg_str);
2887 }
2888 }
2889 /* check space */
2890 if (ha->cmd_len & 3)
2891 ha->cmd_len += (4 - (ha->cmd_len & 3));
2892
2893 if (ha->cmd_cnt > 0) {
2894 if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
2895 ha->ic_all_size) {
2896 TRACE2(("gdth_fill_raw() DPMEM overflow\n"));
2897 ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
2898 return 0;
2899 }
2900 }
2901
2902 /* copy command */
2903 gdth_copy_command(ha);
2904 return cmd_index;
2905 }
2906
2907 static int gdth_special_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp)
2908 {
2909 register gdth_cmd_str *cmdp;
2910 <<<<<<< HEAD:drivers/scsi/gdth.c
2911 =======
2912 struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
2913 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/scsi/gdth.c
2914 int cmd_index;
2915
2916 cmdp= ha->pccb;
2917 TRACE2(("gdth_special_cmd(): "));
2918
2919 if (ha->type==GDT_EISA && ha->cmd_cnt>0)
2920 return 0;
2921
2922 <<<<<<< HEAD:drivers/scsi/gdth.c
2923 gdth_copy_internal_data(ha, scp, (char *)cmdp, sizeof(gdth_cmd_str), 1);
2924 =======
2925 *cmdp = *cmndinfo->internal_cmd_str;
2926 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/scsi/gdth.c
2927 cmdp->RequestBuffer = scp;
2928
2929 /* search free command index */
2930 if (!(cmd_index=gdth_get_cmd_index(ha))) {
2931 TRACE(("GDT: No free command index found\n"));
2932 return 0;
2933 }
2934
2935 /* if it's the first command, set command semaphore */
2936 if (ha->cmd_cnt == 0)
2937 gdth_set_sema0(ha);
2938
2939 /* evaluate command size, check space */
2940 if (cmdp->OpCode == GDT_IOCTL) {
2941 TRACE2(("IOCTL\n"));
2942 ha->cmd_len =
2943 GDTOFFSOF(gdth_cmd_str,u.ioctl.p_param) + sizeof(ulong64);
2944 } else if (cmdp->Service == CACHESERVICE) {
2945 TRACE2(("cache command %d\n",cmdp->OpCode));
2946 if (ha->cache_feat & GDT_64BIT)
2947 ha->cmd_len =
2948 GDTOFFSOF(gdth_cmd_str,u.cache64.sg_lst) + sizeof(gdth_sg64_str);
2949 else
2950 ha->cmd_len =
2951 GDTOFFSOF(gdth_cmd_str,u.cache.sg_lst) + sizeof(gdth_sg_str);
2952 } else if (cmdp->Service == SCSIRAWSERVICE) {
2953 TRACE2(("raw command %d\n",cmdp->OpCode));
2954 if (ha->raw_feat & GDT_64BIT)
2955 ha->cmd_len =
2956 GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst) + sizeof(gdth_sg64_str);
2957 else
2958 ha->cmd_len =
2959 GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst) + sizeof(gdth_sg_str);
2960 }
2961
2962 if (ha->cmd_len & 3)
2963 ha->cmd_len += (4 - (ha->cmd_len & 3));
2964
2965 if (ha->cmd_cnt > 0) {
2966 if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
2967 ha->ic_all_size) {
2968 TRACE2(("gdth_special_cmd() DPMEM overflow\n"));
2969 ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
2970 return 0;
2971 }
2972 }
2973
2974 /* copy command */
2975 gdth_copy_command(ha);
2976 return cmd_index;
2977 }
2978
2979
2980 /* Controller event handling functions */
2981 static gdth_evt_str *gdth_store_event(gdth_ha_str *ha, ushort source,
2982 ushort idx, gdth_evt_data *evt)
2983 {
2984 gdth_evt_str *e;
2985 struct timeval tv;
2986
2987 /* no GDTH_LOCK_HA() ! */
2988 TRACE2(("gdth_store_event() source %d idx %d\n", source, idx));
2989 if (source == 0) /* no source -> no event */
2990 return NULL;
2991
2992 if (ebuffer[elastidx].event_source == source &&
2993 ebuffer[elastidx].event_idx == idx &&
2994 ((evt->size != 0 && ebuffer[elastidx].event_data.size != 0 &&
2995 !memcmp((char *)&ebuffer[elastidx].event_data.eu,
2996 (char *)&evt->eu, evt->size)) ||
2997 (evt->size == 0 && ebuffer[elastidx].event_data.size == 0 &&
2998 !strcmp((char *)&ebuffer[elastidx].event_data.event_string,
2999 (char *)&evt->event_string)))) {
3000 e = &ebuffer[elastidx];
3001 do_gettimeofday(&tv);
3002 e->last_stamp = tv.tv_sec;
3003 ++e->same_count;
3004 } else {
3005 if (ebuffer[elastidx].event_source != 0) { /* entry not free ? */
3006 ++elastidx;
3007 if (elastidx == MAX_EVENTS)
3008 elastidx = 0;
3009 if (elastidx == eoldidx) { /* reached mark ? */
3010 ++eoldidx;
3011 if (eoldidx == MAX_EVENTS)
3012 eoldidx = 0;
3013 }
3014 }
3015 e = &ebuffer[elastidx];
3016 e->event_source = source;
3017 e->event_idx = idx;
3018 do_gettimeofday(&tv);
3019 e->first_stamp = e->last_stamp = tv.tv_sec;
3020 e->same_count = 1;
3021 e->event_data = *evt;
3022 e->application = 0;
3023 }
3024 return e;
3025 }
3026
3027 static int gdth_read_event(gdth_ha_str *ha, int handle, gdth_evt_str *estr)
3028 {
3029 gdth_evt_str *e;
3030 int eindex;
3031 ulong flags;
3032
3033 TRACE2(("gdth_read_event() handle %d\n", handle));
3034 spin_lock_irqsave(&ha->smp_lock, flags);
3035 if (handle == -1)
3036 eindex = eoldidx;
3037 else
3038 eindex = handle;
3039 estr->event_source = 0;
3040
3041 if (eindex >= MAX_EVENTS) {
3042 spin_unlock_irqrestore(&ha->smp_lock, flags);
3043 return eindex;
3044 }
3045 e = &ebuffer[eindex];
3046 if (e->event_source != 0) {
3047 if (eindex != elastidx) {
3048 if (++eindex == MAX_EVENTS)
3049 eindex = 0;
3050 } else {
3051 eindex = -1;
3052 }
3053 memcpy(estr, e, sizeof(gdth_evt_str));
3054 }
3055 spin_unlock_irqrestore(&ha->smp_lock, flags);
3056 return eindex;
3057 }
3058
3059 static void gdth_readapp_event(gdth_ha_str *ha,
3060 unchar application, gdth_evt_str *estr)
3061 {
3062 gdth_evt_str *e;
3063 int eindex;
3064 ulong flags;
3065 unchar found = FALSE;
3066
3067 TRACE2(("gdth_readapp_event() app. %d\n", application));
3068 spin_lock_irqsave(&ha->smp_lock, flags);
3069 eindex = eoldidx;
3070 for (;;) {
3071 e = &ebuffer[eindex];
3072 if (e->event_source == 0)
3073 break;
3074 if ((e->application & application) == 0) {
3075 e->application |= application;
3076 found = TRUE;
3077 break;
3078 }
3079 if (eindex == elastidx)
3080 break;
3081 if (++eindex == MAX_EVENTS)
3082 eindex = 0;
3083 }
3084 if (found)
3085 memcpy(estr, e, sizeof(gdth_evt_str));
3086 else
3087 estr->event_source = 0;
3088 spin_unlock_irqrestore(&ha->smp_lock, flags);
3089 }
3090
3091 static void gdth_clear_events(void)
3092 {
3093 TRACE(("gdth_clear_events()"));
3094
3095 eoldidx = elastidx = 0;
3096 ebuffer[0].event_source = 0;
3097 }
3098
3099
3100 /* SCSI interface functions */
3101
3102 static irqreturn_t __gdth_interrupt(gdth_ha_str *ha,
3103 int gdth_from_wait, int* pIndex)
3104 {
3105 gdt6m_dpram_str __iomem *dp6m_ptr = NULL;
3106 gdt6_dpram_str __iomem *dp6_ptr;
3107 gdt2_dpram_str __iomem *dp2_ptr;
3108 Scsi_Cmnd *scp;
3109 int rval, i;
3110 unchar IStatus;
3111 ushort Service;
3112 ulong flags = 0;
3113 #ifdef INT_COAL
3114 int coalesced = FALSE;
3115 int next = FALSE;
3116 gdth_coal_status *pcs = NULL;
3117 int act_int_coal = 0;
3118 #endif
3119
3120 TRACE(("gdth_interrupt() IRQ %d\n", ha->irq));
3121
3122 /* if polling and not from gdth_wait() -> return */
3123 if (gdth_polling) {
3124 if (!gdth_from_wait) {
3125 return IRQ_HANDLED;
3126 }
3127 }
3128
3129 if (!gdth_polling)
3130 spin_lock_irqsave(&ha->smp_lock, flags);
3131
3132 /* search controller */
3133 IStatus = gdth_get_status(ha);
3134 if (IStatus == 0) {
3135 /* spurious interrupt */
3136 if (!gdth_polling)
3137 spin_unlock_irqrestore(&ha->smp_lock, flags);
3138 return IRQ_HANDLED;
3139 }
3140
3141 #ifdef GDTH_STATISTICS
3142 ++act_ints;
3143 #endif
3144
3145 #ifdef INT_COAL
3146 /* See if the fw is returning coalesced status */
3147 if (IStatus == COALINDEX) {
3148 /* Coalesced status. Setup the initial status
3149 buffer pointer and flags */
3150 pcs = ha->coal_stat;
3151 coalesced = TRUE;
3152 next = TRUE;
3153 }
3154
3155 do {
3156 if (coalesced) {
3157 /* For coalesced requests all status
3158 information is found in the status buffer */
3159 IStatus = (unchar)(pcs->status & 0xff);
3160 }
3161 #endif
3162
3163 if (ha->type == GDT_EISA) {
3164 if (IStatus & 0x80) { /* error flag */
3165 IStatus &= ~0x80;
3166 ha->status = inw(ha->bmic + MAILBOXREG+8);
3167 TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
3168 } else /* no error */
3169 ha->status = S_OK;
3170 ha->info = inl(ha->bmic + MAILBOXREG+12);
3171 ha->service = inw(ha->bmic + MAILBOXREG+10);
3172 ha->info2 = inl(ha->bmic + MAILBOXREG+4);
3173
3174 outb(0xff, ha->bmic + EDOORREG); /* acknowledge interrupt */
3175 outb(0x00, ha->bmic + SEMA1REG); /* reset status semaphore */
3176 } else if (ha->type == GDT_ISA) {
3177 dp2_ptr = ha->brd;
3178 if (IStatus & 0x80) { /* error flag */
3179 IStatus &= ~0x80;
3180 ha->status = readw(&dp2_ptr->u.ic.Status);
3181 TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
3182 } else /* no error */
3183 ha->status = S_OK;
3184 ha->info = readl(&dp2_ptr->u.ic.Info[0]);
3185 ha->service = readw(&dp2_ptr->u.ic.Service);
3186 ha->info2 = readl(&dp2_ptr->u.ic.Info[1]);
3187
3188 writeb(0xff, &dp2_ptr->io.irqdel); /* acknowledge interrupt */
3189 writeb(0, &dp2_ptr->u.ic.Cmd_Index);/* reset command index */
3190 writeb(0, &dp2_ptr->io.Sema1); /* reset status semaphore */
3191 } else if (ha->type == GDT_PCI) {
3192 dp6_ptr = ha->brd;
3193 if (IStatus & 0x80) { /* error flag */
3194 IStatus &= ~0x80;
3195 ha->status = readw(&dp6_ptr->u.ic.Status);
3196 TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
3197 } else /* no error */
3198 ha->status = S_OK;
3199 ha->info = readl(&dp6_ptr->u.ic.Info[0]);
3200 ha->service = readw(&dp6_ptr->u.ic.Service);
3201 ha->info2 = readl(&dp6_ptr->u.ic.Info[1]);
3202
3203 writeb(0xff, &dp6_ptr->io.irqdel); /* acknowledge interrupt */
3204 writeb(0, &dp6_ptr->u.ic.Cmd_Index);/* reset command index */
3205 writeb(0, &dp6_ptr->io.Sema1); /* reset status semaphore */
3206 } else if (ha->type == GDT_PCINEW) {
3207 if (IStatus & 0x80) { /* error flag */
3208 IStatus &= ~0x80;
3209 ha->status = inw(PTR2USHORT(&ha->plx->status));
3210 TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
3211 } else
3212 ha->status = S_OK;
3213 ha->info = inl(PTR2USHORT(&ha->plx->info[0]));
3214 ha->service = inw(PTR2USHORT(&ha->plx->service));
3215 ha->info2 = inl(PTR2USHORT(&ha->plx->info[1]));
3216
3217 outb(0xff, PTR2USHORT(&ha->plx->edoor_reg));
3218 outb(0x00, PTR2USHORT(&ha->plx->sema1_reg));
3219 } else if (ha->type == GDT_PCIMPR) {
3220 dp6m_ptr = ha->brd;
3221 if (IStatus & 0x80) { /* error flag */
3222 IStatus &= ~0x80;
3223 #ifdef INT_COAL
3224 if (coalesced)
3225 ha->status = pcs->ext_status & 0xffff;
3226 else
3227 #endif
3228 ha->status = readw(&dp6m_ptr->i960r.status);
3229 TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
3230 } else /* no error */
3231 ha->status = S_OK;
3232 #ifdef INT_COAL
3233 /* get information */
3234 if (coalesced) {
3235 ha->info = pcs->info0;
3236 ha->info2 = pcs->info1;
3237 ha->service = (pcs->ext_status >> 16) & 0xffff;
3238 } else
3239 #endif
3240 {
3241 ha->info = readl(&dp6m_ptr->i960r.info[0]);
3242 ha->service = readw(&dp6m_ptr->i960r.service);
3243 ha->info2 = readl(&dp6m_ptr->i960r.info[1]);
3244 }
3245 /* event string */
3246 if (IStatus == ASYNCINDEX) {
3247 if (ha->service != SCREENSERVICE &&
3248 (ha->fw_vers & 0xff) >= 0x1a) {
3249 ha->dvr.severity = readb
3250 (&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.severity);
3251 for (i = 0; i < 256; ++i) {
3252 ha->dvr.event_string[i] = readb
3253 (&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.evt_str[i]);
3254 if (ha->dvr.event_string[i] == 0)
3255 break;
3256 }
3257 }
3258 }
3259 #ifdef INT_COAL
3260 /* Make sure that non coalesced interrupts get cleared
3261 before being handled by gdth_async_event/gdth_sync_event */
3262 if (!coalesced)
3263 #endif
3264 {
3265 writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
3266 writeb(0, &dp6m_ptr->i960r.sema1_reg);
3267 }
3268 } else {
3269 TRACE2(("gdth_interrupt() unknown controller type\n"));
3270 if (!gdth_polling)
3271 spin_unlock_irqrestore(&ha->smp_lock, flags);
3272 return IRQ_HANDLED;
3273 }
3274
3275 TRACE(("gdth_interrupt() index %d stat %d info %d\n",
3276 IStatus,ha->status,ha->info));
3277
3278 if (gdth_from_wait) {
3279 *pIndex = (int)IStatus;
3280 }
3281
3282 if (IStatus == ASYNCINDEX) {
3283 TRACE2(("gdth_interrupt() async. event\n"));
3284 gdth_async_event(ha);
3285 if (!gdth_polling)
3286 spin_unlock_irqrestore(&ha->smp_lock, flags);
3287 gdth_next(ha);
3288 return IRQ_HANDLED;
3289 }
3290
3291 if (IStatus == SPEZINDEX) {
3292 TRACE2(("Service unknown or not initialized !\n"));
3293 ha->dvr.size = sizeof(ha->dvr.eu.driver);
3294 ha->dvr.eu.driver.ionode = ha->hanum;
3295 gdth_store_event(ha, ES_DRIVER, 4, &ha->dvr);
3296 if (!gdth_polling)
3297 spin_unlock_irqrestore(&ha->smp_lock, flags);
3298 return IRQ_HANDLED;
3299 }
3300 scp = ha->cmd_tab[IStatus-2].cmnd;
3301 Service = ha->cmd_tab[IStatus-2].service;
3302 ha->cmd_tab[IStatus-2].cmnd = UNUSED_CMND;
3303 if (scp == UNUSED_CMND) {
3304 TRACE2(("gdth_interrupt() index to unused command (%d)\n",IStatus));
3305 ha->dvr.size = sizeof(ha->dvr.eu.driver);
3306 ha->dvr.eu.driver.ionode = ha->hanum;
3307 ha->dvr.eu.driver.index = IStatus;
3308 gdth_store_event(ha, ES_DRIVER, 1, &ha->dvr);
3309 if (!gdth_polling)
3310 spin_unlock_irqrestore(&ha->smp_lock, flags);
3311 return IRQ_HANDLED;
3312 }
3313 if (scp == INTERNAL_CMND) {
3314 TRACE(("gdth_interrupt() answer to internal command\n"));
3315 if (!gdth_polling)
3316 spin_unlock_irqrestore(&ha->smp_lock, flags);
3317 return IRQ_HANDLED;
3318 }
3319
3320 TRACE(("gdth_interrupt() sync. status\n"));
3321 rval = gdth_sync_event(ha,Service,IStatus,scp);
3322 if (!gdth_polling)
3323 spin_unlock_irqrestore(&ha->smp_lock, flags);
3324 if (rval == 2) {
3325 gdth_putq(ha, scp, gdth_cmnd_priv(scp)->priority);
3326 } else if (rval == 1) {
3327 gdth_scsi_done(scp);
3328 }
3329
3330 #ifdef INT_COAL
3331 if (coalesced) {
3332 /* go to the next status in the status buffer */
3333 ++pcs;
3334 #ifdef GDTH_STATISTICS
3335 ++act_int_coal;
3336 if (act_int_coal > max_int_coal) {
3337 max_int_coal = act_int_coal;
3338 printk("GDT: max_int_coal = %d\n",(ushort)max_int_coal);
3339 }
3340 #endif
3341 /* see if there is another status */
3342 if (pcs->status == 0)
3343 /* Stop the coalesce loop */
3344 next = FALSE;
3345 }
3346 } while (next);
3347
3348 /* coalescing only for new GDT_PCIMPR controllers available */
3349 if (ha->type == GDT_PCIMPR && coalesced) {
3350 writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
3351 writeb(0, &dp6m_ptr->i960r.sema1_reg);
3352 }
3353 #endif
3354
3355 gdth_next(ha);
3356 return IRQ_HANDLED;
3357 }
3358
3359 static irqreturn_t gdth_interrupt(int irq, void *dev_id)
3360 {
3361 gdth_ha_str *ha = dev_id;
3362
3363 return __gdth_interrupt(ha, false, NULL);
3364 }
3365
3366 static int gdth_sync_event(gdth_ha_str *ha, int service, unchar index,
3367 Scsi_Cmnd *scp)
3368 {
3369 gdth_msg_str *msg;
3370 gdth_cmd_str *cmdp;
3371 unchar b, t;
3372 struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
3373
3374 cmdp = ha->pccb;
3375 TRACE(("gdth_sync_event() serv %d status %d\n",
3376 service,ha->status));
3377
3378 if (service == SCREENSERVICE) {
3379 msg = ha->pmsg;
3380 TRACE(("len: %d, answer: %d, ext: %d, alen: %d\n",
3381 msg->msg_len,msg->msg_answer,msg->msg_ext,msg->msg_alen));
3382 if (msg->msg_len > MSGLEN+1)
3383 msg->msg_len = MSGLEN+1;
3384 if (msg->msg_len)
3385 if (!(msg->msg_answer && msg->msg_ext)) {
3386 msg->msg_text[msg->msg_len] = '\0';
3387 printk("%s",msg->msg_text);
3388 }
3389
3390 if (msg->msg_ext && !msg->msg_answer) {
3391 while (gdth_test_busy(ha))
3392 gdth_delay(0);
3393 cmdp->Service = SCREENSERVICE;
3394 cmdp->RequestBuffer = SCREEN_CMND;
3395 gdth_get_cmd_index(ha);
3396 gdth_set_sema0(ha);
3397 cmdp->OpCode = GDT_READ;
3398 cmdp->BoardNode = LOCALBOARD;
3399 cmdp->u.screen.reserved = 0;
3400 cmdp->u.screen.su.msg.msg_handle= msg->msg_handle;
3401 cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
3402 ha->cmd_offs_dpmem = 0;
3403 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
3404 + sizeof(ulong64);
3405 ha->cmd_cnt = 0;
3406 gdth_copy_command(ha);
3407 gdth_release_event(ha);
3408 return 0;
3409 }
3410
3411 if (msg->msg_answer && msg->msg_alen) {
3412 /* default answers (getchar() not possible) */
3413 if (msg->msg_alen == 1) {
3414 msg->msg_alen = 0;
3415 msg->msg_len = 1;
3416 msg->msg_text[0] = 0;
3417 } else {
3418 msg->msg_alen -= 2;
3419 msg->msg_len = 2;
3420 msg->msg_text[0] = 1;
3421 msg->msg_text[1] = 0;
3422 }
3423 msg->msg_ext = 0;
3424 msg->msg_answer = 0;
3425 while (gdth_test_busy(ha))
3426 gdth_delay(0);
3427 cmdp->Service = SCREENSERVICE;
3428 cmdp->RequestBuffer = SCREEN_CMND;
3429 gdth_get_cmd_index(ha);
3430 gdth_set_sema0(ha);
3431 cmdp->OpCode = GDT_WRITE;
3432 cmdp->BoardNode = LOCALBOARD;
3433 cmdp->u.screen.reserved = 0;
3434 cmdp->u.screen.su.msg.msg_handle= msg->msg_handle;
3435 cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
3436 ha->cmd_offs_dpmem = 0;
3437 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
3438 + sizeof(ulong64);
3439 ha->cmd_cnt = 0;
3440 gdth_copy_command(ha);
3441 gdth_release_event(ha);
3442 return 0;
3443 }
3444 printk("\n");
3445
3446 } else {
3447 b = scp->device->channel;
3448 t = scp->device->id;
3449 if (cmndinfo->OpCode == -1 && b != ha->virt_bus) {
3450 ha->raw[BUS_L2P(ha,b)].io_cnt[t]--;
3451 }
3452 /* cache or raw service */
3453 if (ha->status == S_BSY) {
3454 TRACE2(("Controller busy -> retry !\n"));
3455 if (cmndinfo->OpCode == GDT_MOUNT)
3456 cmndinfo->OpCode = GDT_CLUST_INFO;
3457 /* retry */
3458 return 2;
3459 }
3460 if (gdth_bufflen(scp))
3461 pci_unmap_sg(ha->pdev, gdth_sglist(scp), gdth_sg_count(scp),
3462 cmndinfo->dma_dir);
3463
3464 if (cmndinfo->sense_paddr)
3465 pci_unmap_page(ha->pdev, cmndinfo->sense_paddr, 16,
3466 PCI_DMA_FROMDEVICE);
3467
3468 if (ha->status == S_OK) {
3469 cmndinfo->status = S_OK;
3470 cmndinfo->info = ha->info;
3471 if (cmndinfo->OpCode != -1) {
3472 TRACE2(("gdth_sync_event(): special cmd 0x%x OK\n",
3473 cmndinfo->OpCode));
3474 /* special commands GDT_CLUST_INFO/GDT_MOUNT ? */
3475 if (cmndinfo->OpCode == GDT_CLUST_INFO) {
3476 ha->hdr[t].cluster_type = (unchar)ha->info;
3477 if (!(ha->hdr[t].cluster_type &
3478 CLUSTER_MOUNTED)) {
3479 /* NOT MOUNTED -> MOUNT */
3480 cmndinfo->OpCode = GDT_MOUNT;
3481 if (ha->hdr[t].cluster_type &
3482 CLUSTER_RESERVED) {
3483 /* cluster drive RESERVED (on the other node) */
3484 cmndinfo->phase = -2; /* reservation conflict */
3485 }
3486 } else {
3487 cmndinfo->OpCode = -1;
3488 }
3489 } else {
3490 if (cmndinfo->OpCode == GDT_MOUNT) {
3491 ha->hdr[t].cluster_type |= CLUSTER_MOUNTED;
3492 ha->hdr[t].media_changed = TRUE;
3493 } else if (cmndinfo->OpCode == GDT_UNMOUNT) {
3494 ha->hdr[t].cluster_type &= ~CLUSTER_MOUNTED;
3495 ha->hdr[t].media_changed = TRUE;
3496 }
3497 cmndinfo->OpCode = -1;
3498 }
3499 /* retry */
3500 cmndinfo->priority = HIGH_PRI;
3501 return 2;
3502 } else {
3503 /* RESERVE/RELEASE ? */
3504 if (scp->cmnd[0] == RESERVE) {
3505 ha->hdr[t].cluster_type |= CLUSTER_RESERVED;
3506 } else if (scp->cmnd[0] == RELEASE) {
3507 ha->hdr[t].cluster_type &= ~CLUSTER_RESERVED;
3508 }
3509 scp->result = DID_OK << 16;
3510 scp->sense_buffer[0] = 0;
3511 }
3512 } else {
3513 cmndinfo->status = ha->status;
3514 cmndinfo->info = ha->info;
3515
3516 if (cmndinfo->OpCode != -1) {
3517 TRACE2(("gdth_sync_event(): special cmd 0x%x error 0x%x\n",
3518 cmndinfo->OpCode, ha->status));
3519 if (cmndinfo->OpCode == GDT_SCAN_START ||
3520 cmndinfo->OpCode == GDT_SCAN_END) {
3521 cmndinfo->OpCode = -1;
3522 /* retry */
3523 cmndinfo->priority = HIGH_PRI;
3524 return 2;
3525 }
3526 memset((char*)scp->sense_buffer,0,16);
3527 scp->sense_buffer[0] = 0x70;
3528 scp->sense_buffer[2] = NOT_READY;
3529 scp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
3530 } else if (service == CACHESERVICE) {
3531 if (ha->status == S_CACHE_UNKNOWN &&
3532 (ha->hdr[t].cluster_type &
3533 CLUSTER_RESERVE_STATE) == CLUSTER_RESERVE_STATE) {
3534 /* bus reset -> force GDT_CLUST_INFO */
3535 ha->hdr[t].cluster_type &= ~CLUSTER_RESERVED;
3536 }
3537 memset((char*)scp->sense_buffer,0,16);
3538 if (ha->status == (ushort)S_CACHE_RESERV) {
3539 scp->result = (DID_OK << 16) | (RESERVATION_CONFLICT << 1);
3540 } else {
3541 scp->sense_buffer[0] = 0x70;
3542 scp->sense_buffer[2] = NOT_READY;
3543 scp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
3544 }
3545 if (!cmndinfo->internal_command) {
3546 ha->dvr.size = sizeof(ha->dvr.eu.sync);
3547 ha->dvr.eu.sync.ionode = ha->hanum;
3548 ha->dvr.eu.sync.service = service;
3549 ha->dvr.eu.sync.status = ha->status;
3550 ha->dvr.eu.sync.info = ha->info;
3551 ha->dvr.eu.sync.hostdrive = t;
3552 if (ha->status >= 0x8000)
3553 gdth_store_event(ha, ES_SYNC, 0, &ha->dvr);
3554 else
3555 gdth_store_event(ha, ES_SYNC, service, &ha->dvr);
3556 }
3557 } else {
3558 /* sense buffer filled from controller firmware (DMA) */
3559 if (ha->status != S_RAW_SCSI || ha->info >= 0x100) {
3560 scp->result = DID_BAD_TARGET << 16;
3561 } else {
3562 scp->result = (DID_OK << 16) | ha->info;
3563 }
3564 }
3565 }
3566 if (!cmndinfo->wait_for_completion)
3567 cmndinfo->wait_for_completion++;
3568 else
3569 return 1;
3570 }
3571
3572 return 0;
3573 }
3574
3575 static char *async_cache_tab[] = {
3576 /* 0*/ "\011\000\002\002\002\004\002\006\004"
3577 "GDT HA %u, service %u, async. status %u/%lu unknown",
3578 /* 1*/ "\011\000\002\002\002\004\002\006\004"
3579 "GDT HA %u, service %u, async. status %u/%lu unknown",
3580 /* 2*/ "\005\000\002\006\004"
3581 "GDT HA %u, Host Drive %lu not ready",
3582 /* 3*/ "\005\000\002\006\004"
3583 "GDT HA %u, Host Drive %lu: REASSIGN not successful and/or data error on reassigned blocks. Drive may crash in the future and should be replaced",
3584 /* 4*/ "\005\000\002\006\004"
3585 "GDT HA %u, mirror update on Host Drive %lu failed",
3586 /* 5*/ "\005\000\002\006\004"
3587 "GDT HA %u, Mirror Drive %lu failed",
3588 /* 6*/ "\005\000\002\006\004"
3589 "GDT HA %u, Mirror Drive %lu: REASSIGN not successful and/or data error on reassigned blocks. Drive may crash in the future and should be replaced",
3590 /* 7*/ "\005\000\002\006\004"
3591 "GDT HA %u, Host Drive %lu write protected",
3592 /* 8*/ "\005\000\002\006\004"
3593 "GDT HA %u, media changed in Host Drive %lu",
3594 /* 9*/ "\005\000\002\006\004"
3595 "GDT HA %u, Host Drive %lu is offline",
3596 /*10*/ "\005\000\002\006\004"
3597 "GDT HA %u, media change of Mirror Drive %lu",
3598 /*11*/ "\005\000\002\006\004"
3599 "GDT HA %u, Mirror Drive %lu is write protected",
3600 /*12*/ "\005\000\002\006\004"
3601 "GDT HA %u, general error on Host Drive %lu. Please check the devices of this drive!",
3602 /*13*/ "\007\000\002\006\002\010\002"
3603 "GDT HA %u, Array Drive %u: Cache Drive %u failed",
3604 /*14*/ "\005\000\002\006\002"
3605 "GDT HA %u, Array Drive %u: FAIL state entered",
3606 /*15*/ "\005\000\002\006\002"
3607 "GDT HA %u, Array Drive %u: error",
3608 /*16*/ "\007\000\002\006\002\010\002"
3609 "GDT HA %u, Array Drive %u: failed drive replaced by Cache Drive %u",
3610 /*17*/ "\005\000\002\006\002"
3611 "GDT HA %u, Array Drive %u: parity build failed",
3612 /*18*/ "\005\000\002\006\002"
3613 "GDT HA %u, Array Drive %u: drive rebuild failed",
3614 /*19*/ "\005\000\002\010\002"
3615 "GDT HA %u, Test of Hot Fix %u failed",
3616 /*20*/ "\005\000\002\006\002"
3617 "GDT HA %u, Array Drive %u: drive build finished successfully",
3618 /*21*/ "\005\000\002\006\002"
3619 "GDT HA %u, Array Drive %u: drive rebuild finished successfully",
3620 /*22*/ "\007\000\002\006\002\010\002"
3621 "GDT HA %u, Array Drive %u: Hot Fix %u activated",
3622 /*23*/ "\005\000\002\006\002"
3623 "GDT HA %u, Host Drive %u: processing of i/o aborted due to serious drive error",
3624 /*24*/ "\005\000\002\010\002"
3625 "GDT HA %u, mirror update on Cache Drive %u completed",
3626 /*25*/ "\005\000\002\010\002"
3627 "GDT HA %u, mirror update on Cache Drive %lu failed",
3628 /*26*/ "\005\000\002\006\002"
3629 "GDT HA %u, Array Drive %u: drive rebuild started",
3630 /*27*/ "\005\000\002\012\001"
3631 "GDT HA %u, Fault bus %u: SHELF OK detected",
3632 /*28*/ "\005\000\002\012\001"
3633 "GDT HA %u, Fault bus %u: SHELF not OK detected",
3634 /*29*/ "\007\000\002\012\001\013\001"
3635 "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug started",
3636 /*30*/ "\007\000\002\012\001\013\001"
3637 "GDT HA %u, Fault bus %u, ID %u: new disk detected",
3638 /*31*/ "\007\000\002\012\001\013\001"
3639 "GDT HA %u, Fault bus %u, ID %u: old disk detected",
3640 /*32*/ "\007\000\002\012\001\013\001"
3641 "GDT HA %u, Fault bus %u, ID %u: plugging an active disk is invalid",
3642 /*33*/ "\007\000\002\012\001\013\001"
3643 "GDT HA %u, Fault bus %u, ID %u: invalid device detected",
3644 /*34*/ "\011\000\002\012\001\013\001\006\004"
3645 "GDT HA %u, Fault bus %u, ID %u: insufficient disk capacity (%lu MB required)",
3646 /*35*/ "\007\000\002\012\001\013\001"
3647 "GDT HA %u, Fault bus %u, ID %u: disk write protected",
3648 /*36*/ "\007\000\002\012\001\013\001"
3649 "GDT HA %u, Fault bus %u, ID %u: disk not available",
3650 /*37*/ "\007\000\002\012\001\006\004"
3651 "GDT HA %u, Fault bus %u: swap detected (%lu)",
3652 /*38*/ "\007\000\002\012\001\013\001"
3653 "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug finished successfully",
3654 /*39*/ "\007\000\002\012\001\013\001"
3655 "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug aborted due to user Hot Plug",
3656 /*40*/ "\007\000\002\012\001\013\001"
3657 "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug aborted",
3658 /*41*/ "\007\000\002\012\001\013\001"
3659 "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug for Hot Fix started",
3660 /*42*/ "\005\000\002\006\002"
3661 "GDT HA %u, Array Drive %u: drive build started",
3662 /*43*/ "\003\000\002"
3663 "GDT HA %u, DRAM parity error detected",
3664 /*44*/ "\005\000\002\006\002"
3665 "GDT HA %u, Mirror Drive %u: update started",
3666 /*45*/ "\007\000\002\006\002\010\002"
3667 "GDT HA %u, Mirror Drive %u: Hot Fix %u activated",
3668 /*46*/ "\005\000\002\006\002"
3669 "GDT HA %u, Array Drive %u: no matching Pool Hot Fix Drive available",
3670 /*47*/ "\005\000\002\006\002"
3671 "GDT HA %u, Array Drive %u: Pool Hot Fix Drive available",
3672 /*48*/ "\005\000\002\006\002"
3673 "GDT HA %u, Mirror Drive %u: no matching Pool Hot Fix Drive available",
3674 /*49*/ "\005\000\002\006\002"
3675 "GDT HA %u, Mirror Drive %u: Pool Hot Fix Drive available",
3676 /*50*/ "\007\000\002\012\001\013\001"
3677 "GDT HA %u, SCSI bus %u, ID %u: IGNORE_WIDE_RESIDUE message received",
3678 /*51*/ "\005\000\002\006\002"
3679 "GDT HA %u, Array Drive %u: expand started",
3680 /*52*/ "\005\000\002\006\002"
3681 "GDT HA %u, Array Drive %u: expand finished successfully",
3682 /*53*/ "\005\000\002\006\002"
3683 "GDT HA %u, Array Drive %u: expand failed",
3684 /*54*/ "\003\000\002"
3685 "GDT HA %u, CPU temperature critical",
3686 /*55*/ "\003\000\002"
3687 "GDT HA %u, CPU temperature OK",
3688 /*56*/ "\005\000\002\006\004"
3689 "GDT HA %u, Host drive %lu created",
3690 /*57*/ "\005\000\002\006\002"
3691 "GDT HA %u, Array Drive %u: expand restarted",
3692 /*58*/ "\005\000\002\006\002"
3693 "GDT HA %u, Array Drive %u: expand stopped",
3694 /*59*/ "\005\000\002\010\002"
3695 "GDT HA %u, Mirror Drive %u: drive build quited",
3696 /*60*/ "\005\000\002\006\002"
3697 "GDT HA %u, Array Drive %u: parity build quited",
3698 /*61*/ "\005\000\002\006\002"
3699 "GDT HA %u, Array Drive %u: drive rebuild quited",
3700 /*62*/ "\005\000\002\006\002"
3701 "GDT HA %u, Array Drive %u: parity verify started",
3702 /*63*/ "\005\000\002\006\002"
3703 "GDT HA %u, Array Drive %u: parity verify done",
3704 /*64*/ "\005\000\002\006\002"
3705 "GDT HA %u, Array Drive %u: parity verify failed",
3706 /*65*/ "\005\000\002\006\002"
3707 "GDT HA %u, Array Drive %u: parity error detected",
3708 /*66*/ "\005\000\002\006\002"
3709 "GDT HA %u, Array Drive %u: parity verify quited",
3710 /*67*/ "\005\000\002\006\002"
3711 "GDT HA %u, Host Drive %u reserved",
3712 /*68*/ "\005\000\002\006\002"
3713 "GDT HA %u, Host Drive %u mounted and released",
3714 /*69*/ "\005\000\002\006\002"
3715 "GDT HA %u, Host Drive %u released",
3716 /*70*/ "\003\000\002"
3717 "GDT HA %u, DRAM error detected and corrected with ECC",
3718 /*71*/ "\003\000\002"
3719 "GDT HA %u, Uncorrectable DRAM error detected with ECC",
3720 /*72*/ "\011\000\002\012\001\013\001\014\001"
3721 "GDT HA %u, SCSI bus %u, ID %u, LUN %u: reassigning block",
3722 /*73*/ "\005\000\002\006\002"
3723 "GDT HA %u, Host drive %u resetted locally",
3724 /*74*/ "\005\000\002\006\002"
3725 "GDT HA %u, Host drive %u resetted remotely",
3726 /*75*/ "\003\000\002"
3727 "GDT HA %u, async. status 75 unknown",
3728 };
3729
3730
3731 static int gdth_async_event(gdth_ha_str *ha)
3732 {
3733 gdth_cmd_str *cmdp;
3734 int cmd_index;
3735
3736 cmdp= ha->pccb;
3737 TRACE2(("gdth_async_event() ha %d serv %d\n",
3738 ha->hanum, ha->service));
3739
3740 if (ha->service == SCREENSERVICE) {
3741 if (ha->status == MSG_REQUEST) {
3742 while (gdth_test_busy(ha))
3743 gdth_delay(0);
3744 cmdp->Service = SCREENSERVICE;
3745 cmdp->RequestBuffer = SCREEN_CMND;
3746 cmd_index = gdth_get_cmd_index(ha);
3747 gdth_set_sema0(ha);
3748 cmdp->OpCode = GDT_READ;
3749 cmdp->BoardNode = LOCALBOARD;
3750 cmdp->u.screen.reserved = 0;
3751 cmdp->u.screen.su.msg.msg_handle= MSG_INV_HANDLE;
3752 cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
3753 ha->cmd_offs_dpmem = 0;
3754 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
3755 + sizeof(ulong64);
3756 ha->cmd_cnt = 0;
3757 gdth_copy_command(ha);
3758 if (ha->type == GDT_EISA)
3759 printk("[EISA slot %d] ",(ushort)ha->brd_phys);
3760 else if (ha->type == GDT_ISA)
3761 printk("[DPMEM 0x%4X] ",(ushort)ha->brd_phys);
3762 else
3763 printk("[PCI %d/%d] ",(ushort)(ha->brd_phys>>8),
3764 (ushort)((ha->brd_phys>>3)&0x1f));
3765 gdth_release_event(ha);
3766 }
3767
3768 } else {
3769 if (ha->type == GDT_PCIMPR &&
3770 (ha->fw_vers & 0xff) >= 0x1a) {
3771 ha->dvr.size = 0;
3772 ha->dvr.eu.async.ionode = ha->hanum;
3773 ha->dvr.eu.async.status = ha->status;
3774 /* severity and event_string already set! */
3775 } else {
3776 ha->dvr.size = sizeof(ha->dvr.eu.async);
3777 ha->dvr.eu.async.ionode = ha->hanum;
3778 ha->dvr.eu.async.service = ha->service;
3779 ha->dvr.eu.async.status = ha->status;
3780 ha->dvr.eu.async.info = ha->info;
3781 *(ulong32 *)ha->dvr.eu.async.scsi_coord = ha->info2;
3782 }
3783 gdth_store_event( ha, ES_ASYNC, ha->service, &ha->dvr );
3784 gdth_log_event( &ha->dvr, NULL );
3785
3786 /* new host drive from expand? */
3787 if (ha->service == CACHESERVICE && ha->status == 56) {
3788 TRACE2(("gdth_async_event(): new host drive %d created\n",
3789 (ushort)ha->info));
3790 /* gdth_analyse_hdrive(hanum, (ushort)ha->info); */
3791 }
3792 }
3793 return 1;
3794 }
3795
3796 static void gdth_log_event(gdth_evt_data *dvr, char *buffer)
3797 {
3798 gdth_stackframe stack;
3799 char *f = NULL;
3800 int i,j;
3801
3802 TRACE2(("gdth_log_event()\n"));
3803 if (dvr->size == 0) {
3804 if (buffer == NULL) {
3805 printk("Adapter %d: %s\n",dvr->eu.async.ionode,dvr->event_string);
3806 } else {
3807 sprintf(buffer,"Adapter %d: %s\n",
3808 dvr->eu.async.ionode,dvr->event_string);
3809 }
3810 } else if (dvr->eu.async.service == CACHESERVICE &&
3811 INDEX_OK(dvr->eu.async.status, async_cache_tab)) {
3812 TRACE2(("GDT: Async. event cache service, event no.: %d\n",
3813 dvr->eu.async.status));
3814
3815 f = async_cache_tab[dvr->eu.async.status];
3816
3817 /* i: parameter to push, j: stack element to fill */
3818 for (j=0,i=1; i < f[0]; i+=2) {
3819 switch (f[i+1]) {
3820 case 4:
3821 stack.b[j++] = *(ulong32*)&dvr->eu.stream[(int)f[i]];
3822 break;
3823 case 2:
3824 stack.b[j++] = *(ushort*)&dvr->eu.stream[(int)f[i]];
3825 break;
3826 case 1:
3827 stack.b[j++] = *(unchar*)&dvr->eu.stream[(int)f[i]];
3828 break;
3829 default:
3830 break;
3831 }
3832 }
3833
3834 if (buffer == NULL) {
3835 printk(&f[(int)f[0]],stack);
3836 printk("\n");
3837 } else {
3838 sprintf(buffer,&f[(int)f[0]],stack);
3839 }
3840
3841 } else {
3842 if (buffer == NULL) {
3843 printk("GDT HA %u, Unknown async. event service %d event no. %d\n",
3844 dvr->eu.async.ionode,dvr->eu.async.service,dvr->eu.async.status);
3845 } else {
3846 sprintf(buffer,"GDT HA %u, Unknown async. event service %d event no. %d",
3847 dvr->eu.async.ionode,dvr->eu.async.service,dvr->eu.async.status);
3848 }
3849 }
3850 }
3851
3852 #ifdef GDTH_STATISTICS
3853 static void gdth_timeout(ulong data)
3854 {
3855 ulong32 i;
3856 Scsi_Cmnd *nscp;
3857 gdth_ha_str *ha;
3858 ulong flags;
3859
3860 <<<<<<< HEAD:drivers/scsi/gdth.c
3861 =======
3862 BUG_ON(list_empty(&gdth_instances));
3863
3864 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/scsi/gdth.c
3865 ha = list_first_entry(&gdth_instances, gdth_ha_str, list);
3866 spin_lock_irqsave(&ha->smp_lock, flags);
3867
3868 for (act_stats=0,i=0; i<GDTH_MAXCMDS; ++i)
3869 if (ha->cmd_tab[i].cmnd != UNUSED_CMND)
3870 ++act_stats;
3871
3872 for (act_rq=0,nscp=ha->req_first; nscp; nscp=(Scsi_Cmnd*)nscp->SCp.ptr)
3873 ++act_rq;
3874
3875 TRACE2(("gdth_to(): ints %d, ios %d, act_stats %d, act_rq %d\n",
3876 act_ints, act_ios, act_stats, act_rq));
3877 act_ints = act_ios = 0;
3878
3879 gdth_timer.expires = jiffies + 30 * HZ;
3880 add_timer(&gdth_timer);
3881 spin_unlock_irqrestore(&ha->smp_lock, flags);
3882 }
3883 #endif
3884
3885 static void __init internal_setup(char *str,int *ints)
3886 {
3887 int i, argc;
3888 char *cur_str, *argv;
3889
3890 TRACE2(("internal_setup() str %s ints[0] %d\n",
3891 str ? str:"NULL", ints ? ints[0]:0));
3892
3893 /* read irq[] from ints[] */
3894 if (ints) {
3895 argc = ints[0];
3896 if (argc > 0) {
3897 if (argc > MAXHA)
3898 argc = MAXHA;
3899 for (i = 0; i < argc; ++i)
3900 irq[i] = ints[i+1];
3901 }
3902 }
3903
3904 /* analyse string */
3905 argv = str;
3906 while (argv && (cur_str = strchr(argv, ':'))) {
3907 int val = 0, c = *++cur_str;
3908
3909 if (c == 'n' || c == 'N')
3910 val = 0;
3911 else if (c == 'y' || c == 'Y')
3912 val = 1;
3913 else
3914 val = (int)simple_strtoul(cur_str, NULL, 0);
3915
3916 if (!strncmp(argv, "disable:", 8))
3917 disable = val;
3918 else if (!strncmp(argv, "reserve_mode:", 13))
3919 reserve_mode = val;
3920 else if (!strncmp(argv, "reverse_scan:", 13))
3921 reverse_scan = val;
3922 else if (!strncmp(argv, "hdr_channel:", 12))
3923 hdr_channel = val;
3924 else if (!strncmp(argv, "max_ids:", 8))
3925 max_ids = val;
3926 else if (!strncmp(argv, "rescan:", 7))
3927 rescan = val;
3928 else if (!strncmp(argv, "shared_access:", 14))
3929 shared_access = val;
3930 else if (!strncmp(argv, "probe_eisa_isa:", 15))
3931 probe_eisa_isa = val;
3932 else if (!strncmp(argv, "reserve_list:", 13)) {
3933 reserve_list[0] = val;
3934 for (i = 1; i < MAX_RES_ARGS; i++) {
3935 cur_str = strchr(cur_str, ',');
3936 if (!cur_str)
3937 break;
3938 if (!isdigit((int)*++cur_str)) {
3939 --cur_str;
3940 break;
3941 }
3942 reserve_list[i] =
3943 (int)simple_strtoul(cur_str, NULL, 0);
3944 }
3945 if (!cur_str)
3946 break;
3947 argv = ++cur_str;
3948 continue;
3949 }
3950
3951 if ((argv = strchr(argv, ',')))
3952 ++argv;
3953 }
3954 }
3955
3956 int __init option_setup(char *str)
3957 {
3958 int ints[MAXHA];
3959 char *cur = str;
3960 int i = 1;
3961
3962 TRACE2(("option_setup() str %s\n", str ? str:"NULL"));
3963
3964 while (cur && isdigit(*cur) && i <= MAXHA) {
3965 ints[i++] = simple_strtoul(cur, NULL, 0);
3966 if ((cur = strchr(cur, ',')) != NULL) cur++;
3967 }
3968
3969 ints[0] = i - 1;
3970 internal_setup(cur, ints);
3971 return 1;
3972 }
3973
3974 static const char *gdth_ctr_name(gdth_ha_str *ha)
3975 {
3976 TRACE2(("gdth_ctr_name()\n"));
3977
3978 if (ha->type == GDT_EISA) {
3979 switch (ha->stype) {
3980 case GDT3_ID:
3981 return("GDT3000/3020");
3982 case GDT3A_ID:
3983 return("GDT3000A/3020A/3050A");
3984 case GDT3B_ID:
3985 return("GDT3000B/3010A");
3986 }
3987 } else if (ha->type == GDT_ISA) {
3988 return("GDT2000/2020");
3989 } else if (ha->type == GDT_PCI) {
3990 switch (ha->pdev->device) {
3991 case PCI_DEVICE_ID_VORTEX_GDT60x0:
3992 return("GDT6000/6020/6050");
3993 case PCI_DEVICE_ID_VORTEX_GDT6000B:
3994 return("GDT6000B/6010");
3995 }
3996 }
3997 /* new controllers (GDT_PCINEW, GDT_PCIMPR, ..) use board_info IOCTL! */
3998
3999 return("");
4000 }
4001
4002 static const char *gdth_info(struct Scsi_Host *shp)
4003 {
4004 gdth_ha_str *ha = shost_priv(shp);
4005
4006 TRACE2(("gdth_info()\n"));
4007 return ((const char *)ha->binfo.type_string);
4008 }
4009
4010 static int gdth_eh_bus_reset(Scsi_Cmnd *scp)
4011 {
4012 gdth_ha_str *ha = shost_priv(scp->device->host);
4013 int i;
4014 ulong flags;
4015 Scsi_Cmnd *cmnd;
4016 unchar b;
4017
4018 TRACE2(("gdth_eh_bus_reset()\n"));
4019
4020 b = scp->device->channel;
4021
4022 /* clear command tab */
4023 spin_lock_irqsave(&ha->smp_lock, flags);
4024 for (i = 0; i < GDTH_MAXCMDS; ++i) {
4025 cmnd = ha->cmd_tab[i].cmnd;
4026 if (!SPECIAL_SCP(cmnd) && cmnd->device->channel == b)
4027 ha->cmd_tab[i].cmnd = UNUSED_CMND;
4028 }
4029 spin_unlock_irqrestore(&ha->smp_lock, flags);
4030
4031 if (b == ha->virt_bus) {
4032 /* host drives */
4033 for (i = 0; i < MAX_HDRIVES; ++i) {
4034 if (ha->hdr[i].present) {
4035 spin_lock_irqsave(&ha->smp_lock, flags);
4036 gdth_polling = TRUE;
4037 while (gdth_test_busy(ha))
4038 gdth_delay(0);
4039 if (gdth_internal_cmd(ha, CACHESERVICE,
4040 GDT_CLUST_RESET, i, 0, 0))
4041 ha->hdr[i].cluster_type &= ~CLUSTER_RESERVED;
4042 gdth_polling = FALSE;
4043 spin_unlock_irqrestore(&ha->smp_lock, flags);
4044 }
4045 }
4046 } else {
4047 /* raw devices */
4048 spin_lock_irqsave(&ha->smp_lock, flags);
4049 for (i = 0; i < MAXID; ++i)
4050 ha->raw[BUS_L2P(ha,b)].io_cnt[i] = 0;
4051 gdth_polling = TRUE;
4052 while (gdth_test_busy(ha))
4053 gdth_delay(0);
4054 gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_RESET_BUS,
4055 BUS_L2P(ha,b), 0, 0);
4056 gdth_polling = FALSE;
4057 spin_unlock_irqrestore(&ha->smp_lock, flags);
4058 }
4059 return SUCCESS;
4060 }
4061
4062 static int gdth_bios_param(struct scsi_device *sdev,struct block_device *bdev,sector_t cap,int *ip)
4063 {
4064 unchar b, t;
4065 gdth_ha_str *ha = shost_priv(sdev->host);
4066 struct scsi_device *sd;
4067 unsigned capacity;
4068
4069 sd = sdev;
4070 capacity = cap;
4071 b = sd->channel;
4072 t = sd->id;
4073 TRACE2(("gdth_bios_param() ha %d bus %d target %d\n", ha->hanum, b, t));
4074
4075 if (b != ha->virt_bus || ha->hdr[t].heads == 0) {
4076 /* raw device or host drive without mapping information */
4077 TRACE2(("Evaluate mapping\n"));
4078 gdth_eval_mapping(capacity,&ip[2],&ip[0],&ip[1]);
4079 } else {
4080 ip[0] = ha->hdr[t].heads;
4081 ip[1] = ha->hdr[t].secs;
4082 ip[2] = capacity / ip[0] / ip[1];
4083 }
4084
4085 TRACE2(("gdth_bios_param(): %d heads, %d secs, %d cyls\n",
4086 ip[0],ip[1],ip[2]));
4087 return 0;
4088 }
4089
4090
4091 static int gdth_queuecommand(struct scsi_cmnd *scp,
4092 void (*done)(struct scsi_cmnd *))
4093 {
4094 gdth_ha_str *ha = shost_priv(scp->device->host);
4095 struct gdth_cmndinfo *cmndinfo;
4096
4097 TRACE(("gdth_queuecommand() cmd 0x%x\n", scp->cmnd[0]));
4098
4099 cmndinfo = gdth_get_cmndinfo(ha);
4100 BUG_ON(!cmndinfo);
4101
4102 scp->scsi_done = done;
4103 gdth_update_timeout(scp, scp->timeout_per_command * 6);
4104 cmndinfo->priority = DEFAULT_PRI;
4105
4106 gdth_set_bufflen(scp, scsi_bufflen(scp));
4107 gdth_set_sg_count(scp, scsi_sg_count(scp));
4108 gdth_set_sglist(scp, scsi_sglist(scp));
4109
4110 return __gdth_queuecommand(ha, scp, cmndinfo);
4111 }
4112
4113 static int __gdth_queuecommand(gdth_ha_str *ha, struct scsi_cmnd *scp,
4114 struct gdth_cmndinfo *cmndinfo)
4115 {
4116 scp->host_scribble = (unsigned char *)cmndinfo;
4117 cmndinfo->wait_for_completion = 1;
4118 cmndinfo->phase = -1;
4119 cmndinfo->OpCode = -1;
4120
4121 #ifdef GDTH_STATISTICS
4122 ++act_ios;
4123 #endif
4124
4125 gdth_putq(ha, scp, cmndinfo->priority);
4126 gdth_next(ha);
4127 return 0;
4128 }
4129
4130
4131 static int gdth_open(struct inode *inode, struct file *filep)
4132 {
4133 gdth_ha_str *ha;
4134
4135 list_for_each_entry(ha, &gdth_instances, list) {
4136 if (!ha->sdev)
4137 ha->sdev = scsi_get_host_dev(ha->shost);
4138 }
4139
4140 TRACE(("gdth_open()\n"));
4141 return 0;
4142 }
4143
4144 static int gdth_close(struct inode *inode, struct file *filep)
4145 {
4146 TRACE(("gdth_close()\n"));
4147 return 0;
4148 }
4149
4150 static int ioc_event(void __user *arg)
4151 {
4152 gdth_ioctl_event evt;
4153 gdth_ha_str *ha;
4154 ulong flags;
4155
4156 if (copy_from_user(&evt, arg, sizeof(gdth_ioctl_event)))
4157 return -EFAULT;
4158 ha = gdth_find_ha(evt.ionode);
4159 if (!ha)
4160 return -EFAULT;
4161
4162 if (evt.erase == 0xff) {
4163 if (evt.event.event_source == ES_TEST)
4164 evt.event.event_data.size=sizeof(evt.event.event_data.eu.test);
4165 else if (evt.event.event_source == ES_DRIVER)
4166 evt.event.event_data.size=sizeof(evt.event.event_data.eu.driver);
4167 else if (evt.event.event_source == ES_SYNC)
4168 evt.event.event_data.size=sizeof(evt.event.event_data.eu.sync);
4169 else
4170 evt.event.event_data.size=sizeof(evt.event.event_data.eu.async);
4171 spin_lock_irqsave(&ha->smp_lock, flags);
4172 gdth_store_event(ha, evt.event.event_source, evt.event.event_idx,
4173 &evt.event.event_data);
4174 spin_unlock_irqrestore(&ha->smp_lock, flags);
4175 } else if (evt.erase == 0xfe) {
4176 gdth_clear_events();
4177 } else if (evt.erase == 0) {
4178 evt.handle = gdth_read_event(ha, evt.handle, &evt.event);
4179 } else {
4180 gdth_readapp_event(ha, evt.erase, &evt.event);
4181 }
4182 if (copy_to_user(arg, &evt, sizeof(gdth_ioctl_event)))
4183 return -EFAULT;
4184 return 0;
4185 }
4186
4187 static int ioc_lockdrv(void __user *arg)
4188 {
4189 gdth_ioctl_lockdrv ldrv;
4190 unchar i, j;
4191 ulong flags;
4192 gdth_ha_str *ha;
4193
4194 if (copy_from_user(&ldrv, arg, sizeof(gdth_ioctl_lockdrv)))
4195 return -EFAULT;
4196 ha = gdth_find_ha(ldrv.ionode);
4197 if (!ha)
4198 return -EFAULT;
4199
4200 for (i = 0; i < ldrv.drive_cnt && i < MAX_HDRIVES; ++i) {
4201 j = ldrv.drives[i];
4202 if (j >= MAX_HDRIVES || !ha->hdr[j].present)
4203 continue;
4204 if (ldrv.lock) {
4205 spin_lock_irqsave(&ha->smp_lock, flags);
4206 ha->hdr[j].lock = 1;
4207 spin_unlock_irqrestore(&ha->smp_lock, flags);
4208 gdth_wait_completion(ha, ha->bus_cnt, j);
4209 gdth_stop_timeout(ha, ha->bus_cnt, j);
4210 } else {
4211 spin_lock_irqsave(&ha->smp_lock, flags);
4212 ha->hdr[j].lock = 0;
4213 spin_unlock_irqrestore(&ha->smp_lock, flags);
4214 gdth_start_timeout(ha, ha->bus_cnt, j);
4215 gdth_next(ha);
4216 }
4217 }
4218 return 0;
4219 }
4220
4221 static int ioc_resetdrv(void __user *arg, char *cmnd)
4222 {
4223 gdth_ioctl_reset res;
4224 gdth_cmd_str cmd;
4225 gdth_ha_str *ha;
4226 int rval;
4227
4228 if (copy_from_user(&res, arg, sizeof(gdth_ioctl_reset)) ||
4229 res.number >= MAX_HDRIVES)
4230 return -EFAULT;
4231 ha = gdth_find_ha(res.ionode);
4232 if (!ha)
4233 return -EFAULT;
4234
4235 if (!ha->hdr[res.number].present)
4236 return 0;
4237 memset(&cmd, 0, sizeof(gdth_cmd_str));
4238 cmd.Service = CACHESERVICE;
4239 cmd.OpCode = GDT_CLUST_RESET;
4240 if (ha->cache_feat & GDT_64BIT)
4241 cmd.u.cache64.DeviceNo = res.number;
4242 else
4243 cmd.u.cache.DeviceNo = res.number;
4244
4245 rval = __gdth_execute(ha->sdev, &cmd, cmnd, 30, NULL);
4246 if (rval < 0)
4247 return rval;
4248 res.status = rval;
4249
4250 if (copy_to_user(arg, &res, sizeof(gdth_ioctl_reset)))
4251 return -EFAULT;
4252 return 0;
4253 }
4254
4255 static int ioc_general(void __user *arg, char *cmnd)
4256 {
4257 gdth_ioctl_general gen;
4258 char *buf = NULL;
4259 ulong64 paddr;
4260 gdth_ha_str *ha;
4261 int rval;
4262
4263 if (copy_from_user(&gen, arg, sizeof(gdth_ioctl_general)))
4264 return -EFAULT;
4265 ha = gdth_find_ha(gen.ionode);
4266 if (!ha)
4267 return -EFAULT;
4268 if (gen.data_len + gen.sense_len != 0) {
4269 if (!(buf = gdth_ioctl_alloc(ha, gen.data_len + gen.sense_len,
4270 FALSE, &paddr)))
4271 return -EFAULT;
4272 if (copy_from_user(buf, arg + sizeof(gdth_ioctl_general),
4273 gen.data_len + gen.sense_len)) {
4274 gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
4275 return -EFAULT;
4276 }
4277
4278 if (gen.command.OpCode == GDT_IOCTL) {
4279 gen.command.u.ioctl.p_param = paddr;
4280 } else if (gen.command.Service == CACHESERVICE) {
4281 if (ha->cache_feat & GDT_64BIT) {
4282 /* copy elements from 32-bit IOCTL structure */
4283 gen.command.u.cache64.BlockCnt = gen.command.u.cache.BlockCnt;
4284 gen.command.u.cache64.BlockNo = gen.command.u.cache.BlockNo;
4285 gen.command.u.cache64.DeviceNo = gen.command.u.cache.DeviceNo;
4286 /* addresses */
4287 if (ha->cache_feat & SCATTER_GATHER) {
4288 gen.command.u.cache64.DestAddr = (ulong64)-1;
4289 gen.command.u.cache64.sg_canz = 1;
4290 gen.command.u.cache64.sg_lst[0].sg_ptr = paddr;
4291 gen.command.u.cache64.sg_lst[0].sg_len = gen.data_len;
4292 gen.command.u.cache64.sg_lst[1].sg_len = 0;
4293 } else {
4294 gen.command.u.cache64.DestAddr = paddr;
4295 gen.command.u.cache64.sg_canz = 0;
4296 }
4297 } else {
4298 if (ha->cache_feat & SCATTER_GATHER) {
4299 gen.command.u.cache.DestAddr = 0xffffffff;
4300 gen.command.u.cache.sg_canz = 1;
4301 gen.command.u.cache.sg_lst[0].sg_ptr = (ulong32)paddr;
4302 gen.command.u.cache.sg_lst[0].sg_len = gen.data_len;
4303 gen.command.u.cache.sg_lst[1].sg_len = 0;
4304 } else {
4305 gen.command.u.cache.DestAddr = paddr;
4306 gen.command.u.cache.sg_canz = 0;
4307 }
4308 }
4309 } else if (gen.command.Service == SCSIRAWSERVICE) {
4310 if (ha->raw_feat & GDT_64BIT) {
4311 /* copy elements from 32-bit IOCTL structure */
4312 char cmd[16];
4313 gen.command.u.raw64.sense_len = gen.command.u.raw.sense_len;
4314 gen.command.u.raw64.bus = gen.command.u.raw.bus;
4315 gen.command.u.raw64.lun = gen.command.u.raw.lun;
4316 gen.command.u.raw64.target = gen.command.u.raw.target;
4317 memcpy(cmd, gen.command.u.raw.cmd, 16);
4318 memcpy(gen.command.u.raw64.cmd, cmd, 16);
4319 gen.command.u.raw64.clen = gen.command.u.raw.clen;
4320 gen.command.u.raw64.sdlen = gen.command.u.raw.sdlen;
4321 gen.command.u.raw64.direction = gen.command.u.raw.direction;
4322 /* addresses */
4323 if (ha->raw_feat & SCATTER_GATHER) {
4324 gen.command.u.raw64.sdata = (ulong64)-1;
4325 gen.command.u.raw64.sg_ranz = 1;
4326 gen.command.u.raw64.sg_lst[0].sg_ptr = paddr;
4327 gen.command.u.raw64.sg_lst[0].sg_len = gen.data_len;
4328 gen.command.u.raw64.sg_lst[1].sg_len = 0;
4329 } else {
4330 gen.command.u.raw64.sdata = paddr;
4331 gen.command.u.raw64.sg_ranz = 0;
4332 }
4333 gen.command.u.raw64.sense_data = paddr + gen.data_len;
4334 } else {
4335 if (ha->raw_feat & SCATTER_GATHER) {
4336 gen.command.u.raw.sdata = 0xffffffff;
4337 gen.command.u.raw.sg_ranz = 1;
4338 gen.command.u.raw.sg_lst[0].sg_ptr = (ulong32)paddr;
4339 gen.command.u.raw.sg_lst[0].sg_len = gen.data_len;
4340 gen.command.u.raw.sg_lst[1].sg_len = 0;
4341 } else {
4342 gen.command.u.raw.sdata = paddr;
4343 gen.command.u.raw.sg_ranz = 0;
4344 }
4345 gen.command.u.raw.sense_data = (ulong32)paddr + gen.data_len;
4346 }
4347 } else {
4348 gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
4349 return -EFAULT;
4350 }
4351 }
4352
4353 rval = __gdth_execute(ha->sdev, &gen.command, cmnd, gen.timeout, &gen.info);
4354 if (rval < 0)
4355 return rval;
4356 gen.status = rval;
4357
4358 if (copy_to_user(arg + sizeof(gdth_ioctl_general), buf,
4359 gen.data_len + gen.sense_len)) {
4360 gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
4361 return -EFAULT;
4362 }
4363 if (copy_to_user(arg, &gen,
4364 sizeof(gdth_ioctl_general) - sizeof(gdth_cmd_str))) {
4365 gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
4366 return -EFAULT;
4367 }
4368 gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
4369 return 0;
4370 }
4371
4372 static int ioc_hdrlist(void __user *arg, char *cmnd)
4373 {
4374 gdth_ioctl_rescan *rsc;
4375 gdth_cmd_str *cmd;
4376 gdth_ha_str *ha;
4377 unchar i;
4378 int rc = -ENOMEM;
4379 u32 cluster_type = 0;
4380
4381 rsc = kmalloc(sizeof(*rsc), GFP_KERNEL);
4382 cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
4383 if (!rsc || !cmd)
4384 goto free_fail;
4385
4386 if (copy_from_user(rsc, arg, sizeof(gdth_ioctl_rescan)) ||
4387 (NULL == (ha = gdth_find_ha(rsc->ionode)))) {
4388 rc = -EFAULT;
4389 goto free_fail;
4390 }
4391 memset(cmd, 0, sizeof(gdth_cmd_str));
4392
4393 for (i = 0; i < MAX_HDRIVES; ++i) {
4394 if (!ha->hdr[i].present) {
4395 rsc->hdr_list[i].bus = 0xff;
4396 continue;
4397 }
4398 rsc->hdr_list[i].bus = ha->virt_bus;
4399 rsc->hdr_list[i].target = i;
4400 rsc->hdr_list[i].lun = 0;
4401 rsc->hdr_list[i].cluster_type = ha->hdr[i].cluster_type;
4402 if (ha->hdr[i].cluster_type & CLUSTER_DRIVE) {
4403 cmd->Service = CACHESERVICE;
4404 cmd->OpCode = GDT_CLUST_INFO;
4405 if (ha->cache_feat & GDT_64BIT)
4406 cmd->u.cache64.DeviceNo = i;
4407 else
4408 cmd->u.cache.DeviceNo = i;
4409 if (__gdth_execute(ha->sdev, cmd, cmnd, 30, &cluster_type) == S_OK)
4410 rsc->hdr_list[i].cluster_type = cluster_type;
4411 }
4412 }
4413
4414 if (copy_to_user(arg, rsc, sizeof(gdth_ioctl_rescan)))
4415 rc = -EFAULT;
4416 else
4417 rc = 0;
4418
4419 free_fail:
4420 kfree(rsc);
4421 kfree(cmd);
4422 return rc;
4423 }
4424
4425 static int ioc_rescan(void __user *arg, char *cmnd)
4426 {
4427 gdth_ioctl_rescan *rsc;
4428 gdth_cmd_str *cmd;
4429 ushort i, status, hdr_cnt;
4430 ulong32 info;
4431 int cyls, hds, secs;
4432 int rc = -ENOMEM;
4433 ulong flags;
4434 gdth_ha_str *ha;
4435
4436 rsc = kmalloc(sizeof(*rsc), GFP_KERNEL);
4437 cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
4438 if (!cmd || !rsc)
4439 goto free_fail;
4440
4441 if (copy_from_user(rsc, arg, sizeof(gdth_ioctl_rescan)) ||
4442 (NULL == (ha = gdth_find_ha(rsc->ionode)))) {
4443 rc = -EFAULT;
4444 goto free_fail;
4445 }
4446 memset(cmd, 0, sizeof(gdth_cmd_str));
4447
4448 if (rsc->flag == 0) {
4449 /* old method: re-init. cache service */
4450 cmd->Service = CACHESERVICE;
4451 if (ha->cache_feat & GDT_64BIT) {
4452 cmd->OpCode = GDT_X_INIT_HOST;
4453 cmd->u.cache64.DeviceNo = LINUX_OS;
4454 } else {
4455 cmd->OpCode = GDT_INIT;
4456 cmd->u.cache.DeviceNo = LINUX_OS;
4457 }
4458
4459 status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
4460 i = 0;
4461 hdr_cnt = (status == S_OK ? (ushort)info : 0);
4462 } else {
4463 i = rsc->hdr_no;
4464 hdr_cnt = i + 1;
4465 }
4466
4467 for (; i < hdr_cnt && i < MAX_HDRIVES; ++i) {
4468 cmd->Service = CACHESERVICE;
4469 cmd->OpCode = GDT_INFO;
4470 if (ha->cache_feat & GDT_64BIT)
4471 cmd->u.cache64.DeviceNo = i;
4472 else
4473 cmd->u.cache.DeviceNo = i;
4474
4475 status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
4476
4477 spin_lock_irqsave(&ha->smp_lock, flags);
4478 rsc->hdr_list[i].bus = ha->virt_bus;
4479 rsc->hdr_list[i].target = i;
4480 rsc->hdr_list[i].lun = 0;
4481 if (status != S_OK) {
4482 ha->hdr[i].present = FALSE;
4483 } else {
4484 ha->hdr[i].present = TRUE;
4485 ha->hdr[i].size = info;
4486 /* evaluate mapping */
4487 ha->hdr[i].size &= ~SECS32;
4488 gdth_eval_mapping(ha->hdr[i].size,&cyls,&hds,&secs);
4489 ha->hdr[i].heads = hds;
4490 ha->hdr[i].secs = secs;
4491 /* round size */
4492 ha->hdr[i].size = cyls * hds * secs;
4493 }
4494 spin_unlock_irqrestore(&ha->smp_lock, flags);
4495 if (status != S_OK)
4496 continue;
4497
4498 /* extended info, if GDT_64BIT, for drives > 2 TB */
4499 /* but we need ha->info2, not yet stored in scp->SCp */
4500
4501 /* devtype, cluster info, R/W attribs */
4502 cmd->Service = CACHESERVICE;
4503 cmd->OpCode = GDT_DEVTYPE;
4504 if (ha->cache_feat & GDT_64BIT)
4505 cmd->u.cache64.DeviceNo = i;
4506 else
4507 cmd->u.cache.DeviceNo = i;
4508
4509 status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
4510
4511 spin_lock_irqsave(&ha->smp_lock, flags);
4512 ha->hdr[i].devtype = (status == S_OK ? (ushort)info : 0);
4513 spin_unlock_irqrestore(&ha->smp_lock, flags);
4514
4515 cmd->Service = CACHESERVICE;
4516 cmd->OpCode = GDT_CLUST_INFO;
4517 if (ha->cache_feat & GDT_64BIT)
4518 cmd->u.cache64.DeviceNo = i;
4519 else
4520 cmd->u.cache.DeviceNo = i;
4521
4522 status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
4523
4524 spin_lock_irqsave(&ha->smp_lock, flags);
4525 ha->hdr[i].cluster_type =
4526 ((status == S_OK && !shared_access) ? (ushort)info : 0);
4527 spin_unlock_irqrestore(&ha->smp_lock, flags);
4528 rsc->hdr_list[i].cluster_type = ha->hdr[i].cluster_type;
4529
4530 cmd->Service = CACHESERVICE;
4531 cmd->OpCode = GDT_RW_ATTRIBS;
4532 if (ha->cache_feat & GDT_64BIT)
4533 cmd->u.cache64.DeviceNo = i;
4534 else
4535 cmd->u.cache.DeviceNo = i;
4536
4537 status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
4538
4539 spin_lock_irqsave(&ha->smp_lock, flags);
4540 ha->hdr[i].rw_attribs = (status == S_OK ? (ushort)info : 0);
4541 spin_unlock_irqrestore(&ha->smp_lock, flags);
4542 }
4543
4544 if (copy_to_user(arg, rsc, sizeof(gdth_ioctl_rescan)))
4545 rc = -EFAULT;
4546 else
4547 rc = 0;
4548
4549 free_fail:
4550 kfree(rsc);
4551 kfree(cmd);
4552 return rc;
4553 }
4554
4555 static int gdth_ioctl(struct inode *inode, struct file *filep,
4556 unsigned int cmd, unsigned long arg)
4557 {
4558 gdth_ha_str *ha;
4559 Scsi_Cmnd *scp;
4560 ulong flags;
4561 char cmnd[MAX_COMMAND_SIZE];
4562 void __user *argp = (void __user *)arg;
4563
4564 memset(cmnd, 0xff, 12);
4565
4566 TRACE(("gdth_ioctl() cmd 0x%x\n", cmd));
4567
4568 switch (cmd) {
4569 case GDTIOCTL_CTRCNT:
4570 {
4571 int cnt = gdth_ctr_count;
4572 if (put_user(cnt, (int __user *)argp))
4573 return -EFAULT;
4574 break;
4575 }
4576
4577 case GDTIOCTL_DRVERS:
4578 {
4579 int ver = (GDTH_VERSION<<8) | GDTH_SUBVERSION;
4580 if (put_user(ver, (int __user *)argp))
4581 return -EFAULT;
4582 break;
4583 }
4584
4585 case GDTIOCTL_OSVERS:
4586 {
4587 gdth_ioctl_osvers osv;
4588
4589 osv.version = (unchar)(LINUX_VERSION_CODE >> 16);
4590 osv.subversion = (unchar)(LINUX_VERSION_CODE >> 8);
4591 osv.revision = (ushort)(LINUX_VERSION_CODE & 0xff);
4592 if (copy_to_user(argp, &osv, sizeof(gdth_ioctl_osvers)))
4593 return -EFAULT;
4594 break;
4595 }
4596
4597 case GDTIOCTL_CTRTYPE:
4598 {
4599 gdth_ioctl_ctrtype ctrt;
4600
4601 if (copy_from_user(&ctrt, argp, sizeof(gdth_ioctl_ctrtype)) ||
4602 (NULL == (ha = gdth_find_ha(ctrt.ionode))))
4603 return -EFAULT;
4604
4605 if (ha->type == GDT_ISA || ha->type == GDT_EISA) {
4606 ctrt.type = (unchar)((ha->stype>>20) - 0x10);
4607 } else {
4608 if (ha->type != GDT_PCIMPR) {
4609 ctrt.type = (unchar)((ha->stype<<4) + 6);
4610 } else {
4611 ctrt.type =
4612 (ha->oem_id == OEM_ID_INTEL ? 0xfd : 0xfe);
4613 if (ha->stype >= 0x300)
4614 ctrt.ext_type = 0x6000 | ha->pdev->subsystem_device;
4615 else
4616 ctrt.ext_type = 0x6000 | ha->stype;
4617 }
4618 ctrt.device_id = ha->pdev->device;
4619 ctrt.sub_device_id = ha->pdev->subsystem_device;
4620 }
4621 ctrt.info = ha->brd_phys;
4622 ctrt.oem_id = ha->oem_id;
4623 if (copy_to_user(argp, &ctrt, sizeof(gdth_ioctl_ctrtype)))
4624 return -EFAULT;
4625 break;
4626 }
4627
4628 case GDTIOCTL_GENERAL:
4629 return ioc_general(argp, cmnd);
4630
4631 case GDTIOCTL_EVENT:
4632 return ioc_event(argp);
4633
4634 case GDTIOCTL_LOCKDRV:
4635 return ioc_lockdrv(argp);
4636
4637 case GDTIOCTL_LOCKCHN:
4638 {
4639 gdth_ioctl_lockchn lchn;
4640 unchar i, j;
4641
4642 if (copy_from_user(&lchn, argp, sizeof(gdth_ioctl_lockchn)) ||
4643 (NULL == (ha = gdth_find_ha(lchn.ionode))))
4644 return -EFAULT;
4645
4646 i = lchn.channel;
4647 if (i < ha->bus_cnt) {
4648 if (lchn.lock) {
4649 spin_lock_irqsave(&ha->smp_lock, flags);
4650 ha->raw[i].lock = 1;
4651 spin_unlock_irqrestore(&ha->smp_lock, flags);
4652 for (j = 0; j < ha->tid_cnt; ++j) {
4653 gdth_wait_completion(ha, i, j);
4654 gdth_stop_timeout(ha, i, j);
4655 }
4656 } else {
4657 spin_lock_irqsave(&ha->smp_lock, flags);
4658 ha->raw[i].lock = 0;
4659 spin_unlock_irqrestore(&ha->smp_lock, flags);
4660 for (j = 0; j < ha->tid_cnt; ++j) {
4661 gdth_start_timeout(ha, i, j);
4662 gdth_next(ha);
4663 }
4664 }
4665 }
4666 break;
4667 }
4668
4669 case GDTIOCTL_RESCAN:
4670 return ioc_rescan(argp, cmnd);
4671
4672 case GDTIOCTL_HDRLIST:
4673 return ioc_hdrlist(argp, cmnd);
4674
4675 case GDTIOCTL_RESET_BUS:
4676 {
4677 gdth_ioctl_reset res;
4678 int rval;
4679
4680 if (copy_from_user(&res, argp, sizeof(gdth_ioctl_reset)) ||
4681 (NULL == (ha = gdth_find_ha(res.ionode))))
4682 return -EFAULT;
4683
4684 scp = kzalloc(sizeof(*scp), GFP_KERNEL);
4685 if (!scp)
4686 return -ENOMEM;
4687 scp->device = ha->sdev;
4688 scp->cmd_len = 12;
4689 scp->device->channel = res.number;
4690 rval = gdth_eh_bus_reset(scp);
4691 res.status = (rval == SUCCESS ? S_OK : S_GENERR);
4692 kfree(scp);
4693
4694 if (copy_to_user(argp, &res, sizeof(gdth_ioctl_reset)))
4695 return -EFAULT;
4696 break;
4697 }
4698
4699 case GDTIOCTL_RESET_DRV:
4700 return ioc_resetdrv(argp, cmnd);
4701
4702 default:
4703 break;
4704 }
4705 return 0;
4706 }
4707
4708
4709 /* flush routine */
4710 static void gdth_flush(gdth_ha_str *ha)
4711 {
4712 int i;
4713 gdth_cmd_str gdtcmd;
4714 char cmnd[MAX_COMMAND_SIZE];
4715 memset(cmnd, 0xff, MAX_COMMAND_SIZE);
4716
4717 TRACE2(("gdth_flush() hanum %d\n", ha->hanum));
4718
4719 for (i = 0; i < MAX_HDRIVES; ++i) {
4720 if (ha->hdr[i].present) {
4721 gdtcmd.BoardNode = LOCALBOARD;
4722 gdtcmd.Service = CACHESERVICE;
4723 gdtcmd.OpCode = GDT_FLUSH;
4724 if (ha->cache_feat & GDT_64BIT) {
4725 gdtcmd.u.cache64.DeviceNo = i;
4726 gdtcmd.u.cache64.BlockNo = 1;
4727 gdtcmd.u.cache64.sg_canz = 0;
4728 } else {
4729 gdtcmd.u.cache.DeviceNo = i;
4730 gdtcmd.u.cache.BlockNo = 1;
4731 gdtcmd.u.cache.sg_canz = 0;
4732 }
4733 TRACE2(("gdth_flush(): flush ha %d drive %d\n", ha->hanum, i));
4734
4735 gdth_execute(ha->shost, &gdtcmd, cmnd, 30, NULL);
4736 }
4737 }
4738 }
4739
4740 <<<<<<< HEAD:drivers/scsi/gdth.c
4741 /* shutdown routine */
4742 static int gdth_halt(struct notifier_block *nb, ulong event, void *buf)
4743 {
4744 gdth_ha_str *ha;
4745 #ifndef __alpha__
4746 gdth_cmd_str gdtcmd;
4747 char cmnd[MAX_COMMAND_SIZE];
4748 #endif
4749
4750 if (notifier_disabled)
4751 return NOTIFY_OK;
4752
4753 TRACE2(("gdth_halt() event %d\n",(int)event));
4754 if (event != SYS_RESTART && event != SYS_HALT && event != SYS_POWER_OFF)
4755 return NOTIFY_DONE;
4756
4757 notifier_disabled = 1;
4758 printk("GDT-HA: Flushing all host drives .. ");
4759 list_for_each_entry(ha, &gdth_instances, list) {
4760 gdth_flush(ha);
4761
4762 #ifndef __alpha__
4763 /* controller reset */
4764 memset(cmnd, 0xff, MAX_COMMAND_SIZE);
4765 gdtcmd.BoardNode = LOCALBOARD;
4766 gdtcmd.Service = CACHESERVICE;
4767 gdtcmd.OpCode = GDT_RESET;
4768 TRACE2(("gdth_halt(): reset controller %d\n", ha->hanum));
4769 gdth_execute(ha->shost, &gdtcmd, cmnd, 10, NULL);
4770 #endif
4771 }
4772 printk("Done.\n");
4773
4774 #ifdef GDTH_STATISTICS
4775 del_timer(&gdth_timer);
4776 #endif
4777 return NOTIFY_OK;
4778 }
4779
4780 =======
4781 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/scsi/gdth.c
4782 /* configure lun */
4783 static int gdth_slave_configure(struct scsi_device *sdev)
4784 {
4785 scsi_adjust_queue_depth(sdev, 0, sdev->host->cmd_per_lun);
4786 sdev->skip_ms_page_3f = 1;
4787 sdev->skip_ms_page_8 = 1;
4788 return 0;
4789 }
4790
4791 static struct scsi_host_template gdth_template = {
4792 .name = "GDT SCSI Disk Array Controller",
4793 .info = gdth_info,
4794 .queuecommand = gdth_queuecommand,
4795 .eh_bus_reset_handler = gdth_eh_bus_reset,
4796 .slave_configure = gdth_slave_configure,
4797 .bios_param = gdth_bios_param,
4798 .proc_info = gdth_proc_info,
4799 .proc_name = "gdth",
4800 .can_queue = GDTH_MAXCMDS,
4801 .this_id = -1,
4802 .sg_tablesize = GDTH_MAXSG,
4803 .cmd_per_lun = GDTH_MAXC_P_L,
4804 .unchecked_isa_dma = 1,
4805 .use_clustering = ENABLE_CLUSTERING,
4806 };
4807
4808 #ifdef CONFIG_ISA
4809 static int __init gdth_isa_probe_one(ulong32 isa_bios)
4810 {
4811 struct Scsi_Host *shp;
4812 gdth_ha_str *ha;
4813 dma_addr_t scratch_dma_handle = 0;
4814 int error, i;
4815
4816 if (!gdth_search_isa(isa_bios))
4817 return -ENXIO;
4818
4819 shp = scsi_host_alloc(&gdth_template, sizeof(gdth_ha_str));
4820 if (!shp)
4821 return -ENOMEM;
4822 ha = shost_priv(shp);
4823
4824 error = -ENODEV;
4825 if (!gdth_init_isa(isa_bios,ha))
4826 goto out_host_put;
4827
4828 /* controller found and initialized */
4829 printk("Configuring GDT-ISA HA at BIOS 0x%05X IRQ %u DRQ %u\n",
4830 isa_bios, ha->irq, ha->drq);
4831
4832 error = request_irq(ha->irq, gdth_interrupt, IRQF_DISABLED, "gdth", ha);
4833 if (error) {
4834 printk("GDT-ISA: Unable to allocate IRQ\n");
4835 goto out_host_put;
4836 }
4837
4838 error = request_dma(ha->drq, "gdth");
4839 if (error) {
4840 printk("GDT-ISA: Unable to allocate DMA channel\n");
4841 goto out_free_irq;
4842 }
4843
4844 set_dma_mode(ha->drq,DMA_MODE_CASCADE);
4845 enable_dma(ha->drq);
4846 shp->unchecked_isa_dma = 1;
4847 shp->irq = ha->irq;
4848 shp->dma_channel = ha->drq;
4849
4850 ha->hanum = gdth_ctr_count++;
4851 ha->shost = shp;
4852
4853 ha->pccb = &ha->cmdext;
4854 ha->ccb_phys = 0L;
4855 ha->pdev = NULL;
4856
4857 error = -ENOMEM;
4858
4859 ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
4860 &scratch_dma_handle);
4861 if (!ha->pscratch)
4862 goto out_dec_counters;
4863 ha->scratch_phys = scratch_dma_handle;
4864
4865 ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
4866 &scratch_dma_handle);
4867 if (!ha->pmsg)
4868 goto out_free_pscratch;
4869 ha->msg_phys = scratch_dma_handle;
4870
4871 #ifdef INT_COAL
4872 ha->coal_stat = pci_alloc_consistent(ha->pdev,
4873 sizeof(gdth_coal_status) * MAXOFFSETS,
4874 &scratch_dma_handle);
4875 if (!ha->coal_stat)
4876 goto out_free_pmsg;
4877 ha->coal_stat_phys = scratch_dma_handle;
4878 #endif
4879
4880 ha->scratch_busy = FALSE;
4881 ha->req_first = NULL;
4882 ha->tid_cnt = MAX_HDRIVES;
4883 if (max_ids > 0 && max_ids < ha->tid_cnt)
4884 ha->tid_cnt = max_ids;
4885 for (i = 0; i < GDTH_MAXCMDS; ++i)
4886 ha->cmd_tab[i].cmnd = UNUSED_CMND;
4887 ha->scan_mode = rescan ? 0x10 : 0;
4888
4889 error = -ENODEV;
4890 if (!gdth_search_drives(ha)) {
4891 printk("GDT-ISA: Error during device scan\n");
4892 goto out_free_coal_stat;
4893 }
4894
4895 if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
4896 hdr_channel = ha->bus_cnt;
4897 ha->virt_bus = hdr_channel;
4898
4899 if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT)
4900 shp->max_cmd_len = 16;
4901
4902 shp->max_id = ha->tid_cnt;
4903 shp->max_lun = MAXLUN;
4904 shp->max_channel = ha->bus_cnt;
4905
4906 spin_lock_init(&ha->smp_lock);
4907 gdth_enable_int(ha);
4908
4909 error = scsi_add_host(shp, NULL);
4910 if (error)
4911 goto out_free_coal_stat;
4912 list_add_tail(&ha->list, &gdth_instances);
4913
4914 scsi_scan_host(shp);
4915
4916 return 0;
4917
4918 out_free_coal_stat:
4919 #ifdef INT_COAL
4920 pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS,
4921 ha->coal_stat, ha->coal_stat_phys);
4922 out_free_pmsg:
4923 #endif
4924 pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
4925 ha->pmsg, ha->msg_phys);
4926 out_free_pscratch:
4927 pci_free_consistent(ha->pdev, GDTH_SCRATCH,
4928 ha->pscratch, ha->scratch_phys);
4929 out_dec_counters:
4930 gdth_ctr_count--;
4931 out_free_irq:
4932 free_irq(ha->irq, ha);
4933 out_host_put:
4934 scsi_host_put(shp);
4935 return error;
4936 }
4937 #endif /* CONFIG_ISA */
4938
4939 #ifdef CONFIG_EISA
4940 static int __init gdth_eisa_probe_one(ushort eisa_slot)
4941 {
4942 struct Scsi_Host *shp;
4943 gdth_ha_str *ha;
4944 dma_addr_t scratch_dma_handle = 0;
4945 int error, i;
4946
4947 if (!gdth_search_eisa(eisa_slot))
4948 return -ENXIO;
4949
4950 shp = scsi_host_alloc(&gdth_template, sizeof(gdth_ha_str));
4951 if (!shp)
4952 return -ENOMEM;
4953 ha = shost_priv(shp);
4954
4955 error = -ENODEV;
4956 if (!gdth_init_eisa(eisa_slot,ha))
4957 goto out_host_put;
4958
4959 /* controller found and initialized */
4960 printk("Configuring GDT-EISA HA at Slot %d IRQ %u\n",
4961 eisa_slot >> 12, ha->irq);
4962
4963 error = request_irq(ha->irq, gdth_interrupt, IRQF_DISABLED, "gdth", ha);
4964 if (error) {
4965 printk("GDT-EISA: Unable to allocate IRQ\n");
4966 goto out_host_put;
4967 }
4968
4969 shp->unchecked_isa_dma = 0;
4970 shp->irq = ha->irq;
4971 shp->dma_channel = 0xff;
4972
4973 ha->hanum = gdth_ctr_count++;
4974 ha->shost = shp;
4975
4976 TRACE2(("EISA detect Bus 0: hanum %d\n", ha->hanum));
4977
4978 ha->pccb = &ha->cmdext;
4979 ha->ccb_phys = 0L;
4980
4981 error = -ENOMEM;
4982
4983 ha->pdev = NULL;
4984 ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
4985 &scratch_dma_handle);
4986 if (!ha->pscratch)
4987 goto out_free_irq;
4988 ha->scratch_phys = scratch_dma_handle;
4989
4990 ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
4991 &scratch_dma_handle);
4992 if (!ha->pmsg)
4993 goto out_free_pscratch;
4994 ha->msg_phys = scratch_dma_handle;
4995
4996 #ifdef INT_COAL
4997 ha->coal_stat = pci_alloc_consistent(ha->pdev,
4998 sizeof(gdth_coal_status) * MAXOFFSETS,
4999 &scratch_dma_handle);
5000 if (!ha->coal_stat)
5001 goto out_free_pmsg;
5002 ha->coal_stat_phys = scratch_dma_handle;
5003 #endif
5004
5005 ha->ccb_phys = pci_map_single(ha->pdev,ha->pccb,
5006 sizeof(gdth_cmd_str), PCI_DMA_BIDIRECTIONAL);
5007 if (!ha->ccb_phys)
5008 goto out_free_coal_stat;
5009
5010 ha->scratch_busy = FALSE;
5011 ha->req_first = NULL;
5012 ha->tid_cnt = MAX_HDRIVES;
5013 if (max_ids > 0 && max_ids < ha->tid_cnt)
5014 ha->tid_cnt = max_ids;
5015 for (i = 0; i < GDTH_MAXCMDS; ++i)
5016 ha->cmd_tab[i].cmnd = UNUSED_CMND;
5017 ha->scan_mode = rescan ? 0x10 : 0;
5018
5019 if (!gdth_search_drives(ha)) {
5020 printk("GDT-EISA: Error during device scan\n");
5021 error = -ENODEV;
5022 goto out_free_ccb_phys;
5023 }
5024
5025 if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
5026 hdr_channel = ha->bus_cnt;
5027 ha->virt_bus = hdr_channel;
5028
5029 if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT)
5030 shp->max_cmd_len = 16;
5031
5032 shp->max_id = ha->tid_cnt;
5033 shp->max_lun = MAXLUN;
5034 shp->max_channel = ha->bus_cnt;
5035
5036 spin_lock_init(&ha->smp_lock);
5037 gdth_enable_int(ha);
5038
5039 error = scsi_add_host(shp, NULL);
5040 if (error)
5041 goto out_free_coal_stat;
5042 list_add_tail(&ha->list, &gdth_instances);
5043
5044 scsi_scan_host(shp);
5045
5046 return 0;
5047
5048 out_free_ccb_phys:
5049 pci_unmap_single(ha->pdev,ha->ccb_phys, sizeof(gdth_cmd_str),
5050 PCI_DMA_BIDIRECTIONAL);
5051 out_free_coal_stat:
5052 #ifdef INT_COAL
5053 pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS,
5054 ha->coal_stat, ha->coal_stat_phys);
5055 out_free_pmsg:
5056 #endif
5057 pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
5058 ha->pmsg, ha->msg_phys);
5059 out_free_pscratch:
5060 pci_free_consistent(ha->pdev, GDTH_SCRATCH,
5061 ha->pscratch, ha->scratch_phys);
5062 out_free_irq:
5063 free_irq(ha->irq, ha);
5064 gdth_ctr_count--;
5065 out_host_put:
5066 scsi_host_put(shp);
5067 return error;
5068 }
5069 #endif /* CONFIG_EISA */
5070
5071 #ifdef CONFIG_PCI
5072 static int __init gdth_pci_probe_one(gdth_pci_str *pcistr, int ctr)
5073 {
5074 struct Scsi_Host *shp;
5075 gdth_ha_str *ha;
5076 dma_addr_t scratch_dma_handle = 0;
5077 int error, i;
5078
5079 shp = scsi_host_alloc(&gdth_template, sizeof(gdth_ha_str));
5080 if (!shp)
5081 return -ENOMEM;
5082 ha = shost_priv(shp);
5083
5084 error = -ENODEV;
5085 if (!gdth_init_pci(&pcistr[ctr],ha))
5086 goto out_host_put;
5087
5088 /* controller found and initialized */
5089 printk("Configuring GDT-PCI HA at %d/%d IRQ %u\n",
5090 pcistr[ctr].pdev->bus->number,
5091 PCI_SLOT(pcistr[ctr].pdev->devfn),
5092 ha->irq);
5093
5094 error = request_irq(ha->irq, gdth_interrupt,
5095 IRQF_DISABLED|IRQF_SHARED, "gdth", ha);
5096 if (error) {
5097 printk("GDT-PCI: Unable to allocate IRQ\n");
5098 goto out_host_put;
5099 }
5100
5101 shp->unchecked_isa_dma = 0;
5102 shp->irq = ha->irq;
5103 shp->dma_channel = 0xff;
5104
5105 ha->hanum = gdth_ctr_count++;
5106 ha->shost = shp;
5107
5108 ha->pccb = &ha->cmdext;
5109 ha->ccb_phys = 0L;
5110
5111 error = -ENOMEM;
5112
5113 ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
5114 &scratch_dma_handle);
5115 if (!ha->pscratch)
5116 goto out_free_irq;
5117 ha->scratch_phys = scratch_dma_handle;
5118
5119 ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
5120 &scratch_dma_handle);
5121 if (!ha->pmsg)
5122 goto out_free_pscratch;
5123 ha->msg_phys = scratch_dma_handle;
5124
5125 #ifdef INT_COAL
5126 ha->coal_stat = pci_alloc_consistent(ha->pdev,
5127 sizeof(gdth_coal_status) * MAXOFFSETS,
5128 &scratch_dma_handle);
5129 if (!ha->coal_stat)
5130 goto out_free_pmsg;
5131 ha->coal_stat_phys = scratch_dma_handle;
5132 #endif
5133
5134 ha->scratch_busy = FALSE;
5135 ha->req_first = NULL;
5136 ha->tid_cnt = pcistr[ctr].pdev->device >= 0x200 ? MAXID : MAX_HDRIVES;
5137 if (max_ids > 0 && max_ids < ha->tid_cnt)
5138 ha->tid_cnt = max_ids;
5139 for (i = 0; i < GDTH_MAXCMDS; ++i)
5140 ha->cmd_tab[i].cmnd = UNUSED_CMND;
5141 ha->scan_mode = rescan ? 0x10 : 0;
5142
5143 error = -ENODEV;
5144 if (!gdth_search_drives(ha)) {
5145 printk("GDT-PCI %d: Error during device scan\n", ha->hanum);
5146 goto out_free_coal_stat;
5147 }
5148
5149 if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
5150 hdr_channel = ha->bus_cnt;
5151 ha->virt_bus = hdr_channel;
5152
5153 /* 64-bit DMA only supported from FW >= x.43 */
5154 if (!(ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT) ||
5155 !ha->dma64_support) {
5156 if (pci_set_dma_mask(pcistr[ctr].pdev, DMA_32BIT_MASK)) {
5157 printk(KERN_WARNING "GDT-PCI %d: "
5158 "Unable to set 32-bit DMA\n", ha->hanum);
5159 goto out_free_coal_stat;
5160 }
5161 } else {
5162 shp->max_cmd_len = 16;
5163 if (!pci_set_dma_mask(pcistr[ctr].pdev, DMA_64BIT_MASK)) {
5164 printk("GDT-PCI %d: 64-bit DMA enabled\n", ha->hanum);
5165 } else if (pci_set_dma_mask(pcistr[ctr].pdev, DMA_32BIT_MASK)) {
5166 printk(KERN_WARNING "GDT-PCI %d: "
5167 "Unable to set 64/32-bit DMA\n", ha->hanum);
5168 goto out_free_coal_stat;
5169 }
5170 }
5171
5172 shp->max_id = ha->tid_cnt;
5173 shp->max_lun = MAXLUN;
5174 shp->max_channel = ha->bus_cnt;
5175
5176 spin_lock_init(&ha->smp_lock);
5177 gdth_enable_int(ha);
5178
5179 error = scsi_add_host(shp, &pcistr[ctr].pdev->dev);
5180 if (error)
5181 goto out_free_coal_stat;
5182 list_add_tail(&ha->list, &gdth_instances);
5183
5184 scsi_scan_host(shp);
5185
5186 return 0;
5187
5188 out_free_coal_stat:
5189 #ifdef INT_COAL
5190 pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS,
5191 ha->coal_stat, ha->coal_stat_phys);
5192 out_free_pmsg:
5193 #endif
5194 pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
5195 ha->pmsg, ha->msg_phys);
5196 out_free_pscratch:
5197 pci_free_consistent(ha->pdev, GDTH_SCRATCH,
5198 ha->pscratch, ha->scratch_phys);
5199 out_free_irq:
5200 free_irq(ha->irq, ha);
5201 gdth_ctr_count--;
5202 out_host_put:
5203 scsi_host_put(shp);
5204 return error;
5205 }
5206 #endif /* CONFIG_PCI */
5207
5208 static void gdth_remove_one(gdth_ha_str *ha)
5209 {
5210 struct Scsi_Host *shp = ha->shost;
5211
5212 TRACE2(("gdth_remove_one()\n"));
5213
5214 scsi_remove_host(shp);
5215
5216 <<<<<<< HEAD:drivers/scsi/gdth.c
5217 =======
5218 gdth_flush(ha);
5219
5220 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/scsi/gdth.c
5221 if (ha->sdev) {
5222 scsi_free_host_dev(ha->sdev);
5223 ha->sdev = NULL;
5224 }
5225
5226 <<<<<<< HEAD:drivers/scsi/gdth.c
5227 gdth_flush(ha);
5228
5229 =======
5230 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/scsi/gdth.c
5231 if (shp->irq)
5232 free_irq(shp->irq,ha);
5233
5234 #ifdef CONFIG_ISA
5235 if (shp->dma_channel != 0xff)
5236 free_dma(shp->dma_channel);
5237 #endif
5238 #ifdef INT_COAL
5239 if (ha->coal_stat)
5240 pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) *
5241 MAXOFFSETS, ha->coal_stat, ha->coal_stat_phys);
5242 #endif
5243 if (ha->pscratch)
5244 pci_free_consistent(ha->pdev, GDTH_SCRATCH,
5245 ha->pscratch, ha->scratch_phys);
5246 if (ha->pmsg)
5247 pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
5248 ha->pmsg, ha->msg_phys);
5249 if (ha->ccb_phys)
5250 pci_unmap_single(ha->pdev,ha->ccb_phys,
5251 sizeof(gdth_cmd_str),PCI_DMA_BIDIRECTIONAL);
5252
5253 scsi_host_put(shp);
5254 }
5255
5256 <<<<<<< HEAD:drivers/scsi/gdth.c
5257 =======
5258 static int gdth_halt(struct notifier_block *nb, ulong event, void *buf)
5259 {
5260 gdth_ha_str *ha;
5261
5262 TRACE2(("gdth_halt() event %d\n", (int)event));
5263 if (event != SYS_RESTART && event != SYS_HALT && event != SYS_POWER_OFF)
5264 return NOTIFY_DONE;
5265
5266 list_for_each_entry(ha, &gdth_instances, list)
5267 gdth_flush(ha);
5268
5269 return NOTIFY_OK;
5270 }
5271
5272 static struct notifier_block gdth_notifier = {
5273 gdth_halt, NULL, 0
5274 };
5275
5276 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/scsi/gdth.c
5277 static int __init gdth_init(void)
5278 {
5279 if (disable) {
5280 printk("GDT-HA: Controller driver disabled from"
5281 " command line !\n");
5282 return 0;
5283 }
5284
5285 printk("GDT-HA: Storage RAID Controller Driver. Version: %s\n",
5286 GDTH_VERSION_STR);
5287
5288 /* initializations */
5289 gdth_polling = TRUE;
5290 gdth_clear_events();
5291
5292 /* As default we do not probe for EISA or ISA controllers */
5293 if (probe_eisa_isa) {
5294 /* scanning for controllers, at first: ISA controller */
5295 #ifdef CONFIG_ISA
5296 ulong32 isa_bios;
5297 for (isa_bios = 0xc8000UL; isa_bios <= 0xd8000UL;
5298 isa_bios += 0x8000UL)
5299 gdth_isa_probe_one(isa_bios);
5300 #endif
5301 #ifdef CONFIG_EISA
5302 {
5303 ushort eisa_slot;
5304 for (eisa_slot = 0x1000; eisa_slot <= 0x8000;
5305 eisa_slot += 0x1000)
5306 gdth_eisa_probe_one(eisa_slot);
5307 }
5308 #endif
5309 }
5310
5311 #ifdef CONFIG_PCI
5312 /* scanning for PCI controllers */
5313 {
5314 gdth_pci_str pcistr[MAXHA];
5315 int cnt,ctr;
5316
5317 cnt = gdth_search_pci(pcistr);
5318 printk("GDT-HA: Found %d PCI Storage RAID Controllers\n", cnt);
5319 gdth_sort_pci(pcistr,cnt);
5320 for (ctr = 0; ctr < cnt; ++ctr)
5321 gdth_pci_probe_one(pcistr, ctr);
5322 }
5323 #endif /* CONFIG_PCI */
5324
5325 TRACE2(("gdth_detect() %d controller detected\n", gdth_ctr_count));
5326
5327 if (list_empty(&gdth_instances))
5328 return -ENODEV;
5329
5330 #ifdef GDTH_STATISTICS
5331 TRACE2(("gdth_detect(): Initializing timer !\n"));
5332 init_timer(&gdth_timer);
5333 gdth_timer.expires = jiffies + HZ;
5334 gdth_timer.data = 0L;
5335 gdth_timer.function = gdth_timeout;
5336 add_timer(&gdth_timer);
5337 #endif
5338 major = register_chrdev(0,"gdth", &gdth_fops);
5339 <<<<<<< HEAD:drivers/scsi/gdth.c
5340 notifier_disabled = 0;
5341 =======
5342 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/scsi/gdth.c
5343 register_reboot_notifier(&gdth_notifier);
5344 gdth_polling = FALSE;
5345 return 0;
5346 }
5347
5348 static void __exit gdth_exit(void)
5349 {
5350 gdth_ha_str *ha;
5351
5352 <<<<<<< HEAD:drivers/scsi/gdth.c
5353 list_for_each_entry(ha, &gdth_instances, list)
5354 gdth_remove_one(ha);
5355 =======
5356 unregister_chrdev(major, "gdth");
5357 unregister_reboot_notifier(&gdth_notifier);
5358 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/scsi/gdth.c
5359
5360 #ifdef GDTH_STATISTICS
5361 <<<<<<< HEAD:drivers/scsi/gdth.c
5362 del_timer(&gdth_timer);
5363 =======
5364 del_timer_sync(&gdth_timer);
5365 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/scsi/gdth.c
5366 #endif
5367 <<<<<<< HEAD:drivers/scsi/gdth.c
5368 unregister_chrdev(major,"gdth");
5369 unregister_reboot_notifier(&gdth_notifier);
5370 =======
5371
5372 list_for_each_entry(ha, &gdth_instances, list)
5373 gdth_remove_one(ha);
5374 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/scsi/gdth.c
5375 }
5376
5377 module_init(gdth_init);
5378 module_exit(gdth_exit);
5379
5380 #ifndef MODULE
5381 __setup("gdth=", option_setup);
5382 #endif
WRT350N Kernel Patches