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Merge git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
[wrt350n-kernel.git] / drivers / scsi / stex.c
blob064580c7bff68399b59ae92ba5f59a04b6bfbabd
1 /*
2 * SuperTrak EX Series Storage Controller driver for Linux
3 *
4 * Copyright (C) 2005, 2006 Promise Technology Inc.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 *
11 * Written By:
12 * Ed Lin <promise_linux@promise.com>
13 *
14 */
15
16 #include <linux/init.h>
17 #include <linux/errno.h>
18 #include <linux/kernel.h>
19 #include <linux/delay.h>
20 #include <linux/time.h>
21 #include <linux/pci.h>
22 #include <linux/blkdev.h>
23 #include <linux/interrupt.h>
24 #include <linux/types.h>
25 #include <linux/module.h>
26 #include <linux/spinlock.h>
27 #include <asm/io.h>
28 #include <asm/irq.h>
29 #include <asm/byteorder.h>
30 #include <scsi/scsi.h>
31 #include <scsi/scsi_device.h>
32 #include <scsi/scsi_cmnd.h>
33 #include <scsi/scsi_host.h>
34 #include <scsi/scsi_tcq.h>
35 #include <scsi/scsi_dbg.h>
36
37 #define DRV_NAME "stex"
38 #define ST_DRIVER_VERSION "3.6.0000.1"
39 #define ST_VER_MAJOR 3
40 #define ST_VER_MINOR 6
41 #define ST_OEM 0
42 #define ST_BUILD_VER 1
43
44 enum {
45 /* MU register offset */
46 IMR0 = 0x10, /* MU_INBOUND_MESSAGE_REG0 */
47 IMR1 = 0x14, /* MU_INBOUND_MESSAGE_REG1 */
48 OMR0 = 0x18, /* MU_OUTBOUND_MESSAGE_REG0 */
49 OMR1 = 0x1c, /* MU_OUTBOUND_MESSAGE_REG1 */
50 IDBL = 0x20, /* MU_INBOUND_DOORBELL */
51 IIS = 0x24, /* MU_INBOUND_INTERRUPT_STATUS */
52 IIM = 0x28, /* MU_INBOUND_INTERRUPT_MASK */
53 ODBL = 0x2c, /* MU_OUTBOUND_DOORBELL */
54 OIS = 0x30, /* MU_OUTBOUND_INTERRUPT_STATUS */
55 OIM = 0x3c, /* MU_OUTBOUND_INTERRUPT_MASK */
56
57 /* MU register value */
58 MU_INBOUND_DOORBELL_HANDSHAKE = 1,
59 MU_INBOUND_DOORBELL_REQHEADCHANGED = 2,
60 MU_INBOUND_DOORBELL_STATUSTAILCHANGED = 4,
61 MU_INBOUND_DOORBELL_HMUSTOPPED = 8,
62 MU_INBOUND_DOORBELL_RESET = 16,
63
64 MU_OUTBOUND_DOORBELL_HANDSHAKE = 1,
65 MU_OUTBOUND_DOORBELL_REQUESTTAILCHANGED = 2,
66 MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED = 4,
67 MU_OUTBOUND_DOORBELL_BUSCHANGE = 8,
68 MU_OUTBOUND_DOORBELL_HASEVENT = 16,
69
70 /* MU status code */
71 MU_STATE_STARTING = 1,
72 MU_STATE_FMU_READY_FOR_HANDSHAKE = 2,
73 MU_STATE_SEND_HANDSHAKE_FRAME = 3,
74 MU_STATE_STARTED = 4,
75 MU_STATE_RESETTING = 5,
76
77 MU_MAX_DELAY = 120,
78 MU_HANDSHAKE_SIGNATURE = 0x55aaaa55,
79 MU_HANDSHAKE_SIGNATURE_HALF = 0x5a5a0000,
80 MU_HARD_RESET_WAIT = 30000,
81 HMU_PARTNER_TYPE = 2,
82
83 /* firmware returned values */
84 SRB_STATUS_SUCCESS = 0x01,
85 SRB_STATUS_ERROR = 0x04,
86 SRB_STATUS_BUSY = 0x05,
87 SRB_STATUS_INVALID_REQUEST = 0x06,
88 SRB_STATUS_SELECTION_TIMEOUT = 0x0A,
89 SRB_SEE_SENSE = 0x80,
90
91 /* task attribute */
92 TASK_ATTRIBUTE_SIMPLE = 0x0,
93 TASK_ATTRIBUTE_HEADOFQUEUE = 0x1,
94 TASK_ATTRIBUTE_ORDERED = 0x2,
95 TASK_ATTRIBUTE_ACA = 0x4,
96
97 /* request count, etc. */
98 MU_MAX_REQUEST = 32,
99
100 /* one message wasted, use MU_MAX_REQUEST+1
101 to handle MU_MAX_REQUEST messages */
102 MU_REQ_COUNT = (MU_MAX_REQUEST + 1),
103 MU_STATUS_COUNT = (MU_MAX_REQUEST + 1),
104
105 STEX_CDB_LENGTH = MAX_COMMAND_SIZE,
106 REQ_VARIABLE_LEN = 1024,
107 STATUS_VAR_LEN = 128,
108 ST_CAN_QUEUE = MU_MAX_REQUEST,
109 ST_CMD_PER_LUN = MU_MAX_REQUEST,
110 ST_MAX_SG = 32,
111
112 /* sg flags */
113 SG_CF_EOT = 0x80, /* end of table */
114 SG_CF_64B = 0x40, /* 64 bit item */
115 SG_CF_HOST = 0x20, /* sg in host memory */
116
117 st_shasta = 0,
118 st_vsc = 1,
119 st_vsc1 = 2,
120 st_yosemite = 3,
121
122 PASSTHRU_REQ_TYPE = 0x00000001,
123 PASSTHRU_REQ_NO_WAKEUP = 0x00000100,
124 ST_INTERNAL_TIMEOUT = 30,
125
126 ST_TO_CMD = 0,
127 ST_FROM_CMD = 1,
128
129 /* vendor specific commands of Promise */
130 MGT_CMD = 0xd8,
131 SINBAND_MGT_CMD = 0xd9,
132 ARRAY_CMD = 0xe0,
133 CONTROLLER_CMD = 0xe1,
134 DEBUGGING_CMD = 0xe2,
135 PASSTHRU_CMD = 0xe3,
136
137 PASSTHRU_GET_ADAPTER = 0x05,
138 PASSTHRU_GET_DRVVER = 0x10,
139
140 CTLR_CONFIG_CMD = 0x03,
141 CTLR_SHUTDOWN = 0x0d,
142
143 CTLR_POWER_STATE_CHANGE = 0x0e,
144 CTLR_POWER_SAVING = 0x01,
145
146 PASSTHRU_SIGNATURE = 0x4e415041,
147 MGT_CMD_SIGNATURE = 0xba,
148
149 INQUIRY_EVPD = 0x01,
150
151 ST_ADDITIONAL_MEM = 0x200000,
152 };
153
154 /* SCSI inquiry data */
155 typedef struct st_inq {
156 u8 DeviceType :5;
157 u8 DeviceTypeQualifier :3;
158 u8 DeviceTypeModifier :7;
159 u8 RemovableMedia :1;
160 u8 Versions;
161 u8 ResponseDataFormat :4;
162 u8 HiSupport :1;
163 u8 NormACA :1;
164 u8 ReservedBit :1;
165 u8 AERC :1;
166 u8 AdditionalLength;
167 u8 Reserved[2];
168 u8 SoftReset :1;
169 u8 CommandQueue :1;
170 u8 Reserved2 :1;
171 u8 LinkedCommands :1;
172 u8 Synchronous :1;
173 u8 Wide16Bit :1;
174 u8 Wide32Bit :1;
175 u8 RelativeAddressing :1;
176 u8 VendorId[8];
177 u8 ProductId[16];
178 u8 ProductRevisionLevel[4];
179 u8 VendorSpecific[20];
180 u8 Reserved3[40];
181 } ST_INQ;
182
183 struct st_sgitem {
184 u8 ctrl; /* SG_CF_xxx */
185 u8 reserved[3];
186 __le32 count;
187 __le32 addr;
188 __le32 addr_hi;
189 };
190
191 struct st_sgtable {
192 __le16 sg_count;
193 __le16 max_sg_count;
194 __le32 sz_in_byte;
195 struct st_sgitem table[ST_MAX_SG];
196 };
197
198 struct handshake_frame {
199 __le32 rb_phy; /* request payload queue physical address */
200 __le32 rb_phy_hi;
201 __le16 req_sz; /* size of each request payload */
202 __le16 req_cnt; /* count of reqs the buffer can hold */
203 __le16 status_sz; /* size of each status payload */
204 __le16 status_cnt; /* count of status the buffer can hold */
205 __le32 hosttime; /* seconds from Jan 1, 1970 (GMT) */
206 __le32 hosttime_hi;
207 u8 partner_type; /* who sends this frame */
208 u8 reserved0[7];
209 __le32 partner_ver_major;
210 __le32 partner_ver_minor;
211 __le32 partner_ver_oem;
212 __le32 partner_ver_build;
213 __le32 extra_offset; /* NEW */
214 __le32 extra_size; /* NEW */
215 u32 reserved1[2];
216 };
217
218 struct req_msg {
219 __le16 tag;
220 u8 lun;
221 u8 target;
222 u8 task_attr;
223 u8 task_manage;
224 u8 prd_entry;
225 u8 payload_sz; /* payload size in 4-byte, not used */
226 u8 cdb[STEX_CDB_LENGTH];
227 u8 variable[REQ_VARIABLE_LEN];
228 };
229
230 struct status_msg {
231 __le16 tag;
232 u8 lun;
233 u8 target;
234 u8 srb_status;
235 u8 scsi_status;
236 u8 reserved;
237 u8 payload_sz; /* payload size in 4-byte */
238 u8 variable[STATUS_VAR_LEN];
239 };
240
241 struct ver_info {
242 u32 major;
243 u32 minor;
244 u32 oem;
245 u32 build;
246 u32 reserved[2];
247 };
248
249 struct st_frame {
250 u32 base[6];
251 u32 rom_addr;
252
253 struct ver_info drv_ver;
254 struct ver_info bios_ver;
255
256 u32 bus;
257 u32 slot;
258 u32 irq_level;
259 u32 irq_vec;
260 u32 id;
261 u32 subid;
262
263 u32 dimm_size;
264 u8 dimm_type;
265 u8 reserved[3];
266
267 u32 channel;
268 u32 reserved1;
269 };
270
271 struct st_drvver {
272 u32 major;
273 u32 minor;
274 u32 oem;
275 u32 build;
276 u32 signature[2];
277 u8 console_id;
278 u8 host_no;
279 u8 reserved0[2];
280 u32 reserved[3];
281 };
282
283 #define MU_REQ_BUFFER_SIZE (MU_REQ_COUNT * sizeof(struct req_msg))
284 #define MU_STATUS_BUFFER_SIZE (MU_STATUS_COUNT * sizeof(struct status_msg))
285 #define MU_BUFFER_SIZE (MU_REQ_BUFFER_SIZE + MU_STATUS_BUFFER_SIZE)
286 #define STEX_EXTRA_SIZE max(sizeof(struct st_frame), sizeof(ST_INQ))
287 #define STEX_BUFFER_SIZE (MU_BUFFER_SIZE + STEX_EXTRA_SIZE)
288
289 struct st_ccb {
290 struct req_msg *req;
291 struct scsi_cmnd *cmd;
292
293 void *sense_buffer;
294 unsigned int sense_bufflen;
295 int sg_count;
296
297 u32 req_type;
298 u8 srb_status;
299 u8 scsi_status;
300 };
301
302 struct st_hba {
303 void __iomem *mmio_base; /* iomapped PCI memory space */
304 void *dma_mem;
305 dma_addr_t dma_handle;
306 size_t dma_size;
307
308 struct Scsi_Host *host;
309 struct pci_dev *pdev;
310
311 u32 req_head;
312 u32 req_tail;
313 u32 status_head;
314 u32 status_tail;
315
316 struct status_msg *status_buffer;
317 void *copy_buffer; /* temp buffer for driver-handled commands */
318 struct st_ccb ccb[MU_MAX_REQUEST];
319 struct st_ccb *wait_ccb;
320 wait_queue_head_t waitq;
321
322 unsigned int mu_status;
323 int out_req_cnt;
324
325 unsigned int cardtype;
326 };
327
328 static const char console_inq_page[] =
329 {
330 0x03,0x00,0x03,0x03,0xFA,0x00,0x00,0x30,
331 0x50,0x72,0x6F,0x6D,0x69,0x73,0x65,0x20, /* "Promise " */
332 0x52,0x41,0x49,0x44,0x20,0x43,0x6F,0x6E, /* "RAID Con" */
333 0x73,0x6F,0x6C,0x65,0x20,0x20,0x20,0x20, /* "sole " */
334 0x31,0x2E,0x30,0x30,0x20,0x20,0x20,0x20, /* "1.00 " */
335 0x53,0x58,0x2F,0x52,0x53,0x41,0x46,0x2D, /* "SX/RSAF-" */
336 0x54,0x45,0x31,0x2E,0x30,0x30,0x20,0x20, /* "TE1.00 " */
337 0x0C,0x20,0x20,0x20,0x20,0x20,0x20,0x20
338 };
339
340 MODULE_AUTHOR("Ed Lin");
341 MODULE_DESCRIPTION("Promise Technology SuperTrak EX Controllers");
342 MODULE_LICENSE("GPL");
343 MODULE_VERSION(ST_DRIVER_VERSION);
344
345 static void stex_gettime(__le32 *time)
346 {
347 struct timeval tv;
348 do_gettimeofday(&tv);
349
350 *time = cpu_to_le32(tv.tv_sec & 0xffffffff);
351 *(time + 1) = cpu_to_le32((tv.tv_sec >> 16) >> 16);
352 }
353
354 static struct status_msg *stex_get_status(struct st_hba *hba)
355 {
356 struct status_msg *status =
357 hba->status_buffer + hba->status_tail;
358
359 ++hba->status_tail;
360 hba->status_tail %= MU_STATUS_COUNT;
361
362 return status;
363 }
364
365 static void stex_set_sense(struct scsi_cmnd *cmd, u8 sk, u8 asc, u8 ascq)
366 {
367 cmd->result = (DRIVER_SENSE << 24) | SAM_STAT_CHECK_CONDITION;
368
369 cmd->sense_buffer[0] = 0x70; /* fixed format, current */
370 cmd->sense_buffer[2] = sk;
371 cmd->sense_buffer[7] = 18 - 8; /* additional sense length */
372 cmd->sense_buffer[12] = asc;
373 cmd->sense_buffer[13] = ascq;
374 }
375
376 static void stex_invalid_field(struct scsi_cmnd *cmd,
377 void (*done)(struct scsi_cmnd *))
378 {
379 /* "Invalid field in cbd" */
380 stex_set_sense(cmd, ILLEGAL_REQUEST, 0x24, 0x0);
381 done(cmd);
382 }
383
384 static struct req_msg *stex_alloc_req(struct st_hba *hba)
385 {
386 struct req_msg *req = ((struct req_msg *)hba->dma_mem) +
387 hba->req_head;
388
389 ++hba->req_head;
390 hba->req_head %= MU_REQ_COUNT;
391
392 return req;
393 }
394
395 static int stex_map_sg(struct st_hba *hba,
396 struct req_msg *req, struct st_ccb *ccb)
397 {
398 struct scsi_cmnd *cmd;
399 struct scatterlist *sg;
400 struct st_sgtable *dst;
401 int i, nseg;
402
403 cmd = ccb->cmd;
404 dst = (struct st_sgtable *)req->variable;
405 dst->max_sg_count = cpu_to_le16(ST_MAX_SG);
406 dst->sz_in_byte = cpu_to_le32(scsi_bufflen(cmd));
407
408 nseg = scsi_dma_map(cmd);
409 if (nseg < 0)
410 return -EIO;
411 if (nseg) {
412 ccb->sg_count = nseg;
413 dst->sg_count = cpu_to_le16((u16)nseg);
414
415 scsi_for_each_sg(cmd, sg, nseg, i) {
416 dst->table[i].count = cpu_to_le32((u32)sg_dma_len(sg));
417 dst->table[i].addr =
418 cpu_to_le32(sg_dma_address(sg) & 0xffffffff);
419 dst->table[i].addr_hi =
420 cpu_to_le32((sg_dma_address(sg) >> 16) >> 16);
421 dst->table[i].ctrl = SG_CF_64B | SG_CF_HOST;
422 }
423 dst->table[--i].ctrl |= SG_CF_EOT;
424 }
425
426 return 0;
427 }
428
429 static void stex_internal_copy(struct scsi_cmnd *cmd,
430 const void *src, size_t *count, int sg_count, int direction)
431 {
432 size_t lcount;
433 size_t len;
434 void *s, *d, *base = NULL;
435 size_t offset;
436
437 if (*count > scsi_bufflen(cmd))
438 *count = scsi_bufflen(cmd);
439 lcount = *count;
440 while (lcount) {
441 len = lcount;
442 s = (void *)src;
443
444 offset = *count - lcount;
445 s += offset;
446 base = scsi_kmap_atomic_sg(scsi_sglist(cmd),
447 sg_count, &offset, &len);
448 if (!base) {
449 *count -= lcount;
450 return;
451 }
452 d = base + offset;
453
454 if (direction == ST_TO_CMD)
455 memcpy(d, s, len);
456 else
457 memcpy(s, d, len);
458
459 lcount -= len;
460 scsi_kunmap_atomic_sg(base);
461 }
462 }
463
464 <<<<<<< HEAD:drivers/scsi/stex.c
465 static int stex_direct_copy(struct scsi_cmnd *cmd,
466 const void *src, size_t count)
467 {
468 size_t cp_len = count;
469 int n_elem = 0;
470
471 n_elem = scsi_dma_map(cmd);
472 if (n_elem < 0)
473 return 0;
474
475 stex_internal_copy(cmd, src, &cp_len, n_elem, ST_TO_CMD);
476
477 scsi_dma_unmap(cmd);
478
479 return cp_len == count;
480 }
481
482 =======
483 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/scsi/stex.c
484 static void stex_controller_info(struct st_hba *hba, struct st_ccb *ccb)
485 {
486 struct st_frame *p;
487 size_t count = sizeof(struct st_frame);
488
489 p = hba->copy_buffer;
490 <<<<<<< HEAD:drivers/scsi/stex.c
491 stex_internal_copy(ccb->cmd, p, &count, ccb->sg_count, ST_FROM_CMD);
492 =======
493 stex_internal_copy(ccb->cmd, p, &count, scsi_sg_count(ccb->cmd),
494 ST_FROM_CMD);
495 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/scsi/stex.c
496 memset(p->base, 0, sizeof(u32)*6);
497 *(unsigned long *)(p->base) = pci_resource_start(hba->pdev, 0);
498 p->rom_addr = 0;
499
500 p->drv_ver.major = ST_VER_MAJOR;
501 p->drv_ver.minor = ST_VER_MINOR;
502 p->drv_ver.oem = ST_OEM;
503 p->drv_ver.build = ST_BUILD_VER;
504
505 p->bus = hba->pdev->bus->number;
506 p->slot = hba->pdev->devfn;
507 p->irq_level = 0;
508 p->irq_vec = hba->pdev->irq;
509 p->id = hba->pdev->vendor << 16 | hba->pdev->device;
510 p->subid =
511 hba->pdev->subsystem_vendor << 16 | hba->pdev->subsystem_device;
512
513 <<<<<<< HEAD:drivers/scsi/stex.c
514 stex_internal_copy(ccb->cmd, p, &count, ccb->sg_count, ST_TO_CMD);
515 =======
516 stex_internal_copy(ccb->cmd, p, &count, scsi_sg_count(ccb->cmd),
517 ST_TO_CMD);
518 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/scsi/stex.c
519 }
520
521 static void
522 stex_send_cmd(struct st_hba *hba, struct req_msg *req, u16 tag)
523 {
524 req->tag = cpu_to_le16(tag);
525 req->task_attr = TASK_ATTRIBUTE_SIMPLE;
526 req->task_manage = 0; /* not supported yet */
527
528 hba->ccb[tag].req = req;
529 hba->out_req_cnt++;
530
531 writel(hba->req_head, hba->mmio_base + IMR0);
532 writel(MU_INBOUND_DOORBELL_REQHEADCHANGED, hba->mmio_base + IDBL);
533 readl(hba->mmio_base + IDBL); /* flush */
534 }
535
536 static int
537 stex_slave_alloc(struct scsi_device *sdev)
538 {
539 /* Cheat: usually extracted from Inquiry data */
540 sdev->tagged_supported = 1;
541
542 scsi_activate_tcq(sdev, sdev->host->can_queue);
543
544 return 0;
545 }
546
547 static int
548 stex_slave_config(struct scsi_device *sdev)
549 {
550 sdev->use_10_for_rw = 1;
551 sdev->use_10_for_ms = 1;
552 sdev->timeout = 60 * HZ;
553 sdev->tagged_supported = 1;
554
555 return 0;
556 }
557
558 static void
559 stex_slave_destroy(struct scsi_device *sdev)
560 {
561 scsi_deactivate_tcq(sdev, 1);
562 }
563
564 static int
565 stex_queuecommand(struct scsi_cmnd *cmd, void (* done)(struct scsi_cmnd *))
566 {
567 struct st_hba *hba;
568 struct Scsi_Host *host;
569 unsigned int id,lun;
570 struct req_msg *req;
571 u16 tag;
572 host = cmd->device->host;
573 id = cmd->device->id;
574 lun = cmd->device->lun;
575 hba = (struct st_hba *) &host->hostdata[0];
576
577 switch (cmd->cmnd[0]) {
578 case MODE_SENSE_10:
579 {
580 static char ms10_caching_page[12] =
581 { 0, 0x12, 0, 0, 0, 0, 0, 0, 0x8, 0xa, 0x4, 0 };
582 unsigned char page;
583 page = cmd->cmnd[2] & 0x3f;
584 if (page == 0x8 || page == 0x3f) {
585 <<<<<<< HEAD:drivers/scsi/stex.c
586 stex_direct_copy(cmd, ms10_caching_page,
587 sizeof(ms10_caching_page));
588 =======
589 size_t cp_len = sizeof(ms10_caching_page);
590 stex_internal_copy(cmd, ms10_caching_page,
591 &cp_len, scsi_sg_count(cmd),
592 ST_TO_CMD);
593 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/scsi/stex.c
594 cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
595 done(cmd);
596 } else
597 stex_invalid_field(cmd, done);
598 return 0;
599 }
600 case REPORT_LUNS:
601 /*
602 * The shasta firmware does not report actual luns in the
603 * target, so fail the command to force sequential lun scan.
604 * Also, the console device does not support this command.
605 */
606 if (hba->cardtype == st_shasta || id == host->max_id - 1) {
607 stex_invalid_field(cmd, done);
608 return 0;
609 }
610 break;
611 case TEST_UNIT_READY:
612 if (id == host->max_id - 1) {
613 cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
614 done(cmd);
615 return 0;
616 }
617 break;
618 case INQUIRY:
619 if (id != host->max_id - 1)
620 break;
621 if (lun == 0 && (cmd->cmnd[1] & INQUIRY_EVPD) == 0) {
622 <<<<<<< HEAD:drivers/scsi/stex.c
623 stex_direct_copy(cmd, console_inq_page,
624 sizeof(console_inq_page));
625 =======
626 size_t cp_len = sizeof(console_inq_page);
627 stex_internal_copy(cmd, console_inq_page,
628 &cp_len, scsi_sg_count(cmd),
629 ST_TO_CMD);
630 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/scsi/stex.c
631 cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
632 done(cmd);
633 } else
634 stex_invalid_field(cmd, done);
635 return 0;
636 case PASSTHRU_CMD:
637 if (cmd->cmnd[1] == PASSTHRU_GET_DRVVER) {
638 struct st_drvver ver;
639 <<<<<<< HEAD:drivers/scsi/stex.c
640 =======
641 size_t cp_len = sizeof(ver);
642 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/scsi/stex.c
643 ver.major = ST_VER_MAJOR;
644 ver.minor = ST_VER_MINOR;
645 ver.oem = ST_OEM;
646 ver.build = ST_BUILD_VER;
647 ver.signature[0] = PASSTHRU_SIGNATURE;
648 ver.console_id = host->max_id - 1;
649 ver.host_no = hba->host->host_no;
650 <<<<<<< HEAD:drivers/scsi/stex.c
651 cmd->result = stex_direct_copy(cmd, &ver, sizeof(ver)) ?
652 =======
653 stex_internal_copy(cmd, &ver, &cp_len,
654 scsi_sg_count(cmd), ST_TO_CMD);
655 cmd->result = sizeof(ver) == cp_len ?
656 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/scsi/stex.c
657 DID_OK << 16 | COMMAND_COMPLETE << 8 :
658 DID_ERROR << 16 | COMMAND_COMPLETE << 8;
659 done(cmd);
660 return 0;
661 }
662 default:
663 break;
664 }
665
666 cmd->scsi_done = done;
667
668 tag = cmd->request->tag;
669
670 if (unlikely(tag >= host->can_queue))
671 return SCSI_MLQUEUE_HOST_BUSY;
672
673 req = stex_alloc_req(hba);
674
675 req->lun = lun;
676 req->target = id;
677
678 /* cdb */
679 memcpy(req->cdb, cmd->cmnd, STEX_CDB_LENGTH);
680
681 hba->ccb[tag].cmd = cmd;
682 hba->ccb[tag].sense_bufflen = SCSI_SENSE_BUFFERSIZE;
683 hba->ccb[tag].sense_buffer = cmd->sense_buffer;
684 hba->ccb[tag].req_type = 0;
685
686 if (cmd->sc_data_direction != DMA_NONE)
687 stex_map_sg(hba, req, &hba->ccb[tag]);
688
689 stex_send_cmd(hba, req, tag);
690 return 0;
691 }
692
693 static void stex_scsi_done(struct st_ccb *ccb)
694 {
695 struct scsi_cmnd *cmd = ccb->cmd;
696 int result;
697
698 if (ccb->srb_status == SRB_STATUS_SUCCESS || ccb->srb_status == 0) {
699 result = ccb->scsi_status;
700 switch (ccb->scsi_status) {
701 case SAM_STAT_GOOD:
702 result |= DID_OK << 16 | COMMAND_COMPLETE << 8;
703 break;
704 case SAM_STAT_CHECK_CONDITION:
705 result |= DRIVER_SENSE << 24;
706 break;
707 case SAM_STAT_BUSY:
708 result |= DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8;
709 break;
710 default:
711 result |= DID_ERROR << 16 | COMMAND_COMPLETE << 8;
712 break;
713 }
714 }
715 else if (ccb->srb_status & SRB_SEE_SENSE)
716 result = DRIVER_SENSE << 24 | SAM_STAT_CHECK_CONDITION;
717 else switch (ccb->srb_status) {
718 case SRB_STATUS_SELECTION_TIMEOUT:
719 result = DID_NO_CONNECT << 16 | COMMAND_COMPLETE << 8;
720 break;
721 case SRB_STATUS_BUSY:
722 result = DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8;
723 break;
724 case SRB_STATUS_INVALID_REQUEST:
725 case SRB_STATUS_ERROR:
726 default:
727 result = DID_ERROR << 16 | COMMAND_COMPLETE << 8;
728 break;
729 }
730
731 cmd->result = result;
732 cmd->scsi_done(cmd);
733 }
734
735 static void stex_copy_data(struct st_ccb *ccb,
736 struct status_msg *resp, unsigned int variable)
737 {
738 size_t count = variable;
739 if (resp->scsi_status != SAM_STAT_GOOD) {
740 if (ccb->sense_buffer != NULL)
741 memcpy(ccb->sense_buffer, resp->variable,
742 min(variable, ccb->sense_bufflen));
743 return;
744 }
745
746 if (ccb->cmd == NULL)
747 return;
748 stex_internal_copy(ccb->cmd,
749 <<<<<<< HEAD:drivers/scsi/stex.c
750 resp->variable, &count, ccb->sg_count, ST_TO_CMD);
751 =======
752 resp->variable, &count, scsi_sg_count(ccb->cmd), ST_TO_CMD);
753 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/scsi/stex.c
754 }
755
756 static void stex_ys_commands(struct st_hba *hba,
757 struct st_ccb *ccb, struct status_msg *resp)
758 {
759 size_t count;
760
761 if (ccb->cmd->cmnd[0] == MGT_CMD &&
762 resp->scsi_status != SAM_STAT_CHECK_CONDITION) {
763 scsi_set_resid(ccb->cmd, scsi_bufflen(ccb->cmd) -
764 le32_to_cpu(*(__le32 *)&resp->variable[0]));
765 return;
766 }
767
768 if (resp->srb_status != 0)
769 return;
770
771 /* determine inquiry command status by DeviceTypeQualifier */
772 if (ccb->cmd->cmnd[0] == INQUIRY &&
773 resp->scsi_status == SAM_STAT_GOOD) {
774 ST_INQ *inq_data;
775
776 count = STEX_EXTRA_SIZE;
777 stex_internal_copy(ccb->cmd, hba->copy_buffer,
778 <<<<<<< HEAD:drivers/scsi/stex.c
779 &count, ccb->sg_count, ST_FROM_CMD);
780 =======
781 &count, scsi_sg_count(ccb->cmd), ST_FROM_CMD);
782 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/scsi/stex.c
783 inq_data = (ST_INQ *)hba->copy_buffer;
784 if (inq_data->DeviceTypeQualifier != 0)
785 ccb->srb_status = SRB_STATUS_SELECTION_TIMEOUT;
786 else
787 ccb->srb_status = SRB_STATUS_SUCCESS;
788 }
789 }
790
791 static void stex_mu_intr(struct st_hba *hba, u32 doorbell)
792 {
793 void __iomem *base = hba->mmio_base;
794 struct status_msg *resp;
795 struct st_ccb *ccb;
796 unsigned int size;
797 u16 tag;
798
799 if (!(doorbell & MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED))
800 return;
801
802 /* status payloads */
803 hba->status_head = readl(base + OMR1);
804 if (unlikely(hba->status_head >= MU_STATUS_COUNT)) {
805 printk(KERN_WARNING DRV_NAME "(%s): invalid status head\n",
806 pci_name(hba->pdev));
807 return;
808 }
809
810 /*
811 * it's not a valid status payload if:
812 * 1. there are no pending requests(e.g. during init stage)
813 * 2. there are some pending requests, but the controller is in
814 * reset status, and its type is not st_yosemite
815 * firmware of st_yosemite in reset status will return pending requests
816 * to driver, so we allow it to pass
817 */
818 if (unlikely(hba->out_req_cnt <= 0 ||
819 (hba->mu_status == MU_STATE_RESETTING &&
820 hba->cardtype != st_yosemite))) {
821 hba->status_tail = hba->status_head;
822 goto update_status;
823 }
824
825 while (hba->status_tail != hba->status_head) {
826 resp = stex_get_status(hba);
827 tag = le16_to_cpu(resp->tag);
828 if (unlikely(tag >= hba->host->can_queue)) {
829 printk(KERN_WARNING DRV_NAME
830 "(%s): invalid tag\n", pci_name(hba->pdev));
831 continue;
832 }
833
834 ccb = &hba->ccb[tag];
835 if (hba->wait_ccb == ccb)
836 hba->wait_ccb = NULL;
837 if (unlikely(ccb->req == NULL)) {
838 printk(KERN_WARNING DRV_NAME
839 "(%s): lagging req\n", pci_name(hba->pdev));
840 hba->out_req_cnt--;
841 continue;
842 }
843
844 size = resp->payload_sz * sizeof(u32); /* payload size */
845 if (unlikely(size < sizeof(*resp) - STATUS_VAR_LEN ||
846 size > sizeof(*resp))) {
847 printk(KERN_WARNING DRV_NAME "(%s): bad status size\n",
848 pci_name(hba->pdev));
849 } else {
850 size -= sizeof(*resp) - STATUS_VAR_LEN; /* copy size */
851 if (size)
852 stex_copy_data(ccb, resp, size);
853 }
854
855 ccb->srb_status = resp->srb_status;
856 ccb->scsi_status = resp->scsi_status;
857
858 if (likely(ccb->cmd != NULL)) {
859 if (hba->cardtype == st_yosemite)
860 stex_ys_commands(hba, ccb, resp);
861
862 if (unlikely(ccb->cmd->cmnd[0] == PASSTHRU_CMD &&
863 ccb->cmd->cmnd[1] == PASSTHRU_GET_ADAPTER))
864 stex_controller_info(hba, ccb);
865
866 scsi_dma_unmap(ccb->cmd);
867 stex_scsi_done(ccb);
868 hba->out_req_cnt--;
869 } else if (ccb->req_type & PASSTHRU_REQ_TYPE) {
870 hba->out_req_cnt--;
871 if (ccb->req_type & PASSTHRU_REQ_NO_WAKEUP) {
872 ccb->req_type = 0;
873 continue;
874 }
875 ccb->req_type = 0;
876 if (waitqueue_active(&hba->waitq))
877 wake_up(&hba->waitq);
878 }
879 }
880
881 update_status:
882 writel(hba->status_head, base + IMR1);
883 readl(base + IMR1); /* flush */
884 }
885
886 static irqreturn_t stex_intr(int irq, void *__hba)
887 {
888 struct st_hba *hba = __hba;
889 void __iomem *base = hba->mmio_base;
890 u32 data;
891 unsigned long flags;
892 int handled = 0;
893
894 spin_lock_irqsave(hba->host->host_lock, flags);
895
896 data = readl(base + ODBL);
897
898 if (data && data != 0xffffffff) {
899 /* clear the interrupt */
900 writel(data, base + ODBL);
901 readl(base + ODBL); /* flush */
902 stex_mu_intr(hba, data);
903 handled = 1;
904 }
905
906 spin_unlock_irqrestore(hba->host->host_lock, flags);
907
908 return IRQ_RETVAL(handled);
909 }
910
911 static int stex_handshake(struct st_hba *hba)
912 {
913 void __iomem *base = hba->mmio_base;
914 struct handshake_frame *h;
915 dma_addr_t status_phys;
916 u32 data;
917 unsigned long before;
918
919 if (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
920 writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
921 readl(base + IDBL);
922 before = jiffies;
923 while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
924 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
925 printk(KERN_ERR DRV_NAME
926 "(%s): no handshake signature\n",
927 pci_name(hba->pdev));
928 return -1;
929 }
930 rmb();
931 msleep(1);
932 }
933 }
934
935 udelay(10);
936
937 data = readl(base + OMR1);
938 if ((data & 0xffff0000) == MU_HANDSHAKE_SIGNATURE_HALF) {
939 data &= 0x0000ffff;
940 if (hba->host->can_queue > data)
941 hba->host->can_queue = data;
942 }
943
944 h = (struct handshake_frame *)(hba->dma_mem + MU_REQ_BUFFER_SIZE);
945 h->rb_phy = cpu_to_le32(hba->dma_handle);
946 h->rb_phy_hi = cpu_to_le32((hba->dma_handle >> 16) >> 16);
947 h->req_sz = cpu_to_le16(sizeof(struct req_msg));
948 h->req_cnt = cpu_to_le16(MU_REQ_COUNT);
949 h->status_sz = cpu_to_le16(sizeof(struct status_msg));
950 h->status_cnt = cpu_to_le16(MU_STATUS_COUNT);
951 stex_gettime(&h->hosttime);
952 h->partner_type = HMU_PARTNER_TYPE;
953 if (hba->dma_size > STEX_BUFFER_SIZE) {
954 h->extra_offset = cpu_to_le32(STEX_BUFFER_SIZE);
955 h->extra_size = cpu_to_le32(ST_ADDITIONAL_MEM);
956 } else
957 h->extra_offset = h->extra_size = 0;
958
959 status_phys = hba->dma_handle + MU_REQ_BUFFER_SIZE;
960 writel(status_phys, base + IMR0);
961 readl(base + IMR0);
962 writel((status_phys >> 16) >> 16, base + IMR1);
963 readl(base + IMR1);
964
965 writel((status_phys >> 16) >> 16, base + OMR0); /* old fw compatible */
966 readl(base + OMR0);
967 writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
968 readl(base + IDBL); /* flush */
969
970 udelay(10);
971 before = jiffies;
972 while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
973 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
974 printk(KERN_ERR DRV_NAME
975 "(%s): no signature after handshake frame\n",
976 pci_name(hba->pdev));
977 return -1;
978 }
979 rmb();
980 msleep(1);
981 }
982
983 writel(0, base + IMR0);
984 readl(base + IMR0);
985 writel(0, base + OMR0);
986 readl(base + OMR0);
987 writel(0, base + IMR1);
988 readl(base + IMR1);
989 writel(0, base + OMR1);
990 readl(base + OMR1); /* flush */
991 hba->mu_status = MU_STATE_STARTED;
992 return 0;
993 }
994
995 static int stex_abort(struct scsi_cmnd *cmd)
996 {
997 struct Scsi_Host *host = cmd->device->host;
998 struct st_hba *hba = (struct st_hba *)host->hostdata;
999 u16 tag = cmd->request->tag;
1000 void __iomem *base;
1001 u32 data;
1002 int result = SUCCESS;
1003 unsigned long flags;
1004
1005 printk(KERN_INFO DRV_NAME
1006 "(%s): aborting command\n", pci_name(hba->pdev));
1007 scsi_print_command(cmd);
1008
1009 base = hba->mmio_base;
1010 spin_lock_irqsave(host->host_lock, flags);
1011 if (tag < host->can_queue && hba->ccb[tag].cmd == cmd)
1012 hba->wait_ccb = &hba->ccb[tag];
1013 else {
1014 for (tag = 0; tag < host->can_queue; tag++)
1015 if (hba->ccb[tag].cmd == cmd) {
1016 hba->wait_ccb = &hba->ccb[tag];
1017 break;
1018 }
1019 if (tag >= host->can_queue)
1020 goto out;
1021 }
1022
1023 data = readl(base + ODBL);
1024 if (data == 0 || data == 0xffffffff)
1025 goto fail_out;
1026
1027 writel(data, base + ODBL);
1028 readl(base + ODBL); /* flush */
1029
1030 stex_mu_intr(hba, data);
1031
1032 if (hba->wait_ccb == NULL) {
1033 printk(KERN_WARNING DRV_NAME
1034 "(%s): lost interrupt\n", pci_name(hba->pdev));
1035 goto out;
1036 }
1037
1038 fail_out:
1039 scsi_dma_unmap(cmd);
1040 hba->wait_ccb->req = NULL; /* nullify the req's future return */
1041 hba->wait_ccb = NULL;
1042 result = FAILED;
1043 out:
1044 spin_unlock_irqrestore(host->host_lock, flags);
1045 return result;
1046 }
1047
1048 static void stex_hard_reset(struct st_hba *hba)
1049 {
1050 struct pci_bus *bus;
1051 int i;
1052 u16 pci_cmd;
1053 u8 pci_bctl;
1054
1055 for (i = 0; i < 16; i++)
1056 pci_read_config_dword(hba->pdev, i * 4,
1057 &hba->pdev->saved_config_space[i]);
1058
1059 /* Reset secondary bus. Our controller(MU/ATU) is the only device on
1060 secondary bus. Consult Intel 80331/3 developer's manual for detail */
1061 bus = hba->pdev->bus;
1062 pci_read_config_byte(bus->self, PCI_BRIDGE_CONTROL, &pci_bctl);
1063 pci_bctl |= PCI_BRIDGE_CTL_BUS_RESET;
1064 pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
1065
1066 /*
1067 * 1 ms may be enough for 8-port controllers. But 16-port controllers
1068 * require more time to finish bus reset. Use 100 ms here for safety
1069 */
1070 msleep(100);
1071 pci_bctl &= ~PCI_BRIDGE_CTL_BUS_RESET;
1072 pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
1073
1074 for (i = 0; i < MU_HARD_RESET_WAIT; i++) {
1075 pci_read_config_word(hba->pdev, PCI_COMMAND, &pci_cmd);
1076 if (pci_cmd != 0xffff && (pci_cmd & PCI_COMMAND_MASTER))
1077 break;
1078 msleep(1);
1079 }
1080
1081 ssleep(5);
1082 for (i = 0; i < 16; i++)
1083 pci_write_config_dword(hba->pdev, i * 4,
1084 hba->pdev->saved_config_space[i]);
1085 }
1086
1087 static int stex_reset(struct scsi_cmnd *cmd)
1088 {
1089 struct st_hba *hba;
1090 unsigned long flags;
1091 unsigned long before;
1092 hba = (struct st_hba *) &cmd->device->host->hostdata[0];
1093
1094 printk(KERN_INFO DRV_NAME
1095 "(%s): resetting host\n", pci_name(hba->pdev));
1096 scsi_print_command(cmd);
1097
1098 hba->mu_status = MU_STATE_RESETTING;
1099
1100 if (hba->cardtype == st_shasta)
1101 stex_hard_reset(hba);
1102
1103 if (hba->cardtype != st_yosemite) {
1104 if (stex_handshake(hba)) {
1105 printk(KERN_WARNING DRV_NAME
1106 "(%s): resetting: handshake failed\n",
1107 pci_name(hba->pdev));
1108 return FAILED;
1109 }
1110 spin_lock_irqsave(hba->host->host_lock, flags);
1111 hba->req_head = 0;
1112 hba->req_tail = 0;
1113 hba->status_head = 0;
1114 hba->status_tail = 0;
1115 hba->out_req_cnt = 0;
1116 spin_unlock_irqrestore(hba->host->host_lock, flags);
1117 return SUCCESS;
1118 }
1119
1120 /* st_yosemite */
1121 writel(MU_INBOUND_DOORBELL_RESET, hba->mmio_base + IDBL);
1122 readl(hba->mmio_base + IDBL); /* flush */
1123 before = jiffies;
1124 while (hba->out_req_cnt > 0) {
1125 if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ)) {
1126 printk(KERN_WARNING DRV_NAME
1127 "(%s): reset timeout\n", pci_name(hba->pdev));
1128 return FAILED;
1129 }
1130 msleep(1);
1131 }
1132
1133 hba->mu_status = MU_STATE_STARTED;
1134 return SUCCESS;
1135 }
1136
1137 static int stex_biosparam(struct scsi_device *sdev,
1138 struct block_device *bdev, sector_t capacity, int geom[])
1139 {
1140 int heads = 255, sectors = 63;
1141
1142 if (capacity < 0x200000) {
1143 heads = 64;
1144 sectors = 32;
1145 }
1146
1147 sector_div(capacity, heads * sectors);
1148
1149 geom[0] = heads;
1150 geom[1] = sectors;
1151 geom[2] = capacity;
1152
1153 return 0;
1154 }
1155
1156 static struct scsi_host_template driver_template = {
1157 .module = THIS_MODULE,
1158 .name = DRV_NAME,
1159 .proc_name = DRV_NAME,
1160 .bios_param = stex_biosparam,
1161 .queuecommand = stex_queuecommand,
1162 .slave_alloc = stex_slave_alloc,
1163 .slave_configure = stex_slave_config,
1164 .slave_destroy = stex_slave_destroy,
1165 .eh_abort_handler = stex_abort,
1166 .eh_host_reset_handler = stex_reset,
1167 .can_queue = ST_CAN_QUEUE,
1168 .this_id = -1,
1169 .sg_tablesize = ST_MAX_SG,
1170 .cmd_per_lun = ST_CMD_PER_LUN,
1171 };
1172
1173 static int stex_set_dma_mask(struct pci_dev * pdev)
1174 {
1175 int ret;
1176 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)
1177 && !pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))
1178 return 0;
1179 ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1180 if (!ret)
1181 ret = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1182 return ret;
1183 }
1184
1185 static int __devinit
1186 stex_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1187 {
1188 struct st_hba *hba;
1189 struct Scsi_Host *host;
1190 int err;
1191
1192 err = pci_enable_device(pdev);
1193 if (err)
1194 return err;
1195
1196 pci_set_master(pdev);
1197
1198 host = scsi_host_alloc(&driver_template, sizeof(struct st_hba));
1199
1200 if (!host) {
1201 printk(KERN_ERR DRV_NAME "(%s): scsi_host_alloc failed\n",
1202 pci_name(pdev));
1203 err = -ENOMEM;
1204 goto out_disable;
1205 }
1206
1207 hba = (struct st_hba *)host->hostdata;
1208 memset(hba, 0, sizeof(struct st_hba));
1209
1210 err = pci_request_regions(pdev, DRV_NAME);
1211 if (err < 0) {
1212 printk(KERN_ERR DRV_NAME "(%s): request regions failed\n",
1213 pci_name(pdev));
1214 goto out_scsi_host_put;
1215 }
1216
1217 hba->mmio_base = ioremap_nocache(pci_resource_start(pdev, 0),
1218 pci_resource_len(pdev, 0));
1219 if ( !hba->mmio_base) {
1220 printk(KERN_ERR DRV_NAME "(%s): memory map failed\n",
1221 pci_name(pdev));
1222 err = -ENOMEM;
1223 goto out_release_regions;
1224 }
1225
1226 err = stex_set_dma_mask(pdev);
1227 if (err) {
1228 printk(KERN_ERR DRV_NAME "(%s): set dma mask failed\n",
1229 pci_name(pdev));
1230 goto out_iounmap;
1231 }
1232
1233 hba->cardtype = (unsigned int) id->driver_data;
1234 if (hba->cardtype == st_vsc && (pdev->subsystem_device & 0xf) == 0x1)
1235 hba->cardtype = st_vsc1;
1236 hba->dma_size = (hba->cardtype == st_vsc1) ?
1237 (STEX_BUFFER_SIZE + ST_ADDITIONAL_MEM) : (STEX_BUFFER_SIZE);
1238 hba->dma_mem = dma_alloc_coherent(&pdev->dev,
1239 hba->dma_size, &hba->dma_handle, GFP_KERNEL);
1240 if (!hba->dma_mem) {
1241 err = -ENOMEM;
1242 printk(KERN_ERR DRV_NAME "(%s): dma mem alloc failed\n",
1243 pci_name(pdev));
1244 goto out_iounmap;
1245 }
1246
1247 hba->status_buffer =
1248 (struct status_msg *)(hba->dma_mem + MU_REQ_BUFFER_SIZE);
1249 hba->copy_buffer = hba->dma_mem + MU_BUFFER_SIZE;
1250 hba->mu_status = MU_STATE_STARTING;
1251
1252 if (hba->cardtype == st_shasta) {
1253 host->max_lun = 8;
1254 host->max_id = 16 + 1;
1255 } else if (hba->cardtype == st_yosemite) {
1256 host->max_lun = 128;
1257 host->max_id = 1 + 1;
1258 } else {
1259 /* st_vsc and st_vsc1 */
1260 host->max_lun = 1;
1261 host->max_id = 128 + 1;
1262 }
1263 host->max_channel = 0;
1264 host->unique_id = host->host_no;
1265 host->max_cmd_len = STEX_CDB_LENGTH;
1266
1267 hba->host = host;
1268 hba->pdev = pdev;
1269 init_waitqueue_head(&hba->waitq);
1270
1271 err = request_irq(pdev->irq, stex_intr, IRQF_SHARED, DRV_NAME, hba);
1272 if (err) {
1273 printk(KERN_ERR DRV_NAME "(%s): request irq failed\n",
1274 pci_name(pdev));
1275 goto out_pci_free;
1276 }
1277
1278 err = stex_handshake(hba);
1279 if (err)
1280 goto out_free_irq;
1281
1282 err = scsi_init_shared_tag_map(host, host->can_queue);
1283 if (err) {
1284 printk(KERN_ERR DRV_NAME "(%s): init shared queue failed\n",
1285 pci_name(pdev));
1286 goto out_free_irq;
1287 }
1288
1289 pci_set_drvdata(pdev, hba);
1290
1291 err = scsi_add_host(host, &pdev->dev);
1292 if (err) {
1293 printk(KERN_ERR DRV_NAME "(%s): scsi_add_host failed\n",
1294 pci_name(pdev));
1295 goto out_free_irq;
1296 }
1297
1298 scsi_scan_host(host);
1299
1300 return 0;
1301
1302 out_free_irq:
1303 free_irq(pdev->irq, hba);
1304 out_pci_free:
1305 dma_free_coherent(&pdev->dev, hba->dma_size,
1306 hba->dma_mem, hba->dma_handle);
1307 out_iounmap:
1308 iounmap(hba->mmio_base);
1309 out_release_regions:
1310 pci_release_regions(pdev);
1311 out_scsi_host_put:
1312 scsi_host_put(host);
1313 out_disable:
1314 pci_disable_device(pdev);
1315
1316 return err;
1317 }
1318
1319 static void stex_hba_stop(struct st_hba *hba)
1320 {
1321 struct req_msg *req;
1322 unsigned long flags;
1323 unsigned long before;
1324 u16 tag = 0;
1325
1326 spin_lock_irqsave(hba->host->host_lock, flags);
1327 req = stex_alloc_req(hba);
1328 memset(req->cdb, 0, STEX_CDB_LENGTH);
1329
1330 if (hba->cardtype == st_yosemite) {
1331 req->cdb[0] = MGT_CMD;
1332 req->cdb[1] = MGT_CMD_SIGNATURE;
1333 req->cdb[2] = CTLR_CONFIG_CMD;
1334 req->cdb[3] = CTLR_SHUTDOWN;
1335 } else {
1336 req->cdb[0] = CONTROLLER_CMD;
1337 req->cdb[1] = CTLR_POWER_STATE_CHANGE;
1338 req->cdb[2] = CTLR_POWER_SAVING;
1339 }
1340
1341 hba->ccb[tag].cmd = NULL;
1342 hba->ccb[tag].sg_count = 0;
1343 hba->ccb[tag].sense_bufflen = 0;
1344 hba->ccb[tag].sense_buffer = NULL;
1345 hba->ccb[tag].req_type |= PASSTHRU_REQ_TYPE;
1346
1347 stex_send_cmd(hba, req, tag);
1348 spin_unlock_irqrestore(hba->host->host_lock, flags);
1349
1350 before = jiffies;
1351 while (hba->ccb[tag].req_type & PASSTHRU_REQ_TYPE) {
1352 if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ))
1353 return;
1354 msleep(10);
1355 }
1356 }
1357
1358 static void stex_hba_free(struct st_hba *hba)
1359 {
1360 free_irq(hba->pdev->irq, hba);
1361
1362 iounmap(hba->mmio_base);
1363
1364 pci_release_regions(hba->pdev);
1365
1366 dma_free_coherent(&hba->pdev->dev, hba->dma_size,
1367 hba->dma_mem, hba->dma_handle);
1368 }
1369
1370 static void stex_remove(struct pci_dev *pdev)
1371 {
1372 struct st_hba *hba = pci_get_drvdata(pdev);
1373
1374 scsi_remove_host(hba->host);
1375
1376 pci_set_drvdata(pdev, NULL);
1377
1378 stex_hba_stop(hba);
1379
1380 stex_hba_free(hba);
1381
1382 scsi_host_put(hba->host);
1383
1384 pci_disable_device(pdev);
1385 }
1386
1387 static void stex_shutdown(struct pci_dev *pdev)
1388 {
1389 struct st_hba *hba = pci_get_drvdata(pdev);
1390
1391 stex_hba_stop(hba);
1392 }
1393
1394 static struct pci_device_id stex_pci_tbl[] = {
1395 /* st_shasta */
1396 { 0x105a, 0x8350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1397 st_shasta }, /* SuperTrak EX8350/8300/16350/16300 */
1398 { 0x105a, 0xc350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1399 st_shasta }, /* SuperTrak EX12350 */
1400 { 0x105a, 0x4302, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1401 st_shasta }, /* SuperTrak EX4350 */
1402 { 0x105a, 0xe350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1403 st_shasta }, /* SuperTrak EX24350 */
1404
1405 /* st_vsc */
1406 { 0x105a, 0x7250, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_vsc },
1407
1408 /* st_yosemite */
1409 { 0x105a, 0x8650, PCI_ANY_ID, 0x4600, 0, 0,
1410 st_yosemite }, /* SuperTrak EX4650 */
1411 { 0x105a, 0x8650, PCI_ANY_ID, 0x4610, 0, 0,
1412 st_yosemite }, /* SuperTrak EX4650o */
1413 { 0x105a, 0x8650, PCI_ANY_ID, 0x8600, 0, 0,
1414 st_yosemite }, /* SuperTrak EX8650EL */
1415 { 0x105a, 0x8650, PCI_ANY_ID, 0x8601, 0, 0,
1416 st_yosemite }, /* SuperTrak EX8650 */
1417 { 0x105a, 0x8650, PCI_ANY_ID, 0x8602, 0, 0,
1418 st_yosemite }, /* SuperTrak EX8654 */
1419 { 0x105a, 0x8650, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1420 st_yosemite }, /* generic st_yosemite */
1421 { } /* terminate list */
1422 };
1423 MODULE_DEVICE_TABLE(pci, stex_pci_tbl);
1424
1425 static struct pci_driver stex_pci_driver = {
1426 .name = DRV_NAME,
1427 .id_table = stex_pci_tbl,
1428 .probe = stex_probe,
1429 .remove = __devexit_p(stex_remove),
1430 .shutdown = stex_shutdown,
1431 };
1432
1433 static int __init stex_init(void)
1434 {
1435 printk(KERN_INFO DRV_NAME
1436 ": Promise SuperTrak EX Driver version: %s\n",
1437 ST_DRIVER_VERSION);
1438
1439 return pci_register_driver(&stex_pci_driver);
1440 }
1441
1442 static void __exit stex_exit(void)
1443 {
1444 pci_unregister_driver(&stex_pci_driver);
1445 }
1446
1447 module_init(stex_init);
1448 module_exit(stex_exit);
WRT350N Kernel Patches