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Merge git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
[wrt350n-kernel.git] / drivers / spi / pxa2xx_spi.c
blobeb1a5ff8b99515dd4907e75ee51301425a8b3d03
1 /*
2 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 */
18
19 #include <linux/init.h>
20 #include <linux/module.h>
21 #include <linux/device.h>
22 #include <linux/ioport.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/platform_device.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/spi/spi.h>
28 #include <linux/workqueue.h>
29 #include <linux/delay.h>
30 #include <linux/clk.h>
31
32 #include <asm/io.h>
33 #include <asm/irq.h>
34 #include <asm/hardware.h>
35 #include <asm/delay.h>
36 #include <asm/dma.h>
37
38 #include <asm/arch/hardware.h>
39 #include <asm/arch/pxa-regs.h>
40 #include <asm/arch/regs-ssp.h>
41 #include <asm/arch/ssp.h>
42 #include <asm/arch/pxa2xx_spi.h>
43
44 MODULE_AUTHOR("Stephen Street");
45 MODULE_DESCRIPTION("PXA2xx SSP SPI Controller");
46 MODULE_LICENSE("GPL");
47
48 #define MAX_BUSES 3
49
50 #define DMA_INT_MASK (DCSR_ENDINTR | DCSR_STARTINTR | DCSR_BUSERR)
51 #define RESET_DMA_CHANNEL (DCSR_NODESC | DMA_INT_MASK)
52 #define IS_DMA_ALIGNED(x) (((u32)(x)&0x07)==0)
53
54 <<<<<<< HEAD:drivers/spi/pxa2xx_spi.c
55 /* for testing SSCR1 changes that require SSP restart, basically
56 * everything except the service and interrupt enables */
57 #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_EBCEI | SSCR1_SCFR \
58 =======
59 /*
60 * for testing SSCR1 changes that require SSP restart, basically
61 * everything except the service and interrupt enables, the pxa270 developer
62 * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this
63 * list, but the PXA255 dev man says all bits without really meaning the
64 * service and interrupt enables
65 */
66 #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
67 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/spi/pxa2xx_spi.c
68 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
69 <<<<<<< HEAD:drivers/spi/pxa2xx_spi.c
70 | SSCR1_RWOT | SSCR1_TRAIL | SSCR1_PINTE \
71 | SSCR1_STRF | SSCR1_EFWR |SSCR1_RFT \
72 | SSCR1_TFT | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
73 =======
74 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
75 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
76 | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \
77 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
78 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/spi/pxa2xx_spi.c
79
80 #define DEFINE_SSP_REG(reg, off) \
81 static inline u32 read_##reg(void *p) { return __raw_readl(p + (off)); } \
82 static inline void write_##reg(u32 v, void *p) { __raw_writel(v, p + (off)); }
83
84 DEFINE_SSP_REG(SSCR0, 0x00)
85 DEFINE_SSP_REG(SSCR1, 0x04)
86 DEFINE_SSP_REG(SSSR, 0x08)
87 DEFINE_SSP_REG(SSITR, 0x0c)
88 DEFINE_SSP_REG(SSDR, 0x10)
89 DEFINE_SSP_REG(SSTO, 0x28)
90 DEFINE_SSP_REG(SSPSP, 0x2c)
91
92 #define START_STATE ((void*)0)
93 #define RUNNING_STATE ((void*)1)
94 #define DONE_STATE ((void*)2)
95 #define ERROR_STATE ((void*)-1)
96
97 #define QUEUE_RUNNING 0
98 #define QUEUE_STOPPED 1
99
100 struct driver_data {
101 /* Driver model hookup */
102 struct platform_device *pdev;
103
104 /* SSP Info */
105 struct ssp_device *ssp;
106
107 /* SPI framework hookup */
108 enum pxa_ssp_type ssp_type;
109 struct spi_master *master;
110
111 /* PXA hookup */
112 struct pxa2xx_spi_master *master_info;
113
114 /* DMA setup stuff */
115 int rx_channel;
116 int tx_channel;
117 u32 *null_dma_buf;
118
119 /* SSP register addresses */
120 void *ioaddr;
121 u32 ssdr_physical;
122
123 /* SSP masks*/
124 u32 dma_cr1;
125 u32 int_cr1;
126 u32 clear_sr;
127 u32 mask_sr;
128
129 /* Driver message queue */
130 struct workqueue_struct *workqueue;
131 struct work_struct pump_messages;
132 spinlock_t lock;
133 struct list_head queue;
134 int busy;
135 int run;
136
137 /* Message Transfer pump */
138 struct tasklet_struct pump_transfers;
139
140 /* Current message transfer state info */
141 struct spi_message* cur_msg;
142 struct spi_transfer* cur_transfer;
143 struct chip_data *cur_chip;
144 size_t len;
145 void *tx;
146 void *tx_end;
147 void *rx;
148 void *rx_end;
149 int dma_mapped;
150 dma_addr_t rx_dma;
151 dma_addr_t tx_dma;
152 size_t rx_map_len;
153 size_t tx_map_len;
154 u8 n_bytes;
155 u32 dma_width;
156 int cs_change;
157 int (*write)(struct driver_data *drv_data);
158 int (*read)(struct driver_data *drv_data);
159 irqreturn_t (*transfer_handler)(struct driver_data *drv_data);
160 void (*cs_control)(u32 command);
161 };
162
163 struct chip_data {
164 u32 cr0;
165 u32 cr1;
166 u32 psp;
167 u32 timeout;
168 u8 n_bytes;
169 u32 dma_width;
170 u32 dma_burst_size;
171 u32 threshold;
172 u32 dma_threshold;
173 u8 enable_dma;
174 u8 bits_per_word;
175 u32 speed_hz;
176 int (*write)(struct driver_data *drv_data);
177 int (*read)(struct driver_data *drv_data);
178 void (*cs_control)(u32 command);
179 };
180
181 static void pump_messages(struct work_struct *work);
182
183 static int flush(struct driver_data *drv_data)
184 {
185 unsigned long limit = loops_per_jiffy << 1;
186
187 void *reg = drv_data->ioaddr;
188
189 do {
190 while (read_SSSR(reg) & SSSR_RNE) {
191 read_SSDR(reg);
192 }
193 } while ((read_SSSR(reg) & SSSR_BSY) && limit--);
194 write_SSSR(SSSR_ROR, reg);
195
196 return limit;
197 }
198
199 static void null_cs_control(u32 command)
200 {
201 }
202
203 static int null_writer(struct driver_data *drv_data)
204 {
205 void *reg = drv_data->ioaddr;
206 u8 n_bytes = drv_data->n_bytes;
207
208 if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00)
209 || (drv_data->tx == drv_data->tx_end))
210 return 0;
211
212 write_SSDR(0, reg);
213 drv_data->tx += n_bytes;
214
215 return 1;
216 }
217
218 static int null_reader(struct driver_data *drv_data)
219 {
220 void *reg = drv_data->ioaddr;
221 u8 n_bytes = drv_data->n_bytes;
222
223 while ((read_SSSR(reg) & SSSR_RNE)
224 && (drv_data->rx < drv_data->rx_end)) {
225 read_SSDR(reg);
226 drv_data->rx += n_bytes;
227 }
228
229 return drv_data->rx == drv_data->rx_end;
230 }
231
232 static int u8_writer(struct driver_data *drv_data)
233 {
234 void *reg = drv_data->ioaddr;
235
236 if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00)
237 || (drv_data->tx == drv_data->tx_end))
238 return 0;
239
240 write_SSDR(*(u8 *)(drv_data->tx), reg);
241 ++drv_data->tx;
242
243 return 1;
244 }
245
246 static int u8_reader(struct driver_data *drv_data)
247 {
248 void *reg = drv_data->ioaddr;
249
250 while ((read_SSSR(reg) & SSSR_RNE)
251 && (drv_data->rx < drv_data->rx_end)) {
252 *(u8 *)(drv_data->rx) = read_SSDR(reg);
253 ++drv_data->rx;
254 }
255
256 return drv_data->rx == drv_data->rx_end;
257 }
258
259 static int u16_writer(struct driver_data *drv_data)
260 {
261 void *reg = drv_data->ioaddr;
262
263 if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00)
264 || (drv_data->tx == drv_data->tx_end))
265 return 0;
266
267 write_SSDR(*(u16 *)(drv_data->tx), reg);
268 drv_data->tx += 2;
269
270 return 1;
271 }
272
273 static int u16_reader(struct driver_data *drv_data)
274 {
275 void *reg = drv_data->ioaddr;
276
277 while ((read_SSSR(reg) & SSSR_RNE)
278 && (drv_data->rx < drv_data->rx_end)) {
279 *(u16 *)(drv_data->rx) = read_SSDR(reg);
280 drv_data->rx += 2;
281 }
282
283 return drv_data->rx == drv_data->rx_end;
284 }
285
286 static int u32_writer(struct driver_data *drv_data)
287 {
288 void *reg = drv_data->ioaddr;
289
290 if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00)
291 || (drv_data->tx == drv_data->tx_end))
292 return 0;
293
294 write_SSDR(*(u32 *)(drv_data->tx), reg);
295 drv_data->tx += 4;
296
297 return 1;
298 }
299
300 static int u32_reader(struct driver_data *drv_data)
301 {
302 void *reg = drv_data->ioaddr;
303
304 while ((read_SSSR(reg) & SSSR_RNE)
305 && (drv_data->rx < drv_data->rx_end)) {
306 *(u32 *)(drv_data->rx) = read_SSDR(reg);
307 drv_data->rx += 4;
308 }
309
310 return drv_data->rx == drv_data->rx_end;
311 }
312
313 static void *next_transfer(struct driver_data *drv_data)
314 {
315 struct spi_message *msg = drv_data->cur_msg;
316 struct spi_transfer *trans = drv_data->cur_transfer;
317
318 /* Move to next transfer */
319 if (trans->transfer_list.next != &msg->transfers) {
320 drv_data->cur_transfer =
321 list_entry(trans->transfer_list.next,
322 struct spi_transfer,
323 transfer_list);
324 return RUNNING_STATE;
325 } else
326 return DONE_STATE;
327 }
328
329 static int map_dma_buffers(struct driver_data *drv_data)
330 {
331 struct spi_message *msg = drv_data->cur_msg;
332 struct device *dev = &msg->spi->dev;
333
334 if (!drv_data->cur_chip->enable_dma)
335 return 0;
336
337 if (msg->is_dma_mapped)
338 return drv_data->rx_dma && drv_data->tx_dma;
339
340 if (!IS_DMA_ALIGNED(drv_data->rx) || !IS_DMA_ALIGNED(drv_data->tx))
341 return 0;
342
343 /* Modify setup if rx buffer is null */
344 if (drv_data->rx == NULL) {
345 *drv_data->null_dma_buf = 0;
346 drv_data->rx = drv_data->null_dma_buf;
347 drv_data->rx_map_len = 4;
348 } else
349 drv_data->rx_map_len = drv_data->len;
350
351
352 /* Modify setup if tx buffer is null */
353 if (drv_data->tx == NULL) {
354 *drv_data->null_dma_buf = 0;
355 drv_data->tx = drv_data->null_dma_buf;
356 drv_data->tx_map_len = 4;
357 } else
358 drv_data->tx_map_len = drv_data->len;
359
360 /* Stream map the rx buffer */
361 drv_data->rx_dma = dma_map_single(dev, drv_data->rx,
362 drv_data->rx_map_len,
363 DMA_FROM_DEVICE);
364 if (dma_mapping_error(drv_data->rx_dma))
365 return 0;
366
367 /* Stream map the tx buffer */
368 drv_data->tx_dma = dma_map_single(dev, drv_data->tx,
369 drv_data->tx_map_len,
370 DMA_TO_DEVICE);
371
372 if (dma_mapping_error(drv_data->tx_dma)) {
373 dma_unmap_single(dev, drv_data->rx_dma,
374 drv_data->rx_map_len, DMA_FROM_DEVICE);
375 return 0;
376 }
377
378 return 1;
379 }
380
381 static void unmap_dma_buffers(struct driver_data *drv_data)
382 {
383 struct device *dev;
384
385 if (!drv_data->dma_mapped)
386 return;
387
388 if (!drv_data->cur_msg->is_dma_mapped) {
389 dev = &drv_data->cur_msg->spi->dev;
390 dma_unmap_single(dev, drv_data->rx_dma,
391 drv_data->rx_map_len, DMA_FROM_DEVICE);
392 dma_unmap_single(dev, drv_data->tx_dma,
393 drv_data->tx_map_len, DMA_TO_DEVICE);
394 }
395
396 drv_data->dma_mapped = 0;
397 }
398
399 /* caller already set message->status; dma and pio irqs are blocked */
400 static void giveback(struct driver_data *drv_data)
401 {
402 struct spi_transfer* last_transfer;
403 unsigned long flags;
404 struct spi_message *msg;
405
406 spin_lock_irqsave(&drv_data->lock, flags);
407 msg = drv_data->cur_msg;
408 drv_data->cur_msg = NULL;
409 drv_data->cur_transfer = NULL;
410 drv_data->cur_chip = NULL;
411 queue_work(drv_data->workqueue, &drv_data->pump_messages);
412 spin_unlock_irqrestore(&drv_data->lock, flags);
413
414 last_transfer = list_entry(msg->transfers.prev,
415 struct spi_transfer,
416 transfer_list);
417
418 if (!last_transfer->cs_change)
419 drv_data->cs_control(PXA2XX_CS_DEASSERT);
420
421 msg->state = NULL;
422 if (msg->complete)
423 msg->complete(msg->context);
424 }
425
426 static int wait_ssp_rx_stall(void *ioaddr)
427 {
428 unsigned long limit = loops_per_jiffy << 1;
429
430 while ((read_SSSR(ioaddr) & SSSR_BSY) && limit--)
431 cpu_relax();
432
433 return limit;
434 }
435
436 static int wait_dma_channel_stop(int channel)
437 {
438 unsigned long limit = loops_per_jiffy << 1;
439
440 while (!(DCSR(channel) & DCSR_STOPSTATE) && limit--)
441 cpu_relax();
442
443 return limit;
444 }
445
446 void dma_error_stop(struct driver_data *drv_data, const char *msg)
447 {
448 void *reg = drv_data->ioaddr;
449
450 /* Stop and reset */
451 DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
452 DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
453 write_SSSR(drv_data->clear_sr, reg);
454 write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg);
455 if (drv_data->ssp_type != PXA25x_SSP)
456 write_SSTO(0, reg);
457 flush(drv_data);
458 write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
459
460 unmap_dma_buffers(drv_data);
461
462 dev_err(&drv_data->pdev->dev, "%s\n", msg);
463
464 drv_data->cur_msg->state = ERROR_STATE;
465 tasklet_schedule(&drv_data->pump_transfers);
466 }
467
468 static void dma_transfer_complete(struct driver_data *drv_data)
469 {
470 void *reg = drv_data->ioaddr;
471 struct spi_message *msg = drv_data->cur_msg;
472
473 /* Clear and disable interrupts on SSP and DMA channels*/
474 write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg);
475 write_SSSR(drv_data->clear_sr, reg);
476 DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
477 DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
478
479 if (wait_dma_channel_stop(drv_data->rx_channel) == 0)
480 dev_err(&drv_data->pdev->dev,
481 "dma_handler: dma rx channel stop failed\n");
482
483 if (wait_ssp_rx_stall(drv_data->ioaddr) == 0)
484 dev_err(&drv_data->pdev->dev,
485 "dma_transfer: ssp rx stall failed\n");
486
487 unmap_dma_buffers(drv_data);
488
489 /* update the buffer pointer for the amount completed in dma */
490 drv_data->rx += drv_data->len -
491 (DCMD(drv_data->rx_channel) & DCMD_LENGTH);
492
493 /* read trailing data from fifo, it does not matter how many
494 * bytes are in the fifo just read until buffer is full
495 * or fifo is empty, which ever occurs first */
496 drv_data->read(drv_data);
497
498 /* return count of what was actually read */
499 msg->actual_length += drv_data->len -
500 (drv_data->rx_end - drv_data->rx);
501
502 /* Release chip select if requested, transfer delays are
503 * handled in pump_transfers */
504 if (drv_data->cs_change)
505 drv_data->cs_control(PXA2XX_CS_DEASSERT);
506
507 /* Move to next transfer */
508 msg->state = next_transfer(drv_data);
509
510 /* Schedule transfer tasklet */
511 tasklet_schedule(&drv_data->pump_transfers);
512 }
513
514 static void dma_handler(int channel, void *data)
515 {
516 struct driver_data *drv_data = data;
517 u32 irq_status = DCSR(channel) & DMA_INT_MASK;
518
519 if (irq_status & DCSR_BUSERR) {
520
521 if (channel == drv_data->tx_channel)
522 dma_error_stop(drv_data,
523 "dma_handler: "
524 "bad bus address on tx channel");
525 else
526 dma_error_stop(drv_data,
527 "dma_handler: "
528 "bad bus address on rx channel");
529 return;
530 }
531
532 /* PXA255x_SSP has no timeout interrupt, wait for tailing bytes */
533 if ((channel == drv_data->tx_channel)
534 && (irq_status & DCSR_ENDINTR)
535 && (drv_data->ssp_type == PXA25x_SSP)) {
536
537 /* Wait for rx to stall */
538 if (wait_ssp_rx_stall(drv_data->ioaddr) == 0)
539 dev_err(&drv_data->pdev->dev,
540 "dma_handler: ssp rx stall failed\n");
541
542 /* finish this transfer, start the next */
543 dma_transfer_complete(drv_data);
544 }
545 }
546
547 static irqreturn_t dma_transfer(struct driver_data *drv_data)
548 {
549 u32 irq_status;
550 void *reg = drv_data->ioaddr;
551
552 irq_status = read_SSSR(reg) & drv_data->mask_sr;
553 if (irq_status & SSSR_ROR) {
554 dma_error_stop(drv_data, "dma_transfer: fifo overrun");
555 return IRQ_HANDLED;
556 }
557
558 /* Check for false positive timeout */
559 if ((irq_status & SSSR_TINT)
560 && (DCSR(drv_data->tx_channel) & DCSR_RUN)) {
561 write_SSSR(SSSR_TINT, reg);
562 return IRQ_HANDLED;
563 }
564
565 if (irq_status & SSSR_TINT || drv_data->rx == drv_data->rx_end) {
566
567 /* Clear and disable timeout interrupt, do the rest in
568 * dma_transfer_complete */
569 if (drv_data->ssp_type != PXA25x_SSP)
570 write_SSTO(0, reg);
571
572 /* finish this transfer, start the next */
573 dma_transfer_complete(drv_data);
574
575 return IRQ_HANDLED;
576 }
577
578 /* Opps problem detected */
579 return IRQ_NONE;
580 }
581
582 static void int_error_stop(struct driver_data *drv_data, const char* msg)
583 {
584 void *reg = drv_data->ioaddr;
585
586 /* Stop and reset SSP */
587 write_SSSR(drv_data->clear_sr, reg);
588 write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg);
589 if (drv_data->ssp_type != PXA25x_SSP)
590 write_SSTO(0, reg);
591 flush(drv_data);
592 write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
593
594 dev_err(&drv_data->pdev->dev, "%s\n", msg);
595
596 drv_data->cur_msg->state = ERROR_STATE;
597 tasklet_schedule(&drv_data->pump_transfers);
598 }
599
600 static void int_transfer_complete(struct driver_data *drv_data)
601 {
602 void *reg = drv_data->ioaddr;
603
604 /* Stop SSP */
605 write_SSSR(drv_data->clear_sr, reg);
606 write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg);
607 if (drv_data->ssp_type != PXA25x_SSP)
608 write_SSTO(0, reg);
609
610 /* Update total byte transfered return count actual bytes read */
611 drv_data->cur_msg->actual_length += drv_data->len -
612 (drv_data->rx_end - drv_data->rx);
613
614 /* Release chip select if requested, transfer delays are
615 * handled in pump_transfers */
616 if (drv_data->cs_change)
617 drv_data->cs_control(PXA2XX_CS_DEASSERT);
618
619 /* Move to next transfer */
620 drv_data->cur_msg->state = next_transfer(drv_data);
621
622 /* Schedule transfer tasklet */
623 tasklet_schedule(&drv_data->pump_transfers);
624 }
625
626 static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
627 {
628 void *reg = drv_data->ioaddr;
629
630 u32 irq_mask = (read_SSCR1(reg) & SSCR1_TIE) ?
631 drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS;
632
633 u32 irq_status = read_SSSR(reg) & irq_mask;
634
635 if (irq_status & SSSR_ROR) {
636 int_error_stop(drv_data, "interrupt_transfer: fifo overrun");
637 return IRQ_HANDLED;
638 }
639
640 if (irq_status & SSSR_TINT) {
641 write_SSSR(SSSR_TINT, reg);
642 if (drv_data->read(drv_data)) {
643 int_transfer_complete(drv_data);
644 return IRQ_HANDLED;
645 }
646 }
647
648 /* Drain rx fifo, Fill tx fifo and prevent overruns */
649 do {
650 if (drv_data->read(drv_data)) {
651 int_transfer_complete(drv_data);
652 return IRQ_HANDLED;
653 }
654 } while (drv_data->write(drv_data));
655
656 if (drv_data->read(drv_data)) {
657 int_transfer_complete(drv_data);
658 return IRQ_HANDLED;
659 }
660
661 if (drv_data->tx == drv_data->tx_end) {
662 write_SSCR1(read_SSCR1(reg) & ~SSCR1_TIE, reg);
663 /* PXA25x_SSP has no timeout, read trailing bytes */
664 if (drv_data->ssp_type == PXA25x_SSP) {
665 if (!wait_ssp_rx_stall(reg))
666 {
667 int_error_stop(drv_data, "interrupt_transfer: "
668 "rx stall failed");
669 return IRQ_HANDLED;
670 }
671 if (!drv_data->read(drv_data))
672 {
673 int_error_stop(drv_data,
674 "interrupt_transfer: "
675 "trailing byte read failed");
676 return IRQ_HANDLED;
677 }
678 int_transfer_complete(drv_data);
679 }
680 }
681
682 /* We did something */
683 return IRQ_HANDLED;
684 }
685
686 static irqreturn_t ssp_int(int irq, void *dev_id)
687 {
688 struct driver_data *drv_data = dev_id;
689 void *reg = drv_data->ioaddr;
690
691 if (!drv_data->cur_msg) {
692
693 write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
694 write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg);
695 if (drv_data->ssp_type != PXA25x_SSP)
696 write_SSTO(0, reg);
697 write_SSSR(drv_data->clear_sr, reg);
698
699 dev_err(&drv_data->pdev->dev, "bad message state "
700 "in interrupt handler\n");
701
702 /* Never fail */
703 return IRQ_HANDLED;
704 }
705
706 return drv_data->transfer_handler(drv_data);
707 }
708
709 int set_dma_burst_and_threshold(struct chip_data *chip, struct spi_device *spi,
710 u8 bits_per_word, u32 *burst_code,
711 u32 *threshold)
712 {
713 struct pxa2xx_spi_chip *chip_info =
714 (struct pxa2xx_spi_chip *)spi->controller_data;
715 int bytes_per_word;
716 int burst_bytes;
717 int thresh_words;
718 int req_burst_size;
719 int retval = 0;
720
721 /* Set the threshold (in registers) to equal the same amount of data
722 * as represented by burst size (in bytes). The computation below
723 * is (burst_size rounded up to nearest 8 byte, word or long word)
724 * divided by (bytes/register); the tx threshold is the inverse of
725 * the rx, so that there will always be enough data in the rx fifo
726 * to satisfy a burst, and there will always be enough space in the
727 * tx fifo to accept a burst (a tx burst will overwrite the fifo if
728 * there is not enough space), there must always remain enough empty
729 * space in the rx fifo for any data loaded to the tx fifo.
730 * Whenever burst_size (in bytes) equals bits/word, the fifo threshold
731 * will be 8, or half the fifo;
732 * The threshold can only be set to 2, 4 or 8, but not 16, because
733 * to burst 16 to the tx fifo, the fifo would have to be empty;
734 * however, the minimum fifo trigger level is 1, and the tx will
735 * request service when the fifo is at this level, with only 15 spaces.
736 */
737
738 /* find bytes/word */
739 if (bits_per_word <= 8)
740 bytes_per_word = 1;
741 else if (bits_per_word <= 16)
742 bytes_per_word = 2;
743 else
744 bytes_per_word = 4;
745
746 /* use struct pxa2xx_spi_chip->dma_burst_size if available */
747 if (chip_info)
748 req_burst_size = chip_info->dma_burst_size;
749 else {
750 switch (chip->dma_burst_size) {
751 default:
752 /* if the default burst size is not set,
753 * do it now */
754 chip->dma_burst_size = DCMD_BURST8;
755 case DCMD_BURST8:
756 req_burst_size = 8;
757 break;
758 case DCMD_BURST16:
759 req_burst_size = 16;
760 break;
761 case DCMD_BURST32:
762 req_burst_size = 32;
763 break;
764 }
765 }
766 if (req_burst_size <= 8) {
767 *burst_code = DCMD_BURST8;
768 burst_bytes = 8;
769 } else if (req_burst_size <= 16) {
770 if (bytes_per_word == 1) {
771 /* don't burst more than 1/2 the fifo */
772 *burst_code = DCMD_BURST8;
773 burst_bytes = 8;
774 retval = 1;
775 } else {
776 *burst_code = DCMD_BURST16;
777 burst_bytes = 16;
778 }
779 } else {
780 if (bytes_per_word == 1) {
781 /* don't burst more than 1/2 the fifo */
782 *burst_code = DCMD_BURST8;
783 burst_bytes = 8;
784 retval = 1;
785 } else if (bytes_per_word == 2) {
786 /* don't burst more than 1/2 the fifo */
787 *burst_code = DCMD_BURST16;
788 burst_bytes = 16;
789 retval = 1;
790 } else {
791 *burst_code = DCMD_BURST32;
792 burst_bytes = 32;
793 }
794 }
795
796 thresh_words = burst_bytes / bytes_per_word;
797
798 /* thresh_words will be between 2 and 8 */
799 *threshold = (SSCR1_RxTresh(thresh_words) & SSCR1_RFT)
800 | (SSCR1_TxTresh(16-thresh_words) & SSCR1_TFT);
801
802 return retval;
803 }
804
805 static unsigned int ssp_get_clk_div(struct ssp_device *ssp, int rate)
806 {
807 unsigned long ssp_clk = clk_get_rate(ssp->clk);
808
809 if (ssp->type == PXA25x_SSP)
810 return ((ssp_clk / (2 * rate) - 1) & 0xff) << 8;
811 else
812 return ((ssp_clk / rate - 1) & 0xfff) << 8;
813 }
814
815 static void pump_transfers(unsigned long data)
816 {
817 struct driver_data *drv_data = (struct driver_data *)data;
818 struct spi_message *message = NULL;
819 struct spi_transfer *transfer = NULL;
820 struct spi_transfer *previous = NULL;
821 struct chip_data *chip = NULL;
822 struct ssp_device *ssp = drv_data->ssp;
823 void *reg = drv_data->ioaddr;
824 u32 clk_div = 0;
825 u8 bits = 0;
826 u32 speed = 0;
827 u32 cr0;
828 u32 cr1;
829 u32 dma_thresh = drv_data->cur_chip->dma_threshold;
830 u32 dma_burst = drv_data->cur_chip->dma_burst_size;
831
832 /* Get current state information */
833 message = drv_data->cur_msg;
834 transfer = drv_data->cur_transfer;
835 chip = drv_data->cur_chip;
836
837 /* Handle for abort */
838 if (message->state == ERROR_STATE) {
839 message->status = -EIO;
840 giveback(drv_data);
841 return;
842 }
843
844 /* Handle end of message */
845 if (message->state == DONE_STATE) {
846 message->status = 0;
847 giveback(drv_data);
848 return;
849 }
850
851 /* Delay if requested at end of transfer*/
852 if (message->state == RUNNING_STATE) {
853 previous = list_entry(transfer->transfer_list.prev,
854 struct spi_transfer,
855 transfer_list);
856 if (previous->delay_usecs)
857 udelay(previous->delay_usecs);
858 }
859
860 /* Check transfer length */
861 if (transfer->len > 8191)
862 {
863 dev_warn(&drv_data->pdev->dev, "pump_transfers: transfer "
864 "length greater than 8191\n");
865 message->status = -EINVAL;
866 giveback(drv_data);
867 return;
868 }
869
870 /* Setup the transfer state based on the type of transfer */
871 if (flush(drv_data) == 0) {
872 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
873 message->status = -EIO;
874 giveback(drv_data);
875 return;
876 }
877 drv_data->n_bytes = chip->n_bytes;
878 drv_data->dma_width = chip->dma_width;
879 drv_data->cs_control = chip->cs_control;
880 drv_data->tx = (void *)transfer->tx_buf;
881 drv_data->tx_end = drv_data->tx + transfer->len;
882 drv_data->rx = transfer->rx_buf;
883 drv_data->rx_end = drv_data->rx + transfer->len;
884 drv_data->rx_dma = transfer->rx_dma;
885 drv_data->tx_dma = transfer->tx_dma;
886 drv_data->len = transfer->len & DCMD_LENGTH;
887 drv_data->write = drv_data->tx ? chip->write : null_writer;
888 drv_data->read = drv_data->rx ? chip->read : null_reader;
889 drv_data->cs_change = transfer->cs_change;
890
891 /* Change speed and bit per word on a per transfer */
892 cr0 = chip->cr0;
893 if (transfer->speed_hz || transfer->bits_per_word) {
894
895 bits = chip->bits_per_word;
896 speed = chip->speed_hz;
897
898 if (transfer->speed_hz)
899 speed = transfer->speed_hz;
900
901 if (transfer->bits_per_word)
902 bits = transfer->bits_per_word;
903
904 clk_div = ssp_get_clk_div(ssp, speed);
905
906 if (bits <= 8) {
907 drv_data->n_bytes = 1;
908 drv_data->dma_width = DCMD_WIDTH1;
909 drv_data->read = drv_data->read != null_reader ?
910 u8_reader : null_reader;
911 drv_data->write = drv_data->write != null_writer ?
912 u8_writer : null_writer;
913 } else if (bits <= 16) {
914 drv_data->n_bytes = 2;
915 drv_data->dma_width = DCMD_WIDTH2;
916 drv_data->read = drv_data->read != null_reader ?
917 u16_reader : null_reader;
918 drv_data->write = drv_data->write != null_writer ?
919 u16_writer : null_writer;
920 } else if (bits <= 32) {
921 drv_data->n_bytes = 4;
922 drv_data->dma_width = DCMD_WIDTH4;
923 drv_data->read = drv_data->read != null_reader ?
924 u32_reader : null_reader;
925 drv_data->write = drv_data->write != null_writer ?
926 u32_writer : null_writer;
927 }
928 /* if bits/word is changed in dma mode, then must check the
929 * thresholds and burst also */
930 if (chip->enable_dma) {
931 if (set_dma_burst_and_threshold(chip, message->spi,
932 bits, &dma_burst,
933 &dma_thresh))
934 if (printk_ratelimit())
935 dev_warn(&message->spi->dev,
936 "pump_transfer: "
937 "DMA burst size reduced to "
938 "match bits_per_word\n");
939 }
940
941 cr0 = clk_div
942 | SSCR0_Motorola
943 | SSCR0_DataSize(bits > 16 ? bits - 16 : bits)
944 | SSCR0_SSE
945 | (bits > 16 ? SSCR0_EDSS : 0);
946 }
947
948 message->state = RUNNING_STATE;
949
950 /* Try to map dma buffer and do a dma transfer if successful */
951 if ((drv_data->dma_mapped = map_dma_buffers(drv_data))) {
952
953 /* Ensure we have the correct interrupt handler */
954 drv_data->transfer_handler = dma_transfer;
955
956 /* Setup rx DMA Channel */
957 DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
958 DSADR(drv_data->rx_channel) = drv_data->ssdr_physical;
959 DTADR(drv_data->rx_channel) = drv_data->rx_dma;
960 if (drv_data->rx == drv_data->null_dma_buf)
961 /* No target address increment */
962 DCMD(drv_data->rx_channel) = DCMD_FLOWSRC
963 | drv_data->dma_width
964 | dma_burst
965 | drv_data->len;
966 else
967 DCMD(drv_data->rx_channel) = DCMD_INCTRGADDR
968 | DCMD_FLOWSRC
969 | drv_data->dma_width
970 | dma_burst
971 | drv_data->len;
972
973 /* Setup tx DMA Channel */
974 DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
975 DSADR(drv_data->tx_channel) = drv_data->tx_dma;
976 DTADR(drv_data->tx_channel) = drv_data->ssdr_physical;
977 if (drv_data->tx == drv_data->null_dma_buf)
978 /* No source address increment */
979 DCMD(drv_data->tx_channel) = DCMD_FLOWTRG
980 | drv_data->dma_width
981 | dma_burst
982 | drv_data->len;
983 else
984 DCMD(drv_data->tx_channel) = DCMD_INCSRCADDR
985 | DCMD_FLOWTRG
986 | drv_data->dma_width
987 | dma_burst
988 | drv_data->len;
989
990 /* Enable dma end irqs on SSP to detect end of transfer */
991 if (drv_data->ssp_type == PXA25x_SSP)
992 DCMD(drv_data->tx_channel) |= DCMD_ENDIRQEN;
993
994 <<<<<<< HEAD:drivers/spi/pxa2xx_spi.c
995 /* Fix me, need to handle cs polarity */
996 drv_data->cs_control(PXA2XX_CS_ASSERT);
997
998 =======
999 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/spi/pxa2xx_spi.c
1000 /* Clear status and start DMA engine */
1001 cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1;
1002 write_SSSR(drv_data->clear_sr, reg);
1003 DCSR(drv_data->rx_channel) |= DCSR_RUN;
1004 DCSR(drv_data->tx_channel) |= DCSR_RUN;
1005 } else {
1006 /* Ensure we have the correct interrupt handler */
1007 drv_data->transfer_handler = interrupt_transfer;
1008
1009 <<<<<<< HEAD:drivers/spi/pxa2xx_spi.c
1010 /* Fix me, need to handle cs polarity */
1011 drv_data->cs_control(PXA2XX_CS_ASSERT);
1012
1013 =======
1014 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/spi/pxa2xx_spi.c
1015 /* Clear status */
1016 cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1;
1017 write_SSSR(drv_data->clear_sr, reg);
1018 }
1019
1020 /* see if we need to reload the config registers */
1021 if ((read_SSCR0(reg) != cr0)
1022 || (read_SSCR1(reg) & SSCR1_CHANGE_MASK) !=
1023 (cr1 & SSCR1_CHANGE_MASK)) {
1024
1025 <<<<<<< HEAD:drivers/spi/pxa2xx_spi.c
1026 =======
1027 /* stop the SSP, and update the other bits */
1028 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/spi/pxa2xx_spi.c
1029 write_SSCR0(cr0 & ~SSCR0_SSE, reg);
1030 if (drv_data->ssp_type != PXA25x_SSP)
1031 write_SSTO(chip->timeout, reg);
1032 <<<<<<< HEAD:drivers/spi/pxa2xx_spi.c
1033 write_SSCR1(cr1, reg);
1034 =======
1035 /* first set CR1 without interrupt and service enables */
1036 write_SSCR1(cr1 & SSCR1_CHANGE_MASK, reg);
1037 /* restart the SSP */
1038 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/spi/pxa2xx_spi.c
1039 write_SSCR0(cr0, reg);
1040 <<<<<<< HEAD:drivers/spi/pxa2xx_spi.c
1041 =======
1042
1043 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/spi/pxa2xx_spi.c
1044 } else {
1045 if (drv_data->ssp_type != PXA25x_SSP)
1046 write_SSTO(chip->timeout, reg);
1047 <<<<<<< HEAD:drivers/spi/pxa2xx_spi.c
1048 write_SSCR1(cr1, reg);
1049 =======
1050 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/spi/pxa2xx_spi.c
1051 }
1052 <<<<<<< HEAD:drivers/spi/pxa2xx_spi.c
1053 =======
1054
1055 /* FIXME, need to handle cs polarity,
1056 * this driver uses struct pxa2xx_spi_chip.cs_control to
1057 * specify a CS handling function, and it ignores most
1058 * struct spi_device.mode[s], including SPI_CS_HIGH */
1059 drv_data->cs_control(PXA2XX_CS_ASSERT);
1060
1061 /* after chip select, release the data by enabling service
1062 * requests and interrupts, without changing any mode bits */
1063 write_SSCR1(cr1, reg);
1064 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/spi/pxa2xx_spi.c
1065 }
1066
1067 static void pump_messages(struct work_struct *work)
1068 {
1069 struct driver_data *drv_data =
1070 container_of(work, struct driver_data, pump_messages);
1071 unsigned long flags;
1072
1073 /* Lock queue and check for queue work */
1074 spin_lock_irqsave(&drv_data->lock, flags);
1075 if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) {
1076 drv_data->busy = 0;
1077 spin_unlock_irqrestore(&drv_data->lock, flags);
1078 return;
1079 }
1080
1081 /* Make sure we are not already running a message */
1082 if (drv_data->cur_msg) {
1083 spin_unlock_irqrestore(&drv_data->lock, flags);
1084 return;
1085 }
1086
1087 /* Extract head of queue */
1088 drv_data->cur_msg = list_entry(drv_data->queue.next,
1089 struct spi_message, queue);
1090 list_del_init(&drv_data->cur_msg->queue);
1091
1092 /* Initial message state*/
1093 drv_data->cur_msg->state = START_STATE;
1094 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
1095 struct spi_transfer,
1096 transfer_list);
1097
1098 /* prepare to setup the SSP, in pump_transfers, using the per
1099 * chip configuration */
1100 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
1101
1102 /* Mark as busy and launch transfers */
1103 tasklet_schedule(&drv_data->pump_transfers);
1104
1105 drv_data->busy = 1;
1106 spin_unlock_irqrestore(&drv_data->lock, flags);
1107 }
1108
1109 static int transfer(struct spi_device *spi, struct spi_message *msg)
1110 {
1111 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1112 unsigned long flags;
1113
1114 spin_lock_irqsave(&drv_data->lock, flags);
1115
1116 if (drv_data->run == QUEUE_STOPPED) {
1117 spin_unlock_irqrestore(&drv_data->lock, flags);
1118 return -ESHUTDOWN;
1119 }
1120
1121 msg->actual_length = 0;
1122 msg->status = -EINPROGRESS;
1123 msg->state = START_STATE;
1124
1125 list_add_tail(&msg->queue, &drv_data->queue);
1126
1127 if (drv_data->run == QUEUE_RUNNING && !drv_data->busy)
1128 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1129
1130 spin_unlock_irqrestore(&drv_data->lock, flags);
1131
1132 return 0;
1133 }
1134
1135 /* the spi->mode bits understood by this driver: */
1136 #define MODEBITS (SPI_CPOL | SPI_CPHA)
1137
1138 static int setup(struct spi_device *spi)
1139 {
1140 struct pxa2xx_spi_chip *chip_info = NULL;
1141 struct chip_data *chip;
1142 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1143 struct ssp_device *ssp = drv_data->ssp;
1144 unsigned int clk_div;
1145
1146 if (!spi->bits_per_word)
1147 spi->bits_per_word = 8;
1148
1149 if (drv_data->ssp_type != PXA25x_SSP
1150 && (spi->bits_per_word < 4 || spi->bits_per_word > 32)) {
1151 dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d "
1152 "b/w not 4-32 for type non-PXA25x_SSP\n",
1153 drv_data->ssp_type, spi->bits_per_word);
1154 return -EINVAL;
1155 }
1156 else if (drv_data->ssp_type == PXA25x_SSP
1157 && (spi->bits_per_word < 4
1158 || spi->bits_per_word > 16)) {
1159 dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d "
1160 "b/w not 4-16 for type PXA25x_SSP\n",
1161 drv_data->ssp_type, spi->bits_per_word);
1162 return -EINVAL;
1163 }
1164
1165 if (spi->mode & ~MODEBITS) {
1166 dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n",
1167 spi->mode & ~MODEBITS);
1168 return -EINVAL;
1169 }
1170
1171 /* Only alloc on first setup */
1172 chip = spi_get_ctldata(spi);
1173 if (!chip) {
1174 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1175 if (!chip) {
1176 dev_err(&spi->dev,
1177 "failed setup: can't allocate chip data\n");
1178 return -ENOMEM;
1179 }
1180
1181 chip->cs_control = null_cs_control;
1182 chip->enable_dma = 0;
1183 chip->timeout = 1000;
1184 chip->threshold = SSCR1_RxTresh(1) | SSCR1_TxTresh(1);
1185 chip->dma_burst_size = drv_data->master_info->enable_dma ?
1186 DCMD_BURST8 : 0;
1187 }
1188
1189 /* protocol drivers may change the chip settings, so...
1190 * if chip_info exists, use it */
1191 chip_info = spi->controller_data;
1192
1193 /* chip_info isn't always needed */
1194 chip->cr1 = 0;
1195 if (chip_info) {
1196 if (chip_info->cs_control)
1197 chip->cs_control = chip_info->cs_control;
1198
1199 chip->timeout = chip_info->timeout;
1200
1201 chip->threshold = (SSCR1_RxTresh(chip_info->rx_threshold) &
1202 SSCR1_RFT) |
1203 (SSCR1_TxTresh(chip_info->tx_threshold) &
1204 SSCR1_TFT);
1205
1206 chip->enable_dma = chip_info->dma_burst_size != 0
1207 && drv_data->master_info->enable_dma;
1208 chip->dma_threshold = 0;
1209
1210 if (chip_info->enable_loopback)
1211 chip->cr1 = SSCR1_LBM;
1212 }
1213
1214 /* set dma burst and threshold outside of chip_info path so that if
1215 * chip_info goes away after setting chip->enable_dma, the
1216 * burst and threshold can still respond to changes in bits_per_word */
1217 if (chip->enable_dma) {
1218 /* set up legal burst and threshold for dma */
1219 if (set_dma_burst_and_threshold(chip, spi, spi->bits_per_word,
1220 &chip->dma_burst_size,
1221 &chip->dma_threshold)) {
1222 dev_warn(&spi->dev, "in setup: DMA burst size reduced "
1223 "to match bits_per_word\n");
1224 }
1225 }
1226
1227 clk_div = ssp_get_clk_div(ssp, spi->max_speed_hz);
1228 chip->speed_hz = spi->max_speed_hz;
1229
1230 chip->cr0 = clk_div
1231 | SSCR0_Motorola
1232 | SSCR0_DataSize(spi->bits_per_word > 16 ?
1233 spi->bits_per_word - 16 : spi->bits_per_word)
1234 | SSCR0_SSE
1235 | (spi->bits_per_word > 16 ? SSCR0_EDSS : 0);
1236 chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
1237 chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0)
1238 | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0);
1239
1240 /* NOTE: PXA25x_SSP _could_ use external clocking ... */
1241 if (drv_data->ssp_type != PXA25x_SSP)
1242 dev_dbg(&spi->dev, "%d bits/word, %ld Hz, mode %d\n",
1243 spi->bits_per_word,
1244 clk_get_rate(ssp->clk)
1245 / (1 + ((chip->cr0 & SSCR0_SCR) >> 8)),
1246 spi->mode & 0x3);
1247 else
1248 dev_dbg(&spi->dev, "%d bits/word, %ld Hz, mode %d\n",
1249 spi->bits_per_word,
1250 clk_get_rate(ssp->clk)
1251 / (1 + ((chip->cr0 & SSCR0_SCR) >> 8)),
1252 spi->mode & 0x3);
1253
1254 if (spi->bits_per_word <= 8) {
1255 chip->n_bytes = 1;
1256 chip->dma_width = DCMD_WIDTH1;
1257 chip->read = u8_reader;
1258 chip->write = u8_writer;
1259 } else if (spi->bits_per_word <= 16) {
1260 chip->n_bytes = 2;
1261 chip->dma_width = DCMD_WIDTH2;
1262 chip->read = u16_reader;
1263 chip->write = u16_writer;
1264 } else if (spi->bits_per_word <= 32) {
1265 chip->cr0 |= SSCR0_EDSS;
1266 chip->n_bytes = 4;
1267 chip->dma_width = DCMD_WIDTH4;
1268 chip->read = u32_reader;
1269 chip->write = u32_writer;
1270 } else {
1271 dev_err(&spi->dev, "invalid wordsize\n");
1272 return -ENODEV;
1273 }
1274 chip->bits_per_word = spi->bits_per_word;
1275
1276 spi_set_ctldata(spi, chip);
1277
1278 return 0;
1279 }
1280
1281 static void cleanup(struct spi_device *spi)
1282 {
1283 struct chip_data *chip = spi_get_ctldata(spi);
1284
1285 kfree(chip);
1286 }
1287
1288 static int __init init_queue(struct driver_data *drv_data)
1289 {
1290 INIT_LIST_HEAD(&drv_data->queue);
1291 spin_lock_init(&drv_data->lock);
1292
1293 drv_data->run = QUEUE_STOPPED;
1294 drv_data->busy = 0;
1295
1296 tasklet_init(&drv_data->pump_transfers,
1297 pump_transfers, (unsigned long)drv_data);
1298
1299 INIT_WORK(&drv_data->pump_messages, pump_messages);
1300 drv_data->workqueue = create_singlethread_workqueue(
1301 drv_data->master->dev.parent->bus_id);
1302 if (drv_data->workqueue == NULL)
1303 return -EBUSY;
1304
1305 return 0;
1306 }
1307
1308 static int start_queue(struct driver_data *drv_data)
1309 {
1310 unsigned long flags;
1311
1312 spin_lock_irqsave(&drv_data->lock, flags);
1313
1314 if (drv_data->run == QUEUE_RUNNING || drv_data->busy) {
1315 spin_unlock_irqrestore(&drv_data->lock, flags);
1316 return -EBUSY;
1317 }
1318
1319 drv_data->run = QUEUE_RUNNING;
1320 drv_data->cur_msg = NULL;
1321 drv_data->cur_transfer = NULL;
1322 drv_data->cur_chip = NULL;
1323 spin_unlock_irqrestore(&drv_data->lock, flags);
1324
1325 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1326
1327 return 0;
1328 }
1329
1330 static int stop_queue(struct driver_data *drv_data)
1331 {
1332 unsigned long flags;
1333 unsigned limit = 500;
1334 int status = 0;
1335
1336 spin_lock_irqsave(&drv_data->lock, flags);
1337
1338 /* This is a bit lame, but is optimized for the common execution path.
1339 * A wait_queue on the drv_data->busy could be used, but then the common
1340 * execution path (pump_messages) would be required to call wake_up or
1341 * friends on every SPI message. Do this instead */
1342 drv_data->run = QUEUE_STOPPED;
1343 while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) {
1344 spin_unlock_irqrestore(&drv_data->lock, flags);
1345 msleep(10);
1346 spin_lock_irqsave(&drv_data->lock, flags);
1347 }
1348
1349 if (!list_empty(&drv_data->queue) || drv_data->busy)
1350 status = -EBUSY;
1351
1352 spin_unlock_irqrestore(&drv_data->lock, flags);
1353
1354 return status;
1355 }
1356
1357 static int destroy_queue(struct driver_data *drv_data)
1358 {
1359 int status;
1360
1361 status = stop_queue(drv_data);
1362 /* we are unloading the module or failing to load (only two calls
1363 * to this routine), and neither call can handle a return value.
1364 * However, destroy_workqueue calls flush_workqueue, and that will
1365 * block until all work is done. If the reason that stop_queue
1366 * timed out is that the work will never finish, then it does no
1367 * good to call destroy_workqueue, so return anyway. */
1368 if (status != 0)
1369 return status;
1370
1371 destroy_workqueue(drv_data->workqueue);
1372
1373 return 0;
1374 }
1375
1376 static int __init pxa2xx_spi_probe(struct platform_device *pdev)
1377 {
1378 struct device *dev = &pdev->dev;
1379 struct pxa2xx_spi_master *platform_info;
1380 struct spi_master *master;
1381 struct driver_data *drv_data = 0;
1382 struct ssp_device *ssp;
1383 int status = 0;
1384
1385 platform_info = dev->platform_data;
1386
1387 ssp = ssp_request(pdev->id, pdev->name);
1388 if (ssp == NULL) {
1389 dev_err(&pdev->dev, "failed to request SSP%d\n", pdev->id);
1390 return -ENODEV;
1391 }
1392
1393 /* Allocate master with space for drv_data and null dma buffer */
1394 master = spi_alloc_master(dev, sizeof(struct driver_data) + 16);
1395 if (!master) {
1396 dev_err(&pdev->dev, "can not alloc spi_master\n");
1397 ssp_free(ssp);
1398 return -ENOMEM;
1399 }
1400 drv_data = spi_master_get_devdata(master);
1401 drv_data->master = master;
1402 drv_data->master_info = platform_info;
1403 drv_data->pdev = pdev;
1404 drv_data->ssp = ssp;
1405
1406 master->bus_num = pdev->id;
1407 master->num_chipselect = platform_info->num_chipselect;
1408 master->cleanup = cleanup;
1409 master->setup = setup;
1410 master->transfer = transfer;
1411
1412 drv_data->ssp_type = ssp->type;
1413 drv_data->null_dma_buf = (u32 *)ALIGN((u32)(drv_data +
1414 sizeof(struct driver_data)), 8);
1415
1416 drv_data->ioaddr = ssp->mmio_base;
1417 drv_data->ssdr_physical = ssp->phys_base + SSDR;
1418 if (ssp->type == PXA25x_SSP) {
1419 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
1420 drv_data->dma_cr1 = 0;
1421 drv_data->clear_sr = SSSR_ROR;
1422 drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR;
1423 } else {
1424 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
1425 drv_data->dma_cr1 = SSCR1_TSRE | SSCR1_RSRE | SSCR1_TINTE;
1426 drv_data->clear_sr = SSSR_ROR | SSSR_TINT;
1427 drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR;
1428 }
1429
1430 status = request_irq(ssp->irq, ssp_int, 0, dev->bus_id, drv_data);
1431 if (status < 0) {
1432 dev_err(&pdev->dev, "can not get IRQ\n");
1433 goto out_error_master_alloc;
1434 }
1435
1436 /* Setup DMA if requested */
1437 drv_data->tx_channel = -1;
1438 drv_data->rx_channel = -1;
1439 if (platform_info->enable_dma) {
1440
1441 /* Get two DMA channels (rx and tx) */
1442 drv_data->rx_channel = pxa_request_dma("pxa2xx_spi_ssp_rx",
1443 DMA_PRIO_HIGH,
1444 dma_handler,
1445 drv_data);
1446 if (drv_data->rx_channel < 0) {
1447 dev_err(dev, "problem (%d) requesting rx channel\n",
1448 drv_data->rx_channel);
1449 status = -ENODEV;
1450 goto out_error_irq_alloc;
1451 }
1452 drv_data->tx_channel = pxa_request_dma("pxa2xx_spi_ssp_tx",
1453 DMA_PRIO_MEDIUM,
1454 dma_handler,
1455 drv_data);
1456 if (drv_data->tx_channel < 0) {
1457 dev_err(dev, "problem (%d) requesting tx channel\n",
1458 drv_data->tx_channel);
1459 status = -ENODEV;
1460 goto out_error_dma_alloc;
1461 }
1462
1463 DRCMR(ssp->drcmr_rx) = DRCMR_MAPVLD | drv_data->rx_channel;
1464 DRCMR(ssp->drcmr_tx) = DRCMR_MAPVLD | drv_data->tx_channel;
1465 }
1466
1467 /* Enable SOC clock */
1468 clk_enable(ssp->clk);
1469
1470 /* Load default SSP configuration */
1471 write_SSCR0(0, drv_data->ioaddr);
1472 write_SSCR1(SSCR1_RxTresh(4) | SSCR1_TxTresh(12), drv_data->ioaddr);
1473 write_SSCR0(SSCR0_SerClkDiv(2)
1474 | SSCR0_Motorola
1475 | SSCR0_DataSize(8),
1476 drv_data->ioaddr);
1477 if (drv_data->ssp_type != PXA25x_SSP)
1478 write_SSTO(0, drv_data->ioaddr);
1479 write_SSPSP(0, drv_data->ioaddr);
1480
1481 /* Initial and start queue */
1482 status = init_queue(drv_data);
1483 if (status != 0) {
1484 dev_err(&pdev->dev, "problem initializing queue\n");
1485 goto out_error_clock_enabled;
1486 }
1487 status = start_queue(drv_data);
1488 if (status != 0) {
1489 dev_err(&pdev->dev, "problem starting queue\n");
1490 goto out_error_clock_enabled;
1491 }
1492
1493 /* Register with the SPI framework */
1494 platform_set_drvdata(pdev, drv_data);
1495 status = spi_register_master(master);
1496 if (status != 0) {
1497 dev_err(&pdev->dev, "problem registering spi master\n");
1498 goto out_error_queue_alloc;
1499 }
1500
1501 return status;
1502
1503 out_error_queue_alloc:
1504 destroy_queue(drv_data);
1505
1506 out_error_clock_enabled:
1507 clk_disable(ssp->clk);
1508
1509 out_error_dma_alloc:
1510 if (drv_data->tx_channel != -1)
1511 pxa_free_dma(drv_data->tx_channel);
1512 if (drv_data->rx_channel != -1)
1513 pxa_free_dma(drv_data->rx_channel);
1514
1515 out_error_irq_alloc:
1516 free_irq(ssp->irq, drv_data);
1517
1518 out_error_master_alloc:
1519 spi_master_put(master);
1520 ssp_free(ssp);
1521 return status;
1522 }
1523
1524 static int pxa2xx_spi_remove(struct platform_device *pdev)
1525 {
1526 struct driver_data *drv_data = platform_get_drvdata(pdev);
1527 struct ssp_device *ssp = drv_data->ssp;
1528 int status = 0;
1529
1530 if (!drv_data)
1531 return 0;
1532
1533 /* Remove the queue */
1534 status = destroy_queue(drv_data);
1535 if (status != 0)
1536 /* the kernel does not check the return status of this
1537 * this routine (mod->exit, within the kernel). Therefore
1538 * nothing is gained by returning from here, the module is
1539 * going away regardless, and we should not leave any more
1540 * resources allocated than necessary. We cannot free the
1541 * message memory in drv_data->queue, but we can release the
1542 * resources below. I think the kernel should honor -EBUSY
1543 * returns but... */
1544 dev_err(&pdev->dev, "pxa2xx_spi_remove: workqueue will not "
1545 "complete, message memory not freed\n");
1546
1547 /* Disable the SSP at the peripheral and SOC level */
1548 write_SSCR0(0, drv_data->ioaddr);
1549 clk_disable(ssp->clk);
1550
1551 /* Release DMA */
1552 if (drv_data->master_info->enable_dma) {
1553 DRCMR(ssp->drcmr_rx) = 0;
1554 DRCMR(ssp->drcmr_tx) = 0;
1555 pxa_free_dma(drv_data->tx_channel);
1556 pxa_free_dma(drv_data->rx_channel);
1557 }
1558
1559 /* Release IRQ */
1560 free_irq(ssp->irq, drv_data);
1561
1562 /* Release SSP */
1563 ssp_free(ssp);
1564
1565 /* Disconnect from the SPI framework */
1566 spi_unregister_master(drv_data->master);
1567
1568 /* Prevent double remove */
1569 platform_set_drvdata(pdev, NULL);
1570
1571 return 0;
1572 }
1573
1574 static void pxa2xx_spi_shutdown(struct platform_device *pdev)
1575 {
1576 int status = 0;
1577
1578 if ((status = pxa2xx_spi_remove(pdev)) != 0)
1579 dev_err(&pdev->dev, "shutdown failed with %d\n", status);
1580 }
1581
1582 #ifdef CONFIG_PM
1583
1584 static int pxa2xx_spi_suspend(struct platform_device *pdev, pm_message_t state)
1585 {
1586 struct driver_data *drv_data = platform_get_drvdata(pdev);
1587 struct ssp_device *ssp = drv_data->ssp;
1588 int status = 0;
1589
1590 status = stop_queue(drv_data);
1591 if (status != 0)
1592 return status;
1593 write_SSCR0(0, drv_data->ioaddr);
1594 clk_disable(ssp->clk);
1595
1596 return 0;
1597 }
1598
1599 static int pxa2xx_spi_resume(struct platform_device *pdev)
1600 {
1601 struct driver_data *drv_data = platform_get_drvdata(pdev);
1602 struct ssp_device *ssp = drv_data->ssp;
1603 int status = 0;
1604
1605 /* Enable the SSP clock */
1606 clk_disable(ssp->clk);
1607
1608 /* Start the queue running */
1609 status = start_queue(drv_data);
1610 if (status != 0) {
1611 dev_err(&pdev->dev, "problem starting queue (%d)\n", status);
1612 return status;
1613 }
1614
1615 return 0;
1616 }
1617 #else
1618 #define pxa2xx_spi_suspend NULL
1619 #define pxa2xx_spi_resume NULL
1620 #endif /* CONFIG_PM */
1621
1622 static struct platform_driver driver = {
1623 .driver = {
1624 .name = "pxa2xx-spi",
1625 .bus = &platform_bus_type,
1626 .owner = THIS_MODULE,
1627 },
1628 .remove = pxa2xx_spi_remove,
1629 .shutdown = pxa2xx_spi_shutdown,
1630 .suspend = pxa2xx_spi_suspend,
1631 .resume = pxa2xx_spi_resume,
1632 };
1633
1634 static int __init pxa2xx_spi_init(void)
1635 {
1636 return platform_driver_probe(&driver, pxa2xx_spi_probe);
1637 }
1638 module_init(pxa2xx_spi_init);
1639
1640 static void __exit pxa2xx_spi_exit(void)
1641 {
1642 platform_driver_unregister(&driver);
1643 }
1644 module_exit(pxa2xx_spi_exit);
WRT350N Kernel Patches