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Merge git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
[wrt350n-kernel.git] / drivers / ssb / driver_pcicore.c
blobb899776963610451431fc42e7c929e253972465b
1 /*
2 * Sonics Silicon Backplane
3 * Broadcom PCI-core driver
4 *
5 * Copyright 2005, Broadcom Corporation
6 * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
7 *
8 * Licensed under the GNU/GPL. See COPYING for details.
9 */
10
11 #include <linux/ssb/ssb.h>
12 #include <linux/pci.h>
13 #include <linux/delay.h>
14 <<<<<<< HEAD:drivers/ssb/driver_pcicore.c
15 =======
16 #include <linux/ssb/ssb_embedded.h>
17 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/ssb/driver_pcicore.c
18
19 #include "ssb_private.h"
20
21
22 static inline
23 u32 pcicore_read32(struct ssb_pcicore *pc, u16 offset)
24 {
25 return ssb_read32(pc->dev, offset);
26 }
27
28 static inline
29 void pcicore_write32(struct ssb_pcicore *pc, u16 offset, u32 value)
30 {
31 ssb_write32(pc->dev, offset, value);
32 }
33
34 <<<<<<< HEAD:drivers/ssb/driver_pcicore.c
35 =======
36 static inline
37 u16 pcicore_read16(struct ssb_pcicore *pc, u16 offset)
38 {
39 return ssb_read16(pc->dev, offset);
40 }
41
42 static inline
43 void pcicore_write16(struct ssb_pcicore *pc, u16 offset, u16 value)
44 {
45 ssb_write16(pc->dev, offset, value);
46 }
47
48 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/ssb/driver_pcicore.c
49 /**************************************************
50 * Code for hostmode operation.
51 **************************************************/
52
53 #ifdef CONFIG_SSB_PCICORE_HOSTMODE
54
55 #include <asm/paccess.h>
56 /* Probe a 32bit value on the bus and catch bus exceptions.
57 * Returns nonzero on a bus exception.
58 * This is MIPS specific */
59 #define mips_busprobe32(val, addr) get_dbe((val), ((u32 *)(addr)))
60
61 /* Assume one-hot slot wiring */
62 #define SSB_PCI_SLOT_MAX 16
63
64 /* Global lock is OK, as we won't have more than one extpci anyway. */
65 static DEFINE_SPINLOCK(cfgspace_lock);
66 /* Core to access the external PCI config space. Can only have one. */
67 static struct ssb_pcicore *extpci_core;
68
69 static u32 ssb_pcicore_pcibus_iobase = 0x100;
70 static u32 ssb_pcicore_pcibus_membase = SSB_PCI_DMA;
71
72 int pcibios_plat_dev_init(struct pci_dev *d)
73 {
74 struct resource *res;
75 int pos, size;
76 u32 *base;
77
78 ssb_printk(KERN_INFO "PCI: Fixing up device %s\n",
79 pci_name(d));
80
81 /* Fix up resource bases */
82 for (pos = 0; pos < 6; pos++) {
83 res = &d->resource[pos];
84 if (res->flags & IORESOURCE_IO)
85 base = &ssb_pcicore_pcibus_iobase;
86 else
87 base = &ssb_pcicore_pcibus_membase;
88 <<<<<<< HEAD:drivers/ssb/driver_pcicore.c
89 =======
90 res->flags |= IORESOURCE_PCI_FIXED;
91 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/ssb/driver_pcicore.c
92 if (res->end) {
93 size = res->end - res->start + 1;
94 if (*base & (size - 1))
95 *base = (*base + size) & ~(size - 1);
96 res->start = *base;
97 res->end = res->start + size - 1;
98 *base += size;
99 pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
100 }
101 /* Fix up PCI bridge BAR0 only */
102 if (d->bus->number == 0 && PCI_SLOT(d->devfn) == 0)
103 break;
104 }
105 /* Fix up interrupt lines */
106 d->irq = ssb_mips_irq(extpci_core->dev) + 2;
107 pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
108
109 return 0;
110 }
111
112 static void __init ssb_fixup_pcibridge(struct pci_dev *dev)
113 {
114 <<<<<<< HEAD:drivers/ssb/driver_pcicore.c
115 =======
116 u8 lat;
117
118 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/ssb/driver_pcicore.c
119 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) != 0)
120 return;
121
122 <<<<<<< HEAD:drivers/ssb/driver_pcicore.c
123 ssb_printk(KERN_INFO "PCI: fixing up bridge\n");
124 =======
125 ssb_printk(KERN_INFO "PCI: Fixing up bridge %s\n", pci_name(dev));
126 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/ssb/driver_pcicore.c
127
128 /* Enable PCI bridge bus mastering and memory space */
129 pci_set_master(dev);
130 <<<<<<< HEAD:drivers/ssb/driver_pcicore.c
131 pcibios_enable_device(dev, ~0);
132 =======
133 if (pcibios_enable_device(dev, ~0) < 0) {
134 ssb_printk(KERN_ERR "PCI: SSB bridge enable failed\n");
135 return;
136 }
137 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/ssb/driver_pcicore.c
138
139 /* Enable PCI bridge BAR1 prefetch and burst */
140 pci_write_config_dword(dev, SSB_BAR1_CONTROL, 3);
141
142 /* Make sure our latency is high enough to handle the devices behind us */
143 <<<<<<< HEAD:drivers/ssb/driver_pcicore.c
144 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xa8);
145 =======
146 lat = 168;
147 ssb_printk(KERN_INFO "PCI: Fixing latency timer of device %s to %u\n",
148 pci_name(dev), lat);
149 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
150 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/ssb/driver_pcicore.c
151 }
152 DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ssb_fixup_pcibridge);
153
154 int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
155 {
156 return ssb_mips_irq(extpci_core->dev) + 2;
157 }
158
159 static u32 get_cfgspace_addr(struct ssb_pcicore *pc,
160 unsigned int bus, unsigned int dev,
161 unsigned int func, unsigned int off)
162 {
163 u32 addr = 0;
164 u32 tmp;
165
166 <<<<<<< HEAD:drivers/ssb/driver_pcicore.c
167 if (unlikely(pc->cardbusmode && dev > 1))
168 =======
169 /* We do only have one cardbus device behind the bridge. */
170 if (pc->cardbusmode && (dev >= 1))
171 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/ssb/driver_pcicore.c
172 goto out;
173 <<<<<<< HEAD:drivers/ssb/driver_pcicore.c
174 =======
175
176 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/ssb/driver_pcicore.c
177 if (bus == 0) {
178 /* Type 0 transaction */
179 if (unlikely(dev >= SSB_PCI_SLOT_MAX))
180 goto out;
181 /* Slide the window */
182 tmp = SSB_PCICORE_SBTOPCI_CFG0;
183 tmp |= ((1 << (dev + 16)) & SSB_PCICORE_SBTOPCI1_MASK);
184 pcicore_write32(pc, SSB_PCICORE_SBTOPCI1, tmp);
185 /* Calculate the address */
186 addr = SSB_PCI_CFG;
187 addr |= ((1 << (dev + 16)) & ~SSB_PCICORE_SBTOPCI1_MASK);
188 addr |= (func << 8);
189 addr |= (off & ~3);
190 } else {
191 /* Type 1 transaction */
192 pcicore_write32(pc, SSB_PCICORE_SBTOPCI1,
193 SSB_PCICORE_SBTOPCI_CFG1);
194 /* Calculate the address */
195 addr = SSB_PCI_CFG;
196 addr |= (bus << 16);
197 addr |= (dev << 11);
198 addr |= (func << 8);
199 addr |= (off & ~3);
200 }
201 out:
202 return addr;
203 }
204
205 static int ssb_extpci_read_config(struct ssb_pcicore *pc,
206 unsigned int bus, unsigned int dev,
207 unsigned int func, unsigned int off,
208 void *buf, int len)
209 {
210 int err = -EINVAL;
211 u32 addr, val;
212 void __iomem *mmio;
213
214 SSB_WARN_ON(!pc->hostmode);
215 if (unlikely(len != 1 && len != 2 && len != 4))
216 goto out;
217 addr = get_cfgspace_addr(pc, bus, dev, func, off);
218 if (unlikely(!addr))
219 goto out;
220 err = -ENOMEM;
221 mmio = ioremap_nocache(addr, len);
222 if (!mmio)
223 goto out;
224
225 if (mips_busprobe32(val, mmio)) {
226 val = 0xffffffff;
227 goto unmap;
228 }
229
230 val = readl(mmio);
231 val >>= (8 * (off & 3));
232
233 switch (len) {
234 case 1:
235 *((u8 *)buf) = (u8)val;
236 break;
237 case 2:
238 *((u16 *)buf) = (u16)val;
239 break;
240 case 4:
241 *((u32 *)buf) = (u32)val;
242 break;
243 }
244 err = 0;
245 unmap:
246 iounmap(mmio);
247 out:
248 return err;
249 }
250
251 static int ssb_extpci_write_config(struct ssb_pcicore *pc,
252 unsigned int bus, unsigned int dev,
253 unsigned int func, unsigned int off,
254 const void *buf, int len)
255 {
256 int err = -EINVAL;
257 u32 addr, val = 0;
258 void __iomem *mmio;
259
260 SSB_WARN_ON(!pc->hostmode);
261 if (unlikely(len != 1 && len != 2 && len != 4))
262 goto out;
263 addr = get_cfgspace_addr(pc, bus, dev, func, off);
264 if (unlikely(!addr))
265 goto out;
266 err = -ENOMEM;
267 mmio = ioremap_nocache(addr, len);
268 if (!mmio)
269 goto out;
270
271 if (mips_busprobe32(val, mmio)) {
272 val = 0xffffffff;
273 goto unmap;
274 }
275
276 switch (len) {
277 case 1:
278 val = readl(mmio);
279 val &= ~(0xFF << (8 * (off & 3)));
280 val |= *((const u8 *)buf) << (8 * (off & 3));
281 break;
282 case 2:
283 val = readl(mmio);
284 val &= ~(0xFFFF << (8 * (off & 3)));
285 val |= *((const u16 *)buf) << (8 * (off & 3));
286 break;
287 case 4:
288 val = *((const u32 *)buf);
289 break;
290 }
291 writel(val, mmio);
292
293 err = 0;
294 unmap:
295 iounmap(mmio);
296 out:
297 return err;
298 }
299
300 static int ssb_pcicore_read_config(struct pci_bus *bus, unsigned int devfn,
301 int reg, int size, u32 *val)
302 {
303 unsigned long flags;
304 int err;
305
306 spin_lock_irqsave(&cfgspace_lock, flags);
307 err = ssb_extpci_read_config(extpci_core, bus->number, PCI_SLOT(devfn),
308 PCI_FUNC(devfn), reg, val, size);
309 spin_unlock_irqrestore(&cfgspace_lock, flags);
310
311 return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
312 }
313
314 static int ssb_pcicore_write_config(struct pci_bus *bus, unsigned int devfn,
315 int reg, int size, u32 val)
316 {
317 unsigned long flags;
318 int err;
319
320 spin_lock_irqsave(&cfgspace_lock, flags);
321 err = ssb_extpci_write_config(extpci_core, bus->number, PCI_SLOT(devfn),
322 PCI_FUNC(devfn), reg, &val, size);
323 spin_unlock_irqrestore(&cfgspace_lock, flags);
324
325 return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
326 }
327
328 static struct pci_ops ssb_pcicore_pciops = {
329 .read = ssb_pcicore_read_config,
330 .write = ssb_pcicore_write_config,
331 };
332
333 static struct resource ssb_pcicore_mem_resource = {
334 .name = "SSB PCIcore external memory",
335 .start = SSB_PCI_DMA,
336 .end = SSB_PCI_DMA + SSB_PCI_DMA_SZ - 1,
337 <<<<<<< HEAD:drivers/ssb/driver_pcicore.c
338 .flags = IORESOURCE_MEM,
339 =======
340 .flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED,
341 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/ssb/driver_pcicore.c
342 };
343
344 static struct resource ssb_pcicore_io_resource = {
345 .name = "SSB PCIcore external I/O",
346 .start = 0x100,
347 .end = 0x7FF,
348 <<<<<<< HEAD:drivers/ssb/driver_pcicore.c
349 .flags = IORESOURCE_IO,
350 =======
351 .flags = IORESOURCE_IO | IORESOURCE_PCI_FIXED,
352 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/ssb/driver_pcicore.c
353 };
354
355 static struct pci_controller ssb_pcicore_controller = {
356 .pci_ops = &ssb_pcicore_pciops,
357 .io_resource = &ssb_pcicore_io_resource,
358 .mem_resource = &ssb_pcicore_mem_resource,
359 .mem_offset = 0x24000000,
360 };
361
362 static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
363 {
364 u32 val;
365
366 if (WARN_ON(extpci_core))
367 return;
368 extpci_core = pc;
369
370 ssb_dprintk(KERN_INFO PFX "PCIcore in host mode found\n");
371 /* Reset devices on the external PCI bus */
372 val = SSB_PCICORE_CTL_RST_OE;
373 val |= SSB_PCICORE_CTL_CLK_OE;
374 pcicore_write32(pc, SSB_PCICORE_CTL, val);
375 val |= SSB_PCICORE_CTL_CLK; /* Clock on */
376 pcicore_write32(pc, SSB_PCICORE_CTL, val);
377 udelay(150); /* Assertion time demanded by the PCI standard */
378 val |= SSB_PCICORE_CTL_RST; /* Deassert RST# */
379 pcicore_write32(pc, SSB_PCICORE_CTL, val);
380 val = SSB_PCICORE_ARBCTL_INTERN;
381 pcicore_write32(pc, SSB_PCICORE_ARBCTL, val);
382 udelay(1); /* Assertion time demanded by the PCI standard */
383
384 <<<<<<< HEAD:drivers/ssb/driver_pcicore.c
385 /*TODO cardbus mode */
386 =======
387 if (pc->dev->bus->has_cardbus_slot) {
388 ssb_dprintk(KERN_INFO PFX "CardBus slot detected\n");
389 pc->cardbusmode = 1;
390 /* GPIO 1 resets the bridge */
391 ssb_gpio_out(pc->dev->bus, 1, 1);
392 ssb_gpio_outen(pc->dev->bus, 1, 1);
393 pcicore_write16(pc, SSB_PCICORE_SPROM(0),
394 pcicore_read16(pc, SSB_PCICORE_SPROM(0))
395 | 0x0400);
396 }
397 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/ssb/driver_pcicore.c
398
399 /* 64MB I/O window */
400 pcicore_write32(pc, SSB_PCICORE_SBTOPCI0,
401 SSB_PCICORE_SBTOPCI_IO);
402 /* 64MB config space */
403 pcicore_write32(pc, SSB_PCICORE_SBTOPCI1,
404 SSB_PCICORE_SBTOPCI_CFG0);
405 /* 1GB memory window */
406 pcicore_write32(pc, SSB_PCICORE_SBTOPCI2,
407 SSB_PCICORE_SBTOPCI_MEM | SSB_PCI_DMA);
408
409 /* Enable PCI bridge BAR0 prefetch and burst */
410 val = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
411 ssb_extpci_write_config(pc, 0, 0, 0, PCI_COMMAND, &val, 2);
412 /* Clear error conditions */
413 val = 0;
414 ssb_extpci_write_config(pc, 0, 0, 0, PCI_STATUS, &val, 2);
415
416 /* Enable PCI interrupts */
417 pcicore_write32(pc, SSB_PCICORE_IMASK,
418 SSB_PCICORE_IMASK_INTA);
419
420 /* Ok, ready to run, register it to the system.
421 * The following needs change, if we want to port hostmode
422 * to non-MIPS platform. */
423 <<<<<<< HEAD:drivers/ssb/driver_pcicore.c
424 set_io_port_base((unsigned long)ioremap_nocache(SSB_PCI_MEM, 0x04000000));
425 =======
426 ssb_pcicore_controller.io_map_base = (unsigned long)ioremap_nocache(SSB_PCI_MEM, 0x04000000);
427 set_io_port_base(ssb_pcicore_controller.io_map_base);
428 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/ssb/driver_pcicore.c
429 /* Give some time to the PCI controller to configure itself with the new
430 * values. Not waiting at this point causes crashes of the machine. */
431 mdelay(10);
432 register_pci_controller(&ssb_pcicore_controller);
433 }
434
435 static int pcicore_is_in_hostmode(struct ssb_pcicore *pc)
436 {
437 struct ssb_bus *bus = pc->dev->bus;
438 u16 chipid_top;
439 u32 tmp;
440
441 chipid_top = (bus->chip_id & 0xFF00);
442 if (chipid_top != 0x4700 &&
443 chipid_top != 0x5300)
444 return 0;
445
446 <<<<<<< HEAD:drivers/ssb/driver_pcicore.c
447 if (bus->sprom.r1.boardflags_lo & SSB_PCICORE_BFL_NOPCI)
448 =======
449 if (bus->sprom.boardflags_lo & SSB_PCICORE_BFL_NOPCI)
450 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/ssb/driver_pcicore.c
451 return 0;
452
453 /* The 200-pin BCM4712 package does not bond out PCI. Even when
454 * PCI is bonded out, some boards may leave the pins floating. */
455 if (bus->chip_id == 0x4712) {
456 if (bus->chip_package == SSB_CHIPPACK_BCM4712S)
457 return 0;
458 if (bus->chip_package == SSB_CHIPPACK_BCM4712M)
459 return 0;
460 }
461 if (bus->chip_id == 0x5350)
462 return 0;
463
464 return !mips_busprobe32(tmp, (bus->mmio + (pc->dev->core_index * SSB_CORE_SIZE)));
465 }
466 #endif /* CONFIG_SSB_PCICORE_HOSTMODE */
467
468
469 /**************************************************
470 * Generic and Clientmode operation code.
471 **************************************************/
472
473 static void ssb_pcicore_init_clientmode(struct ssb_pcicore *pc)
474 {
475 /* Disable PCI interrupts. */
476 ssb_write32(pc->dev, SSB_INTVEC, 0);
477 }
478
479 void ssb_pcicore_init(struct ssb_pcicore *pc)
480 {
481 struct ssb_device *dev = pc->dev;
482 struct ssb_bus *bus;
483
484 if (!dev)
485 return;
486 bus = dev->bus;
487 if (!ssb_device_is_enabled(dev))
488 ssb_device_enable(dev, 0);
489
490 #ifdef CONFIG_SSB_PCICORE_HOSTMODE
491 pc->hostmode = pcicore_is_in_hostmode(pc);
492 if (pc->hostmode)
493 ssb_pcicore_init_hostmode(pc);
494 #endif /* CONFIG_SSB_PCICORE_HOSTMODE */
495 if (!pc->hostmode)
496 ssb_pcicore_init_clientmode(pc);
497 }
498
499 static u32 ssb_pcie_read(struct ssb_pcicore *pc, u32 address)
500 {
501 pcicore_write32(pc, 0x130, address);
502 return pcicore_read32(pc, 0x134);
503 }
504
505 static void ssb_pcie_write(struct ssb_pcicore *pc, u32 address, u32 data)
506 {
507 pcicore_write32(pc, 0x130, address);
508 pcicore_write32(pc, 0x134, data);
509 }
510
511 static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
512 u8 address, u16 data)
513 {
514 const u16 mdio_control = 0x128;
515 const u16 mdio_data = 0x12C;
516 u32 v;
517 int i;
518
519 v = 0x80; /* Enable Preamble Sequence */
520 v |= 0x2; /* MDIO Clock Divisor */
521 pcicore_write32(pc, mdio_control, v);
522
523 v = (1 << 30); /* Start of Transaction */
524 v |= (1 << 28); /* Write Transaction */
525 v |= (1 << 17); /* Turnaround */
526 v |= (u32)device << 22;
527 v |= (u32)address << 18;
528 v |= data;
529 pcicore_write32(pc, mdio_data, v);
530 /* Wait for the device to complete the transaction */
531 udelay(10);
532 for (i = 0; i < 10; i++) {
533 v = pcicore_read32(pc, mdio_control);
534 if (v & 0x100 /* Trans complete */)
535 break;
536 msleep(1);
537 }
538 pcicore_write32(pc, mdio_control, 0);
539 }
540
541 static void ssb_broadcast_value(struct ssb_device *dev,
542 u32 address, u32 data)
543 {
544 /* This is used for both, PCI and ChipCommon core, so be careful. */
545 BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
546 BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
547
548 ssb_write32(dev, SSB_PCICORE_BCAST_ADDR, address);
549 ssb_read32(dev, SSB_PCICORE_BCAST_ADDR); /* flush */
550 ssb_write32(dev, SSB_PCICORE_BCAST_DATA, data);
551 ssb_read32(dev, SSB_PCICORE_BCAST_DATA); /* flush */
552 }
553
554 static void ssb_commit_settings(struct ssb_bus *bus)
555 {
556 struct ssb_device *dev;
557
558 dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
559 if (WARN_ON(!dev))
560 return;
561 /* This forces an update of the cached registers. */
562 ssb_broadcast_value(dev, 0xFD8, 0);
563 }
564
565 int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
566 struct ssb_device *dev)
567 {
568 struct ssb_device *pdev = pc->dev;
569 struct ssb_bus *bus;
570 int err = 0;
571 u32 tmp;
572
573 might_sleep();
574
575 if (!pdev)
576 goto out;
577 bus = pdev->bus;
578
579 /* Enable interrupts for this device. */
580 if (bus->host_pci &&
581 ((pdev->id.revision >= 6) || (pdev->id.coreid == SSB_DEV_PCIE))) {
582 u32 coremask;
583
584 /* Calculate the "coremask" for the device. */
585 coremask = (1 << dev->core_index);
586
587 err = pci_read_config_dword(bus->host_pci, SSB_PCI_IRQMASK, &tmp);
588 if (err)
589 goto out;
590 tmp |= coremask << 8;
591 err = pci_write_config_dword(bus->host_pci, SSB_PCI_IRQMASK, tmp);
592 if (err)
593 goto out;
594 } else {
595 u32 intvec;
596
597 intvec = ssb_read32(pdev, SSB_INTVEC);
598 if ((bus->chip_id & 0xFF00) == 0x4400) {
599 /* Workaround: On the BCM44XX the BPFLAG routing
600 * bit is wrong. Use a hardcoded constant. */
601 intvec |= 0x00000002;
602 } else {
603 tmp = ssb_read32(dev, SSB_TPSFLAG);
604 tmp &= SSB_TPSFLAG_BPFLAG;
605 intvec |= tmp;
606 }
607 ssb_write32(pdev, SSB_INTVEC, intvec);
608 }
609
610 /* Setup PCIcore operation. */
611 if (pc->setup_done)
612 goto out;
613 if (pdev->id.coreid == SSB_DEV_PCI) {
614 tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
615 tmp |= SSB_PCICORE_SBTOPCI_PREF;
616 tmp |= SSB_PCICORE_SBTOPCI_BURST;
617 pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
618
619 if (pdev->id.revision < 5) {
620 tmp = ssb_read32(pdev, SSB_IMCFGLO);
621 tmp &= ~SSB_IMCFGLO_SERTO;
622 tmp |= 2;
623 tmp &= ~SSB_IMCFGLO_REQTO;
624 tmp |= 3 << SSB_IMCFGLO_REQTO_SHIFT;
625 ssb_write32(pdev, SSB_IMCFGLO, tmp);
626 ssb_commit_settings(bus);
627 } else if (pdev->id.revision >= 11) {
628 tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
629 tmp |= SSB_PCICORE_SBTOPCI_MRM;
630 pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
631 }
632 } else {
633 WARN_ON(pdev->id.coreid != SSB_DEV_PCIE);
634 //TODO: Better make defines for all these magic PCIE values.
635 if ((pdev->id.revision == 0) || (pdev->id.revision == 1)) {
636 /* TLP Workaround register. */
637 tmp = ssb_pcie_read(pc, 0x4);
638 tmp |= 0x8;
639 ssb_pcie_write(pc, 0x4, tmp);
640 }
641 if (pdev->id.revision == 0) {
642 const u8 serdes_rx_device = 0x1F;
643
644 ssb_pcie_mdio_write(pc, serdes_rx_device,
645 2 /* Timer */, 0x8128);
646 ssb_pcie_mdio_write(pc, serdes_rx_device,
647 6 /* CDR */, 0x0100);
648 ssb_pcie_mdio_write(pc, serdes_rx_device,
649 7 /* CDR BW */, 0x1466);
650 } else if (pdev->id.revision == 1) {
651 /* DLLP Link Control register. */
652 tmp = ssb_pcie_read(pc, 0x100);
653 tmp |= 0x40;
654 ssb_pcie_write(pc, 0x100, tmp);
655 }
656 }
657 pc->setup_done = 1;
658 out:
659 return err;
660 }
661 EXPORT_SYMBOL(ssb_pcicore_dev_irqvecs_enable);
WRT350N Kernel Patches