drivers/usb/host/ehci-pci.c

   1 /*
   2  * EHCI HCD (Host Controller Driver) PCI Bus Glue.
   3  *
   4  * Copyright (c) 2000-2004 by David Brownell
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License as published by the
   8  * Free Software Foundation; either version 2 of the License, or (at your
   9  * option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful, but
  12  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  14  * for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software Foundation,
  18  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19  */
  20
  21 #ifndef CONFIG_PCI
  22 #error "This file is PCI bus glue.  CONFIG_PCI must be defined."
  23 #endif
  24
  25 /*-------------------------------------------------------------------------*/
  26
  27 /* called after powerup, by probe or system-pm "wakeup" */
  28 static int ehci_pci_reinit(struct ehci_hcd *ehci, struct pci_dev *pdev)
  29 {
  30         u32                     temp;
  31         int                     retval;
  32
  33         /* optional debug port, normally in the first BAR */
  34         temp = pci_find_capability(pdev, 0x0a);
  35         if (temp) {
  36                 pci_read_config_dword(pdev, temp, &temp);
  37                 temp >>= 16;
  38                 if ((temp & (3 << 13)) == (1 << 13)) {
  39                         temp &= 0x1fff;
  40                         ehci->debug = ehci_to_hcd(ehci)->regs + temp;
  41                         temp = ehci_readl(ehci, &ehci->debug->control);
  42                         ehci_info(ehci, "debug port %d%s\n",
  43                                 HCS_DEBUG_PORT(ehci->hcs_params),
  44                                 (temp & DBGP_ENABLED)
  45                                         ? " IN USE"
  46                                         : "");
  47                         if (!(temp & DBGP_ENABLED))
  48                                 ehci->debug = NULL;
  49                 }
  50         }
  51
  52         /* we expect static quirk code to handle the "extended capabilities"
  53          * (currently just BIOS handoff) allowed starting with EHCI 0.96
  54          */
  55
  56         /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
  57         retval = pci_set_mwi(pdev);
  58         if (!retval)
  59                 ehci_dbg(ehci, "MWI active\n");
  60
  61         return 0;
  62 }
  63
  64 /* called during probe() after chip reset completes */
  65 static int ehci_pci_setup(struct usb_hcd *hcd)
  66 {
  67         struct ehci_hcd         *ehci = hcd_to_ehci(hcd);
  68         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
  69         u32                     temp;
  70         int                     retval;
  71
  72         switch (pdev->vendor) {
  73         case PCI_VENDOR_ID_TOSHIBA_2:
  74                 /* celleb's companion chip */
  75                 if (pdev->device == 0x01b5) {
  76 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
  77                         ehci->big_endian_mmio = 1;
  78 #else
  79                         ehci_warn(ehci,
  80                                   "unsupported big endian Toshiba quirk\n");
  81 #endif
  82                 }
  83                 break;
  84         }
  85
  86         ehci->caps = hcd->regs;
  87         ehci->regs = hcd->regs +
  88                 HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase));
  89
  90         dbg_hcs_params(ehci, "reset");
  91         dbg_hcc_params(ehci, "reset");
  92
  93         /* ehci_init() causes memory for DMA transfers to be
  94          * allocated.  Thus, any vendor-specific workarounds based on
  95          * limiting the type of memory used for DMA transfers must
  96          * happen before ehci_init() is called. */
  97         switch (pdev->vendor) {
  98         case PCI_VENDOR_ID_NVIDIA:
  99                 /* NVidia reports that certain chips don't handle
 100                  * QH, ITD, or SITD addresses above 2GB.  (But TD,
 101                  * data buffer, and periodic schedule are normal.)
 102                  */
 103                 switch (pdev->device) {
 104                 case 0x003c:    /* MCP04 */
 105                 case 0x005b:    /* CK804 */
 106                 case 0x00d8:    /* CK8 */
 107                 case 0x00e8:    /* CK8S */
 108                         if (pci_set_consistent_dma_mask(pdev,
 109                                                 DMA_31BIT_MASK) < 0)
 110                                 ehci_warn(ehci, "can't enable NVidia "
 111                                         "workaround for >2GB RAM\n");
 112                         break;
 113                 }
 114                 break;
 115         }
 116
 117         /* cache this readonly data; minimize chip reads */
 118         ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
 119
 120         retval = ehci_halt(ehci);
 121         if (retval)
 122                 return retval;
 123
 124         /* data structure init */
 125         retval = ehci_init(hcd);
 126         if (retval)
 127                 return retval;
 128
 129         switch (pdev->vendor) {
 130         case PCI_VENDOR_ID_TDI:
 131                 if (pdev->device == PCI_DEVICE_ID_TDI_EHCI) {
 132                         ehci->is_tdi_rh_tt = 1;
 133                         tdi_reset(ehci);
 134                 }
 135                 break;
 136         case PCI_VENDOR_ID_AMD:
 137                 /* AMD8111 EHCI doesn't work, according to AMD errata */
 138                 if (pdev->device == 0x7463) {
 139                         ehci_info(ehci, "ignoring AMD8111 (errata)\n");
 140                         retval = -EIO;
 141                         goto done;
 142                 }
 143                 break;
 144         case PCI_VENDOR_ID_NVIDIA:
 145                 switch (pdev->device) {
 146                 /* Some NForce2 chips have problems with selective suspend;
 147                  * fixed in newer silicon.
 148                  */
 149                 case 0x0068:
 150                         if (pdev->revision < 0xa4)
 151                                 ehci->no_selective_suspend = 1;
 152                         break;
 153                 }
 154                 break;
 155         }
 156
 157         ehci_reset(ehci);
 158
 159         /* at least the Genesys GL880S needs fixup here */
 160         temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params);
 161         temp &= 0x0f;
 162         if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) {
 163                 ehci_dbg(ehci, "bogus port configuration: "
 164                         "cc=%d x pcc=%d < ports=%d\n",
 165                         HCS_N_CC(ehci->hcs_params),
 166                         HCS_N_PCC(ehci->hcs_params),
 167                         HCS_N_PORTS(ehci->hcs_params));
 168
 169                 switch (pdev->vendor) {
 170                 case 0x17a0:            /* GENESYS */
 171                         /* GL880S: should be PORTS=2 */
 172                         temp |= (ehci->hcs_params & ~0xf);
 173                         ehci->hcs_params = temp;
 174                         break;
 175                 case PCI_VENDOR_ID_NVIDIA:
 176                         /* NF4: should be PCC=10 */
 177                         break;
 178                 }
 179         }
 180
 181         /* Serial Bus Release Number is at PCI 0x60 offset */
 182         pci_read_config_byte(pdev, 0x60, &ehci->sbrn);
 183
 184         /* Workaround current PCI init glitch:  wakeup bits aren't
 185          * being set from PCI PM capability.
 186          */
 187         if (!device_can_wakeup(&pdev->dev)) {
 188                 u16     port_wake;
 189
 190                 pci_read_config_word(pdev, 0x62, &port_wake);
 191                 if (port_wake & 0x0001)
 192                         device_init_wakeup(&pdev->dev, 1);
 193         }
 194
 195 #ifdef  CONFIG_USB_SUSPEND
 196         /* REVISIT: the controller works fine for wakeup iff the root hub
 197          * itself is "globally" suspended, but usbcore currently doesn't
 198          * understand such things.
 199          *
 200          * System suspend currently expects to be able to suspend the entire
 201          * device tree, device-at-a-time.  If we failed selective suspend
 202          * reports, system suspend would fail; so the root hub code must claim
 203          * success.  That's lying to usbcore, and it matters for for runtime
 204          * PM scenarios with selective suspend and remote wakeup...
 205          */
 206         if (ehci->no_selective_suspend && device_can_wakeup(&pdev->dev))
 207                 ehci_warn(ehci, "selective suspend/wakeup unavailable\n");
 208 #endif
 209
 210         retval = ehci_pci_reinit(ehci, pdev);
 211 done:
 212         return retval;
 213 }
 214
 215 /*-------------------------------------------------------------------------*/
 216
 217 #ifdef  CONFIG_PM
 218
 219 /* suspend/resume, section 4.3 */
 220
 221 /* These routines rely on the PCI bus glue
 222  * to handle powerdown and wakeup, and currently also on
 223  * transceivers that don't need any software attention to set up
 224  * the right sort of wakeup.
 225  * Also they depend on separate root hub suspend/resume.
 226  */
 227
 228 static int ehci_pci_suspend(struct usb_hcd *hcd, pm_message_t message)
 229 {
 230         struct ehci_hcd         *ehci = hcd_to_ehci(hcd);
 231         unsigned long           flags;
 232         int                     rc = 0;
 233
 234         if (time_before(jiffies, ehci->next_statechange))
 235                 msleep(10);
 236
 237         /* Root hub was already suspended. Disable irq emission and
 238          * mark HW unaccessible, bail out if RH has been resumed. Use
 239          * the spinlock to properly synchronize with possible pending
 240          * RH suspend or resume activity.
 241          *
 242          * This is still racy as hcd->state is manipulated outside of
 243          * any locks =P But that will be a different fix.
 244          */
 245         spin_lock_irqsave (&ehci->lock, flags);
 246         if (hcd->state != HC_STATE_SUSPENDED) {
 247                 rc = -EINVAL;
 248                 goto bail;
 249         }
 250         ehci_writel(ehci, 0, &ehci->regs->intr_enable);
 251         (void)ehci_readl(ehci, &ehci->regs->intr_enable);
 252
 253         /* make sure snapshot being resumed re-enumerates everything */
 254         if (message.event == PM_EVENT_PRETHAW) {
 255                 ehci_halt(ehci);
 256                 ehci_reset(ehci);
 257         }
 258
 259         clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
 260  bail:
 261         spin_unlock_irqrestore (&ehci->lock, flags);
 262
 263         // could save FLADJ in case of Vaux power loss
 264         // ... we'd only use it to handle clock skew
 265
 266         return rc;
 267 }
 268
 269 static int ehci_pci_resume(struct usb_hcd *hcd)
 270 {
 271         struct ehci_hcd         *ehci = hcd_to_ehci(hcd);
 272         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 273
 274         // maybe restore FLADJ
 275
 276         if (time_before(jiffies, ehci->next_statechange))
 277                 msleep(100);
 278
 279         /* Mark hardware accessible again as we are out of D3 state by now */
 280         set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
 281
 282         /* If CF is still set, we maintained PCI Vaux power.
 283          * Just undo the effect of ehci_pci_suspend().
 284          */
 285         if (ehci_readl(ehci, &ehci->regs->configured_flag) == FLAG_CF) {
 286                 int     mask = INTR_MASK;
 287
 288                 if (!device_may_wakeup(&hcd->self.root_hub->dev))
 289                         mask &= ~STS_PCD;
 290                 ehci_writel(ehci, mask, &ehci->regs->intr_enable);
 291                 ehci_readl(ehci, &ehci->regs->intr_enable);
 292                 return 0;
 293         }
 294
 295         ehci_dbg(ehci, "lost power, restarting\n");
 296         usb_root_hub_lost_power(hcd->self.root_hub);
 297
 298         /* Else reset, to cope with power loss or flush-to-storage
 299          * style "resume" having let BIOS kick in during reboot.
 300          */
 301         (void) ehci_halt(ehci);
 302         (void) ehci_reset(ehci);
 303         (void) ehci_pci_reinit(ehci, pdev);
 304
 305         /* emptying the schedule aborts any urbs */
 306         spin_lock_irq(&ehci->lock);
 307         if (ehci->reclaim)
 308                 end_unlink_async(ehci);
 309         ehci_work(ehci);
 310         spin_unlock_irq(&ehci->lock);
 311
 312         ehci_writel(ehci, ehci->command, &ehci->regs->command);
 313         ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
 314         ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */
 315
 316         /* here we "know" root ports should always stay powered */
 317         ehci_port_power(ehci, 1);
 318         ehci_handover_companion_ports(ehci);
 319
 320         hcd->state = HC_STATE_SUSPENDED;
 321         return 0;
 322 }
 323 #endif
 324
 325 static const struct hc_driver ehci_pci_hc_driver = {
 326         .description =          hcd_name,
 327         .product_desc =         "EHCI Host Controller",
 328         .hcd_priv_size =        sizeof(struct ehci_hcd),
 329
 330         /*
 331          * generic hardware linkage
 332          */
 333         .irq =                  ehci_irq,
 334         .flags =                HCD_MEMORY | HCD_USB2,
 335
 336         /*
 337          * basic lifecycle operations
 338          */
 339         .reset =                ehci_pci_setup,
 340         .start =                ehci_run,
 341 #ifdef  CONFIG_PM
 342         .suspend =              ehci_pci_suspend,
 343         .resume =               ehci_pci_resume,
 344 #endif
 345         .stop =                 ehci_stop,
 346         .shutdown =             ehci_shutdown,
 347
 348         /*
 349          * managing i/o requests and associated device resources
 350          */
 351         .urb_enqueue =          ehci_urb_enqueue,
 352         .urb_dequeue =          ehci_urb_dequeue,
 353         .endpoint_disable =     ehci_endpoint_disable,
 354
 355         /*
 356          * scheduling support
 357          */
 358         .get_frame_number =     ehci_get_frame,
 359
 360         /*
 361          * root hub support
 362          */
 363         .hub_status_data =      ehci_hub_status_data,
 364         .hub_control =          ehci_hub_control,
 365         .bus_suspend =          ehci_bus_suspend,
 366         .bus_resume =           ehci_bus_resume,
 367         .relinquish_port =      ehci_relinquish_port,
 368 };
 369
 370 /*-------------------------------------------------------------------------*/
 371
 372 /* PCI driver selection metadata; PCI hotplugging uses this */
 373 static const struct pci_device_id pci_ids [] = { {
 374         /* handle any USB 2.0 EHCI controller */
 375         PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_EHCI, ~0),
 376         .driver_data =  (unsigned long) &ehci_pci_hc_driver,
 377         },
 378         { /* end: all zeroes */ }
 379 };
 380 MODULE_DEVICE_TABLE(pci, pci_ids);
 381
 382 /* pci driver glue; this is a "new style" PCI driver module */
 383 static struct pci_driver ehci_pci_driver = {
 384         .name =         (char *) hcd_name,
 385         .id_table =     pci_ids,
 386
 387         .probe =        usb_hcd_pci_probe,
 388         .remove =       usb_hcd_pci_remove,
 389
 390 #ifdef  CONFIG_PM
 391         .suspend =      usb_hcd_pci_suspend,
 392         .resume =       usb_hcd_pci_resume,
 393 #endif
 394         .shutdown =     usb_hcd_pci_shutdown,
 395 };