Merge git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
[wrt350n-kernel.git] / include / asm-arm / arch-ns9xxx / regs-sys.h
blob749262f86204ea4ad365ee267f0ee243f1f0a327
1 /*
2 * include/asm-arm/arch-ns9xxx/regs-sys.h
4 * Copyright (C) 2006 by Digi International Inc.
5 * All rights reserved.
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
11 #ifndef __ASM_ARCH_REGSSYS_H
12 #define __ASM_ARCH_REGSSYS_H
14 #include <asm/hardware.h>
16 /* System Control Module */
18 /* AHB Arbiter Gen Configuration */
19 #define SYS_AHBAGENCONF __REG(0xa0900000)
21 /* BRC */
22 #define SYS_BRC(x) __REG2(0xa0900004, (x))
24 /* Timer x Reload Count register */
25 #define SYS_TRC(x) __REG2(0xa0900044, (x))
27 /* Timer x Read register */
28 #define SYS_TR(x) __REG2(0xa0900084, (x))
30 /* Interrupt Vector Address Register Level x */
31 #define SYS_IVA(x) __REG2(0xa09000c4, (x))
33 /* Interrupt Configuration registers */
34 #define SYS_IC(x) __REG2(0xa0900144, (x))
36 /* ISRADDR */
37 #define SYS_ISRADDR __REG(0xa0900164)
39 /* Interrupt Status Active */
40 #define SYS_ISA __REG(0xa0900168)
42 /* Interrupt Status Raw */
43 #define SYS_ISR __REG(0xa090016c)
45 /* Timer Interrupt Status register */
46 #define SYS_TIS __REG(0xa0900170)
48 /* PLL Configuration register */
49 #define SYS_PLL __REG(0xa0900188)
51 /* PLL FS status */
52 #define SYS_PLL_FS __REGBITS(24, 23)
54 /* PLL ND status */
55 #define SYS_PLL_ND __REGBITS(20, 16)
57 /* PLL Configuration register: PLL SW change */
58 #define SYS_PLL_SWC __REGBIT(15)
59 #define SYS_PLL_SWC_NO __REGVAL(SYS_PLL_SWC, 0)
60 #define SYS_PLL_SWC_YES __REGVAL(SYS_PLL_SWC, 1)
62 /* Timer x Control register */
63 #define SYS_TC(x) __REG2(0xa0900190, (x))
65 /* Timer x Control register: Timer enable */
66 #define SYS_TCx_TEN __REGBIT(15)
67 #define SYS_TCx_TEN_DIS __REGVAL(SYS_TCx_TEN, 0)
68 #define SYS_TCx_TEN_EN __REGVAL(SYS_TCx_TEN, 1)
70 /* Timer x Control register: CPU debug mode */
71 #define SYS_TCx_TDBG __REGBIT(10)
72 #define SYS_TCx_TDBG_CONT __REGVAL(SYS_TCx_TDBG, 0)
73 #define SYS_TCx_TDBG_STOP __REGVAL(SYS_TCx_TDBG, 1)
75 /* Timer x Control register: Interrupt clear */
76 #define SYS_TCx_INTC __REGBIT(9)
77 #define SYS_TCx_INTC_UNSET __REGVAL(SYS_TCx_INTC, 0)
78 #define SYS_TCx_INTC_SET __REGVAL(SYS_TCx_INTC, 1)
80 /* Timer x Control register: Timer clock select */
81 #define SYS_TCx_TLCS __REGBITS(8, 6)
82 #define SYS_TCx_TLCS_CPU __REGVAL(SYS_TCx_TLCS, 0) /* CPU clock */
83 #define SYS_TCx_TLCS_DIV2 __REGVAL(SYS_TCx_TLCS, 1) /* CPU clock / 2 */
84 #define SYS_TCx_TLCS_DIV4 __REGVAL(SYS_TCx_TLCS, 2) /* CPU clock / 4 */
85 #define SYS_TCx_TLCS_DIV8 __REGVAL(SYS_TCx_TLCS, 3) /* CPU clock / 8 */
86 #define SYS_TCx_TLCS_DIV16 __REGVAL(SYS_TCx_TLCS, 4) /* CPU clock / 16 */
87 #define SYS_TCx_TLCS_DIV32 __REGVAL(SYS_TCx_TLCS, 5) /* CPU clock / 32 */
88 #define SYS_TCx_TLCS_DIV64 __REGVAL(SYS_TCx_TLCS, 6) /* CPU clock / 64 */
89 #define SYS_TCx_TLCS_EXT __REGVAL(SYS_TCx_TLCS, 7)
91 /* Timer x Control register: Timer mode */
92 #define SYS_TCx_TM __REGBITS(5, 4)
93 #define SYS_TCx_TM_IEE __REGVAL(SYS_TCx_TM, 0) /* Internal timer or external event */
94 #define SYS_TCx_TM_ELL __REGVAL(SYS_TCx_TM, 1) /* External low-level, gated timer */
95 #define SYS_TCx_TM_EHL __REGVAL(SYS_TCx_TM, 2) /* External high-level, gated timer */
96 #define SYS_TCx_TM_CONCAT __REGVAL(SYS_TCx_TM, 3) /* Concatenate the lower timer. */
98 /* Timer x Control register: Interrupt select */
99 #define SYS_TCx_INTS __REGBIT(3)
100 #define SYS_TCx_INTS_DIS __REGVAL(SYS_TCx_INTS, 0)
101 #define SYS_TCx_INTS_EN __REGVAL(SYS_TCx_INTS, 1)
103 /* Timer x Control register: Up/down select */
104 #define SYS_TCx_UDS __REGBIT(2)
105 #define SYS_TCx_UDS_UP __REGVAL(SYS_TCx_UDS, 0)
106 #define SYS_TCx_UDS_DOWN __REGVAL(SYS_TCx_UDS, 1)
108 /* Timer x Control register: 32- or 16-bit timer */
109 #define SYS_TCx_TSZ __REGBIT(1)
110 #define SYS_TCx_TSZ_16 __REGVAL(SYS_TCx_TSZ, 0)
111 #define SYS_TCx_TSZ_32 __REGVAL(SYS_TCx_TSZ, 1)
113 /* Timer x Control register: Reload enable */
114 #define SYS_TCx_REN __REGBIT(0)
115 #define SYS_TCx_REN_DIS __REGVAL(SYS_TCx_REN, 0)
116 #define SYS_TCx_REN_EN __REGVAL(SYS_TCx_REN, 1)
118 /* System Memory Chip Select x Dynamic Memory Base */
119 #define SYS_SMCSDMB(x) __REG2(0xa09001d0, (x) << 1)
121 /* System Memory Chip Select x Dynamic Memory Mask */
122 #define SYS_SMCSDMM(x) __REG2(0xa09001d4, (x) << 1)
124 /* System Memory Chip Select x Static Memory Base */
125 #define SYS_SMCSSMB(x) __REG2(0xa09001f0, (x) << 1)
127 /* System Memory Chip Select x Static Memory Base: Chip select x base */
128 #define SYS_SMCSSMB_CSxB __REGBITS(31, 12)
130 /* System Memory Chip Select x Static Memory Mask */
131 #define SYS_SMCSSMM(x) __REG2(0xa09001f4, (x) << 1)
133 /* System Memory Chip Select x Static Memory Mask: Chip select x mask */
134 #define SYS_SMCSSMM_CSxM __REGBITS(31, 12)
136 /* System Memory Chip Select x Static Memory Mask: Chip select x enable */
137 #define SYS_SMCSSMM_CSEx __REGBIT(0)
138 #define SYS_SMCSSMM_CSEx_DIS __REGVAL(SYS_SMCSSMM_CSEx, 0)
139 #define SYS_SMCSSMM_CSEx_EN __REGVAL(SYS_SMCSSMM_CSEx, 1)
141 /* General purpose, user-defined ID register */
142 #define SYS_GENID __REG(0xa0900210)
144 /* External Interrupt x Control register */
145 #define SYS_EIC(x) __REG2(0xa0900214, (x))
147 /* External Interrupt x Control register: Status */
148 #define SYS_EIC_STS __REGBIT(3)
150 /* External Interrupt x Control register: Clear */
151 #define SYS_EIC_CLR __REGBIT(2)
153 /* External Interrupt x Control register: Polarity */
154 #define SYS_EIC_PLTY __REGBIT(1)
155 #define SYS_EIC_PLTY_AH __REGVAL(SYS_EIC_PLTY, 0)
156 #define SYS_EIC_PLTY_AL __REGVAL(SYS_EIC_PLTY, 1)
158 /* External Interrupt x Control register: Level edge */
159 #define SYS_EIC_LVEDG __REGBIT(0)
160 #define SYS_EIC_LVEDG_LEVEL __REGVAL(SYS_EIC_LVEDG, 0)
161 #define SYS_EIC_LVEDG_EDGE __REGVAL(SYS_EIC_LVEDG, 1)
163 #endif /* ifndef __ASM_ARCH_REGSSYS_H */