include/asm-arm/arch-sa1100/h3600_gpio.h

   1 /*
   2  *
   3  * Definitions for H3600 Handheld Computer
   4  *
   5  * Copyright 2000 Compaq Computer Corporation.
   6  *
   7  * Use consistent with the GNU GPL is permitted,
   8  * provided that this copyright notice is
   9  * preserved in its entirety in all copies and derived works.
  10  *
  11  * COMPAQ COMPUTER CORPORATION MAKES NO WARRANTIES, EXPRESSED OR IMPLIED,
  12  * AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS
  13  * FITNESS FOR ANY PARTICULAR PURPOSE.
  14  *
  15  * Author: Jamey Hicks.
  16  *
  17  * History:
  18  *
  19  * 2001-10-??   Andrew Christian   Added support for iPAQ H3800
  20  *
  21  */
  22
  23 #ifndef _INCLUDE_H3600_GPIO_H_
  24 #define _INCLUDE_H3600_GPIO_H_
  25
  26 /*
  27  * GPIO lines that are common across ALL iPAQ models are in "h3600.h"
  28  * This file contains machine-specific definitions
  29  */
  30
  31 #define GPIO_H3600_SUSPEND              GPIO_GPIO (0)
  32 /* GPIO[2:9] used by LCD on H3600/3800, used as GPIO on H3100 */
  33 #define GPIO_H3100_BT_ON                GPIO_GPIO (2)
  34 #define GPIO_H3100_GPIO3                GPIO_GPIO (3)
  35 #define GPIO_H3100_QMUTE                GPIO_GPIO (4)
  36 #define GPIO_H3100_LCD_3V_ON            GPIO_GPIO (5)
  37 #define GPIO_H3100_AUD_ON               GPIO_GPIO (6)
  38 #define GPIO_H3100_AUD_PWR_ON           GPIO_GPIO (7)
  39 #define GPIO_H3100_IR_ON                GPIO_GPIO (8)
  40 #define GPIO_H3100_IR_FSEL              GPIO_GPIO (9)
  41
  42 /* for H3600, audio sample rate clock generator */
  43 #define GPIO_H3600_CLK_SET0             GPIO_GPIO (12)
  44 #define GPIO_H3600_CLK_SET1             GPIO_GPIO (13)
  45
  46 #define GPIO_H3600_ACTION_BUTTON        GPIO_GPIO (18)
  47 #define GPIO_H3600_SOFT_RESET           GPIO_GPIO (20)   /* Also known as BATT_FAULT */
  48 #define GPIO_H3600_OPT_LOCK             GPIO_GPIO (22)
  49 #define GPIO_H3600_OPT_DET              GPIO_GPIO (27)
  50
  51 /* H3800 specific pins */
  52 #define GPIO_H3800_AC_IN                GPIO_GPIO (12)
  53 #define GPIO_H3800_COM_DSR              GPIO_GPIO (13)
  54 #define GPIO_H3800_MMC_INT              GPIO_GPIO (18)
  55 #define GPIO_H3800_NOPT_IND             GPIO_GPIO (20)   /* Almost exactly the same as GPIO_H3600_OPT_DET */
  56 #define GPIO_H3800_OPT_BAT_FAULT        GPIO_GPIO (22)
  57 #define GPIO_H3800_CLK_OUT              GPIO_GPIO (27)
  58
  59 /****************************************************/
  60
  61 #define IRQ_GPIO_H3600_ACTION_BUTTON    IRQ_GPIO18
  62 #define IRQ_GPIO_H3600_OPT_DET          IRQ_GPIO27
  63
  64 #define IRQ_GPIO_H3800_MMC_INT          IRQ_GPIO18
  65 #define IRQ_GPIO_H3800_NOPT_IND         IRQ_GPIO20 /* almost same as OPT_DET */
  66
  67 /* H3100 / 3600 EGPIO pins */
  68 #define EGPIO_H3600_VPP_ON              (1 << 0)
  69 #define EGPIO_H3600_CARD_RESET          (1 << 1)   /* reset the attached pcmcia/compactflash card.  active high. */
  70 #define EGPIO_H3600_OPT_RESET           (1 << 2)   /* reset the attached option pack.  active high. */
  71 #define EGPIO_H3600_CODEC_NRESET        (1 << 3)   /* reset the onboard UDA1341.  active low. */
  72 #define EGPIO_H3600_OPT_NVRAM_ON        (1 << 4)   /* apply power to optionpack nvram, active high. */
  73 #define EGPIO_H3600_OPT_ON              (1 << 5)   /* full power to option pack.  active high. */
  74 #define EGPIO_H3600_LCD_ON              (1 << 6)   /* enable 3.3V to LCD.  active high. */
  75 #define EGPIO_H3600_RS232_ON            (1 << 7)   /* UART3 transceiver force on.  Active high. */
  76
  77 /* H3600 only EGPIO pins */
  78 #define EGPIO_H3600_LCD_PCI             (1 << 8)   /* LCD control IC enable.  active high. */
  79 #define EGPIO_H3600_IR_ON               (1 << 9)   /* apply power to IR module.  active high. */
  80 #define EGPIO_H3600_AUD_AMP_ON          (1 << 10)  /* apply power to audio power amp.  active high. */
  81 #define EGPIO_H3600_AUD_PWR_ON          (1 << 11)  /* apply power to reset of audio circuit.  active high. */
  82 #define EGPIO_H3600_QMUTE               (1 << 12)  /* mute control for onboard UDA1341.  active high. */
  83 #define EGPIO_H3600_IR_FSEL             (1 << 13)  /* IR speed select: 1->fast, 0->slow */
  84 #define EGPIO_H3600_LCD_5V_ON           (1 << 14)  /* enable 5V to LCD. active high. */
  85 #define EGPIO_H3600_LVDD_ON             (1 << 15)  /* enable 9V and -6.5V to LCD. */
  86
  87 /********************* H3800, ASIC #2 ********************/
  88
  89 #define _H3800_ASIC2_Base            (H3600_EGPIO_VIRT)
  90 #define H3800_ASIC2_OFFSET(s,x,y)    \
  91     (*((volatile s *) (_H3800_ASIC2_Base + _H3800_ASIC2_ ## x ## _Base + _H3800_ASIC2_ ## x ## _ ## y)))
  92 #define H3800_ASIC2_NOFFSET(s,x,n,y) \
  93     (*((volatile s *) (_H3800_ASIC2_Base + _H3800_ASIC2_ ## x ## _ ## n ## _Base + _H3800_ASIC2_ ## x ## _ ## y)))
  94
  95 #define _H3800_ASIC2_GPIO_Base                 0x0000
  96 #define _H3800_ASIC2_GPIO_Direction            0x0000    /* R/W, 16 bits 1:input, 0:output */
  97 #define _H3800_ASIC2_GPIO_InterruptType        0x0004    /* R/W, 12 bits 1:edge, 0:level          */
  98 #define _H3800_ASIC2_GPIO_InterruptEdgeType    0x0008    /* R/W, 12 bits 1:rising, 0:falling */
  99 #define _H3800_ASIC2_GPIO_InterruptLevelType   0x000C    /* R/W, 12 bits 1:high, 0:low  */
 100 #define _H3800_ASIC2_GPIO_InterruptClear       0x0010    /* W,   12 bits */
 101 #define _H3800_ASIC2_GPIO_InterruptFlag        0x0010    /* R,   12 bits - reads int status */
 102 #define _H3800_ASIC2_GPIO_Data                 0x0014    /* R/W, 16 bits */
 103 #define _H3800_ASIC2_GPIO_BattFaultOut         0x0018    /* R/W, 16 bit - sets level on batt fault */
 104 #define _H3800_ASIC2_GPIO_InterruptEnable      0x001c    /* R/W, 12 bits 1:enable interrupt */
 105 #define _H3800_ASIC2_GPIO_Alternate            0x003c    /* R/W, 12+1 bits - set alternate functions */
 106
 107 #define H3800_ASIC2_GPIO_Direction          H3800_ASIC2_OFFSET( u16, GPIO, Direction )
 108 #define H3800_ASIC2_GPIO_InterruptType      H3800_ASIC2_OFFSET( u16, GPIO, InterruptType )
 109 #define H3800_ASIC2_GPIO_InterruptEdgeType  H3800_ASIC2_OFFSET( u16, GPIO, InterruptEdgeType )
 110 #define H3800_ASIC2_GPIO_InterruptLevelType H3800_ASIC2_OFFSET( u16, GPIO, InterruptLevelType )
 111 #define H3800_ASIC2_GPIO_InterruptClear     H3800_ASIC2_OFFSET( u16, GPIO, InterruptClear )
 112 #define H3800_ASIC2_GPIO_InterruptFlag      H3800_ASIC2_OFFSET( u16, GPIO, InterruptFlag )
 113 #define H3800_ASIC2_GPIO_Data               H3800_ASIC2_OFFSET( u16, GPIO, Data )
 114 #define H3800_ASIC2_GPIO_BattFaultOut       H3800_ASIC2_OFFSET( u16, GPIO, BattFaultOut )
 115 #define H3800_ASIC2_GPIO_InterruptEnable    H3800_ASIC2_OFFSET( u16, GPIO, InterruptEnable )
 116 #define H3800_ASIC2_GPIO_Alternate          H3800_ASIC2_OFFSET( u16, GPIO, Alternate )
 117
 118 #define GPIO_H3800_ASIC2_IN_Y1_N          (1 << 0)   /* Output: Touchscreen Y1 */
 119 #define GPIO_H3800_ASIC2_IN_X0            (1 << 1)   /* Output: Touchscreen X0 */
 120 #define GPIO_H3800_ASIC2_IN_Y0            (1 << 2)   /* Output: Touchscreen Y0 */
 121 #define GPIO_H3800_ASIC2_IN_X1_N          (1 << 3)   /* Output: Touchscreen X1 */
 122 #define GPIO_H3800_ASIC2_BT_RST           (1 << 4)   /* Output: Bluetooth reset */
 123 #define GPIO_H3800_ASIC2_PEN_IRQ          (1 << 5)   /* Input : Pen down        */
 124 #define GPIO_H3800_ASIC2_SD_DETECT        (1 << 6)   /* Input : SD detect */
 125 #define GPIO_H3800_ASIC2_EAR_IN_N         (1 << 7)   /* Input : Audio jack plug inserted */
 126 #define GPIO_H3800_ASIC2_OPT_PCM_RESET    (1 << 8)   /* Output: */
 127 #define GPIO_H3800_ASIC2_OPT_RESET        (1 << 9)   /* Output: */
 128 #define GPIO_H3800_ASIC2_USB_DETECT_N     (1 << 10)  /* Input : */
 129 #define GPIO_H3800_ASIC2_SD_CON_SLT       (1 << 11)  /* Input : */
 130
 131 #define _H3800_ASIC2_KPIO_Base                 0x0200
 132 #define _H3800_ASIC2_KPIO_Direction            0x0000    /* R/W, 12 bits 1:input, 0:output */
 133 #define _H3800_ASIC2_KPIO_InterruptType        0x0004    /* R/W, 12 bits 1:edge, 0:level          */
 134 #define _H3800_ASIC2_KPIO_InterruptEdgeType    0x0008    /* R/W, 12 bits 1:rising, 0:falling */
 135 #define _H3800_ASIC2_KPIO_InterruptLevelType   0x000C    /* R/W, 12 bits 1:high, 0:low  */
 136 #define _H3800_ASIC2_KPIO_InterruptClear       0x0010    /* W,   20 bits - 8 special */
 137 #define _H3800_ASIC2_KPIO_InterruptFlag        0x0010    /* R,   20 bits - 8 special - reads int status */
 138 #define _H3800_ASIC2_KPIO_Data                 0x0014    /* R/W, 16 bits */
 139 #define _H3800_ASIC2_KPIO_BattFaultOut         0x0018    /* R/W, 16 bit - sets level on batt fault */
 140 #define _H3800_ASIC2_KPIO_InterruptEnable      0x001c    /* R/W, 20 bits - 8 special */
 141 #define _H3800_ASIC2_KPIO_Alternate            0x003c    /* R/W, 6 bits */
 142
 143 #define H3800_ASIC2_KPIO_Direction          H3800_ASIC2_OFFSET( u16, KPIO, Direction )
 144 #define H3800_ASIC2_KPIO_InterruptType      H3800_ASIC2_OFFSET( u16, KPIO, InterruptType )
 145 #define H3800_ASIC2_KPIO_InterruptEdgeType  H3800_ASIC2_OFFSET( u16, KPIO, InterruptEdgeType )
 146 #define H3800_ASIC2_KPIO_InterruptLevelType H3800_ASIC2_OFFSET( u16, KPIO, InterruptLevelType )
 147 #define H3800_ASIC2_KPIO_InterruptClear     H3800_ASIC2_OFFSET( u32, KPIO, InterruptClear )
 148 #define H3800_ASIC2_KPIO_InterruptFlag      H3800_ASIC2_OFFSET( u32, KPIO, InterruptFlag )
 149 #define H3800_ASIC2_KPIO_Data               H3800_ASIC2_OFFSET( u16, KPIO, Data )
 150 #define H3800_ASIC2_KPIO_BattFaultOut       H3800_ASIC2_OFFSET( u16, KPIO, BattFaultOut )
 151 #define H3800_ASIC2_KPIO_InterruptEnable    H3800_ASIC2_OFFSET( u32, KPIO, InterruptEnable )
 152 #define H3800_ASIC2_KPIO_Alternate          H3800_ASIC2_OFFSET( u16, KPIO, Alternate )
 153
 154 #define H3800_ASIC2_KPIO_SPI_INT        ( 1 << 16 )
 155 #define H3800_ASIC2_KPIO_OWM_INT        ( 1 << 17 )
 156 #define H3800_ASIC2_KPIO_ADC_INT        ( 1 << 18 )
 157 #define H3800_ASIC2_KPIO_UART_0_INT     ( 1 << 19 )
 158 #define H3800_ASIC2_KPIO_UART_1_INT     ( 1 << 20 )
 159 #define H3800_ASIC2_KPIO_TIMER_0_INT    ( 1 << 21 )
 160 #define H3800_ASIC2_KPIO_TIMER_1_INT    ( 1 << 22 )
 161 #define H3800_ASIC2_KPIO_TIMER_2_INT    ( 1 << 23 )
 162
 163 #define KPIO_H3800_ASIC2_RECORD_BTN_N     (1 << 0)   /* Record button */
 164 #define KPIO_H3800_ASIC2_KEY_5W1_N        (1 << 1)   /* Keypad */
 165 #define KPIO_H3800_ASIC2_KEY_5W2_N        (1 << 2)   /* */
 166 #define KPIO_H3800_ASIC2_KEY_5W3_N        (1 << 3)   /* */
 167 #define KPIO_H3800_ASIC2_KEY_5W4_N        (1 << 4)   /* */
 168 #define KPIO_H3800_ASIC2_KEY_5W5_N        (1 << 5)   /* */
 169 #define KPIO_H3800_ASIC2_KEY_LEFT_N       (1 << 6)   /* */
 170 #define KPIO_H3800_ASIC2_KEY_RIGHT_N      (1 << 7)   /* */
 171 #define KPIO_H3800_ASIC2_KEY_AP1_N        (1 << 8)   /* Old "Calendar" */
 172 #define KPIO_H3800_ASIC2_KEY_AP2_N        (1 << 9)   /* Old "Schedule" */
 173 #define KPIO_H3800_ASIC2_KEY_AP3_N        (1 << 10)  /* Old "Q"        */
 174 #define KPIO_H3800_ASIC2_KEY_AP4_N        (1 << 11)  /* Old "Undo"     */
 175
 176 /* Alternate KPIO functions (set by default) */
 177 #define KPIO_ALT_H3800_ASIC2_KEY_5W1_N        (1 << 1)   /* Action key */
 178 #define KPIO_ALT_H3800_ASIC2_KEY_5W2_N        (1 << 2)   /* J1 of keypad input */
 179 #define KPIO_ALT_H3800_ASIC2_KEY_5W3_N        (1 << 3)   /* J2 of keypad input */
 180 #define KPIO_ALT_H3800_ASIC2_KEY_5W4_N        (1 << 4)   /* J3 of keypad input */
 181 #define KPIO_ALT_H3800_ASIC2_KEY_5W5_N        (1 << 5)   /* J4 of keypad input */
 182
 183 #define _H3800_ASIC2_SPI_Base                  0x0400
 184 #define _H3800_ASIC2_SPI_Control               0x0000    /* R/W 8 bits */
 185 #define _H3800_ASIC2_SPI_Data                  0x0004    /* R/W 8 bits */
 186 #define _H3800_ASIC2_SPI_ChipSelectDisabled    0x0008    /* W   8 bits */
 187
 188 #define H3800_ASIC2_SPI_Control             H3800_ASIC2_OFFSET( u8, SPI, Control )
 189 #define H3800_ASIC2_SPI_Data                H3800_ASIC2_OFFSET( u8, SPI, Data )
 190 #define H3800_ASIC2_SPI_ChipSelectDisabled  H3800_ASIC2_OFFSET( u8, SPI, ChipSelectDisabled )
 191
 192 #define _H3800_ASIC2_PWM_0_Base                0x0600
 193 #define _H3800_ASIC2_PWM_1_Base                0x0700
 194 #define _H3800_ASIC2_PWM_TimeBase              0x0000    /* R/W 6 bits */
 195 #define _H3800_ASIC2_PWM_PeriodTime            0x0004    /* R/W 12 bits */
 196 #define _H3800_ASIC2_PWM_DutyTime              0x0008    /* R/W 12 bits */
 197
 198 #define H3800_ASIC2_PWM_0_TimeBase          H3800_ASIC2_NOFFSET(  u8, PWM, 0, TimeBase )
 199 #define H3800_ASIC2_PWM_0_PeriodTime        H3800_ASIC2_NOFFSET( u16, PWM, 0, PeriodTime )
 200 #define H3800_ASIC2_PWM_0_DutyTime          H3800_ASIC2_NOFFSET( u16, PWM, 0, DutyTime )
 201
 202 #define H3800_ASIC2_PWM_1_TimeBase          H3800_ASIC2_NOFFSET(  u8, PWM, 1, TimeBase )
 203 #define H3800_ASIC2_PWM_1_PeriodTime        H3800_ASIC2_NOFFSET( u16, PWM, 1, PeriodTime )
 204 #define H3800_ASIC2_PWM_1_DutyTime          H3800_ASIC2_NOFFSET( u16, PWM, 1, DutyTime )
 205
 206 #define H3800_ASIC2_PWM_TIMEBASE_MASK             0xf    /* Low 4 bits sets time base, max = 8 */
 207 #define H3800_ASIC2_PWM_TIMEBASE_ENABLE    ( 1 << 4 )    /* Enable clock */
 208 #define H3800_ASIC2_PWM_TIMEBASE_CLEAR     ( 1 << 5 )    /* Clear the PWM */
 209
 210 #define _H3800_ASIC2_LED_0_Base                0x0800
 211 #define _H3800_ASIC2_LED_1_Base                0x0880
 212 #define _H3800_ASIC2_LED_2_Base                0x0900
 213 #define _H3800_ASIC2_LED_TimeBase              0x0000    /* R/W  7 bits */
 214 #define _H3800_ASIC2_LED_PeriodTime            0x0004    /* R/W 12 bits */
 215 #define _H3800_ASIC2_LED_DutyTime              0x0008    /* R/W 12 bits */
 216 #define _H3800_ASIC2_LED_AutoStopCount         0x000c    /* R/W 16 bits */
 217
 218 #define H3800_ASIC2_LED_0_TimeBase          H3800_ASIC2_NOFFSET(  u8, LED, 0, TimeBase )
 219 #define H3800_ASIC2_LED_0_PeriodTime        H3800_ASIC2_NOFFSET( u16, LED, 0, PeriodTime )
 220 #define H3800_ASIC2_LED_0_DutyTime          H3800_ASIC2_NOFFSET( u16, LED, 0, DutyTime )
 221 #define H3800_ASIC2_LED_0_AutoStopClock     H3800_ASIC2_NOFFSET( u16, LED, 0, AutoStopClock )
 222
 223 #define H3800_ASIC2_LED_1_TimeBase          H3800_ASIC2_NOFFSET(  u8, LED, 1, TimeBase )
 224 #define H3800_ASIC2_LED_1_PeriodTime        H3800_ASIC2_NOFFSET( u16, LED, 1, PeriodTime )
 225 #define H3800_ASIC2_LED_1_DutyTime          H3800_ASIC2_NOFFSET( u16, LED, 1, DutyTime )
 226 #define H3800_ASIC2_LED_1_AutoStopClock     H3800_ASIC2_NOFFSET( u16, LED, 1, AutoStopClock )
 227
 228 #define H3800_ASIC2_LED_2_TimeBase          H3800_ASIC2_NOFFSET(  u8, LED, 2, TimeBase )
 229 #define H3800_ASIC2_LED_2_PeriodTime        H3800_ASIC2_NOFFSET( u16, LED, 2, PeriodTime )
 230 #define H3800_ASIC2_LED_2_DutyTime          H3800_ASIC2_NOFFSET( u16, LED, 2, DutyTime )
 231 #define H3800_ASIC2_LED_2_AutoStopClock     H3800_ASIC2_NOFFSET( u16, LED, 2, AutoStopClock )
 232
 233 #define H3800_ASIC2_LED_TIMEBASE_MASK            0x0f    /* Low 4 bits sets time base, max = 13 */
 234 #define H3800_ASIC2_LED_TIMEBASE_BLINK     ( 1 << 4 )    /* Enable blinking */
 235 #define H3800_ASIC2_LED_TIMEBASE_AUTOSTOP  ( 1 << 5 )
 236 #define H3800_ASIC2_LED_TIMEBASE_ALWAYS    ( 1 << 6 )    /* Enable blink always */
 237
 238 #define _H3800_ASIC2_UART_0_Base               0x0A00
 239 #define _H3800_ASIC2_UART_1_Base               0x0C00
 240 #define _H3800_ASIC2_UART_Receive              0x0000    /* R    8 bits */
 241 #define _H3800_ASIC2_UART_Transmit             0x0000    /*   W  8 bits */
 242 #define _H3800_ASIC2_UART_IntEnable            0x0004    /* R/W  8 bits */
 243 #define _H3800_ASIC2_UART_IntVerify            0x0008    /* R/W  8 bits */
 244 #define _H3800_ASIC2_UART_FIFOControl          0x000c    /* R/W  8 bits */
 245 #define _H3800_ASIC2_UART_LineControl          0x0010    /* R/W  8 bits */
 246 #define _H3800_ASIC2_UART_ModemStatus          0x0014    /* R/W  8 bits */
 247 #define _H3800_ASIC2_UART_LineStatus           0x0018    /* R/W  8 bits */
 248 #define _H3800_ASIC2_UART_ScratchPad           0x001c    /* R/W  8 bits */
 249 #define _H3800_ASIC2_UART_DivisorLatchL        0x0020    /* R/W  8 bits */
 250 #define _H3800_ASIC2_UART_DivisorLatchH        0x0024    /* R/W  8 bits */
 251
 252 #define H3800_ASIC2_UART_0_Receive          H3800_ASIC2_NOFFSET(  u8, UART, 0, Receive )
 253 #define H3800_ASIC2_UART_0_Transmit         H3800_ASIC2_NOFFSET(  u8, UART, 0, Transmit )
 254 #define H3800_ASIC2_UART_0_IntEnable        H3800_ASIC2_NOFFSET(  u8, UART, 0, IntEnable )
 255 #define H3800_ASIC2_UART_0_IntVerify        H3800_ASIC2_NOFFSET(  u8, UART, 0, IntVerify )
 256 #define H3800_ASIC2_UART_0_FIFOControl      H3800_ASIC2_NOFFSET(  u8, UART, 0, FIFOControl )
 257 #define H3800_ASIC2_UART_0_LineControl      H3800_ASIC2_NOFFSET(  u8, UART, 0, LineControl )
 258 #define H3800_ASIC2_UART_0_ModemStatus      H3800_ASIC2_NOFFSET(  u8, UART, 0, ModemStatus )
 259 #define H3800_ASIC2_UART_0_LineStatus       H3800_ASIC2_NOFFSET(  u8, UART, 0, LineStatus )
 260 #define H3800_ASIC2_UART_0_ScratchPad       H3800_ASIC2_NOFFSET(  u8, UART, 0, ScratchPad )
 261 #define H3800_ASIC2_UART_0_DivisorLatchL    H3800_ASIC2_NOFFSET(  u8, UART, 0, DivisorLatchL )
 262 #define H3800_ASIC2_UART_0_DivisorLatchH    H3800_ASIC2_NOFFSET(  u8, UART, 0, DivisorLatchH )
 263
 264 #define H3800_ASIC2_UART_1_Receive          H3800_ASIC2_NOFFSET(  u8, UART, 1, Receive )
 265 #define H3800_ASIC2_UART_1_Transmit         H3800_ASIC2_NOFFSET(  u8, UART, 1, Transmit )
 266 #define H3800_ASIC2_UART_1_IntEnable        H3800_ASIC2_NOFFSET(  u8, UART, 1, IntEnable )
 267 #define H3800_ASIC2_UART_1_IntVerify        H3800_ASIC2_NOFFSET(  u8, UART, 1, IntVerify )
 268 #define H3800_ASIC2_UART_1_FIFOControl      H3800_ASIC2_NOFFSET(  u8, UART, 1, FIFOControl )
 269 #define H3800_ASIC2_UART_1_LineControl      H3800_ASIC2_NOFFSET(  u8, UART, 1, LineControl )
 270 #define H3800_ASIC2_UART_1_ModemStatus      H3800_ASIC2_NOFFSET(  u8, UART, 1, ModemStatus )
 271 #define H3800_ASIC2_UART_1_LineStatus       H3800_ASIC2_NOFFSET(  u8, UART, 1, LineStatus )
 272 #define H3800_ASIC2_UART_1_ScratchPad       H3800_ASIC2_NOFFSET(  u8, UART, 1, ScratchPad )
 273 #define H3800_ASIC2_UART_1_DivisorLatchL    H3800_ASIC2_NOFFSET(  u8, UART, 1, DivisorLatchL )
 274 #define H3800_ASIC2_UART_1_DivisorLatchH    H3800_ASIC2_NOFFSET(  u8, UART, 1, DivisorLatchH )
 275
 276 #define _H3800_ASIC2_TIMER_Base                0x0E00
 277 #define _H3800_ASIC2_TIMER_Command             0x0000    /* R/W  8 bits */
 278
 279 #define H3800_ASIC2_TIMER_Command           H3800_ASIC2_OFFSET( u8, Timer, Command )
 280
 281 #define H3800_ASIC2_TIMER_GAT_0            ( 1 << 0 )    /* Gate enable, counter 0 */
 282 #define H3800_ASIC2_TIMER_GAT_1            ( 1 << 1 )    /* Gate enable, counter 1 */
 283 #define H3800_ASIC2_TIMER_GAT_2            ( 1 << 2 )    /* Gate enable, counter 2 */
 284 #define H3800_ASIC2_TIMER_CLK_0            ( 1 << 3 )    /* Clock enable, counter 0 */
 285 #define H3800_ASIC2_TIMER_CLK_1            ( 1 << 4 )    /* Clock enable, counter 1 */
 286 #define H3800_ASIC2_TIMER_CLK_2            ( 1 << 5 )    /* Clock enable, counter 2 */
 287 #define H3800_ASIC2_TIMER_MODE_0           ( 1 << 6 )    /* Mode 0 enable, counter 0 */
 288 #define H3800_ASIC2_TIMER_MODE_1           ( 1 << 7 )    /* Mode 0 enable, counter 1 */
 289
 290 #define _H3800_ASIC2_CLOCK_Base                0x1000
 291 #define _H3800_ASIC2_CLOCK_Enable              0x0000    /* R/W  18 bits */
 292
 293 #define H3800_ASIC2_CLOCK_Enable            H3800_ASIC2_OFFSET( u32, CLOCK, Enable )
 294
 295 #define H3800_ASIC2_CLOCK_AUDIO_1              0x0001    /* Enable 4.1 MHz clock for 8Khz and 4khz sample rate */
 296 #define H3800_ASIC2_CLOCK_AUDIO_2              0x0002    /* Enable 12.3 MHz clock for 48Khz and 32khz sample rate */
 297 #define H3800_ASIC2_CLOCK_AUDIO_3              0x0004    /* Enable 5.6 MHz clock for 11 kHZ sample rate */
 298 #define H3800_ASIC2_CLOCK_AUDIO_4              0x0008    /* Enable 11.289 MHz clock for 44 and 22 kHz sample rate */
 299 #define H3800_ASIC2_CLOCK_ADC              ( 1 << 4 )    /* 1.024 MHz clock to ADC */
 300 #define H3800_ASIC2_CLOCK_SPI              ( 1 << 5 )    /* 4.096 MHz clock to SPI */
 301 #define H3800_ASIC2_CLOCK_OWM              ( 1 << 6 )    /* 4.096 MHz clock to OWM */
 302 #define H3800_ASIC2_CLOCK_PWM              ( 1 << 7 )    /* 2.048 MHz clock to PWM */
 303 #define H3800_ASIC2_CLOCK_UART_1           ( 1 << 8 )    /* 24.576 MHz clock to UART1 (turn off bit 16) */
 304 #define H3800_ASIC2_CLOCK_UART_0           ( 1 << 9 )    /* 24.576 MHz clock to UART0 (turn off bit 17) */
 305 #define H3800_ASIC2_CLOCK_SD_1             ( 1 << 10 )   /* 16.934 MHz to SD */
 306 #define H3800_ASIC2_CLOCK_SD_2             ( 2 << 10 )   /* 24.576 MHz to SD */
 307 #define H3800_ASIC2_CLOCK_SD_3             ( 3 << 10 )   /* 33.869 MHz to SD */
 308 #define H3800_ASIC2_CLOCK_SD_4             ( 4 << 10 )   /* 49.152 MHz to SD */
 309 #define H3800_ASIC2_CLOCK_EX0              ( 1 << 13 )   /* Enable 32.768 kHz crystal */
 310 #define H3800_ASIC2_CLOCK_EX1              ( 1 << 14 )   /* Enable 24.576 MHz crystal */
 311 #define H3800_ASIC2_CLOCK_EX2              ( 1 << 15 )   /* Enable 33.869 MHz crystal */
 312 #define H3800_ASIC2_CLOCK_SLOW_UART_1      ( 1 << 16 )   /* Enable 3.686 MHz to UART1 (turn off bit 8) */
 313 #define H3800_ASIC2_CLOCK_SLOW_UART_0      ( 1 << 17 )   /* Enable 3.686 MHz to UART0 (turn off bit 9) */
 314
 315 #define _H3800_ASIC2_ADC_Base                  0x1200
 316 #define _H3800_ASIC2_ADC_Multiplexer           0x0000    /* R/W 4 bits - low 3 bits set channel */
 317 #define _H3800_ASIC2_ADC_ControlStatus         0x0004    /* R/W 8 bits */
 318 #define _H3800_ASIC2_ADC_Data                  0x0008    /* R   10 bits */
 319
 320 #define H3800_ASIC2_ADC_Multiplexer       H3800_ASIC2_OFFSET(  u8, ADC, Multiplexer )
 321 #define H3800_ASIC2_ADC_ControlStatus     H3800_ASIC2_OFFSET(  u8, ADC, ControlStatus )
 322 #define H3800_ASIC2_ADC_Data              H3800_ASIC2_OFFSET( u16, ADC, Data )
 323
 324 #define H3600_ASIC2_ADC_MUX_CHANNEL_MASK         0x07    /* Low 3 bits sets channel.  max = 4 */
 325 #define H3600_ASIC2_ADC_MUX_CLKEN          ( 1 << 3 )    /* Enable clock */
 326
 327 #define H3600_ASIC2_ADC_CSR_ADPS_MASK            0x0f    /* Low 4 bits sets prescale, max = 8 */
 328 #define H3600_ASIC2_ADC_CSR_FREE_RUN       ( 1 << 4 )
 329 #define H3600_ASIC2_ADC_CSR_INT_ENABLE     ( 1 << 5 )
 330 #define H3600_ASIC2_ADC_CSR_START          ( 1 << 6 )    /* Set to start conversion.  Goes to 0 when done */
 331 #define H3600_ASIC2_ADC_CSR_ENABLE         ( 1 << 7 )    /* 1:power up ADC, 0:power down */
 332
 333
 334 #define _H3800_ASIC2_INTR_Base                 0x1600
 335 #define _H3800_ASIC2_INTR_MaskAndFlag          0x0000    /* R/(W) 8bits */
 336 #define _H3800_ASIC2_INTR_ClockPrescale        0x0004    /* R/(W) 5bits */
 337 #define _H3800_ASIC2_INTR_TimerSet             0x0008    /* R/(W) 8bits */
 338
 339 #define H3800_ASIC2_INTR_MaskAndFlag      H3800_ASIC2_OFFSET( u8, INTR, MaskAndFlag )
 340 #define H3800_ASIC2_INTR_ClockPrescale    H3800_ASIC2_OFFSET( u8, INTR, ClockPrescale )
 341 #define H3800_ASIC2_INTR_TimerSet         H3800_ASIC2_OFFSET( u8, INTR, TimerSet )
 342
 343 #define H3800_ASIC2_INTR_GLOBAL_MASK       ( 1 << 0 )    /* Global interrupt mask */
 344 #define H3800_ASIC2_INTR_POWER_ON_RESET    ( 1 << 1 )    /* 01: Power on reset (bits 1 & 2 ) */
 345 #define H3800_ASIC2_INTR_EXTERNAL_RESET    ( 2 << 1 )    /* 10: External reset (bits 1 & 2 ) */
 346 #define H3800_ASIC2_INTR_MASK_UART_0       ( 1 << 4 )
 347 #define H3800_ASIC2_INTR_MASK_UART_1       ( 1 << 5 )
 348 #define H3800_ASIC2_INTR_MASK_TIMER        ( 1 << 6 )
 349 #define H3800_ASIC2_INTR_MASK_OWM          ( 1 << 7 )
 350
 351 #define H3800_ASIC2_INTR_CLOCK_PRESCALE          0x0f    /* 4 bits, max 14 */
 352 #define H3800_ASIC2_INTR_SET               ( 1 << 4 )    /* Time base enable */
 353
 354
 355 #define _H3800_ASIC2_OWM_Base                  0x1800
 356 #define _H3800_ASIC2_OWM_Command               0x0000    /* R/W 4 bits command register */
 357 #define _H3800_ASIC2_OWM_Data                  0x0004    /* R/W 8 bits, transmit / receive buffer */
 358 #define _H3800_ASIC2_OWM_Interrupt             0x0008    /* R/W Command register */
 359 #define _H3800_ASIC2_OWM_InterruptEnable       0x000c    /* R/W Command register */
 360 #define _H3800_ASIC2_OWM_ClockDivisor          0x0010    /* R/W 5 bits of divisor and pre-scale */
 361
 362 #define H3800_ASIC2_OWM_Command            H3800_ASIC2_OFFSET( u8, OWM, Command )
 363 #define H3800_ASIC2_OWM_Data               H3800_ASIC2_OFFSET( u8, OWM, Data )
 364 #define H3800_ASIC2_OWM_Interrupt          H3800_ASIC2_OFFSET( u8, OWM, Interrupt )
 365 #define H3800_ASIC2_OWM_InterruptEnable    H3800_ASIC2_OFFSET( u8, OWM, InterruptEnable )
 366 #define H3800_ASIC2_OWM_ClockDivisor       H3800_ASIC2_OFFSET( u8, OWM, ClockDivisor )
 367
 368 #define H3800_ASIC2_OWM_CMD_ONE_WIRE_RESET ( 1 << 0 )    /* Set to force reset on 1-wire bus */
 369 #define H3800_ASIC2_OWM_CMD_SRA            ( 1 << 1 )    /* Set to switch to Search ROM accelerator mode */
 370 #define H3800_ASIC2_OWM_CMD_DQ_OUTPUT      ( 1 << 2 )    /* Write only - forces bus low */
 371 #define H3800_ASIC2_OWM_CMD_DQ_INPUT       ( 1 << 3 )    /* Read only - reflects state of bus */
 372
 373 #define H3800_ASIC2_OWM_INT_PD             ( 1 << 0 )    /* Presence detect */
 374 #define H3800_ASIC2_OWM_INT_PDR            ( 1 << 1 )    /* Presence detect result */
 375 #define H3800_ASIC2_OWM_INT_TBE            ( 1 << 2 )    /* Transmit buffer empty */
 376 #define H3800_ASIC2_OWM_INT_TEMT           ( 1 << 3 )    /* Transmit shift register empty */
 377 #define H3800_ASIC2_OWM_INT_RBF            ( 1 << 4 )    /* Receive buffer full */
 378
 379 #define H3800_ASIC2_OWM_INTEN_EPD          ( 1 << 0 )    /* Enable receive buffer full interrupt */
 380 #define H3800_ASIC2_OWM_INTEN_IAS          ( 1 << 1 )    /* Enable transmit shift register empty interrupt */
 381 #define H3800_ASIC2_OWM_INTEN_ETBE         ( 1 << 2 )    /* Enable transmit buffer empty interrupt */
 382 #define H3800_ASIC2_OWM_INTEN_ETMT         ( 1 << 3 )    /* INTR active state */
 383 #define H3800_ASIC2_OWM_INTEN_ERBF         ( 1 << 4 )    /* Enable presence detect interrupt */
 384
 385 #define _H3800_ASIC2_FlashCtl_Base             0x1A00
 386
 387 /****************************************************/
 388 /* H3800, ASIC #1
 389  * This ASIC is accesed through ASIC #2, and
 390  * mapped into the 1c00 - 1f00 region
 391  */
 392
 393 #define H3800_ASIC1_OFFSET(s,x,y)   \
 394      (*((volatile s *) (_H3800_ASIC2_Base + _H3800_ASIC1_ ## x ## _Base + (_H3800_ASIC1_ ## x ## _ ## y << 1))))
 395
 396 #define _H3800_ASIC1_MMC_Base             0x1c00
 397
 398 #define _H3800_ASIC1_MMC_StartStopClock     0x00    /* R/W 8bit                                  */
 399 #define _H3800_ASIC1_MMC_Status             0x02    /* R   See below, default 0x0040             */
 400 #define _H3800_ASIC1_MMC_ClockRate          0x04    /* R/W 8bit, low 3 bits are clock divisor    */
 401 #define _H3800_ASIC1_MMC_SPIRegister        0x08    /* R/W 8bit, see below                       */
 402 #define _H3800_ASIC1_MMC_CmdDataCont        0x0a    /* R/W 8bit, write to start MMC adapter      */
 403 #define _H3800_ASIC1_MMC_ResponseTimeout    0x0c    /* R/W 8bit, clocks before response timeout  */
 404 #define _H3800_ASIC1_MMC_ReadTimeout        0x0e    /* R/W 16bit, clocks before received data timeout */
 405 #define _H3800_ASIC1_MMC_BlockLength        0x10    /* R/W 10bit */
 406 #define _H3800_ASIC1_MMC_NumOfBlocks        0x12    /* R/W 16bit, in block mode, number of blocks  */
 407 #define _H3800_ASIC1_MMC_InterruptMask      0x1a    /* R/W 8bit */
 408 #define _H3800_ASIC1_MMC_CommandNumber      0x1c    /* R/W 6 bits */
 409 #define _H3800_ASIC1_MMC_ArgumentH          0x1e    /* R/W 16 bits  */
 410 #define _H3800_ASIC1_MMC_ArgumentL          0x20    /* R/W 16 bits */
 411 #define _H3800_ASIC1_MMC_ResFifo            0x22    /* R   8 x 16 bits - contains response FIFO */
 412 #define _H3800_ASIC1_MMC_BufferPartFull     0x28    /* R/W 8 bits */
 413
 414 #define H3800_ASIC1_MMC_StartStopClock    H3800_ASIC1_OFFSET(  u8, MMC, StartStopClock )
 415 #define H3800_ASIC1_MMC_Status            H3800_ASIC1_OFFSET( u16, MMC, Status )
 416 #define H3800_ASIC1_MMC_ClockRate         H3800_ASIC1_OFFSET(  u8, MMC, ClockRate )
 417 #define H3800_ASIC1_MMC_SPIRegister       H3800_ASIC1_OFFSET(  u8, MMC, SPIRegister )
 418 #define H3800_ASIC1_MMC_CmdDataCont       H3800_ASIC1_OFFSET(  u8, MMC, CmdDataCont )
 419 #define H3800_ASIC1_MMC_ResponseTimeout   H3800_ASIC1_OFFSET(  u8, MMC, ResponseTimeout )
 420 #define H3800_ASIC1_MMC_ReadTimeout       H3800_ASIC1_OFFSET( u16, MMC, ReadTimeout )
 421 #define H3800_ASIC1_MMC_BlockLength       H3800_ASIC1_OFFSET( u16, MMC, BlockLength )
 422 #define H3800_ASIC1_MMC_NumOfBlocks       H3800_ASIC1_OFFSET( u16, MMC, NumOfBlocks )
 423 #define H3800_ASIC1_MMC_InterruptMask     H3800_ASIC1_OFFSET(  u8, MMC, InterruptMask )
 424 #define H3800_ASIC1_MMC_CommandNumber     H3800_ASIC1_OFFSET(  u8, MMC, CommandNumber )
 425 #define H3800_ASIC1_MMC_ArgumentH         H3800_ASIC1_OFFSET( u16, MMC, ArgumentH )
 426 #define H3800_ASIC1_MMC_ArgumentL         H3800_ASIC1_OFFSET( u16, MMC, ArgumentL )
 427 #define H3800_ASIC1_MMC_ResFifo           H3800_ASIC1_OFFSET( u16, MMC, ResFifo )
 428 #define H3800_ASIC1_MMC_BufferPartFull    H3800_ASIC1_OFFSET(  u8, MMC, BufferPartFull )
 429
 430 #define H3800_ASIC1_MMC_STOP_CLOCK                   (1 << 0)   /* Write to "StartStopClock" register */
 431 #define H3800_ASIC1_MMC_START_CLOCK                  (1 << 1)
 432
 433 #define H3800_ASIC1_MMC_STATUS_READ_TIMEOUT          (1 << 0)
 434 #define H3800_ASIC1_MMC_STATUS_RESPONSE_TIMEOUT      (1 << 1)
 435 #define H3800_ASIC1_MMC_STATUS_CRC_WRITE_ERROR       (1 << 2)
 436 #define H3800_ASIC1_MMC_STATUS_CRC_READ_ERROR        (1 << 3)
 437 #define H3800_ASIC1_MMC_STATUS_SPI_READ_ERROR        (1 << 4)  /* SPI data token error received */
 438 #define H3800_ASIC1_MMC_STATUS_CRC_RESPONSE_ERROR    (1 << 5)
 439 #define H3800_ASIC1_MMC_STATUS_FIFO_EMPTY            (1 << 6)
 440 #define H3800_ASIC1_MMC_STATUS_FIFO_FULL             (1 << 7)
 441 #define H3800_ASIC1_MMC_STATUS_CLOCK_ENABLE          (1 << 8)  /* MultiMediaCard clock stopped */
 442 #define H3800_ASIC1_MMC_STATUS_DATA_TRANSFER_DONE    (1 << 11) /* Write operation, indicates transfer finished */
 443 #define H3800_ASIC1_MMC_STATUS_END_PROGRAM           (1 << 12) /* End write and read operations */
 444 #define H3800_ASIC1_MMC_STATUS_END_COMMAND_RESPONSE  (1 << 13) /* End command response */
 445
 446 #define H3800_ASIC1_MMC_SPI_REG_SPI_ENABLE           (1 << 0)  /* Enables SPI mode */
 447 #define H3800_ASIC1_MMC_SPI_REG_CRC_ON               (1 << 1)  /* 1:turn on CRC    */
 448 #define H3800_ASIC1_MMC_SPI_REG_SPI_CS_ENABLE        (1 << 2)  /* 1:turn on SPI CS */
 449 #define H3800_ASIC1_MMC_SPI_REG_CS_ADDRESS_MASK      0x38      /* Bits 3,4,5 are the SPI CS relative address */
 450
 451 #define H3800_ASIC1_MMC_CMD_DATA_CONT_FORMAT_NO_RESPONSE  0x00
 452 #define H3800_ASIC1_MMC_CMD_DATA_CONT_FORMAT_R1           0x01
 453 #define H3800_ASIC1_MMC_CMD_DATA_CONT_FORMAT_R2           0x02
 454 #define H3800_ASIC1_MMC_CMD_DATA_CONT_FORMAT_R3           0x03
 455 #define H3800_ASIC1_MMC_CMD_DATA_CONT_DATA_ENABLE         (1 << 2)  /* This command contains a data transfer */
 456 #define H3800_ASIC1_MMC_CMD_DATA_CONT_WRITE               (1 << 3)  /* This data transfer is a write */
 457 #define H3800_ASIC1_MMC_CMD_DATA_CONT_STREAM_MODE         (1 << 4)  /* This data transfer is in stream mode */
 458 #define H3800_ASIC1_MMC_CMD_DATA_CONT_BUSY_BIT            (1 << 5)  /* Busy signal expected after current cmd */
 459 #define H3800_ASIC1_MMC_CMD_DATA_CONT_INITIALIZE          (1 << 6)  /* Enables the 80 bits for initializing card */
 460
 461 #define H3800_ASIC1_MMC_INT_MASK_DATA_TRANSFER_DONE       (1 << 0)
 462 #define H3800_ASIC1_MMC_INT_MASK_PROGRAM_DONE             (1 << 1)
 463 #define H3800_ASIC1_MMC_INT_MASK_END_COMMAND_RESPONSE     (1 << 2)
 464 #define H3800_ASIC1_MMC_INT_MASK_BUFFER_READY             (1 << 3)
 465
 466 #define H3800_ASIC1_MMC_BUFFER_PART_FULL                  (1 << 0)
 467
 468 /********* GPIO **********/
 469
 470 #define _H3800_ASIC1_GPIO_Base        0x1e00
 471
 472 #define _H3800_ASIC1_GPIO_Mask          0x30    /* R/W 0:don't mask, 1:mask interrupt */
 473 #define _H3800_ASIC1_GPIO_Direction     0x32    /* R/W 0:input, 1:output              */
 474 #define _H3800_ASIC1_GPIO_Out           0x34    /* R/W 0:output low, 1:output high    */
 475 #define _H3800_ASIC1_GPIO_TriggerType   0x36    /* R/W 0:level, 1:edge                */
 476 #define _H3800_ASIC1_GPIO_EdgeTrigger   0x38    /* R/W 0:falling, 1:rising            */
 477 #define _H3800_ASIC1_GPIO_LevelTrigger  0x3A    /* R/W 0:low, 1:high level detect     */
 478 #define _H3800_ASIC1_GPIO_LevelStatus   0x3C    /* R/W 0:none, 1:detect               */
 479 #define _H3800_ASIC1_GPIO_EdgeStatus    0x3E    /* R/W 0:none, 1:detect               */
 480 #define _H3800_ASIC1_GPIO_State         0x40    /* R   See masks below  (default 0)         */
 481 #define _H3800_ASIC1_GPIO_Reset         0x42    /* R/W See masks below  (default 0x04)      */
 482 #define _H3800_ASIC1_GPIO_SleepMask     0x44    /* R/W 0:don't mask, 1:mask trigger in sleep mode  */
 483 #define _H3800_ASIC1_GPIO_SleepDir      0x46    /* R/W direction 0:input, 1:output in sleep mode    */
 484 #define _H3800_ASIC1_GPIO_SleepOut      0x48    /* R/W level 0:low, 1:high in sleep mode           */
 485 #define _H3800_ASIC1_GPIO_Status        0x4A    /* R   Pin status                                  */
 486 #define _H3800_ASIC1_GPIO_BattFaultDir  0x4C    /* R/W direction 0:input, 1:output in batt_fault   */
 487 #define _H3800_ASIC1_GPIO_BattFaultOut  0x4E    /* R/W level 0:low, 1:high in batt_fault           */
 488
 489 #define H3800_ASIC1_GPIO_Mask         H3800_ASIC1_OFFSET( u16, GPIO, Mask )
 490 #define H3800_ASIC1_GPIO_Direction    H3800_ASIC1_OFFSET( u16, GPIO, Direction )
 491 #define H3800_ASIC1_GPIO_Out          H3800_ASIC1_OFFSET( u16, GPIO, Out )
 492 #define H3800_ASIC1_GPIO_TriggerType  H3800_ASIC1_OFFSET( u16, GPIO, TriggerType )
 493 #define H3800_ASIC1_GPIO_EdgeTrigger  H3800_ASIC1_OFFSET( u16, GPIO, EdgeTrigger )
 494 #define H3800_ASIC1_GPIO_LevelTrigger H3800_ASIC1_OFFSET( u16, GPIO, LevelTrigger )
 495 #define H3800_ASIC1_GPIO_LevelStatus  H3800_ASIC1_OFFSET( u16, GPIO, LevelStatus )
 496 #define H3800_ASIC1_GPIO_EdgeStatus   H3800_ASIC1_OFFSET( u16, GPIO, EdgeStatus )
 497 #define H3800_ASIC1_GPIO_State        H3800_ASIC1_OFFSET(  u8, GPIO, State )
 498 #define H3800_ASIC1_GPIO_Reset        H3800_ASIC1_OFFSET(  u8, GPIO, Reset )
 499 #define H3800_ASIC1_GPIO_SleepMask    H3800_ASIC1_OFFSET( u16, GPIO, SleepMask )
 500 #define H3800_ASIC1_GPIO_SleepDir     H3800_ASIC1_OFFSET( u16, GPIO, SleepDir )
 501 #define H3800_ASIC1_GPIO_SleepOut     H3800_ASIC1_OFFSET( u16, GPIO, SleepOut )
 502 #define H3800_ASIC1_GPIO_Status       H3800_ASIC1_OFFSET( u16, GPIO, Status )
 503 #define H3800_ASIC1_GPIO_BattFaultDir H3800_ASIC1_OFFSET( u16, GPIO, BattFaultDir )
 504 #define H3800_ASIC1_GPIO_BattFaultOut H3800_ASIC1_OFFSET( u16, GPIO, BattFaultOut )
 505
 506 #define H3800_ASIC1_GPIO_STATE_MASK            (1 << 0)
 507 #define H3800_ASIC1_GPIO_STATE_DIRECTION       (1 << 1)
 508 #define H3800_ASIC1_GPIO_STATE_OUT             (1 << 2)
 509 #define H3800_ASIC1_GPIO_STATE_TRIGGER_TYPE    (1 << 3)
 510 #define H3800_ASIC1_GPIO_STATE_EDGE_TRIGGER    (1 << 4)
 511 #define H3800_ASIC1_GPIO_STATE_LEVEL_TRIGGER   (1 << 5)
 512
 513 #define H3800_ASIC1_GPIO_RESET_SOFTWARE        (1 << 0)
 514 #define H3800_ASIC1_GPIO_RESET_AUTO_SLEEP      (1 << 1)
 515 #define H3800_ASIC1_GPIO_RESET_FIRST_PWR_ON    (1 << 2)
 516
 517 /* These are all outputs */
 518 #define GPIO_H3800_ASIC1_IR_ON_N          (1 << 0)   /* Apply power to the IR Module */
 519 #define GPIO_H3800_ASIC1_SD_PWR_ON        (1 << 1)   /* Secure Digital power on */
 520 #define GPIO_H3800_ASIC1_RS232_ON         (1 << 2)   /* Turn on power to the RS232 chip ? */
 521 #define GPIO_H3800_ASIC1_PULSE_GEN        (1 << 3)   /* Goes to speaker / earphone */
 522 #define GPIO_H3800_ASIC1_CH_TIMER         (1 << 4)   /* */
 523 #define GPIO_H3800_ASIC1_LCD_5V_ON        (1 << 5)   /* Enables LCD_5V */
 524 #define GPIO_H3800_ASIC1_LCD_ON           (1 << 6)   /* Enables LCD_3V */
 525 #define GPIO_H3800_ASIC1_LCD_PCI          (1 << 7)   /* Connects to PDWN on LCD controller */
 526 #define GPIO_H3800_ASIC1_VGH_ON           (1 << 8)   /* Drives VGH on the LCD (+9??) */
 527 #define GPIO_H3800_ASIC1_VGL_ON           (1 << 9)   /* Drivers VGL on the LCD (-6??) */
 528 #define GPIO_H3800_ASIC1_FL_PWR_ON        (1 << 10)  /* Frontlight power on */
 529 #define GPIO_H3800_ASIC1_BT_PWR_ON        (1 << 11)  /* Bluetooth power on */
 530 #define GPIO_H3800_ASIC1_SPK_ON           (1 << 12)  /* */
 531 #define GPIO_H3800_ASIC1_EAR_ON_N         (1 << 13)  /* */
 532 #define GPIO_H3800_ASIC1_AUD_PWR_ON       (1 << 14)  /* */
 533
 534 /* Write enable for the flash */
 535
 536 #define _H3800_ASIC1_FlashWP_Base         0x1F00
 537 #define _H3800_ASIC1_FlashWP_VPP_ON         0x00    /* R   1: write, 0: protect */
 538 #define H3800_ASIC1_FlashWP_VPP_ON       H3800_ASIC1_OFFSET( u8, FlashWP, VPP_ON )
 539
 540 #endif /* _INCLUDE_H3600_GPIO_H_ */