include/asm-blackfin/mach-bf527/bfin_serial_5xx.h

   1 #include <linux/serial.h>
   2 #include <asm/dma.h>
   3 #include <asm/portmux.h>
   4
   5 #define NR_PORTS                2
   6
   7 #define OFFSET_THR              0x00    /* Transmit Holding register            */
   8 #define OFFSET_RBR              0x00    /* Receive Buffer register              */
   9 #define OFFSET_DLL              0x00    /* Divisor Latch (Low-Byte)             */
  10 #define OFFSET_IER              0x04    /* Interrupt Enable Register            */
  11 #define OFFSET_DLH              0x04    /* Divisor Latch (High-Byte)            */
  12 #define OFFSET_IIR              0x08    /* Interrupt Identification Register    */
  13 #define OFFSET_LCR              0x0C    /* Line Control Register                */
  14 #define OFFSET_MCR              0x10    /* Modem Control Register               */
  15 #define OFFSET_LSR              0x14    /* Line Status Register                 */
  16 #define OFFSET_MSR              0x18    /* Modem Status Register                */
  17 #define OFFSET_SCR              0x1C    /* SCR Scratch Register                 */
  18 #define OFFSET_GCTL             0x24    /* Global Control Register              */
  19
  20 #define UART_GET_CHAR(uart)     bfin_read16(((uart)->port.membase + OFFSET_RBR))
  21 #define UART_GET_DLL(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLL))
  22 #define UART_GET_IER(uart)      bfin_read16(((uart)->port.membase + OFFSET_IER))
  23 #define UART_GET_DLH(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLH))
  24 #define UART_GET_IIR(uart)      bfin_read16(((uart)->port.membase + OFFSET_IIR))
  25 #define UART_GET_LCR(uart)      bfin_read16(((uart)->port.membase + OFFSET_LCR))
  26 <<<<<<< HEAD:include/asm-blackfin/mach-bf527/bfin_serial_5xx.h
  27 #define UART_GET_LSR(uart)      bfin_read16(((uart)->port.membase + OFFSET_LSR))
  28 =======
  29 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:include/asm-blackfin/mach-bf527/bfin_serial_5xx.h
  30 #define UART_GET_GCTL(uart)     bfin_read16(((uart)->port.membase + OFFSET_GCTL))
  31
  32 #define UART_PUT_CHAR(uart, v)   bfin_write16(((uart)->port.membase + OFFSET_THR), v)
  33 #define UART_PUT_DLL(uart, v)    bfin_write16(((uart)->port.membase + OFFSET_DLL), v)
  34 #define UART_PUT_IER(uart, v)    bfin_write16(((uart)->port.membase + OFFSET_IER), v)
  35 #define UART_PUT_DLH(uart, v)    bfin_write16(((uart)->port.membase + OFFSET_DLH), v)
  36 #define UART_PUT_LCR(uart, v)    bfin_write16(((uart)->port.membase + OFFSET_LCR), v)
  37 #define UART_PUT_GCTL(uart, v)   bfin_write16(((uart)->port.membase + OFFSET_GCTL), v)
  38
  39 #if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
  40 # define CONFIG_SERIAL_BFIN_CTSRTS
  41
  42 # ifndef CONFIG_UART0_CTS_PIN
  43 #  define CONFIG_UART0_CTS_PIN -1
  44 # endif
  45
  46 # ifndef CONFIG_UART0_RTS_PIN
  47 #  define CONFIG_UART0_RTS_PIN -1
  48 # endif
  49
  50 # ifndef CONFIG_UART1_CTS_PIN
  51 #  define CONFIG_UART1_CTS_PIN -1
  52 # endif
  53
  54 # ifndef CONFIG_UART1_RTS_PIN
  55 #  define CONFIG_UART1_RTS_PIN -1
  56 # endif
  57 #endif
  58 /*
  59  * The pin configuration is different from schematic
  60  */
  61 struct bfin_serial_port {
  62         struct uart_port port;
  63         unsigned int old_status;
  64 <<<<<<< HEAD:include/asm-blackfin/mach-bf527/bfin_serial_5xx.h
  65 =======
  66         unsigned int lsr;
  67 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:include/asm-blackfin/mach-bf527/bfin_serial_5xx.h
  68 #ifdef CONFIG_SERIAL_BFIN_DMA
  69         int tx_done;
  70         int tx_count;
  71         struct circ_buf rx_dma_buf;
  72         struct timer_list rx_dma_timer;
  73         int rx_dma_nrows;
  74         unsigned int tx_dma_channel;
  75         unsigned int rx_dma_channel;
  76         struct work_struct tx_dma_workqueue;
  77 <<<<<<< HEAD:include/asm-blackfin/mach-bf527/bfin_serial_5xx.h
  78 #else
  79         struct work_struct cts_workqueue;
  80 =======
  81 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:include/asm-blackfin/mach-bf527/bfin_serial_5xx.h
  82 #endif
  83 #ifdef CONFIG_SERIAL_BFIN_CTSRTS
  84 <<<<<<< HEAD:include/asm-blackfin/mach-bf527/bfin_serial_5xx.h
  85 =======
  86         struct work_struct cts_workqueue;
  87 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:include/asm-blackfin/mach-bf527/bfin_serial_5xx.h
  88         int cts_pin;
  89         int rts_pin;
  90 #endif
  91 };
  92
  93 <<<<<<< HEAD:include/asm-blackfin/mach-bf527/bfin_serial_5xx.h
  94 =======
  95 /* The hardware clears the LSR bits upon read, so we need to cache
  96  * some of the more fun bits in software so they don't get lost
  97  * when checking the LSR in other code paths (TX).
  98  */
  99 static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart)
 100 {
 101         unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR);
 102         uart->lsr |= (lsr & (BI|FE|PE|OE));
 103         return lsr | uart->lsr;
 104 }
 105
 106 static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
 107 {
 108         uart->lsr = 0;
 109         bfin_write16(uart->port.membase + OFFSET_LSR, -1);
 110 }
 111
 112 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:include/asm-blackfin/mach-bf527/bfin_serial_5xx.h
 113 struct bfin_serial_port bfin_serial_ports[NR_PORTS];
 114 struct bfin_serial_res {
 115         unsigned long uart_base_addr;
 116         int uart_irq;
 117 #ifdef CONFIG_SERIAL_BFIN_DMA
 118         unsigned int uart_tx_dma_channel;
 119         unsigned int uart_rx_dma_channel;
 120 #endif
 121 #ifdef CONFIG_SERIAL_BFIN_CTSRTS
 122         int uart_cts_pin;
 123         int uart_rts_pin;
 124 #endif
 125 };
 126
 127 struct bfin_serial_res bfin_serial_resource[] = {
 128 #ifdef CONFIG_SERIAL_BFIN_UART0
 129         {
 130          0xFFC00400,
 131          IRQ_UART0_RX,
 132 #ifdef CONFIG_SERIAL_BFIN_DMA
 133          CH_UART0_TX,
 134          CH_UART0_RX,
 135 #endif
 136 #ifdef CONFIG_BFIN_UART0_CTSRTS
 137          CONFIG_UART0_CTS_PIN,
 138          CONFIG_UART0_RTS_PIN,
 139 #endif
 140          },
 141 #endif
 142 #ifdef CONFIG_SERIAL_BFIN_UART1
 143         {
 144          0xFFC02000,
 145          IRQ_UART1_RX,
 146 #ifdef CONFIG_SERIAL_BFIN_DMA
 147          CH_UART1_TX,
 148          CH_UART1_RX,
 149 #endif
 150 #ifdef CONFIG_BFIN_UART1_CTSRTS
 151          CONFIG_UART1_CTS_PIN,
 152          CONFIG_UART1_RTS_PIN,
 153 #endif
 154          },
 155 #endif
 156 };
 157
 158 int nr_ports = ARRAY_SIZE(bfin_serial_resource);
 159
 160 #define DRIVER_NAME "bfin-uart"
 161
 162 static void bfin_serial_hw_init(struct bfin_serial_port *uart)
 163 {
 164
 165 #ifdef CONFIG_SERIAL_BFIN_UART0
 166         peripheral_request(P_UART0_TX, DRIVER_NAME);
 167         peripheral_request(P_UART0_RX, DRIVER_NAME);
 168 #endif
 169
 170 #ifdef CONFIG_SERIAL_BFIN_UART1
 171         peripheral_request(P_UART1_TX, DRIVER_NAME);
 172         peripheral_request(P_UART1_RX, DRIVER_NAME);
 173 #endif
 174
 175 #ifdef CONFIG_SERIAL_BFIN_CTSRTS
 176         if (uart->cts_pin >= 0) {
 177                 gpio_request(uart->cts_pin, DRIVER_NAME);
 178                 gpio_direction_input(uart->cts_pin);
 179         }
 180
 181         if (uart->rts_pin >= 0) {
 182                 gpio_request(uart->rts_pin, DRIVER_NAME);
 183                 gpio_direction_output(uart->rts_pin, 0);
 184         }
 185 #endif
 186 }